Integrated assembly and method of forming an integrated assembly

Abstract

Some embodiments include an integrated assembly and methods of forming an integrated assembly. A column of channel material is disposed within a memory region, and a conductive pillar is disposed within another region. A source structure is coupled to a lower region of the column of channel material. A panel extends across the memory region and the another region. A doped semiconductor material is proximate the panel within the memory region and the another region. The doped semiconductor material is at least a portion of the source structure within the memory region. A liner is proximate and laterally surrounds the conductive pillar. The liner is between the conductive pillar and the doped semiconductor material. Some embodiments include methods of forming an integrated assembly.

Description

Technical Field

[0001] The present invention relates to a method for forming an integrated assembly (e.g., an integrated memory device) and the integrated assembly itself. Background Technology

[0002] Memory provides data storage devices for electronic systems. Flash memory is a type of memory widely used in modern computers and devices. For example, modern personal computers store the BIOS on flash memory chips. As another example, it is increasingly common for computers and other devices to use flash memory, in the form of solid-state drives, instead of traditional hard disk drives. As yet another example, flash memory is prevalent in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and allows manufacturers to provide the ability to remotely upgrade devices for enhanced features.

[0003] NAND can be the basic architecture of flash memory and can be configured to include vertically stacked memory cells.

[0004] Before describing NAND in detail, it may be helpful to describe the relationships between memory arrays within an integrated layout more generally. Figure 1A block diagram of a prior art device 1000 is shown, comprising: a memory array 1002 having a plurality of memory cells 1003 arranged in rows and columns; access lines 1004 (e.g., word lines WL0 to WLm for conducting signals); and first data lines 1006 (e.g., bit lines BL0 to BLn for conducting signals). Access lines 1004 and first data lines 1006 are used to transmit information to and from the memory cells 1003. Row decoders 1007 and column decoders 1008 decode address signals A0 to AX on address lines 1009 to determine which memory cells in the memory cells 1003 will be accessed. Sensing amplifier circuitry 1015 operates to determine the value of information read from the memory cells 1003. I / O circuitry 1017 transmits the value of information between the memory array 1002 and the input / output (I / O) lines 1005. Signals DQ0 to DQN on I / O lines 1005 can represent values ​​of information to be read from or written to memory cell 1003. Other devices can communicate with device 1000 via I / O line 1005, address line 1009, or control line 1020. Memory control unit 1018 controls memory operations to be performed on memory cell 1003 and uses signals on control line 1020. Device 1000 can receive supply voltage signals Vcc and Vss on first supply line 1030 and second supply line 1032, respectively. Device 1000 includes selection circuitry 1040 and input / output (I / O) circuitry 1017. Selection circuitry 1040 can respond to signals CSEL1 to CSELn via I / O circuitry 1017 to select signals on first data line 1006 and second data line 1013, which can represent values ​​of information to be read from or programmed into memory cell 1003. The column decoder 1008 can selectively activate the CSEL1 to CSELn signals based on the A0 to AX address signals on the address lines 1009. The selection circuit 1040 can select the signals on the first data line 1006 and the second data line 1013 to enable communication between the memory array 1002 and the I / O circuit 1017 during read and program operations.

[0005] Figure 1 The memory array 1002 can be a NAND memory array, and Figure 2 Showing what can be used Figure 1A schematic diagram of a three-dimensional NAND memory device 200 of a memory array 1002. Device 200 includes multiple strings of charge storage devices. In a first direction (Z-Z'), each string of charge storage devices may include, for example, thirty-two charge storage devices stacked one on top of the other, where each charge storage device corresponds to, for example, one of thirty-two rows (e.g., row 0 to row 31). The charge storage devices of the respective strings may share a common channel region, for example, a common channel region formed in pillars of a respective semiconductor material (e.g., polysilicon), around which the charge storage device strings are formed. In a second direction (X-X'), each first group of the multiple strings, for example, sixteen first groups, may include, for example, eight strings sharing multiple (e.g., thirty-two) access lines (i.e., "global control gate (CG) lines," also referred to as word lines WL). Each of the access lines may couple a charge storage device within a layer. When each charge storage device includes a cell capable of storing two bits of information, charge storage devices coupled by the same access line (and therefore corresponding to the same layer) can be logically grouped into, for example, two pages, such as P0 / P32, P1 / P33, P2 / P34, etc. In the third direction (Y-Y'), each second group in the multiple strings, for example, eight second groups, may include sixteen strings coupled by corresponding data lines of eight data lines. The size of the memory block may include 1,024 pages and approximately 16 MB in total (e.g., 16WL × 32 rows × 2 bits = 1,024 pages / block, block size = 1,024 pages × 16KB / page = 16 MB). The number of strings, layers, access lines, data lines, first groups, second groups, and / or pages can be compared. Figure 2 The numbers shown are either larger or smaller.

[0006] Figure 3 Showing in the X-X' direction Figure 2 A cross-sectional view of a memory block 300 of a 3D NAND memory device 200, the memory block 300 comprising about Figure 2 The description refers to fifteen strings of charge storage devices within one of the sixteen first groups of strings. The multi-string memory block 300 can be divided into multiple subsets 310, 320, 330 (e.g., tile columns), such as tile columns. I Puzzle Series j and puzzle series KEach subset (e.g., a tile array) comprises a “partial block” (sub-block) of memory block 300. A global drain-side select-gate (SGD) line 340 may be coupled to the SGDs of multiple strings. For example, the global SGD line 340 may be coupled to multiple (e.g., three) sub-SGD lines 342, 344, 346 via corresponding sub-SGD drivers of multiple (e.g., three) sub-SGD drivers 332, 334, 336, where each sub-SGD line corresponds to a corresponding subset (e.g., a tile array). Each sub-SGD driver of sub-SGD drivers 332, 334, 336 may simultaneously couple or disconnect the SGD of the corresponding partial block (e.g., a tile array) string, independent of the SGDs of the strings of other partial blocks. A global source-side select-gate (SGS) line 360 ​​may be coupled to the SGS of multiple strings. For example, a global SGS line 360 ​​may be coupled to a plurality of sub-SGS lines 362, 364, and 366 via corresponding sub-SGS drivers among a plurality of sub-SGS drivers 322, 324, and 326, wherein each sub-SGS line corresponds to a corresponding subset (e.g., a tile column). Each of the sub-SGS drivers 322, 324, and 326 may couple or disconnect the SGS of the corresponding partial block (e.g., a tile column) string independently of the SGS of the strings of other partial blocks. A global access line (e.g., a global CG line) 350 may be coupled to a charge storage device corresponding to a corresponding row of each of the multiple strings. Each global CG line (e.g., global CG line 350) may be coupled to a plurality of sub-access lines (e.g., sub-CG lines) 352, 354, and 356 via corresponding sub-string drivers among a plurality of sub-string drivers 312, 314, and 316. Each substring driver in the substring driver can simultaneously couple or disconnect the charge storage device corresponding to the corresponding sub-block and / or row, independently of the charge storage devices of other sub-blocks and / or other rows. The charge storage devices corresponding to the corresponding subset (e.g., sub-block) and the corresponding row may include charge storage devices of "sub-rows" (e.g., a single "patch"). The string corresponding to the corresponding subset (e.g., sub-block) may be coupled to the corresponding sub-source in sub-sources 372, 374, and 376 (e.g., "patch source"), wherein each sub-source is coupled to a corresponding power source.

[0007] Alternatively, refer to Figure 4 The schematic diagram illustrates a NAND memory device 200.

[0008] Memory array 200 includes word lines 2021 to 202 N And bit lines 2281 to 228 M .

[0009] Memory array 200 also includes NAND strings 2061 to 206 M Each NAND string contains 2081 to 208 charge storage transistors. NCharge storage transistors can store charge using floating gate materials (e.g., polysilicon) or charge trapping materials (e.g., silicon nitride, metal nanodots, etc.).

[0010] Charge storage transistor 208 is located at the intersection of word line 202 and string 206. Charge storage transistor 208 represents a non-volatile memory cell for storing data. The charge storage transistor 208 of each NAND string 206 is connected in series from source to drain between a source select device (e.g., source-side selected gate SGS) 210 and a drain select device (e.g., drain-side selected gate SGD) 212. Each source select device 210 is located at the intersection of string 206 and source select line 214, and each drain select device 212 is located at the intersection of string 206 and drain select line 215. Select devices 210 and 212 can be any suitable access device, and are used... Figure 4 The boxes in the text generally illustrate this.

[0011] The source of each source select device 210 is connected to a common source line 216. The drain of each source select device 210 is connected to the source of the first charge storage transistor 208 of the corresponding NAND string 206. For example, the drain of source select device 2101 is connected to the source of the charge storage transistor 2081 of the corresponding NAND string 2061. The source select device 210 is connected to the source select line 214.

[0012] The drain of each drain selector 212 is connected to the bit line (i.e., digital line) 228 at its drain contact. For example, the drain of drain selector 2121 is connected to bit line 2281. The source of each drain selector 212 is connected to the drain of the first charge storage transistor 208 of the corresponding NAND string 206. For example, the source of drain selector 2121 is connected to the charge storage transistor 208 of the corresponding NAND string 2061. N The drain electrode.

[0013] The charge storage transistor 208 includes a source 230, a drain 232, a charge storage region 234, and a control gate 236. The control gate 236 of the charge storage transistor 208 is coupled to a word line 202. Columns of the charge storage transistor 208 are those transistors coupled to a given positioning line 228 within a NAND string 206. Rows of the charge storage transistor 208 are those transistors typically coupled to a given word line 202.

[0014] Block erasure of vertically stacked memory cells in a three-dimensional NAND architecture can be performed by generating hole carriers below them and then using an electric field to sweep the hole carriers upward along the memory cells.

[0015] A gate-controlled structure of a transistor can be used to provide gate-induced drain leakage (GIDL), which generates holes for block erasure of memory cells. The transistor can be a source-side selected (SGS) device as described above. The channel material associated with the memory cell string can be configured as channel material pillars, and regions of such pillars can be gated and coupled to the SGS device. The gatedly coupled portion of the channel material pillar is the portion overlapping the gate of the SGS device.

[0016] It is desirable that at least some of the gated coupling portions of the heavily doped channel material be used. In some applications, it is desirable that the gated coupling portions comprise both a heavily doped lower region and a lightly doped upper region; wherein both regions overlap with the gate of the SGS device. Specifically, overlapping with the lightly doped region provides the SGS device with non-drain "off" characteristics, and overlapping with the heavily doped region provides the SGS device with drain GIDL characteristics. The terms "heavily doped" and "lightly doped" are used relative to each other rather than relative to a particular conventional meaning. Thus, a "heavily doped" region is more heavily doped than the adjacent "lightly doped" region and may or may not include heavy doping in the conventional sense. Similarly, a "lightly doped" region is less doped than the adjacent "heavily doped" region and may or may not include light doping in the conventional sense. In some applications, the term "lightly doped" refers to having a doping density of less than or equal to about 10. 18 Semiconductor materials with dopant concentrations of 10 atoms per cubic centimeter, and the term "heavily doped" refers to semiconductor materials with dopant concentrations greater than or equal to about 10 atoms per cubic centimeter. 22 Semiconductor materials with dopants of 1 atom / cubic centimeter.

[0017] The channel material can be initially doped to a light doping level, and then a heavily doped region can be formed by diffusion from the bottom doped semiconductor material outward.

[0018] There is a desire to develop improved methods for forming integrated memories (e.g., NAND memory). There is also a desire to develop improved memory devices. Summary of the Invention

[0019] On one hand, this application provides an integrated assembly comprising: a memory region and another region adjacent to the memory region; a channel material pillar disposed in the memory region and a conductive pillar disposed in the other region; a source structure coupled to a lower region of the channel material pillar; a panel extending across the memory region and the other region and separating a first memory block region from a second memory block region; a doped semiconductor material adjacent to the panel in the memory region and the other region; the doped semiconductor material being at least a portion of the source structure in the memory region; and a liner adjacent to and laterally surrounding the conductive pillar; the liner being between the conductive pillar and the doped semiconductor material.

[0020] On the other hand, this application further provides an integrated assembly comprising: a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions; a first channel material pillar disposed within the first memory region; a second channel material pillar disposed within the second memory region; a conductive pillar disposed within the intermediate region; a panel extending across the first memory region, the intermediate region, and the second memory region; the panel being laterally positioned between the first memory block region and the second memory block region; a doped semiconductor material disposed within and adjacent to the panel in the first memory region, the second memory region, and the intermediate region; the doped semiconductor material being at least a portion of a conductive electrode structure within the first and second memory regions; and an insulating ring laterally surrounding the conductive pillar and between the conductive pillar and the doped semiconductor material; the doped semiconductor material directly contacts the outer edge of the insulating ring, and the conductive pillar directly contacts the inner edge of the insulating ring.

[0021] In another aspect, this application further provides a method of forming an integrated assembly, comprising: forming a configuration including a first memory region, a second memory region laterally offset from the first memory region, and an intermediate region laterally located between the first and second memory regions; the configuration comprising a first stack extending across the first memory region, the second memory region, and the intermediate region; the first stack comprising alternating semiconductor-containing regions and intermediate regions; at least three of the semiconductor-containing regions being present, wherein one of the semiconductor-containing regions is a central semiconductor-containing region and is vertically located between the other two semiconductor-containing regions; the configuration further comprising a second stack extending across the first memory region, the second memory region, and the intermediate region, wherein the second stack is above the first stack; the second stack comprising alternating first and second levels, wherein the first level comprises a sacrificial material, and the second level comprises an insulating material; forming pillars extending through the second stack and at least partially into the first stack of the first and second memory regions, the pillars comprising cell material and channel material; forming extending through... The process involves: passing through the second stack in the intermediate region and at least partially entering the protected conductive pillar of the first stack; the protected conductive pillar having a protective material of conductive material laterally surrounding the conductive pillar; forming a slit opening through the second stack to reach the central semiconductor material region of the first stack; the slit opening extending across the first memory region, the intermediate region, and the second memory region; removing the central semiconductor material region from the first memory region, the intermediate region, and the second memory region using one or more etchants flowing into the slit opening, the protective material being resistant to the one or more etchants; the removal of the central semiconductor material region forming a conduit in the first stack within the first and second memory regions; extending the conduit through the cell material and reaching the channel material of the pillar; forming a doped semiconductor material within the extended conduit; diffusing a dopant outward from the doped semiconductor material into the channel material, the outwardly diffused dopant extending upward to at least one of the first layers; and replacing at least some of the sacrificial materials of the first layers with a conductive material. Attached Figure Description

[0022] Figure 1 A block diagram of a prior art memory device with a memory array having memory cells is shown.

[0023] Figure 2 Shown in the form of a 3D NAND memory device Figure 1 A schematic diagram of a prior art memory device.

[0024] Figure 3 Showing along the X-X' direction Figure 2 A cross-sectional view of a prior art 3D NAND memory device.

[0025] Figure 4 This is a schematic diagram of a conventional NAND memory array.

[0026] Figure 5-5B This is a schematic top view of a region of the instance integrated assembly during the instance processing stage of an instance embodiment method for forming an instance memory device. Figure 5 ) and a pair of schematic cross-sectional side views ( Figure 5A and 5B ). Figure 5A and 5B The cross-sectional side views are respectively along Figure 5 Lines AA and BB. Figure 5 Top view along Figure 5A and 5B The line CC.

[0027] Figure 6A and 6B Is Figure 5-5B The instance processing phase after the instance processing phase Figure 5-5B A schematic cross-sectional side view of the area of ​​an example integrated assembly. Figure 6A and 6B The cross-sectional side views are respectively along with Figure 5A and 5B Same cross-section.

[0028] Figure 7A and 7B Is Figure 6A and 6B The instance processing phase after the instance processing phase Figure 5-5B A schematic cross-sectional side view of the area of ​​an example integrated assembly. Figure 7A and 7B The cross-sectional side views are respectively along with Figure 5A and 5B Same cross-section.

[0029] Figure 8A and 8B Is Figure 7A and 7B The instance processing phase after the instance processing phase Figure 5-5B A schematic cross-sectional side view of the area of ​​an example integrated assembly. Figure 8A and 8B The cross-sectional side views are respectively along with Figure 5A and 5B Same cross-section.

[0030] Figure 9A and9B Is Figure 8A and 8B The instance processing phase after the instance processing phase Figure 5-5B A schematic cross-sectional side view of the area of ​​an example integrated assembly. Figure 9A and 9B The cross-sectional side views are respectively along with Figure 5A and 5B Same cross-section.

[0031] Figure 10A and 10B Is Figure 9A and 9B The instance processing phase after the instance processing phase Figure 5-5B A schematic cross-sectional side view of the area of ​​an example integrated assembly. Figure 10A and 10B The cross-sectional side views are respectively along with Figure 5A and 5B Same cross-section.

[0032] Figure 11A and 11B Is Figure 10A and 10B The instance processing phase after the instance processing phase Figure 5-5B A schematic cross-sectional side view of the area of ​​an example integrated assembly. Figure 11A and 11B The cross-sectional side views are respectively along with Figure 5A and 5B Same cross-section.

[0033] Figure 12A and 12B yes Figure 11A and 11B A schematic cross-sectional side view of a region of an example integrated assembly, and showing the components of such an assembly, excluding... Figure 11A and 11B Additional vertical extension areas beyond those shown in the diagram. Figure 12A-1 And 12A-2 is relative to Figure 12A Alternative instances of the processing phase shown at the processing phase Figure 12A A schematic cross-sectional side view of the area.

[0034] Figure 12C yes Figure 12A and 12B A schematic top view of the assembly. Figure 12A and 12B The cross-sectional side views are respectively along Figure 12C Lines AA and BB. Figure 12C Top view along Figure 12A and12B The line CC. Figure 12C-1 In relation to Figure 12C Alternative instance processing phases and their counterparts in the instance processing phase. Figure 12A-1 The same processing stage is shown Figure 12C A schematic cross-sectional top view of the area. Figure 12C-1 The view along Figure 12A-1 The line CC, and Figure 12A-1 The view along Figure 12C-1 Line AA. Detailed Implementation

[0035] Some embodiments include using an insulating protective material to protect the conductive pillars during etching of the material associated with the integrated assembly. Some embodiments include the integrated assembly having an insulating protective material laterally surrounding the conductive pillars. Example Embodiment Reference Figure 5-1 2. Description.

[0036] Figure 5 A top view is shown along several instance regions of the instance integrated assembly 10. The illustrated region of assembly 10 includes a pair of memory regions (memory array regions) 12a and 12b (array-1 and array-2), and includes an intermediate region 14 located between the memory regions. In some embodiments, memory regions 12a and 12b may be referred to as a first region laterally displaced (laterally offset) relative to each other, and intermediate region 14 may be referred to as another region (or a second region) located between the laterally displaced (laterally offset) first regions.

[0037] Unit material pillars 16 are arranged within memory regions 12a and 12b. Pillars 16 may be substantially identical to each other, where "substantially identical" means identical within reasonable manufacturing and measurement tolerances. Pillars 16 may be compactly arranged within each of memory regions 12a and 12b, for example, in a hexagonal close-packed (HCP) arrangement. Hundreds, thousands, millions, hundreds of thousands, etc., of pillars 16 may be arranged within each of memory regions 12a and 12b.

[0038] Each of the pillars 16 includes an outer region 18 containing memory cell material, a channel material 20 adjacent to the outer region 18, and an insulating material 22 surrounded by the channel material 20.

[0039] The cell material within region 18 may include tunneling materials, charge storage materials, and charge blocking materials. The tunneling material (also referred to as the gate dielectric material) may include any suitable composition; and in some embodiments, it may include one or more of silicon dioxide, alumina, hafnium oxide, zirconium oxide, etc. The charge storage material may include any suitable composition; and in some embodiments, it may include a floating gate material (e.g., polycrystalline silicon) or a charge trapping material (e.g., one or more of silicon nitride, silicon oxynitride, conductive nanodots, etc.). The charge blocking material may include any suitable composition; and in some embodiments, it may include one or more of silicon dioxide, alumina, hafnium oxide, zirconium oxide, etc.

[0040] The channel material 20 includes a semiconductor material. The semiconductor material may include any suitable composition; and in some embodiments, it may include one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc., substantially composed of one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc., or composed of one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc.; wherein the term III / V semiconductor material refers to a semiconductor material comprising elements selected from Groups III and V of the periodic table (where Groups III and V are older nomenclature and are now referred to as Groups 13 and 15). In some embodiments, the semiconductor material may include suitably doped silicon, substantially composed of suitably doped silicon, or composed of suitably doped silicon.

[0041] The channel material 20 can be considered as configured as channel material pillars 24. In the illustrated embodiment, the channel material pillars 24 are... Figure 5 In a top view, the channel material pillars are configured as rings, with such rings surrounding the insulating material 22. This configuration of the channel material pillars can be considered as corresponding to a “hollow” channel configuration, where the insulating material 22 is disposed within the hollow body of the channel material pillar. In other embodiments, the channel material 22 may be configured as a solid pillar. In some embodiments, the channel material pillars within memory region 12a may be referred to as first channel material pillars, and the channel material pillars within memory region 12b may be referred to as second channel material pillars. The channel material pillars may be arranged in any suitable configuration within the first memory region 12a and the second memory region 12b. In some embodiments, the channel material pillars may be arranged in a compact configuration, such as a hexagonal close-packed (HCP) configuration.

[0042] The insulating material 22 may include any suitable composition; and in some embodiments, it may include silicon dioxide, be substantially composed of silicon dioxide, or be composed of silicon dioxide.

[0043] Posts 26 are arranged within the intermediate zone 14. Each of the described posts 26 comprises conductive material 28 transversely surrounded by an insulating liner 30. Posts 26 can be arranged in any suitable configuration, and their size and composition may be the same or different from each other.

[0044] The conductive material 28 may include any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). In some embodiments, the conductive material 28 may include one or more of tungsten, titanium nitride, and tungsten nitride. For example, the conductive material 28 may include a conductive liner and may include tungsten filler laterally surrounded by the conductive liner, which includes one or both of titanium nitride and tungsten nitride along the insulating liner 30.

[0045] The insulating material 30 is configured as an insulating ring (or insulating liner) 31 surrounding the conductive post.

[0046] In some embodiments, material 30 may be referred to as a protective material because it is resistant to etching conditions (example etching conditions are described below with reference to Figures 7 and 8). Material 30 may comprise any suitable composition. In some embodiments, material 30 may comprise one or more of doped silicon oxide, doped silicon nitride, silicon oxynitride, and carbon. For example, material 30 may comprise carbon-doped silicon oxide (e.g., silicon dioxide), substantially composed of carbon-doped silicon oxide (e.g., silicon dioxide), or composed of carbon-doped silicon oxide (e.g., silicon dioxide); wherein the carbon concentration is about 10. 15 From one atom per cubic centimeter to about 10 25 In the range of atoms per cubic centimeter. As another example, material 30 may comprise carbon-doped silicon nitride, substantially composed of carbon-doped silicon nitride, or composed of carbon-doped silicon nitride; wherein the carbon concentration is in the range of about 10. 15 From one atom per cubic centimeter to about 10 25 In the range of atoms per cubic centimeter. As another example, material 30 may include SiON, be substantially composed of SiON, or be composed of SiON, wherein this chemical formula indicates the major component rather than a specific stoichiometry. In some embodiments, SiON may be referred to as silicon oxynitride. The concentrations of Si and O present may range from about 20 atomic percent (at%) to about 70 at%, and the concentration of nitrogen present may range from about 0.01 at% to about 35 at%, within the range of about 10 15 From one atom per cubic centimeter to about 10 25Within the range of atoms per cubic centimeter, etc. As another example, material 30 may include carbon, be substantially composed of carbon, or be composed of carbon. Carbon may be in any suitable form and, in some embodiments, may be entirely amorphous, or at least substantially entirely amorphous, wherein the term “substantially entirely amorphous” means entirely amorphous within reasonable manufacturing and measurement tolerances.

[0047] In the illustrated embodiment, the protective material 30 is immediately adjacent to the conductive material 28 of the pillar 26. In other embodiments, the protective material 30 may be spaced apart from the conductive material 28 of the pillar 26 by one or more intermediate buffer materials (e.g., silicon dioxide). Figure 5 The diagram is shown as including only a single homogeneous component. In other embodiments (see below) Figure 12A-1 (as described in 12C-1), the protective material 30 may include a laminate of two or more different compositions.

[0048] In some embodiments, the conductive material 28 of the pillar 26 may be considered as configured as a conductive pillar 32. Such a conductive pillar may be "live" and therefore can be used as an electrical interconnect. Alternatively, the pillar may be "dummy" and may be used solely to provide structural support.

[0049] Hundreds, thousands, or millions of columns 26 can be set within the central area 14.

[0050] Intermediate region 14 may include numerous regions associated with the integrated memory, including, for example, stepped regions, peak regions, bridging regions, etc. If the conductive pillar 32 is energized, such pillars can be used to interconnect components associated with memory regions 12a and 12b to the circuitry below the illustrated regions of the integrated assembly 10. For example, conductive pillars can be used to connect bit lines to sensing circuitry (e.g., sensing amplifier circuitry), to connect SGD devices to control circuitry, etc.

[0051] Figure 5 The conductive post 32 can be referred to as a "protected conductive post" because such a post is protected by a protective material 30 of a conductive material 28 that surrounds the post laterally.

[0052] The slit opening orientation is 38 degrees. Figure 5 The slit opening is schematically shown in the diagram using dashed lines. The orientation 38 of the slit opening extends along the indicated y-axis.

[0053] Figure 5A and 5B Cross-sectional side views of the intermediate region 14 and the memory region 12a are shown respectively. Figure 5A The view along Figure 5 Line AA, and Figure 5B The view along Figure 5BB line. Figure 5 The view along Figure 5A and 5B The line CC. Figure 5A and 5B The view is schematically illustrated. Figure 5 The instance structure shown in the top view, but not with Figure 5 Provide the same proportion.

[0054] Figure 5A and 5B An example configuration is shown in which insulating material 50 forms a support structure for stacking 52.

[0055] The insulating material 50 may include any suitable composition, and in some embodiments may include silicon dioxide, consisting essentially of silicon dioxide, or composed of silicon dioxide.

[0056] In the illustrated embodiment, the conductive structure 54 is located within the insulating material 50. The conductive structure 54 may include any suitable conductive material; such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.) and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.).

[0057] One or more of the conductive structures 54 may be coupled to a logic circuit system (e.g., CMOS) disposed beneath the insulating material 50. Figure 5A A logic circuit system is shown, which may include components 56a and 56b corresponding to, for example, a control circuit system and / or a sensing circuit system (e.g., a sense amplifier circuit system, a driver circuit system, etc.). Figure 5B A logic circuit system is shown configured to include a component 56c (e.g., a control circuit system) coupled to a source structure including stack 52.

[0058] The logic circuit system 56 may be supported by a semiconductor material (not shown). Such semiconductor materials may include, for example, monocrystalline silicon (Si), consist essentially of monocrystalline silicon (Si), or consist entirely of monocrystalline silicon (Si). The semiconductor material may be referred to as a semiconductor substrate or a semiconductor base. The term "semiconductor substrate" means any construction that includes semiconductor material, including but not limited to bulk semiconductor material, such as a semiconductor wafer (alone or in a combination including other materials), and a layer of semiconductor material (alone or in a combination including other materials). The term "substrate" refers to any support structure that includes (but is not limited to) the semiconductor substrate described above. The configuration described herein may be referred to as an integrated configuration supported by a semiconductor substrate and therefore may be considered as an integrated assembly.

[0059] Stack 52 can be referred to as the first stack and can be considered as a cross-stack. Figure 5 The memory regions (12a and 12b) and intermediate region (14) extend from each other. The stack 52 contains conductive material 58 and includes regions 60 and 62 above the conductive material 58. Region 60 may be referred to as a semiconductor material-containing region.

[0060] Conductive material 58 is configured as island 40 in the intermediate region 14, such as Figure 5A As shown in the diagram. These islands are laterally spaced from each other by an insulating material 42. The insulating material 42 may include any suitable composition, and in some embodiments may include silicon dioxide, be substantially composed of silicon dioxide, or be composed of silicon dioxide. The insulating material 42 may or may not have the same composition as the insulating material 50.

[0061] In the illustrated embodiment, three regions are present in region 60, and these regions are labeled 60a, 60b, and 60c. Regions 60a and 60c contain semiconductor material 64. Such semiconductor material may include conductive doped semiconductor material, such as conductive doped silicon. In some embodiments, the silicon may be n-type doped, and therefore may be doped with one or both of phosphorus and arsenic. The conductive doped silicon in regions 60a and 60c may be doped to at least about 10⁻⁶ using one or more suitable conductivity-enhancing dopants. 22 The concentration is atoms per cubic centimeter. The semiconductor material in region 60a may be the same as the semiconductor material in region 60c, as shown, or may be different from the semiconductor material in region 60c.

[0062] Central region 60b includes material 34. Material 34 may include undoped semiconductor material, such as undoped silicon. The term "undoped" does not necessarily mean that there are absolutely no dopants present in the semiconductor material, but rather that the amount of any dopants present in such semiconductor material is generally understood to be negligible. For example, depending on the context, undoped silicon can be understood to include less than about 10 16 atoms per cubic centimeter, less than approximately 10 15 The dopant concentration is expressed as atoms per cubic centimeter, etc. In some embodiments, material 34 may comprise silicon, be substantially composed of silicon, or be composed of silicon. In some embodiments, material 34 is a sacrificial material (as referenced below). Figure 7B The processing described is discussed in more detail, so material 34 may include any suitable sacrificial material, including but not limited to undoped semiconductor materials (e.g., undoped silicon).

[0063] Regions 60a-c can be considered as vertically stacked on top of each other, wherein region 60b is a central region containing semiconductor material (in some embodiments) and is vertically located between regions 60a and 60c.

[0064] Intermediate region 62 alternates with region 60 within stack 52. Region 62 includes material 66. Material 66 may be insulating, conductive, etc. In some embodiments, material 66 may be insulating and may include one or more of silicon dioxide, aluminum oxide, hafnium oxide, silicon nitride, silicon oxynitride, etc., substantially composed of one or more of silicon dioxide, aluminum oxide, hafnium oxide, silicon nitride, silicon oxynitride, etc., or composed of one or more of silicon dioxide, aluminum oxide, hafnium oxide, silicon nitride, silicon oxynitride, etc. Regions 62a and 62b may include the same composition as each other (as shown), or may include compositions different from each other. One or both of regions 62 may include a homogeneous composition (as shown) or may include a laminate of two or more different compositions.

[0065] Although stack 52 is shown as including three of regions 60 (which may be regions containing semiconductor material) and two of intermediate regions 62, it should be understood that the stack may include any suitable number of regions 60 and 62. In some embodiments, stack 52 may include at least three of regions 60 and at least two of intermediate regions 62.

[0066] Region 60 can be formed to any suitable thickness, and in some embodiments, it can be formed to a thickness ranging from about 100 nanometers (nm) to about 300 nm. Region 62 can be formed to any suitable thickness, and in some embodiments, it can be formed to a thickness ranging from about 5 nm to about 20 nm.

[0067] A second stack 68 is formed over a first stack 52. The second stack 68 has alternating first levels 70 and second levels 72. The first level 70 includes material 74, and the second level 72 includes material 76. Materials 74 and 76 may include any suitable composition. In some embodiments, material 74 may include silicon nitride, and is substantially composed of silicon nitride or is composed of silicon nitride; and material 76 may include silicon dioxide, and is substantially composed of silicon dioxide or is composed of silicon dioxide. Material 74 may be referred to as a sacrificial material, and material 76 may be referred to as an insulating material.

[0068] Stacks 52 and 68 can be considered together as part of construction 78. In the illustrated embodiment, such a construction also includes islands 40, some of which are connected to... Figure 5A The CMOS circuit system 56 is coupled in the embodiment shown.

[0069] Pillar 26 is formed to extend through the first stack 68, through regions 60 and 62 of the second stack 52, and to reach the conductive material 58. Pillar 26 includes conductive pillars 32, and in the illustrated embodiment, such conductive pillars are electrically coupled to conductive islands 40 including the conductive material 58. In embodiments where the conductive pillars 32 are “charged” pillars, the conductive pillars 32 may be coupled to the CMOS circuit system 56. Alternatively, in embodiments where at least some of the conductive pillars are “dummy” configurations for structural support rather than for electrical connection, at least some of the conductive pillars 32 may not be coupled to the CMOS circuit system.

[0070] In the illustrated embodiment, each of the islands 40 supports one of the conductive pillars 32. In other embodiments, at least one of the islands 40 may support two or more of the conductive pillars.

[0071] Cell material pillars 16 are formed to extend through the first stack 68 and partially into the second stack 52, as shown in 5B. In the illustrated embodiment, cell material pillars 16 extend into the lower region 60a of the stack 52 but not into the conductive material 58. Cell material pillars 16 include cell material 18, channel material pillars 24, and dielectric material 22. In some embodiments, memory regions 12a and 12b (containing Figure 5B The fragment of stack 52 within the area shown can be considered to correspond to the above reference. Figure 1-4 The source structure is similar to the source structure described in the existing technology.

[0072] Figure 5A and 5B A slit opening 82 is shown formed along the slit opening orientation 38. The slit opening passes through the first stack 68 and enters into the second stack 52. In the illustrated embodiment, the slit opening terminates on the material 34. In other embodiments, the slit opening may extend into the material 34.

[0073] In the illustrated embodiment, the slit opening has a substantially vertical sidewall surface; wherein the term "substantially vertical" means vertically straight within reasonable manufacturing and measurement tolerances. In other embodiments, the sidewall surface of the slit opening may be tapered.

[0074] A protective material 84 is formed within the slit opening 82 and along the sidewall surface of the slit opening. The protective material 84 may include any suitable composition. In some embodiments, the protective material 84 may include silicon, be substantially composed of silicon, or be composed of silicon; and specifically may include virtually undoped material (e.g., including an inherent dopant concentration, and in some embodiments, including less than or equal to about 10). 16Silicon with a dopant concentration of atoms per cubic centimeter. In some embodiments, the protective material 84 may include one or more of the following: metals (e.g., tungsten, titanium, etc.), metal-containing materials (e.g., metal silicides, metal nitrides, metal carbides, metal borides, etc.), and semiconductor materials (e.g., silicon, germanium, etc.).

[0075] Figure 5A and 5B The area shown in assembly 10 may be the lower part of the assembly, and it should be understood that the assembly may include... Figure 5A and 5B The layer shown is 68, which is a stack of more layers.

[0076] refer to Figure 6A and 6B One or more etchings are used to penetrate the protective material 84 at the bottom of the slit opening 82 to expose the central semiconductor material region 60b of the first stack 52. The slit opening 82 spans... Figure 5 The memory area and intermediate area (areas 12a, 12b and 14) extend. Therefore, removing the protective material 84 from the bottom of the slit opening 82 exposes the memory area (e.g., Figure 6B Within memory area 12a) and intermediate area 14 Figure 6A Material 34 within )

[0077] refer to Figure 7A and 7B The sacrificial material 34 in the central region 60b is removed to form a conduit 86 in regions 12a, 12b and 14 (where regions 12a and 14 are in Figure 7B and 7A (as shown in the image).

[0078] The conduit 86 can be formed using any suitable process, and in some embodiments, it can be formed using one or more etchants containing hydrofluoric acid. In the illustrated embodiment, intermediate regions 62a and 62b are retained after the conduit 86 is formed. In other embodiments, depending on the composition of the intermediate regions and the composition of the etchant used to remove material 34, such intermediate regions can be removed during conduit formation.

[0079] Figure 7A The protective material 30 is shown to be resistant to the etchant used to form the conduit 86. In some embodiments, the material 34 exposed within the slit 82 may be considered to be selectively removed relative to the protective material 30. For the purposes of interpreting this disclosure and the appended claims, if the first material is removed faster than the second material, then the first material is considered to be selectively removed relative to the second material; this may include, but is not limited to, a condition where the first material is 100% selective relative to the second material.

[0080] refer to Figure 8BThe conduit 86 extends through the unit material 18 to expose the sidewall surface of the semiconductor material (channel material) 20. Figure 8A This demonstrates that no significant changes occur within the intermediate region 14 during the extension of the conduit 86 through the unit material 18. In other words, the protective material 30 is resistant to etching used to extend the conduit 86 through the unit material 18.

[0081] refer to Figure 9A and 9B The conductive doped semiconductor material 88 is formed inside the conduit 86. Figure 8A and 8B Semiconductor material 88 may include any suitable composition; and in some embodiments, it may include one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc., substantially composed of one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc., or composed of one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc. In some embodiments, semiconductor material 88 may include heavily doped (e.g., doped to at least about 10) an n-type dopant (e.g., doped to at least about 10). 22 Silicon with a concentration of (atoms per cubic centimeter). Conductive material 88 can be considered as a source structure assembly 90 configured to be coupled to the lower region of the channel material pillar 24. In some embodiments, Figure 9B The material within the first stack 52 can all be considered as part of the conductive electrode structure 43. This can be achieved in the formation of... Figure 7A and 7B During catheter 86, areas 62a and 62b were removed (as referenced above). Figure 7A and 7B (as discussed), such that these regions are not part of the source structure including stack 52. In some embodiments, regions 62a and 62b may be conductive so as not to adversely affect the conductivity along the source structure including stack 52, or may be insulating and kept thin enough so as not to problematically affect the conductivity along the source structure including stack 52.

[0082] Material 88 becomes memory regions 12a and 12a and 12b (in Figure 9B The central area 60b of the stack 52 within area 12a) is shown.

[0083] In the illustrated embodiment, the doped semiconductor material 88 directly contacts the channel material 20 of the channel material pillar 24.

[0084] refer to Figure 10A and 10BMaterials 84 and 88 are removed from the opening (slit) 82 by one or more suitable etching processes. The material can be removed using any suitable etchant. The slit opening 82 can be stamped to any suitable depth within the source structure 43.

[0085] The dopant diffuses outward from the conductive doped semiconductor material 88 into the semiconductor material (channel material) 20 to form a heavily doped region 92 in the lower portion of the channel material pillar 24. The approximate upper boundary of the dopant within the heavily doped region 92 is indicated by line 93.

[0086] Outward diffusion from the doped material 88 to the semiconductor material 20 can be achieved by any suitable process, including, for example, suitable heat treatment (e.g., heat treatment at a temperature exceeding about 300°C for a duration of at least about two minutes).

[0087] Remove 74 sacrificial materials from Tier 1 (70). Figure 9A and 9B And replaced with conductive material 94. Although conductive material 94 is shown as completely filling the first layer 70, in other embodiments, at least some of the materials disposed within the first layer 70 may be insulating materials (e.g., dielectric barrier materials).

[0088] The conductive material 94 may include a suitable composition; and in some embodiments, it may include a tungsten core at least partially surrounded by titanium nitride. The dielectric barrier material may include any suitable composition; and in some embodiments, it may include one or more of alumina, hafnium oxide, zirconium oxide, etc.

[0089] Figure 10A and 10B The first layer 70 is a conductive layer, and the stack 68 can be considered as including alternating insulating layers (intermediate layers) 72 and conductive layers 70.

[0090] refer to Figure 11A and 11B Panel material 96 is formed within the slit opening 82. Panel material 96 may include any suitable composition; and in some embodiments, it may include silicon dioxide, be substantially composed of silicon dioxide, or be composed of silicon dioxide. Although panel material 96 is shown as a single homogeneous composition, in other embodiments, panel material may include a laminate of two or more different compositions.

[0091] Panel material 96 forms across memory regions (e.g., Figure 11B 12a) and the intermediate area ( Figure 11A The extended panel 98 of area 14)

[0092] Figure 11BThe assembly 10 can be considered as a memory device including memory cell 100 and select device (SGS device) 102. The lowermost part of conductive layer 70 is designated 70a and extends through doped region 92 to conductive layer 70a. Conductive layer 70a includes SGS device 102. In the illustrated embodiment, the dopant extends partially across layer 70a to achieve a desired balance between the non-drain "off" characteristics and drain GIDL characteristics of the SGS device.

[0093] Although only one of the conductive layers is shown as being incorporated into the SGS device, in other embodiments, multiple conductive layers may be incorporated into the SGS device. The conductive layers may be electrically coupled (joined together) to be incorporated into the long-channel SGS device. If multiple conductive layers are incorporated into the SGS device, then outwardly diffusing dopant may extend upward across two or more of the conductive layers 70 incorporated into the SGS device.

[0094] Memory cells 100 (e.g., NAND memory cells) are stacked vertically on top of each other. Each memory cell includes a region of semiconductor material (channel material) 20 and a region of conductive layer 70 (control gate region). Regions of conductive layer 70 not included in memory cell 100 can be considered as word line regions (routing regions) coupling the control gate region to driver circuitry and / or other suitable circuitry. Memory cell 100 includes cell material (e.g., tunneling material, charge storage material, and charge blocking material) within region 18.

[0095] In some embodiments, the conductive level 70 associated with memory cell 100 may be referred to as a word line / control gate level (or memory cell level) because it contains word lines and control gates associated with the vertically stacked memory cells of the NAND string. The NAND string may include any suitable number of memory cell levels. For example, a NAND string may have 8 memory cell levels, 16 memory cell levels, 32 memory cell levels, 64 memory cell levels, 512 memory cell levels, 1024 memory cell levels, etc.

[0096] Source structure 43 may be similar to source structure 216 described in the "Background Art" section. As shown, the source structure is shown coupled to a control circuitry system (e.g., CMOS) 56c. The control circuitry system may be located below the source structure (as shown) or in any other suitable orientation. The source structure may be coupled to the control circuitry system 56c at any suitable stage of processing.

[0097] In some embodiments, the channel material column 24 can be considered as representing the span Figure 11BThe memory region 12a extends from a plurality of substantially identical channel material pillars; wherein the term “substantially identical” means identical within reasonable tolerances for manufacture and measurement. Panel 98 may divide the pillars between a first block 104 and a second block 106. Thus, a memory cell 100 on one side of panel 98 may be considered to be within the first block 104, and a memory cell 100 on the other side of panel 98 may be considered to be within the second block 106. Blocks 104 and 106 may be analogous to the memory block (or memory sub-block) described above in the “Background” section of this disclosure.

[0098] Figure 12A and 12B Show Figure 11A and 11B The configuration is shown, and the individual structures (e.g., panel 98, conductive pillar 32, and unit material pillar 16) extend vertically and are coupled to additional circuit elements. Stack 68 may extend vertically to extend along a large portion of structures 98, 32, and 16.

[0099] Figure 12B The unit material column 16 extends upward to the bit line 108. The SGD device 110 is schematically illustrated as being adjacent to the upper region of the column 16 and below the bit line 108.

[0100] Bit line 108 can be relative to Figure 12B The cross-sectional view extends into and out of the page.

[0101] Column 16, bit line 108, SGD device 110, SGS device 102, and memory cell 100 can be considered together to form a structure similar to the one described above. Figure 1-4 The NAND type configurations described herein.

[0102] exist Figure 12B In the view, the SGD device 110 is indicated as coupled to the conductive post 32, and in Figure 12A In the view, conductive post 32 is indicated to be coupled to SGD device 110. Therefore, in some embodiments, SGD device 110 associated with memory region 12a can be coupled to logic circuitry (e.g., 56a and 56b) via conductive post 32 associated with intermediate region 14.

[0103] SGD device 110 is an example of a component that can be associated with cell material pillar 16 and coupled to a logic circuit system via conductive pillar 32. In other embodiments, as an alternative to or supplement to SGD device 110, other components may be coupled to the logic circuit system via one or more of the conductive pillars 32. For example, bit lines may be coupled to the logic circuit system via conductive pillar 32, and in such embodiments, the logic circuit system may include a sensing circuit system (e.g., a sensing amplifier circuit system) that couples the bit lines via conductive pillar 32. Typically, one or more components may be operatively located near cell material pillar 16 (and / or channel material pillar 24) and coupled to the logic circuit system 56 via conductive pillar 32.

[0104] Figure 12C Show along Figure 12A and 12B A top view of section CC. Panel 98 extends across memory regions 12a and 12b and across intermediate region 14. Panel 98 is laterally positioned between first memory block region 104 and second memory block region 106, and subdivides the first memory block region 104 and the second memory block region 106 (i.e., separates the first memory block region from the second memory block region).

[0105] In the illustrated embodiment, doped semiconductor material 88 is located adjacent to segments of panel 98 within intermediate region 14, memory region 12a, and memory region 12b. The doped semiconductor material 88 within memory regions 12a and 12b is adjacent to and electrically coupled to channel material pillars 24. In contrast, the doped semiconductor material 88 is not adjacent to conductive pillars 32, but rather has an insulating protective material 30 positioned between the doped semiconductor material 88 and the conductive pillars 32, preventing the conductive pillars from being electrically coupled to the doped semiconductor material 88. The insulating protective material 30 can extend along the conductive pillars to any suitable height and, for example, can extend the entire vertical height of the conductive pillars 32 (e.g., Figure 12A (as shown in the image).

[0106] Figure 12C The panel 98 shown may be one of a plurality of panels extending across regions 12a, 12b, and 14 and spacing the first and second memory block regions apart from each other. Accordingly, the memory block regions 104 and 106 shown may represent those that can be used to store memory blocks. Figure 12C The large number of memory blocks formed at the stage of the process.

[0107] exist Figure 12CIn the illustrated embodiment, the insulating material 30 is configured as an insulating ring 31 laterally surrounding the conductive post 32. The inner region of the ring 31 directly contacts the conductive post, and the outer edge of the ring 31 directly contacts the doped semiconductor material 88. In other embodiments, an additional material may be disposed between the protective material 30 and the conductive material of the conductive post. Such additional material may comprise an insulating liner, such as a liner comprising silicon dioxide, substantially silicon dioxide, or composed of silicon dioxide.

[0108] Protective material 30 may consist of only a single homogeneous material (e.g. Figure 12A and 12C As shown in the embodiments, it may include a layer of two or more different materials. For example, Figure 12A-1 Figure 12C-1 illustrates an example embodiment in which the protective material 30 is a laminate of two different compositions 30a and 30b, and correspondingly, the insulating ring 31 is a laminate of the two different compositions. Compositions 30a and 30b may include any of the compositions described above suitable for composition 30 (e.g., carbon-doped silicon dioxide, carbon-doped silicon nitride, amorphous carbon, silicon oxynitride, etc.).

[0109] In some embodiments, additional material may be located laterally outside the protective material 30, and may be present during the formation of the conduit 86. Figure 7B ) and / or during transverse etching through unit material 18 ( Figure 8B Etching. For example, Figure 12A-2 A configuration similar to that of Figure 12 is shown, but with an insulating material 120 outside the protective material 30. In some embodiments, the protective material 30 may be considered as an inner ring 31, and the material 120 may be considered as an outer ring 121 laterally surrounding the inner ring 31. In the illustrated embodiment, the doped material 88 passes through the outer ring 121 to directly contact the inner ring 31.

[0110] Material 120 may include any suitable material, and in some embodiments may include silicon dioxide, consisting essentially of silicon dioxide, or consisting of silicon dioxide.

[0111] Figure 12A-2 It is also shown that the conductive post 32 may have a lower region within the first stack 52, the lateral width of which differs from that of the upper region within the second stack 68 (and in the illustrated embodiment, the lower region is wider than the upper region). For example, if the lower region is patterned within the lower stack 52 before the upper region is patterned within the upper stack 68, then the lower region of the conductive post 32 may be formed to have a different lateral width than the upper region of the conductive post. In some embodiments, the lower region of the conductive post 32 may be patterned within the lower stack 52 before the upper stack 68 is formed.

[0112] The assemblies and structures discussed above can be used within integrated circuits (the term "integrated circuit" refers to electronic circuits supported by a semiconductor substrate) and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can comprise multi-layered, multi-chip modules. Electronic systems can be any of the following wide range of systems: for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, and so on.

[0113] Unless otherwise specified, the various materials, substances, compositions, etc. described herein can be formed by any suitable method now known or to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0114] The terms “dielectric” and “insulating” are used to describe materials having insulating electrical properties. These terms are considered synonymous in this disclosure. The term “dielectric” in some cases and the term “insulating” (or “electrically insulating”) in others may be used within this disclosure to provide linguistic variation to simplify the premises of the following claims, rather than to indicate any significant chemical or electrical differences.

[0115] The terms "electrical connection" and "electrical coupling" are both used in this disclosure. The terms are considered synonymous. The use of one term in some instances and another in others may be to provide linguistic variation within this disclosure to simplify the presuppositions in the appended claims.

[0116] The specific orientations of the various embodiments in the figures are for illustrative purposes only, and in some applications, embodiments may be rotated relative to the shown orientation. The descriptions provided herein and the following claims relate to any structure having the described relationships between various features, regardless of whether the structure is in a specific orientation of the figures or rotated relative to such an orientation.

[0117] Unless otherwise specified, the cross-sectional views in the accompanying drawings show only the features within the plane of the cross-section and do not show the material behind the plane of the cross-section in order to simplify the drawings.

[0118] When a structure is referred to as "on another structure," "adjacent to another structure," or "against another structure," the structure may be directly on the other structure or there may be an intervening structure. Conversely, when a structure is referred to as "directly on another structure," "directly adjacent to another structure," or "directly against another structure," there is no intervening structure. The terms "directly below," "directly above," etc., do not indicate direct physical contact (unless otherwise explicitly stated), but instead indicate upright alignment.

[0119] A structure (e.g., a layer, material, etc.) may be referred to as “vertically extending” to indicate that the structure generally extends upward from the underlying substrate (e.g., a base plate). A vertically extending structure may or may not extend substantially orthogonally to the upper surface of the substrate.

[0120] Some embodiments include an integrated assembly having a memory region and another region adjacent to the memory region. Channel material pillars are disposed within the memory region, and conductive pillars are disposed within the other region. A source structure is coupled to a lower region of the channel material pillars. A panel extends across the memory region and the other region, and spaces a first memory block region from a second memory block region. A doped semiconductor material is immediately adjacent to the panel within the memory region and the other region. The doped semiconductor material is at least a portion of the source structure within the memory region. A liner is immediately adjacent to and laterally surrounds the conductive pillars. The liner lies between the conductive pillars and the doped semiconductor material.

[0121] Some embodiments include an integrated assembly having a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions. First channel material pillars are disposed within the first memory region, and second channel material pillars are disposed within the second memory region. Conductive pillars are disposed within the intermediate region. A panel extends across the first memory region, the intermediate region, and the second memory region. The panel is laterally positioned between the first and second memory block regions. Doped semiconductor material is disposed within the first memory region, the second memory region, and the intermediate region, and is adjacent to the panel. The doped semiconductor material is at least a portion of the conductive electrode structure within the first and second memory regions. An insulating ring laterally surrounds the conductive pillars and is located between the conductive pillars and the doped semiconductor material. The doped semiconductor material directly contacts the outer edge of the insulating ring, and the conductive pillars directly contact the inner edge of the insulating ring.

[0122] Some embodiments include a method of forming an integrated assembly. A configuration is formed comprising a first memory region, a second memory region laterally offset from the first memory region, and an intermediate region laterally located between the first and second memory regions. The configuration includes a first stack extending across the first memory region, the second memory region, and the intermediate region. The first stack includes alternating semiconductor-containing regions and intermediate regions. At least three semiconductor-containing regions are present, wherein one of the semiconductor-containing regions is a central semiconductor-containing region and is vertically located between the other two semiconductor-containing regions. The configuration also includes a second stack extending across the first memory region, the second memory region, and the intermediate region, wherein the second stack is above the first stack. The second stack includes alternating first and second levels, wherein the first level includes a sacrificial material and the second level includes an insulating material. Pillars are formed extending through the second stack and at least partially into the first stack of the first and second memory regions. The pillars include cell material and channel material. Protected conductive pillars are formed extending through the intermediate region of the second stack and at least partially into the first stack. The protected conductive pillars have a protective material of conductive material laterally surrounding the conductive pillars. A slit opening is formed through the second stack to reach the central semiconductor-containing region of the first stack. A slit opening extends across a first memory region, an intermediate region, and a second memory region. A central semiconductor-containing region is removed from the first, intermediate, and second memory regions using one or more etchants flowing into the slit opening. A protective material is resistant to the one or more etchants. The removal of the central semiconductor-containing region forms a conduit in a first stack within the first and second memory regions. The conduit extends through the cell material and reaches the channel material of the pillar. A doped semiconductor material is formed within the extended conduit. A dopant is diffused outward from the doped semiconductor material into the channel material. The outwardly diffused dopant extends upward to at least one of the first layers. At least some of the sacrificial materials in the first layers are replaced with a conductive material.

[0123] As per the regulations, the subject matter disclosed herein has been described in more or less specific language regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes exemplary embodiments. Therefore, the claims have the full scope as stated in the writings and should be properly interpreted in accordance with the principle of equivalence.

Claims

1. An integrated assembly comprising: The memory area and another area adjacent to the memory area; Channel material pillars arranged in the memory region and conductive pillars arranged in the other region; A source structure coupled to the lower region of the channel material pillar; A panel that extends across the memory region and the other region, and separates the first memory block region from the second memory block region; A doped semiconductor material is disposed adjacent to the panel in the memory region and the other region; the doped semiconductor material is at least a portion of the source structure in the memory region; as well as A liner is located adjacent to and laterally surrounds the conductive post; the liner is between the conductive post and the doped semiconductor material.

2. The integrated assembly of claim 1, wherein the conductive post has a vertical height, and wherein the liner extends to the full vertical height of the conductive post.

3. The integrated assembly of claim 1, wherein at least some of the conductive pillars are coupled to a logic circuit system beneath the at least some of the conductive pillars.

4. The integrated assembly of claim 3, comprising an SGD device operably positioned close to the channel material post; and wherein the SGD device is coupled to the conductive post and, through the conductive post, to the logic circuit system.

5. The integrated assembly of claim 1, wherein the doped semiconductor material comprises silicon.

6. The integrated assembly of claim 1, wherein the lining comprises only a single homogeneous composition.

7. The integrated assembly of claim 1, wherein the liner comprises a laminate of two or more different compositions.

8. The integrated assembly of claim 1, wherein the liner comprises doped silicon oxide.

9. The integrated assembly of claim 1, wherein the liner comprises carbon-doped silicon oxide.

10. The integrated assembly according to claim 9, wherein the carbon concentration is about 10. 15 From one atom per cubic centimeter to about 10 25 Within the range of atoms per cubic centimeter.

11. The integrated assembly of claim 1, wherein the liner comprises doped silicon nitride.

12. The integrated assembly of claim 1, wherein the liner comprises carbon-doped silicon nitride.

13. The integrated assembly according to claim 12, wherein the carbon concentration is approximately 10. 15 From one atom per cubic centimeter to about 10 25 Within the range of atoms per cubic centimeter.

14. The integrated assembly of claim 1, wherein the lining comprises SiON, and wherein the chemical formula indicates the principal component rather than a specific stoichiometry.

15. The integrated assembly of claim 14, wherein the concentrations of silicon and oxygen are in the range of about 20 at% to about 70 at%.

16. The integrated assembly of claim 14, wherein the concentration of nitrogen is in the range of about 0.01 at% to about 35 at%.

17. The integrated assembly of claim 14, wherein the nitrogen concentration is approximately 10. 15 From one atom per cubic centimeter to about 10 25 Within the range of atoms per cubic centimeter.

18. The integrated assembly of claim 1, wherein the lining is substantially composed of carbon.

19. The integrated assembly of claim 18, wherein the carbon is substantially entirely in an amorphous phase.

20. The integrated assembly of claim 1, comprising a vertically stacked conductive hierarchy above the memory region and the other region; and wherein the channel material pillars and the conductive pillars extend through the vertically stacked conductive hierarchy.

21. The integrated assembly of claim 20, wherein the upper conductive layer in the vertically stacked conductive layers is a memory cell layer, and wherein the lower conductive layer in the vertically stacked conductive layers is a selection device layer.

22. An integrated assembly comprising: A first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions; A first channel material column is arranged within the first memory region; The second channel material column is arranged within the second memory region; Conductive pillars are arranged within the intermediate area; A panel that extends across the first memory region, the intermediate region, and the second memory region; the panel is laterally positioned between the first memory block region and the second memory block region; A doped semiconductor material is located within and adjacent to the panel in the first memory region, the second memory region, and the intermediate region; the doped semiconductor material is at least a portion of the conductive electrode structure in the first and second memory regions. as well as An insulating ring is laterally encircled by the conductive post and lies between the conductive post and the doped semiconductor material; the doped semiconductor material directly contacts the outer edge of the insulating ring, and the conductive post directly contacts the inner edge of the insulating ring.

23. The integrated assembly of claim 22, wherein the insulating ring comprises only a single homogeneous composition.

24. The integrated assembly of claim 22, wherein the insulating ring comprises a laminate of two or more different compositions.

25. The integrated assembly of claim 22, wherein the insulating ring comprises carbon-doped silicon oxide.

26. The integrated assembly of claim 22, wherein the insulating ring comprises carbon-doped silicon nitride.

27. The integrated assembly of claim 22, wherein the insulating ring comprises SiON, and wherein the chemical formula indicates the principal component rather than a specific stoichiometry.

28. The integrated assembly of claim 22, wherein the insulating ring is substantially composed of carbon.

29. The integrated assembly of claim 22, wherein the insulating ring is an inner ring and is laterally surrounded by an outer ring.

30. The integrated assembly of claim 29, wherein the doped semiconductor material passes through the outer ring and is in direct contact with the inner ring.

31. The integrated assembly of claim 30, wherein the outer ring comprises silicon dioxide.

32. The integrated assembly of claim 22, wherein the doped semiconductor material comprises silicon.

33. The integrated assembly of claim 22, wherein the component is operatively proximate to the channel material pillar and is also coupled to the conductive pillar, and wherein the conductive pillar is electrically coupled to a logic circuit system.

34. The integrated assembly of claim 33, wherein the component includes an SGD device.

35. A method for forming an integrated assembly, comprising: A configuration is formed comprising a first memory region, a second memory region laterally offset from the first memory region, and an intermediate region laterally located between the first and second memory regions; the configuration comprises a first stack extending across the first memory region, the second memory region, and the intermediate region; the first stack comprises alternating semiconductor-containing regions and intermediate regions; at least three semiconductor-containing regions are present, wherein one of the semiconductor-containing regions is a central semiconductor-containing region and is vertically located between the other two semiconductor-containing regions; the configuration further comprises a second stack extending across the first memory region, the second memory region, and the intermediate region, wherein the second stack is above the first stack; the second stack comprises alternating first and second levels, wherein the first level comprises a sacrificial material, and the second level comprises an insulating material; A pillar is formed that extends through the second stack of the first and second memory regions and at least partially enters the first stack of the first and second memory regions, the pillar comprising cell material and channel material; A second stack is formed that extends through the intermediate region and at least partially enters the first stack, with a protected conductive pillar having a protective material of conductive material laterally surrounding the pillar. A slit opening is formed to reach the central semiconductor material region of the first stack through the second stack; The slit opening extends across the first memory region, the intermediate region, and the second memory region; The central semiconductor material region is removed from the first memory region, the intermediate region, and the second memory region using one or more etchants flowing into the slit opening, wherein the protective material is resistant to the one or more etchants; the removal of the central semiconductor material region forms a conduit in the first stack within the first and second memory regions; The conduit extends through the unit material and reaches the channel material of the column; Doped semiconductor material is formed within the extended conduit; The dopant is diffused outward from the doped semiconductor material into the channel material, and the outwardly diffused dopant extends upward to at least one of the first layers; as well as Replace at least some of the sacrificial materials in the first layer with conductive materials.

36. The method of claim 35, wherein the protective material directly abuts against the conductive material of the conductive post.

37. The method of claim 35, further comprising forming a source selection device including at least one of the first layers.

38. The method of claim 35, wherein the protective material comprises only a single homogeneous composition.

39. The method of claim 35, wherein the protective material comprises a laminate of two or more different compositions.

40. The method of claim 35, wherein the protective material comprises carbon-doped silicon oxide.

41. The method of claim 35, wherein the protective material comprises carbon-doped silicon nitride.

42. The method of claim 35, wherein the protective material comprises SiON, and wherein the chemical formula indicates the main component rather than a specific stoichiometry.

43. The method of claim 35, wherein the protective material is composed of carbon.

Images