Three-dimensional memory structure, method of manufacturing the same, memory, and storage device

Abstract

The present disclosure relates to a three-dimensional memory structure, a manufacturing method thereof, a memory, and a storage device. The method includes sequentially forming a bottom dielectric layer, a metal silicide layer, and a top dielectric layer on a stack structure including a channel structure; forming an auxiliary channel structure penetrating through the top dielectric layer, the metal silicide layer, and the bottom dielectric layer, and electrically connecting the auxiliary channel structure with the channel structure; and forming a select gate isolation structure penetrating through the top dielectric layer and the metal silicide layer.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more specifically, to a three-dimensional storage structure and its manufacturing method, a memory, and a storage device. Background Technology

[0002] With the continuous development of semiconductor technology, people are constantly pursuing semiconductor devices with smaller size and higher performance.

[0003] Three-dimensional (3D) memory structures can achieve greater storage capacity in a smaller volume compared to 2D memories. However, semiconductor manufacturers are still pursuing 3D memory structures with even higher storage densities. In 3D memory structures, reducing the distance between memory strings can reduce the horizontal size of the structure. Traditional 3D memory structures can have, for example, nine rows of channels within a single memory block, densely packed to reduce the horizontal size. However, when these channels are divided into two groups, the top select gate isolation cutout has to destroy the middle row of channels, wasting a row and increasing the distance between the two groups of channels on either side. Those skilled in the art desire to reduce the horizontal size of 3D memory structures. Summary of the Invention

[0004] The embodiments disclosed herein can at least solve one or more of the technical problems in the prior art described above, or can be used to solve some other technical problems in the prior art.

[0005] Embodiments of this disclosure provide a method for manufacturing a three-dimensional memory structure, the method comprising: sequentially forming a bottom dielectric layer, a metal silicide layer, and a top dielectric layer on a stacked structure including a channel structure; forming an auxiliary channel structure penetrating the top dielectric layer, the metal silicide layer, and the bottom dielectric layer, and electrically connecting the auxiliary channel structure to the channel structure; and forming a select gate isolation structure penetrating the top dielectric layer and the metal silicide layer.

[0006] In some embodiments, the step of forming the metal silicide layer includes: sequentially forming a polysilicon layer and a metal layer on the bottom dielectric layer; performing an alloying reaction on the polysilicon layer and a portion of the metal layer to convert the polysilicon layer into the metal silicide layer; and removing any remaining metal layer.

[0007] In some embodiments, the method further includes doping the polycrystalline silicon layer.

[0008] In some embodiments, the step of forming the polysilicon layer includes: making the formed polysilicon layer a doped polysilicon layer by in-situ doping.

[0009] In some embodiments, the material of the metal layer includes nickel; and by controlling the temperature of the alloy reaction and the amount of nickel in the metal layer, the material of the metal silicide layer includes: Ni₂Si, Ni 31 Si 12 At least one of NiSi and NiSi2.

[0010] In some embodiments, prior to the step of forming the auxiliary channel structure, the method further includes: forming an auxiliary channel via, wherein the auxiliary channel via penetrates the top dielectric layer, the metal silicide layer, and the bottom dielectric layer; and wherein the step of forming the auxiliary channel structure includes: forming an auxiliary insulating layer in the auxiliary channel via and exposing the channel structure from the bottom of the auxiliary channel via; forming an auxiliary channel layer on the inner wall of the auxiliary insulating layer, wherein the auxiliary channel layer is connected to the channel structure.

[0011] In some embodiments, prior to forming the select gate isolation structure, the method further includes: forming a select gate isolation trench through the top dielectric layer and the metal silicide layer; and wherein the step of forming the select gate isolation structure includes: forming the select gate isolation structure in the select gate isolation trench.

[0012] In some implementations, the selective gate isolation groove has a wavy shape in a direction perpendicular to the stacking direction of the stacked structure to avoid adjacent auxiliary channel structures.

[0013] A second aspect of this disclosure also provides a method for manufacturing a three-dimensional memory structure, the method comprising: sequentially forming a bottom dielectric layer, a polysilicon layer, and a top dielectric layer on a stacked structure including a channel structure; converting the polysilicon layer into a metal silicide layer; forming an auxiliary channel structure extending from the top dielectric layer to the bottom dielectric layer, and electrically connecting the auxiliary channel structure to the channel structure; and forming a select gate isolation structure extending through the top dielectric layer and the metal silicide layer.

[0014] In some embodiments, after the step of forming the top dielectric layer and before the step of forming the auxiliary channel structure, the method further includes: forming an auxiliary channel via penetrating the top dielectric layer and the polysilicon layer; and wherein the step of converting the polysilicon layer into a metal silicide layer includes: forming a metal-filled structure in the auxiliary channel via and on the top dielectric layer; performing an alloying reaction on the polysilicon layer and the metal-filled structure to convert the polysilicon layer into the metal silicide layer and obtain a residual metal-filled structure; and removing the residual metal-filled structure.

[0015] In some embodiments, after the step of forming the top dielectric layer and before the step of forming the select gate isolation structure, the method further includes: forming a select gate isolation trench through the top dielectric layer and the polysilicon layer; and wherein the step of converting the polysilicon layer into a metal silicide layer includes: forming a metal-filled structure in the select gate isolation trench and on the top dielectric layer; performing an alloying reaction on the polysilicon layer and the metal-filled structure to convert the polysilicon layer into the metal silicide layer and obtain a residual metal-filled structure; and removing the residual metal-filled structure.

[0016] In some embodiments, the formation of the metal-filled structure, the alloying reaction, and the removal of the residual metal-filled structure are repeated cyclically to ensure that the polycrystalline silicon layer is completely transformed into the metal silicide layer.

[0017] In some embodiments, the material of the metal-filled structure includes nickel; and by controlling the temperature of the alloy reaction and the amount of nickel in the metal-filled structure, the material of the metal silicide layer includes: Ni₂Si, Ni 31 Si 12 At least one of NiSi and NiSi2.

[0018] In some embodiments, the method further includes doping the polycrystalline silicon layer.

[0019] In some embodiments, the step of forming the polysilicon layer includes: making the formed polysilicon layer a doped polysilicon layer by in-situ doping.

[0020] In some embodiments, prior to the step of forming the auxiliary channel structure, the method further includes: forming an auxiliary channel via penetrating the top dielectric layer, the metal silicide layer, and the bottom dielectric layer; and wherein the step of forming the auxiliary channel structure includes: forming an auxiliary insulating layer in the auxiliary channel via and exposing the channel structure from the bottom of the auxiliary channel via; forming an auxiliary channel layer on the inner wall of the auxiliary insulating layer, wherein the auxiliary channel layer is connected to the channel structure.

[0021] In some embodiments, prior to forming the select gate isolation structure, the method further includes: forming a select gate isolation trench through the top dielectric layer and the metal silicide layer; and wherein the step of forming the select gate isolation structure includes: forming the select gate isolation structure in the select gate isolation trench.

[0022] In some embodiments, the selective gate isolation groove has a wave-like shape in a direction perpendicular to the stacking direction of the stacked structure to bypass the adjacent auxiliary channel structure.

[0023] Thirdly, embodiments of this disclosure provide a three-dimensional memory structure, the three-dimensional memory structure comprising: a stacked structure including a channel structure; an auxiliary stacked structure including a bottom dielectric layer, a metal silicide layer and a top dielectric layer sequentially stacked on the stacked structure in the stacking direction of the stacked structure; an auxiliary channel structure penetrating the auxiliary stacked structure and electrically connected to the channel structure; and at least one select gate isolation structure, the select gate isolation structure penetrating the top dielectric layer and the metal silicide layer.

[0024] In some embodiments, the selective gate isolation structure has a wave-like shape to bypass the adjacent auxiliary channel structure.

[0025] In some embodiments, the material of the metal silicide layer includes: Ni2Si, Ni 31 Si 12 At least one of NiSi and NiSi2.

[0026] In some embodiments, the material of the metal silicide layer includes metal silicides and dopants.

[0027] In another aspect, embodiments of this disclosure provide a memory, including: the aforementioned three-dimensional storage structure; and peripheral circuitry electrically connected to the three-dimensional storage structure.

[0028] In another aspect, embodiments of this disclosure provide a storage device, including: the aforementioned three-dimensional memory; and a controller electrically connected to the three-dimensional storage structure and used to control the three-dimensional memory.

[0029] The three-dimensional storage structure provided by this disclosure includes an auxiliary channel structure above the main channel structure. Control of the main channel structure is achieved by controlling the auxiliary channel structure. The hierarchical structure of the auxiliary channel structure is simpler than that of the main channel structure, and the diameter of the auxiliary channel structure is smaller than that of the main channel structure, thus allowing for more flexible design space for the selection gate isolation structure between the auxiliary channel structures. The selection gate isolation structure does not disrupt the main channel structure, allowing more channels in a single stacked structure to perform storage functions, thereby increasing the storage density of the three-dimensional storage structure.

[0030] Using a metal silicide layer as the select gate allows for easier control of the select gate's performance, and the manufacturing process is relatively simple.

[0031] The method for manufacturing a three-dimensional memory structure provided by the embodiments of this disclosure has a relatively flexible process route, and the performance of the formed metal silicide layer is controllable. In the step of forming a select gate isolation structure between the auxiliary channel structures, the relatively loose spacing between the auxiliary channel structures makes the step of forming the select gate isolation structure easier and reduces damage to the channel structure. Attached Figure Description

[0032] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0033] Figure 1 This is a schematic structural diagram of a three-dimensional storage structure according to an embodiment of the present disclosure;

[0034] Figure 1A yes Figure 1 A magnified view of point A;

[0035] Figure 2 yes Figure 1 Top view;

[0036] Figure 3 This is a flowchart of a method for manufacturing a three-dimensional storage structure according to an embodiment of the present disclosure;

[0037] Figures 4 to 12 This is a process diagram based on an embodiment of the present disclosure;

[0038] Figure 13 This is a flowchart of a method for manufacturing a three-dimensional storage structure according to an embodiment of the present disclosure;

[0039] Figure 14 This is a flowchart of a method for manufacturing a three-dimensional storage structure according to another embodiment of the present disclosure;

[0040] Figures 15 to 20 This is a process diagram based on another embodiment of the present disclosure;

[0041] Figure 21 This is a flowchart of a method for manufacturing a three-dimensional storage structure according to yet another embodiment of the present disclosure;

[0042] Figures 22 to 31 This is a process diagram according to yet another embodiment of this disclosure;

[0043] Figure 32 This is a schematic diagram of a memory according to an embodiment of the present disclosure;

[0044] Figure 33 This is a schematic diagram of a storage device according to an embodiment of the present disclosure. Detailed Implementation

[0045] To better understand this disclosure, various aspects of this disclosure will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this disclosure and are not intended to limit the scope of this disclosure in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0046] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the feature.

[0047] In the accompanying drawings, the thickness, dimensions, and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. For example, the thickness of the bottom dielectric layer and the thickness of the metal silicide layer are not proportional to those used in actual production. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0048] It should also be understood that the terms "comprising," "including," "having," "containing," and / or "comprising," when used in this specification, indicate the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. Furthermore, when a statement such as "at least one of..." appears after a list of listed features, it modifies the entire list of features, not individual elements in the list. Additionally, when describing embodiments of this disclosure, the word "may" is used to mean "one or more embodiments of this disclosure." And the term "exemplary" is intended to refer to an example or illustration.

[0049] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that, unless expressly stated in this disclosure, terms as defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0050] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this disclosure are not limited to the order in which they are described, but can be performed in any order or in parallel. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0051] Figure 1 This is a schematic structural diagram of a three-dimensional storage structure according to an embodiment of the present disclosure. (Reference) Figure 1 The three-dimensional storage structure provided in this embodiment may include: a stacked structure 2, an auxiliary stacked structure 3, an auxiliary channel structure 4, and a selection gate isolation structure 5.

[0052] Exemplarily, the stacked structure 2 is disposed on the substrate 1. The substrate 1 may include stacked multilayers, and the material of the substrate 1 may include at least one of single-crystal silicon (Si), single-crystal germanium (Ge), III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. The stacked structure 2 includes an insulating layer 201 and a sacrificial layer 202 alternately stacked to form a stacked structure, and at least one channel structure 21 extending through the stacked structure. The channel structure 21 may extend into the substrate 1. Figure 1A As shown, the portion of the channel structure 21 corresponding to the sacrificial layer 202 may include, from the outside to the inside, a barrier layer 211, a charge storage layer 212, a tunneling layer 213, a channel layer 214, and an insulating core filling layer 215. Further, the channel structure 21 also includes a plug 216 located on its top and electrically connected to the channel layer 214. The top surface of the plug 216 can serve as a large conductive surface. The portion of the channel structure 21 corresponding to the sacrificial layer 202 can function as a storage cell, and one channel structure 21 serves as a storage string in the circuit.

[0053] The auxiliary stacked structure 3 includes the stacking direction of the stacked structure 2 ( Figure 1 The bottom dielectric layer 31, the metal silicide layer 32 and the top dielectric layer 33 are stacked sequentially on the vertical side of the stacked structure 2.

[0054] The auxiliary channel structure 4 penetrates the auxiliary laminate structure 3 and connects to the channel structure 21. Specifically, the auxiliary channel structure 4 can be connected to the plug 216 of the channel structure 21, thereby being electrically connected to the channel layer 214. The auxiliary channel structure 4 may include, in the horizontal direction, an auxiliary insulating layer 410, an auxiliary channel layer 420, and an auxiliary filler core 430 from the outside to the inside. The auxiliary channel structure 4 also includes an auxiliary plug 440 located on top of it and electrically connected to the auxiliary channel layer 420.

[0055] The metal silicide layer 32 can serve as a top control gate, and the auxiliary channel structure 4 can control the on / off state of the corresponding memory string. Specifically, the three-dimensional memory structure can include: a source electrically connected to the channel structure 21, and a bit line electrically connected to the auxiliary channel structure 4. The electrical signal between the source and the bit line needs to flow through the channel layer 214 of the channel structure 21 and the auxiliary channel layer 420 of the auxiliary channel structure 4. The metal silicide layer 32 can serve as a top control gate to transfer voltage to the auxiliary channel layer 420, causing the carriers in the auxiliary channel layer 420 to segregate into a channel suitable for conduction, thereby allowing the channel layer 214 and the bit line to be energized. If the metal silicide layer 32 does not transfer voltage, the material of the auxiliary channel layer 420 can ensure that the electrical connection between the channel layer 214 and the bit line is broken.

[0056] like Figure 1 and Figure 2 As shown, the selected gate isolation structure 5 penetrates the top dielectric layer 33 and the metal silicide layer 32 in the stacking direction of the stacked structure 2. Multiple selected gate isolation structures 5 divide the metal silicide layer 32 into electrically isolated blocks and divide multiple auxiliary channel structures 4 (i.e., multiple memory strings) into multiple groups, enabling the addressing of this three-dimensional memory structure during use. Exemplarily, the selected gate isolation structure 5 is located in a direction parallel to the stacked structure 2 (… Figure 2 The vertical extension of the channel structure 5 has a wave-like shape to bypass adjacent auxiliary channel structures 4. This selective gate isolation structure 5 allows for a more compact arrangement of multiple auxiliary channel structures 4 (channel structures 21), improving the storage density of the three-dimensional storage structure.

[0057] For example, substrate 1 may include peripheral circuitry (not shown); or substrate 1 may be modified by subsequent processes; or interconnect layers and vertical interconnect channels may be provided on auxiliary stacked structure 3, with the upper side of the vertical interconnect channels electrically connected to peripheral circuit wafers (not shown) by means of, for example, bonding, to further form the final product.

[0058] By setting multiple parallel selective gate isolation structures 5, the number of gate isolation structures that need to penetrate the stacked structure 2 is reduced, allowing the distance between the two sets of channel structures 21 to be closer, which helps to improve the storage density of the three-dimensional memory structure. Therefore, the three-dimensional memory structure provided in this application can have a high storage density.

[0059] In an exemplary embodiment, the material of the metal silicide layer 32 includes: Ni2Si, Ni 31 Si 12The metal silicide layer 32 is at least one of NiSi and NiSi2. The resistivity of the metal silicide layer 32 is low, resulting in a low RC delay in the three-dimensional storage structure using it as the control gate. By controlling the material of the metal silicide layer 32, its work function can be adjusted to suit different requirements. Exemplarily, the material of the metal silicide layer 32 includes metal silicides and dopants.

[0060] The following is combined with the appendix Figures 3 to 31 This disclosure details three methods for manufacturing three-dimensional storage structures.

[0061] like Figure 3 As shown, in an exemplary embodiment, the method 1000 for manufacturing a three-dimensional storage structure includes the following steps:

[0062] Step S101: A bottom dielectric layer 31, a metal silicide layer 32, and a top dielectric layer 33 are sequentially formed on the stacked structure 2, including the channel structure 21. Figure 5 )

[0063] Step S102: An auxiliary channel structure 4 is formed, penetrating the top dielectric layer 33, the metal silicide layer 32, and the bottom dielectric layer 31, and the auxiliary channel structure 4 is electrically connected to the channel structure 21. Figure 12 )

[0064] Step S103: A selected gate isolation structure 5 is formed that penetrates the top dielectric layer 33 and the metal silicide layer 32. In an exemplary embodiment, the selected gate isolation structure 5 divides the metal silicide layer 32 into at least two parts and divides the plurality of auxiliary channel structures 4 into at least two groups. Figure 2 )

[0065] Before step S101, the method 1000 provided in this embodiment may further include: the step of forming a stacked structure 2 on the substrate 1. For example... Figure 4 As shown, an insulating layer 201 and a sacrificial layer 202 are alternately stacked on a substrate 1. A channel structure 21 extends through these insulating layers 201 and sacrificial layers 202.

[0066] For example, see Figures 4 to 7 Step S101 includes the following sub-steps: forming a bottom dielectric layer 31; sequentially forming a polysilicon layer 320 and a metal layer 34 on the bottom dielectric layer 31; and then performing an alloying reaction on the polysilicon layer 320 and the metal layer 34 to transform the polysilicon layer 320 into a metal silicide layer 32. Specifically, the polysilicon layer 320 can undergo an alloying reaction with a portion of the metal layer 34, such as the portion of the metal layer 34 that is attached to the polysilicon layer 320, and a residual metal layer 341 can be obtained. The residual metal layer 341 can be removed after the alloying reaction.

[0067] like Figure 4and Figure 5 As shown, a bottom dielectric layer 31 covers the stacked structure 2, thereby covering the top surface of the channel structure 21. A polysilicon layer 320 is formed on the bottom dielectric layer 31. The polysilicon layer 320 is made of polysilicon, which gives it electrical conductivity, and its work function can be flexibly adjusted by doping with impurities. Furthermore, its phase can be controlled during the formation of the polysilicon layer 320. A metal layer 34 is disposed on the polysilicon layer 320, and the material of the metal layer 34 may include metals such as nickel, titanium, tungsten, and cobalt.

[0068] Exemplarily, the step of forming the polysilicon layer 320 includes an in-situ doping process such that the formed polysilicon layer is a doped polysilicon layer. Exemplarily, the polysilicon layer 320 is doped using a process such as ion implantation after its formation.

[0069] like Figure 6 As shown, the polycrystalline silicon layer 320 transforms into a metal silicide layer 32 after the alloying reaction. The amount of metal atoms in the metal layer 34 can be relatively large, resulting in residual metal layer 341 remaining after some atoms have entered the polycrystalline silicon layer 320. The residual metal layer 341 can then be removed to obtain the desired product. Figure 7 The structure shown is as follows. In this embodiment, the polysilicon layer 320 is a complete layer, thus the resulting metal silicide layer 32 has a uniform phase and stable properties.

[0070] For example, the method provided in this embodiment may dope the metal silicide layer 32 after the step of forming the metal silicide layer 32.

[0071] In an exemplary embodiment, the material of the metal layer 34 includes nickel. In this embodiment, by controlling the temperature of the alloy reaction and the amount of nickel in the metal layer 34, the material of the metal silicide layer 32 includes: Ni2Si, Ni 31 Si 12 At least one of NiSi and NiSi2. This allows the work function of the metal silicide layer 32 to be flexibly adjusted according to actual needs.

[0072] like Figure 8 As shown, a top dielectric layer 33 is disposed on the metal silicide layer 32.

[0073] After the top dielectric layer 33 is formed, an auxiliary channel via 40 can be formed, penetrating the top dielectric layer 33, the metal silicide layer 32, and the bottom dielectric layer 31, such as... Figure 9 As shown. The auxiliary channel holes 40 correspond one-to-one with the channel structure 21, and expose the channel structure 21.

[0074] In step S102, an auxiliary insulating layer 410 can be formed in the auxiliary channel hole 40, and the channel structure 21 can be exposed from the bottom of the auxiliary channel hole 40. For example... Figure 10 As shown, the bottom layer 411 of the auxiliary insulating layer 410 covers the channel structure 21. The bottom layer 411 can be removed by anisotropic etching to obtain the desired result. Figure 11 The structure shown.

[0075] An auxiliary channel layer (not shown) is then formed on the inner wall of the auxiliary insulation layer 410. The auxiliary channel layer is connected to the channel structure 21. An auxiliary filler core can also be filled within the auxiliary channel layer, and an auxiliary plug can be placed on the auxiliary channel layer. For example... Figure 12 As shown, the auxiliary channel structure 4 penetrates the auxiliary stacked structure 3 and is connected to the channel structure 21.

[0076] The method of this embodiment further includes forming a select gate isolation trench 50 penetrating the top dielectric layer 33 and the metal silicide layer 32. Understandably, the select gate isolation trench 50 may have a wavy shape in a direction perpendicular to the stacking direction of the stacked structure 2 to avoid adjacent auxiliary channel structures 4. A select gate isolation structure 5 can then be formed in the select gate isolation trench 50 to obtain... Figure 2 The three-dimensional storage structure shown.

[0077] For example, a stepped structure may subsequently be formed in the stacked structure 2, the sacrificial layer 202 may be replaced with a gate layer to form a gate line isolation structure, and a conductive channel (not shown) may be formed on the stepped structure.

[0078] like Figure 13 As shown, the method 2000 for manufacturing a three-dimensional storage structure according to an exemplary embodiment includes the following steps:

[0079] Step S201: A bottom dielectric layer 31, a polysilicon layer 320, and a top dielectric layer 33 are sequentially formed on the stacked structure 2, including the channel structure 21. (Refer to...) Figure 15 A stacked structure 2 is disposed on the substrate 1, and an auxiliary stacked structure 3 is disposed on the stacked structure 2. The substrate 1 and the stacked structure 2 in this embodiment are similar to those in embodiment 1.

[0080] Step S202: The polysilicon layer 320 is converted into a metal silicide layer 32. Figure 18 )

[0081] Step S203: An auxiliary channel structure 4 is formed, penetrating the top dielectric layer 33, the metal silicide layer 32, and the bottom dielectric layer 31, and the auxiliary channel structure 4 is electrically connected to the channel structure 21. Figure 12 )

[0082] Step S204: A selected gate isolation structure 5 is formed, penetrating the top dielectric layer 33 and the metal silicide layer 32. The selected gate isolation structure 5 divides the metal silicide layer 32 into at least two parts and divides the plurality of auxiliary channel structures 4 into at least two groups. Figure 1 )

[0083] like Figure 14 As shown, before converting the polysilicon layer 320 into a metal silicide layer 32, step S2031 can be performed first: forming an auxiliary channel via 400 penetrating the top dielectric layer 33 and the polysilicon layer 320. For example... Figure 16 As shown, the auxiliary channel hole 400 can expose the polysilicon layer 320.

[0084] The subsequent steps of converting the polysilicon layer 320 into a metal silicide layer 32 may include steps S2021 to S2023.

[0085] In an exemplary embodiment, a metal-filled structure 35 may be formed in the auxiliary channel via 400 and on the top dielectric layer 33 to obtain, for example, Figure 17 The structure shown is such that the metal-filled structure 35 contacts the polysilicon layer 320 through the auxiliary channel via 400. The material of the metal-filled structure 35 can refer to the metal layer 34 of the aforementioned embodiment.

[0086] Then, an alloying reaction can be performed on the polysilicon layer 320 and the metal-filled structure 35 to transform the polysilicon layer 320 into a metal silicide layer 32 and obtain a residual metal-filled structure 351. For example... Figure 17 and Figure 18 As shown, the portion of the previous metal-filled structure 35 that contacts the polysilicon layer 320 enters the polysilicon layer 320, while the portion that does not contact the polysilicon layer 320 may not participate in the alloy reaction. It should be noted that the ability of the metal-filled structure 35 to penetrate into the top dielectric layer 33 is much lower than its ability to penetrate into the polysilicon layer 320. After the alloy reaction, a residual metal-filled structure 351 is obtained.

[0087] After removing the residual metal filling structure 351, the following was obtained: Figure 19 The structure shown is illustrated. The steps for forming the metal silicide in this embodiment are compatible with the steps for forming the auxiliary channel structure. By forming the metal silicide layer through the auxiliary channel holes, this embodiment offers a fast reaction speed, short process time, and the ability to form the metal silicide layer in a single step, resulting in a relatively simple process.

[0088] For example, prior to step S203, the auxiliary channel via 400 may extend through the bottom dielectric layer 31 to expose the channel structure 21, such as... Figure 20As shown. Furthermore, an auxiliary channel structure 4 is formed in the extended auxiliary channel hole 40. Steps S203 and S204 of this embodiment can be referred to steps S102 and S103 of the aforementioned embodiment (…). Figures 9 to 12 , Figure 1 ).

[0089] like Figure 21 As shown, the method 3000 for manufacturing a three-dimensional storage structure according to an exemplary embodiment includes the following steps:

[0090] In step S301, a bottom dielectric layer 31, a polysilicon layer 320, and a top dielectric layer 33 are sequentially formed on the stacked structure 2 including the channel structure 21. Exemplarily, the polysilicon layer 320 may be doped. This doping step may be performed before the formation of the top dielectric layer 33. Exemplarily, in-situ doping makes the formed polysilicon layer 320 a doped polysilicon layer. The substrate 1 and stacked structure 2 of this embodiment may be similar to those of Embodiment 1.

[0091] In step S302, an auxiliary channel structure 4 is formed that penetrates the top dielectric layer 33, the polysilicon layer 320 and the bottom dielectric layer 31, and the auxiliary channel structure 4 is electrically connected to the channel structure 21.

[0092] Step S303: The polysilicon layer 320 is converted into a metal silicide layer 32.

[0093] In step S304, a selective gate isolation structure 5 is formed that penetrates the top dielectric layer 33 and the metal silicide layer 32. The selective gate isolation structure 5 divides the metal silicide layer 32 into at least two parts and divides the plurality of auxiliary channel structures 4 into at least two groups.

[0094] In this embodiment, the step of forming the auxiliary channel structure 4 includes forming the auxiliary channel hole 40. For example... Figure 22 As shown, the auxiliary channel via 40 penetrates the top dielectric layer 33, the polysilicon layer 320 and the bottom dielectric layer 31, and exposes the channel structure 21 in the stacked structure 2.

[0095] Then an auxiliary insulating layer 410 is formed in the auxiliary channel hole 40, and as shown in the figure. Figure 23 As shown, the bottom layer 411 of the auxiliary insulating layer 410 covers the channel structure 21. The bottom layer 411 can be removed by anisotropic etching to expose the channel structure 21 from the bottom of the auxiliary channel hole 40.

[0096] Subsequently, an auxiliary channel layer connected to the channel structure 21 is formed on the inner wall of the auxiliary insulation layer 410. An auxiliary filler core can also be filled within the auxiliary channel layer, and an auxiliary plug can be disposed on the auxiliary channel layer. For example... Figure 24 As shown, the auxiliary channel structure 4 penetrates the auxiliary stacked structure 3 and is connected to the channel structure 21.

[0097] Prior to step S303, a select gate isolation trench 50 is formed penetrating the top dielectric layer 33 and the polysilicon layer 320. For example... Figure 25 As shown, the polysilicon layer 320 is exposed through the selected gate isolation trench 50. The step of converting the polysilicon layer 320 into a metal silicide layer 32 may include: forming a metal-filled structure 36 in the selected gate isolation trench 50 and on the top dielectric layer 33, then performing an alloying reaction on the polysilicon layer 320 and the metal-filled structure 36 to convert the polysilicon layer 320 into a metal silicide layer 32, thereby obtaining a residual metal-filled structure 361, and then removing the residual metal-filled structure 361.

[0098] like Figure 26 As shown, the metal-filled structure 36 contacts the polysilicon layer 320 through the selected gate isolation trench 50.

[0099] like Figure 27 As shown, after the alloy reaction, the portion of the previous metal-filled structure 36 that was in contact with the polysilicon layer 320 enters the polysilicon layer 320, while the portion that was not in contact with the polysilicon layer 320 may not have participated in the alloy reaction. It should be noted that the ability of the metal-filled structure 36 to penetrate into the top dielectric layer 33 is much lower than its ability to penetrate into the polysilicon layer 320. After the alloy reaction, a residual metal-filled structure 361 and residual voids 360 are obtained.

[0100] After removing the residual metal filling structure 361, the following was obtained: Figure 28 The structure shown. (As illustrated) Figure 28 As shown, since the volume of the selected gate isolation trench 50 is relatively small, that is, after all the original metal atoms in the residual void 360 are consumed, only a portion of the polycrystalline silicon layer 320 undergoes an alloy reaction, forming a mixed polycrystalline silicon layer 321.

[0101] Therefore, the steps of forming the metal-filled structure 36a, performing the alloy reaction, and removing the residual metal-filled structure 361a can be repeated to ensure that the polysilicon layer 320 is completely transformed into the metal silicide layer 32.

[0102] like Figure 28 and Figure 29 As shown, the material of the mixed polysilicon layer 321 near the select gate isolation trench 50 includes metal silicide, while the material of the mixed polysilicon layer 321 away from the select gate isolation trench 50 is still polysilicon or doped polysilicon. The newly formed metal-filled structure 36a is in contact with the mixed polysilicon layer 321.

[0103] like Figure 30 As shown, after the alloying reaction is carried out again, the material of the mixed polycrystalline silicon layer 321 is completely transformed, forming a metal silicide layer 32. The residual metal-filled structure 361a can be removed in a subsequent step to obtain the desired result. Figure 31 The structure shown. Figure 31 In the process, at least one selective gate isolation trench 50 divides the top dielectric layer 33 and the metal silicide layer 32 of the auxiliary stack structure 3 into at least two parts.

[0104] Then step S304 can be performed. Step S304 of this application can refer to step S103 of the aforementioned embodiment. Figure 12 , Figure 1 ).

[0105] The step of forming the metal silicide layer in this embodiment is compatible with the step of forming the selective gate isolation structure, and the auxiliary channel structure has good size and shape.

[0106] like Figure 32 As shown, an embodiment of this disclosure provides a memory that may include the aforementioned three-dimensional storage structure 61 and peripheral circuitry 62. The peripheral circuitry 62 is electrically connected to the three-dimensional storage structure 61 to facilitate the functionality of the three-dimensional storage structure 61 within the circuit. The peripheral circuitry 62 may be stacked or arranged in parallel with the three-dimensional storage structure 61, and the two may be bonded or electrically connected using other methods. The peripheral circuitry 62 may include, for example, a page buffer / sensor amplifier, a column decoder / bit line (BL) driver, a row decoder / word line (WL) driver, a voltage generator, a control logic unit, registers, an interface, and a data bus.

[0107] like Figure 33 As shown, this disclosure also provides a storage device 7, including at least one storage unit 71, a controller 72, and a connector 73. The connector 73 is used to couple the storage device 7 to an external device.

[0108] For example, the controller 72 and at least one memory 71 can be integrated into the memory card. The memory card may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC, RS) card, etc. MMC, MMCmicro, eMMC), SD cards (SD, miniSD, microSD, SDHC), Universal Flash Memory (UFS), etc. For example, the controller 72 and at least one memory 71 can be integrated into a solid-state drive (SSD).

[0109] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the described technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions in this disclosure.

Claims

1. A method for manufacturing a three-dimensional storage structure, characterized in that, include: A bottom dielectric layer, a polysilicon layer, and a top dielectric layer are sequentially formed on a stacked structure including a channel structure. Form auxiliary channel holes or selective gate isolation trenches that penetrate the top dielectric layer and the polysilicon layer; After forming the top dielectric layer, the polysilicon layer is converted into a metal silicide layer: a metal-filled structure is formed in the auxiliary channel via or the select gate isolation trench and on the top dielectric layer; the polysilicon layer and the metal-filled structure are alloyed to convert the polysilicon layer into the metal silicide layer and obtain a residual metal-filled structure; and the residual metal-filled structure is removed. An auxiliary channel structure is formed that extends from the top dielectric layer to the bottom dielectric layer, and the auxiliary channel structure is electrically connected to the channel structure. as well as A selective gate isolation structure is formed that extends through the top dielectric layer and the metal silicide layer.

2. The method according to claim 1, wherein, The process of forming the metal-filled structure, performing the alloy reaction, and removing the residual metal-filled structure is repeated to ensure that the polycrystalline silicon layer is completely transformed into the metal silicide layer.

3. The method according to any one of claims 1 or 2, wherein, The material of the metal-filled structure includes nickel; as well as By controlling the temperature of the alloy reaction and the amount of nickel in the metal-filled structure, the material of the metal silicide layer includes: Ni2Si, Ni 31 Si 12 At least one of NiSi and NiSi2.

4. The method according to claim 1, wherein, Also includes: The polycrystalline silicon layer is doped.

5. The method according to claim 1, wherein, The steps for forming the polycrystalline silicon layer include: In-situ doping ensures that the resulting polycrystalline silicon layer is a doped polycrystalline silicon layer.

6. The method according to claim 1, wherein, Prior to the step of forming the auxiliary channel structure, the method further includes: Forming auxiliary channel vias penetrating the top dielectric layer, the metal silicide layer, and the bottom dielectric layer; and The steps for forming the auxiliary channel structure include: An auxiliary insulating layer is formed in the auxiliary channel hole, and the channel structure is exposed from the bottom of the auxiliary channel hole; An auxiliary channel layer is formed on the inner wall of the auxiliary insulating layer, wherein the auxiliary channel layer is connected to the channel structure.

7. The method according to claim 1, wherein, Before forming the selected gate isolation structure, the method further includes: Forming a selective gate isolation trench that extends through the top dielectric layer and the metal silicide layer; and The steps for forming the selected gate isolation structure include: The selective gate isolation structure is formed in the selective gate isolation slot.

8. The method according to claim 7, wherein, In a direction perpendicular to the stacking direction of the stacked structure, the selective gate isolation groove has a wave-like shape to bypass the adjacent auxiliary channel structure.

9. A three-dimensional storage structure manufactured according to any one of claims 1 to 8, characterized in that, include: Stacked structures, including channel structures; An auxiliary stacked structure includes a bottom dielectric layer, a metal silicide layer, and a top dielectric layer that are sequentially stacked on the stacked structure in the stacking direction of the stacked structure. An auxiliary channel structure penetrates the auxiliary laminated structure and is electrically connected to the channel structure; as well as At least one selected gate isolation structure extends through the top dielectric layer and the metal silicide layer.

10. The three-dimensional storage structure according to claim 9, wherein, The selective gate isolation structure has a wave-like shape to bypass the adjacent auxiliary channel structure.

11. The three-dimensional storage structure according to claim 9, wherein, The materials of the metal silicide layer include: Ni2Si, Ni 31 Si 12 At least one of NiSi and NiSi2.

12. The three-dimensional storage structure according to claim 9, wherein, The material of the metal silicide layer includes metal silicides and dopants.

13. A memory, characterized in that, include: The three-dimensional storage structure as described in any one of claims 9 to 12; and The peripheral circuit is electrically connected to the three-dimensional storage structure.

14. A storage device, characterized in that, include: The memory as described in claim 13; and A controller, electrically connected to the storage structure, is used to control the memory.

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