Three-dimensional memory and methods of making the same, memory systems, electronic devices

Abstract

The application provides a three-dimensional memory, a preparation method thereof, a storage system and an electronic device. The preparation method of the three-dimensional memory comprises the following steps: forming a laminated structure comprising a plurality of stacked layers, and forming a plurality of stepped terraces in the laminated structure; forming a dielectric layer covering the stepped terraces, and forming a top selection gate cutout perpendicular to a laminated surface of the laminated structure in the dielectric layer; forming a virtual channel hole penetrating through the dielectric layer and the stepped terraces; and filling the top selection gate cutout and the virtual channel hole with an insulating material to form a top selection gate structure and a virtual channel structure, respectively, wherein the virtual channel hole comprises a first virtual channel hole, a projection of the first virtual channel hole on the laminated surface has an overlapping area with a projection of the top selection gate cutout on the laminated surface, and an extension length of the overlapping area in a first direction parallel to the top selection gate cutout is less than a maximum opening size of the first virtual channel hole in a direction parallel to the first direction.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and more particularly, to a three-dimensional memory, a preparation method thereof, a storage system, and an electronic device. BACKGROUND

[0002] With the demand for high storage density and large storage capacity of memory, three-dimensional memory (e.g., 3D NAND memory) emerges as the times require. In some examples, the three-dimensional memory includes a core region and a staircase region. The core region can be used to form memory cells stacked in a vertical direction, and the staircase region can be used to form an energization channel of a word line leading to the memory cells.

[0003] In addition, a top select gate structure and a dummy channel structure can be formed in the staircase region. However, due to the spatial relationship of the top select gate cutout and the dummy channel hole and the sequence of the preparation process, overetching of the dummy channel hole can occur, thereby affecting the topography of the dummy channel structure. SUMMARY

[0004] The present application provides a preparation method of a three-dimensional memory, the preparation method comprising: forming a stack structure comprising a plurality of stacked layers, and forming a plurality of staircase steps in the stack structure; forming a dielectric layer covering the staircase steps, and forming a top select gate cutout perpendicular to a stack surface of the stack structure in the dielectric layer; forming a dummy channel hole penetrating through the dielectric layer and the staircase steps; and filling the top select gate cutout and the dummy channel hole with an insulating material to form a top select gate structure and a dummy channel structure, respectively, wherein the dummy channel hole comprises a first dummy channel hole, a projection of the first dummy channel hole on the stack surface has an overlapping region with a projection of the top select gate cutout on the stack surface, and an extension length of the overlapping region in a first direction parallel to the top select gate cutout is less than a maximum opening size of the first dummy channel hole in a direction parallel to the first direction.

[0005] In one embodiment, an extension length of the overlapping region in a second direction perpendicular to the top select gate cutout is equal to a width of the top select gate cutout.

[0006] In one embodiment, the method further comprises: forming a contact hole penetrating through the dielectric layer and extending to the staircase steps.

[0007] In one embodiment, the dummy channel hole further comprises: a second dummy channel hole, and forming the dummy channel hole penetrating through the dielectric layer and the staircase steps comprises: forming the second dummy channel hole and the first dummy channel hole along at least two sides of the contact hole.

[0008] In one embodiment, the second dummy trench hole and the first dummy trench hole formed on at least two sides of each of the contact holes are in a triangular structure.

[0009] In one embodiment, forming the dummy trench hole through the dielectric layer and the stepped terrace includes forming a patterned etching mask layer on a top surface of the dielectric layer, and etching the dielectric layer and the stepped terrace with the patterned etching mask layer as a mask to form the first dummy trench hole and the second dummy trench hole.

[0010] In one embodiment, forming the patterned etching mask layer on the top surface of the dielectric layer includes forming an etching mask layer on the top surface of the dielectric layer, and forming a first dummy trench hole pattern and a second dummy trench hole pattern in the etching mask layer to form the patterned etching mask layer, and etching the dielectric layer and the stepped terrace with the patterned etching mask layer as a mask includes etching the dielectric layer and the stepped terrace via the first dummy trench hole pattern and the second dummy trench hole pattern, wherein an extension length of the first dummy trench hole pattern in a first direction from the predetermined overlapping area of the top select gate cutout is less than a maximum dimension of the first dummy trench hole pattern in the first direction, and an extension length of the predetermined overlapping area in a second direction perpendicular to the top select gate cutout is equal to a width of the top select gate cutout.

[0011] In one embodiment, the stack structure is divided into a stepped region including the stepped terrace, and a core region adjacent to the stepped region, and the method further includes forming the top select gate cutout perpendicular to a stack surface of the stack structure in the core region.

[0012] Another aspect of the present disclosure provides a three-dimensional memory, including: a stack structure including a plurality of stacked layers, the stack structure having a stepped terrace formed therein; a dielectric layer covering the stepped terrace; a top select gate structure located in the dielectric layer and perpendicular to a stack surface of the stack structure; and a dummy trench structure through the dielectric layer and the stepped terrace, and including a first dummy trench structure, at least a portion of the first dummy trench structure overlapping the top select gate structure, wherein an extension length of the at least a portion in a first direction parallel to the top select gate structure is less than a maximum opening dimension of the first dummy trench structure in the first direction.

[0013] In one embodiment, an extension length of the at least a portion in a second direction perpendicular to the top select gate structure is equal to a width of the top select gate structure.

[0014] In one embodiment, the three-dimensional memory further includes a contact structure extending through the dielectric layer and to the staircase.

[0015] In one embodiment, the dummy channel structure further includes a second dummy channel structure, the second dummy channel structure and the first dummy channel structure being located at least on two sides of the contact structure.

[0016] In one embodiment, the second dummy channel structure and the first dummy channel structure located at least on two sides of each of the contact structures are in a triangular structure.

[0017] In one embodiment, the stack structure is divided into a staircase region including the staircase and a core region adjacent to the staircase region, the three-dimensional memory further includes the top select gate structure located in the core region and perpendicular to a stack plane of the stack structure.

[0018] Another aspect of the present disclosure provides a storage system. The storage system includes a controller and the three-dimensional memory as described above, the controller being coupled to the three-dimensional memory and configured to control the three-dimensional memory to store data.

[0019] Another aspect of the present disclosure provides an electronic device including the storage system as described above.

[0020] The three-dimensional memory and the method of manufacturing the same according to one or more embodiments of the present disclosure can have at least one of the following advantages:

[0021] 1) forming the dummy channel hole after forming the top select gate cut, which can fill the top select gate cut and the dummy channel hole simultaneously in a subsequent same process step, thereby reducing the process steps and lowering the production cost;

[0022] 2) setting the extension length of the overlapping region in a first direction parallel to the top select gate cut to be less than the maximum opening size of the first dummy channel hole in the first direction, which can reduce the overlapping area of the first dummy channel hole and the top select gate cut, reduce the phenomenon of the first dummy channel hole expanding in the first direction in the etching process, and prevent the risk of over-etching of the first dummy channel hole in the first direction; and

[0023] 3) setting the extension length of the overlapping region in the first direction parallel to the top select gate cut to be less than the maximum opening size of the first dummy channel hole in the first direction, which is conducive to optimizing the pattern topography of the first dummy channel hole. BRIEF DESCRIPTION OF DRAWINGS

[0024] Other features, objects, and advantages of the present application will become more apparent from the following detailed description, when read in conjunction with the accompanying drawings. In the drawings, which are not intended to be drawn to scale:

[0025] Figure 1 is a flow diagram of a method of fabricating a three-dimensional memory according to an example embodiment of the present application;

[0026] Figures 2 to 5 is a process step diagram of a method of fabricating a three-dimensional memory according to an example embodiment of the present application;

[0027] Figure 6 is a top-down view schematic of a method of fabricating a three-dimensional memory according to an example embodiment of the present application after formation of top select gate cuts and dummy channel holes;

[0028] Figure 7 is a zoomed-in view schematic of a first dummy channel hole according to an example embodiment of the present application;

[0029] Figure 8 is a structure schematic of a method of fabricating a three-dimensional memory according to the related art after formation of top select gate cuts and dummy channel holes;

[0030] Figure 9 is a pattern schematic of a patterned etch mask layer according to an example embodiment of the present application;

[0031] Figure 10A and Figure 10B is a process step diagram of a method of fabricating a three-dimensional memory according to an example embodiment of the present application;

[0032] Figure 11 is a structure schematic of a three-dimensional memory according to an example embodiment of the present application;

[0033] Figure 12 is a structure schematic of a memory system according to an embodiment of the present application; and

[0034] Figure 13 is a structure schematic of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0035] For a better understanding of the present application, various aspects of the present application will be described in greater detail below with reference to the accompanying drawings. It is to be understood that the detailed description is merely descriptive of example embodiments of the present application and not intended to limit the scope of the present application in any way.

[0036] It should be noted that the terms first, second, third, etc. are used herein only to distinguish one feature from another, and do not denote any order, quantity, or importance, but rather are used to identify one feature from another. As such, a first direction discussed herein can also be termed a second direction, and vice versa, without departing from the teachings of the present application.

[0037] In the drawings, the thicknesses of components, sizes, and the like, are exaggerated for clarity. The drawings are merely schematic and are not intended to portray proportionate sizes of a product. As used herein, the terms "substantially", "approximately", and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art.

[0038] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used in this specification, the terms "comprises", "comprising", "includes" and / or "including" mean the presence of stated features, integers, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, elements, components, and / or combinations thereof.

[0039] The exemplary embodiments disclosed herein are described with reference to the drawings. The exemplary embodiments disclosed herein are not to be interpreted in the scope of the specific shapes and sizes shown, but include various equivalent structures capable of achieving the same functions, and shape and size deviations resulting from, for example, manufacturing. The positions shown in the drawings are schematic in nature and are not intended to limit the positions of the components.

[0040] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0041] As used herein, the term "layer" refers to a portion of material comprising a region having height. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. A layer can extend over the entire lower or upper layer structure, or can have a range smaller than that of the lower or upper layer structure. Furthermore, a layer can be a region of a homogeneous or non-homogeneous continuous structure whose height is less than the height of the continuous structure. For example, a layer can be located at the top and bottom surfaces of a continuous structure or between any set of horizontal planes. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, and can include one or more layers, and / or can have one or more layers on, above, and / or below it. A layer can contain multiple layers.

[0042] Figure 1 This is a flowchart of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application.

[0043] like Figure 1 As shown, the fabrication method 1000 of the three-dimensional memory provided in this application may include: S1, forming a stacked structure including multiple stacked layers, and forming multiple stepped sections in the stacked structure; S2, forming a dielectric layer covering the stepped sections, and forming a top selection gate cutout perpendicular to the stacked surface of the stacked structure in the dielectric layer; S3, forming a virtual channel hole penetrating the dielectric layer and the stepped sections; and S4, filling the top selection gate cutout and the virtual channel hole with an insulating material to form a top selection gate structure and a virtual channel structure, respectively, wherein the virtual channel hole includes a first virtual channel hole, the projection of the first virtual channel hole on the stacked surface has an overlapping area with the projection of the top selection gate cutout on the stacked surface, and the extension length of the overlapping area in a first direction parallel to the top selection gate cutout is less than the maximum opening size of the first virtual channel hole in the first direction parallel to the first direction. Steps S1 to S4 will be described in detail below.

[0044] Step S1

[0045] like Figure 2As shown, a stack structure 100 including a plurality of stack layers can be formed and a plurality of stepped terraces 200 can be formed in the stack structure 100. For example, a stack structure 100 including a plurality of stack layers can be formed on one side of a substrate (not shown) and a plurality of stepped terraces 200 can be formed in the stack structure 100. Specifically, the stack structure 100 can be formed by alternately stacking the insulating layers 110 and the sacrificial layers 120 on one side of the substrate. For example, the plurality of stepped terraces 200 can be formed in an edge region or a middle region of the stack structure 100. For example, each of the stepped terraces 200 can be formed of a plurality of stack layers, i.e., a plurality of alternately stacked insulating layers 110 and sacrificial layers 120. Of course, in another exemplary embodiment, each of the stepped terraces 200 can also be formed of one stack layer, i.e., one adjacent insulating layer 110 and sacrificial layer 120. It should be understood that the specific thickness of each of the stepped terraces 200 depends on the requirement of the number of word lines to be controlled for each of the stepped terraces 200 in the actual process. For example, the region of the stack structure 100 corresponding to the plurality of stepped terraces 200, which is referred to as a stepped region, can be used to arrange the word line connection structures. The region of the stack structure 100 corresponding to the plurality of channel structures, which is referred to as a core region (not shown), can be used to form the array of memory cell strings.

[0046] In the exemplary embodiments of the present application, the substrate (not shown) can be, for example, a polysilicon substrate, a single-crystal silicon (Si) substrate, a single-crystal germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a substrate including other elemental semiconductors or compound semiconductors such as GaAs, InP, or SiC, etc. In one embodiment, the substrate can also be a stack structure such as Si / SiGe, etc. In further embodiments, the substrate can also be other epitaxial structures such as silicon-germanium-on-insulator (SGOI), etc.

[0047] In the exemplary embodiments of the present application, forming the stack structure 100 on the substrate can be achieved by one or more deposition processes. The deposition processes for forming the stack structure 100 include, but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof. It should be understood that the number and thickness of the insulating layers 110 and the sacrificial layers 120 are not limited to the number and thickness shown in FIG. 1, and a person skilled in the art can set any number and thickness of the insulating layers 110 and the sacrificial layers 120 as needed without departing from the concept of the present application. In addition, the materials of the insulating layers 110 and the sacrificial layers 120 can be selected from suitable materials known in the art. For example, the insulating layers 110 can be oxide layers such as silicon oxide, and the sacrificial layers 120 can be nitride layers such as silicon nitride. Figure 2 In the exemplary embodiments of the present application, forming the stack structure 100 on the substrate can be achieved by one or more deposition processes. The deposition processes for forming the stack structure 100 include, but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof. It should be understood that the number and thickness of the insulating layers 110 and the sacrificial layers 120 are not limited to the number and thickness shown in FIG. 1, and a person skilled in the art can set any number and thickness of the insulating layers 110 and the sacrificial layers 120 as needed without departing from the concept of the present application. In addition, the materials of the insulating layers 110 and the sacrificial layers 120 can be selected from suitable materials known in the art. For example, the insulating layers 110 can be oxide layers such as silicon oxide, and the sacrificial layers 120 can be nitride layers such as silicon nitride.

[0048] For example, forming a plurality of stepped steps 200 in the stacked structure 100 may include: firstly, forming a plurality of stepped steps 200 in the stepped region by performing a repeated etch-trimming process on the stacked structure 100 using a patterned mask (not shown). The patterned mask may include a photoresist or a carbon-based polymer material and may be removed after the stepped steps are formed.

[0049] Step S2

[0050] like Figure 2 As shown, a medium layer 300 can be formed to cover the stepped steps 200. Furthermore, as... Figure 3 As shown, a top selection gate notch 400 perpendicular to the stack plane (XY plane) of the stacked structure 100 can be formed in the dielectric layer 300. Exemplarily, the dielectric layer 300 covering the step 200 can be formed using atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof. Exemplarily, the top selection gate notch 400 perpendicular to the stack plane (XY plane) of the stacked structure 100 can be formed in the dielectric layer 300 by an etching process, i.e., the top selection gate notch 400 can be set in a direction Z perpendicular to the stack plane (XY plane) of the stacked structure 100. Exemplarily, the top selection gate notch 400 can extend in a direction X parallel to the stack plane (XY plane) of the stacked structure 100.

[0051] In an exemplary embodiment of this application, the stacked structure 100 may be divided into a step region including a stepped area and a core region adjacent to the step region. Exemplarily, a top selection gate notch 400 perpendicular to the stacked plane (XY plane) of the stacked structure 100 in the direction Z may be formed in the core region. Exemplarily, at least two top selection gate notches 400 may have a certain spacing between them. At least two top selection gate notches 400 may be formed in the same process step, that is, at least two top selection gate notches 400 may share the same mask. The top selection gate notch 400 may divide the block storage area in the three-dimensional memory into a finger storage area F( Figure 6 It should be understood that this application does not specifically limit the number of steps 200, the thickness of the dielectric layer penetrated by the top selected gate cutout 400 in the step area, and the number of stacked layers penetrated by the top selected gate cutout 400 in the core area. The number of steps 200, the thickness of the dielectric layer penetrated by the top selected gate cutout 400, and the number of stacked layers penetrated by the top selected gate cutout 400 can be adjusted as needed, depending on the need for a number of smaller storage units in the three-dimensional memory.

[0052] In an exemplary embodiment of this application, the dielectric layer 300 can be formed on the top surface and sidewalls of the stepped steps 200 by depositing oxide, which may be selected from, for example, a silicon oxide-based material. The dielectric layer 300 may be formed by filling silicon oxide based on TEOS. Exemplarily, the dielectric layer 300 may be a multilayer structure, first forming a first sub-film layer with good stepped step coverage, such as silicon oxide (SiO2) deposited by high-density plasma (HDP) or silicon oxide deposited by atomic layer deposition (ALD); then forming a second sub-film layer with high filling efficiency, such as silicon oxide based on TEOS (TESO-based SiO2). In an exemplary embodiment, the density of the first sub-film layer is higher than that of the second sub-film layer, thereby the first sub-film layer has good stepped step coverage, while the second sub-film layer has high filling efficiency. As an example, the formed dielectric layer 300 may also be planarized using processes such as chemical mechanical polishing, so that the dielectric layer 300 provides a substantially flat upper surface for the stepped region of the stacked structure 100.

[0053] In exemplary embodiments of this application, the top select gate notch 400 can be formed using, for example, dry or wet etching processes. Exemplarily, for the sake of brevity and clarity, only one top select gate notch 400 located in the step region and one top select gate notch 400 located in the core region are described below as examples. It should be understood that this application does not specifically limit the number of top select gate notches; the number of top select gate notches can be adjusted as needed, depending on the requirement for a number of smaller storage units in the three-dimensional memory.

[0054] Step S3

[0055] like Figure 5 As shown, a virtual channel hole 500 can be formed penetrating the dielectric layer 300 and the stepped step 200. Exemplarily, the virtual channel hole 500 penetrating the dielectric layer 300 and the stepped step 200 can be formed by, for example, a dry etching process. It should be understood that the virtual channel structure formed by the virtual channel hole 500 can serve a supporting function to prevent the overall structure from collapsing after the sacrificial layer 120 is subsequently removed or after the contact hole 600 is formed.

[0056] In an exemplary embodiment of this application, forming a virtual channel hole 500 penetrating the dielectric layer 300 and the stepped step 200 may include: firstly, as... Figure 4As shown, a patterned etching mask layer 700 is formed on the top surface of the dielectric layer 300. Then, the dielectric layer 300 and the staircase 200 are etched through the patterned etching mask layer 700 to form a dummy trench 500. Specifically, the dielectric layer 300 and the staircase 200 can be etched through the patterned etching mask layer 700 to form the dummy trench 500 that penetrates through the dielectric layer 300 and the staircase 200.

[0057] Step S4

[0058] The top select gate cut 400 and the dummy trench 500 can be filled with an insulating material to form a top select gate structure 800 and a dummy trench structure 900, respectively. As shown, Figure 10A and Figure 10B The top select gate cut 400 and the dummy trench 500 can be filled with an insulating material to form a top select gate structure 800 and a dummy trench structure 900, respectively. As shown, Figure 10B The insulating material can include silicon oxide, silicon oxynitride, silicon nitride, TEOS, or silicon oxide doped with fluorine, carbon, nitrogen, and / or hydrogen, or any suitable insulating material. It is to be understood that there can be a spacing between the top select gate structures 800. The top select gate structures 800 can divide the block storage region in the three-dimensional memory into finger storage regions F.

[0059] In exemplary embodiments of the present application, a contact hole 600 that penetrates through the dielectric layer 300 and extends to the staircase 200 can also be formed. Figure 6 As shown, a plurality of contact holes 600 can be formed in the staircase region by a lithography and etching process. Then, a conductive material such as tungsten alloy can be filled in the contact holes 600 to form a contact structure. The contact structure can be electrically connected to a subsequently formed gate to draw a gate current out. Specifically, the contact structure is in contact with the subsequently formed gate so that an electrical signal can be provided to or transmitted out from the subsequently formed gate.

[0060] In exemplary embodiments of the present application, as shown, Figure 6 A top view of the top select gate cut 400, the dummy trench 500, and the contact hole 600 is shown. As shown, the dummy trench 500 can include a first dummy trench 510, and a projection of the first dummy trench 510 on a layer plane (X-Y plane) has an overlapping region 511 with a projection of the top select gate cut 400 on the layer plane (X-Y plane).

[0061] Exemplarily, the first dummy trench hole 510 can include a main support dummy trench hole 510' and a secondary support dummy trench hole 510". The main support dummy trench hole 510' can be located in the vicinity of the contact hole 600, while the secondary support dummy trench hole 510" is located far away from the contact hole 600. The dummy trench structures formed by the main support dummy trench hole 510' and the secondary support dummy trench hole 510" can both play a supporting role to prevent the overall structure from collapsing after the formation of the contact hole 600. Exemplarily, the main support dummy trench hole 510' and the secondary support dummy trench hole 510" can have substantially the same structure in a second direction D2 (i.e., parallel to the Y direction) perpendicular to the extension direction X of the top select gate cut 400, and can have a certain difference in the maximum opening size in a first direction D1 parallel to the extension direction X of the top select gate cut 400. For example, the maximum opening size 513 of the main support dummy trench hole 510' in the first direction D1 can be about 270 angstroms, and the maximum opening size 513' of the secondary support dummy trench hole 510" in the first direction D1 can be about 180 angstroms. In other words, the maximum opening size 513 of the main support dummy trench hole 510' located near the contact hole 600 can be greater than the maximum opening size 513' of the secondary support dummy trench hole 510" located far away from the contact hole 600. In this way, the support effect of the dummy trench structure formed by the main support dummy trench hole 510' is better, and the collapse or deformation of the structure near the contact hole 600 can be better reduced when the contact hole 600 is formed.

[0062] As Figure 7 An enlarged schematic view of the main support dummy trench hole 510' is shown. The extension length 512 of the overlapping area 511 of the main support dummy trench hole 510' and the top select gate cut 400 in the first direction D1 parallel to the extension direction of the top select gate cut 400 can be smaller than the maximum opening size 513 of the main support dummy trench hole 510' in the first direction D1. Similarly, the extension length of the overlapping area of the secondary support dummy trench hole 510" and the top select gate cut 400 in the first direction D1 parallel to the extension direction of the top select gate cut 400 can be smaller than the maximum opening size 513' of the secondary support dummy trench hole 510" in the first direction D1.

[0063] In a conventional process, after the formation of the top select gate cut 400, the projection of the top select gate cut 400 and the first dummy trench hole 510 on the layer plane (X-Y plane) will have an overlapping area during the process of forming the first dummy trench hole 510. During the process of forming the first dummy trench hole 510 and gradually increasing its cross-sectional size and extension length, the etching material (e.g., etching gas) can pass through the top select gate cut 400 to make the first dummy trench hole 510 along a direction parallel to the extension direction of the top select gate cut 400 (e.g., the Y direction), which can cause the collapse of the structure near the contact hole 600. Figure 8The first direction D1) is over-etched, so that the finally formed first dummy channel hole 510 has a sharp corner along the first direction D1 (refer to Figure 8 ), which further affects the pattern topography of the first dummy channel hole 510. In addition, it also reduces the spacing distance of the adjacent first dummy channel hole 510 in the first direction D1. However, in the present application, by setting the first size 512 to be smaller than the maximum opening size 513, the lateral expansion or even over-etching of the overlapping area 511 due to two times of etching can be avoided in the process of forming the first dummy channel hole 510 after the formation of the top select gate cutout 400.

[0064] In the exemplary embodiments of the present application, as Figure 7 shown, the extension length 514 of the overlapping area 511 in the second direction D2 perpendicular to the extension direction of the top select gate cutout 400 can be approximately equal to the width of the top select gate cutout 400. In actual process, the risk of over-etching of the first dummy channel hole 510 in the second direction D2 is smaller. Therefore, by setting the extension length 514 of the overlapping area 511 in the second direction D2 to be approximately equal to the width of the top select gate cutout 400, the first dummy channel structure formed by the first dummy channel hole 510 can play a better supporting role to prevent the collapse of the overall structure after the removal of the sacrificial layer 120 or the formation of the contact hole 600.

[0065] In the exemplary embodiments of the present application, the dummy channel hole 500 can also include a second dummy channel hole 520 Figure 6 ). The second dummy channel hole 520 and the first dummy channel hole 510 can be located on at least two sides of the contact hole 600. Exemplarily, the second dummy channel hole 520 and the main supporting dummy channel hole 510' can be arranged along the circumferential direction of the contact hole 600. For example, the second dummy channel hole 520 and the main supporting dummy channel hole 510' can jointly surround the contact hole 600. The second dummy channel hole 520 and the main supporting dummy channel hole 510' arranged on at least two sides of each contact hole 600 can form a triangular structure. As Figure 6As shown, two adjacent second dummy trench holes 520 and one main support dummy trench hole 510' can jointly surround the contact hole 600. Each contact hole 600 is surrounded by three dummy trench holes, so that the main support dummy trench hole 510' and the second dummy trench holes 520 can not only play a supporting role, but also prevent the electrical wiring in the area near the contact hole 600 from being bent when the applied external force exceeds the allowable range. In other embodiments, each contact hole 600 can be surrounded by four or more dummy trench holes, depending on the expected layout to be created on the surface of the semiconductor chip. In the example of three dummy trench holes, the contact hole 600 can have a rectangular or square shape, while the main support dummy trench hole 510' can have a rectangular shape, and the remaining two second dummy trench holes 520 can have irregular shapes. As shown in FIG. 5B, the three dummy trench holes 510', 510" and 520 can be respectively arranged at the three vertices of a triangle, and the two irregularly shaped second dummy trench holes 520 can have a "figure-eight" structure. Exemplarily, the second dummy trench holes 520 can have irregular L shapes. Figure 6 As shown in FIG. 5B, the three dummy trench holes 510', 510" and 520 can be respectively arranged at the three vertices of a triangle, and the two irregularly shaped second dummy trench holes 520 can have a "figure-eight" structure. Exemplarily, the second dummy trench holes 520 can have irregular L shapes.

[0066] In the exemplary embodiments of the present application, the dummy trench hole 500 can further include a third dummy trench hole 530( Figure 6 ). The third dummy trench hole 530 can be located in the stepped region and have a certain spacing from the top select gate cutout 400. In actual processes, in order to avoid the risk of over-etching of the dummy trench hole 500 due to the overlapping area of the projection of the dummy trench hole 500 in the stepped region and the top select gate cutout 400 in the layer plane (X-Y plane), when the dummy trench hole is set, the dummy trench hole is set to have a certain spacing from the top select gate cutout, such as the third dummy trench hole 530 having a certain spacing from the top select gate cutout 400. However, there will inevitably be a dummy trench hole (such as the first dummy trench hole 510) having an overlapping area with the top select gate cutout 400 in the stepped step of the stepped region. Therefore, in order to avoid the risk of over-etching of the first dummy trench hole 510, the present application sets the formation of the main support dummy trench hole 510' and the auxiliary support dummy trench hole 510" in the first dummy trench hole 510 to have an overlapping area with the top select gate cutout 400, as described above.

[0067] Exemplarily, forming the patterned etching mask layer 700 on the top surface of the medium layer 300 can include: forming the etching mask layer 700 on the top surface of the medium layer 300; and forming a first dummy trench hole pattern 710 and a second dummy trench hole pattern 720 in the etching mask layer 700 Figure 9) to form a patterned etch mask layer 700. Exemplarily, etching the dielectric layer 300 and the staircase 200 via the first dummy trench pattern 710 and the second dummy trench pattern 720 can include: etching the dielectric layer 300 and the staircase 200 with the patterned etch mask layer 700 as a mask. The first dummy trench pattern 710 can have an extension length in the first direction D1 over a predetermined overlap region 711 of the top select gate cutout 400 that can be less than a maximum dimension of the first dummy trench pattern 710 in the first direction D1, and an extension length in a second direction D2 perpendicular to the top select gate cutout 400 can be approximately equal to a width of the top select gate cutout. Exemplarily, a third dummy trench pattern 730 and a contact hole pattern 740 can also be formed in the etch mask layer 700, i.e., the patterned etch mask layer 700 can also include the third dummy trench pattern 730 and the contact hole pattern 740. It should be understood that the number of dummy trench patterns and contact hole patterns is not specifically limited in the present application, and the number of dummy trench patterns and contact hole patterns can be adjusted as needed, depending on the volume size of the three-dimensional memory.

[0068] In exemplary embodiments of the present application, a gate replacement process can also be performed. Specifically, first, a dry or wet process can be used to remove the sacrificial layer 120 to form a sacrificial gap; then, a thin film deposition process such as CVD, PVD, ALD or any combination thereof can be used to fill the sacrificial gap with a conductive material to form a gate layer 130 Figure 11 The gate layer 130 can be used as part of a conduction circuit for transmitting signals to the storage unit.

[0069] Another aspect of the present application provides a three-dimensional memory. Figure 11 is a structural schematic diagram of a three-dimensional memory according to another exemplary embodiment of the present application.

[0070] As Figure 11 shown, the three-dimensional memory can include a stack structure 100', a dielectric layer 300, a top select gate structure (not shown), and a dummy channel structure 900.

[0071] The stack structure 100' can include a plurality of stack layers. Illustratively, the stack structure 100' including the plurality of stack layers can be formed on one side of a semiconductor layer (not shown). The semiconductor layer can include polysilicon. The stack structure 100' can include insulating layers 110 and gate layers 130 stacked alternately. The stack structure 100' can have a staircase 200 therein. Illustratively, a plurality of staircases 200 can be located in an edge region or a middle region of the stack structure 100'. Illustratively, each staircase 200 can be formed by a plurality of stack layers (i.e., a plurality of insulating layers 110 and gate layers 130 stacked alternately). Of course, in another illustrative embodiment, each staircase 200 can also be formed by one stack layer (i.e., one adjacent insulating layer 110 and gate layer 130). It should be appreciated that the specific thickness of each staircase 200 depends on the requirement of the number of word lines to be controlled for each staircase 200 in the actual process. Illustratively, the region of the stack structure 100' corresponding to the plurality of staircases 200, referred to as a staircase region, can be used to arrange word line connection structures. The region of the stack structure 100' corresponding to the plurality of channel structures, referred to as a core region (not shown), can be used to form the array of memory cell strings.

[0072] The dielectric layer 300 can cover the staircase 200. Illustratively, the dielectric layer 300 covering the staircase 200 can be formed using atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof.

[0073] Reference can be made to Figure 10B The top select gate structure 800 can be located in the dielectric layer 300 and perpendicular to the stack plane (X-Y plane) of the stack structure 100'. The dummy channel structure 900 can penetrate through the dielectric layer 300 and the staircase 200. The dummy channel structure 900 can include an insulating material. The dummy channel structure 900 can include a first dummy channel structure (not shown), at least a portion of which can overlap the top select gate structure 800. It should be appreciated that the first dummy channel structure can be formed by filling the first dummy channel hole 510 Figure 6 ) with the insulating material. The portion of the first dummy channel structure overlapping the top select gate structure 800 (hereinafter referred to as the "overlapping region") can have an extension in a first direction parallel to the top select gate structure smaller than the maximum extension length of the first dummy channel structure in the first direction. In the illustrative embodiment of the present application, the overlapping region can have an extension in a second direction perpendicular to the first direction of the top select gate structure 800 equal to the width of the top select gate structure 800.

[0074] In the exemplary embodiments of the present application, the three-dimensional memory can further include a contact structure extending through the dielectric layer 300 and to the staircase 200. Exemplarily, the contact structure can be formed by filling a conductive material such as tungsten alloy in the contact hole 600. The contact structure can form an electrical connection with a subsequently formed gate (in the gate layer 130), thereby to draw a gate current out. Specifically, the contact structure is in contact with the subsequently formed gate, thereby to provide an electrical signal to the subsequently formed gate, or to transmit an electrical signal out from the subsequently formed gate.

[0075] In the exemplary embodiments of the present application, the first dummy channel structure can include a main support dummy channel structure and a secondary support dummy channel structure. It is to be understood that the main support dummy channel structure and the secondary support dummy channel structure can be formed by filling an insulating material in the main support dummy channel hole 510' and the secondary support dummy channel hole 510" ( Figure 6 ), respectively. The main support dummy channel structure can be located in the vicinity of the contact structure, in contrast to the secondary support dummy channel structure which is located farther away from the contact structure. Both the main support dummy channel structure and the secondary support dummy channel structure can serve a support function to prevent the overall structure from collapsing. Exemplarily, the main support dummy channel structure and the secondary support dummy channel structure can have substantially the same structure in the second direction D2 perpendicular to the top select gate structure 800, and can have a difference in the maximum opening size in the first direction Dl parallel to the top select gate structure 800. For example, the main support dummy channel structure can have a maximum opening size in the first direction Dl of about 270 angstroms, and the secondary support dummy channel structure can have a maximum opening size in the first direction Dl of about 180 angstroms. In other words, the main support dummy channel structure located in the vicinity of the contact structure can have a larger maximum opening size 513 than the secondary support dummy channel structure located farther away from the contact structure. This way, the main support dummy channel structure provides a better support function, and can better reduce the collapse or deformation of the structure in the vicinity of the contact structure during the formation of the contact structure. It is to be understood that the top select gate structure 800 can be formed by filling the top select gate cut 400 ( Figure 6 ) with an insulating material.

[0076] In the exemplary embodiments of the present application, the dummy channel structure 900 can further include a second dummy channel structure (not shown). The second dummy channel structure and the first dummy channel structure can be located on at least two sides of the contact structure. It is to be understood that the second dummy channel structure can be formed by filling a second dummy channel hole 520 ( Figure 6) formed. Illustratively, the second dummy trench structures and the main support dummy trench structure can be disposed along a circumferential direction of the contact structure. For example, the second dummy trench structures and the main support dummy trench structure can collectively encircle the contact structure. The second dummy trench structures and the main support dummy trench structure disposed along the circumferential direction of each contact structure can form a triangular structure. Two adjacent second dummy trench structures and one main support dummy trench structure can collectively encircle the contact structure. Each contact structure is encircled by three dummy trench structures, such that the main support dummy trench structure and the second dummy trench structures can both serve a support function and prevent the electrical routing in the region near the contact structure from bending during the formation of the contact structure when the applied external force exceeds the tolerable range. In other embodiments, each contact structure can be encircled by four or more dummy trench structures, depending on the intended layout to be created on the surface of the semiconductor chip. In the example of three dummy trench structures, the contact structure can have a rectangular or square shape, while the main support dummy trench structure can have a rectangular shape, and the remaining two second dummy trench structures can have irregular shapes. The three dummy trench structures can be disposed on the three vertices of a triangle, respectively, and the two second dummy trench structures with irregular shapes can form a "figure-eight" structure. Illustratively, the second dummy trench structures can have irregular L-shapes.

[0077] In the example embodiment of the present application, the dummy trench structure 900 can further include a third dummy trench structure (not shown). The third dummy trench structure is closer to the trench structure in the core region relative to the first dummy trench structure, and the third dummy trench structure is disposed offset from the top select structure. It should be understood that the third dummy trench structure can be formed by filling the third dummy trench hole 530 Figure 6

[0078] In the example embodiment of the present application, as shown in FIG. 1A, the stack structure 100' can be divided into a staircase region including a staircase and a core region adjacent to the staircase region. The three-dimensional memory can further include a top select gate structure (not shown) located in the core region. Illustratively, there can be a certain spacing between the plurality of top select gate structures. The top select gate structure can divide the block storage region F in the three-dimensional memory. Figure 11

[0079] Since the content and structures involved in the preparation method 1000 described above can be fully or partially applicable to the three-dimensional memory described herein, the content related thereto or similar thereto will not be repeated here.

[0080] Although the example preparation method and structure of the three-dimensional memory are described herein, it can be understood that one or more features can be omitted, replaced, or added from the structure of the three-dimensional memory. In addition, the example layers and their materials are merely illustrative.​​

[0081] Figure 12 is a structural schematic diagram of a storage system 2000 according to an embodiment of the present application.

[0082] As Figure 12 indicated, the present application at least one embodiment also provides a storage system 2000. The storage system 2000 can include a memory 2100 and a controller 2200. The memory 2100 can be the same as the memory described in any of the embodiments above, and the present application will not be repeated here. The storage system 2000 can be a two-dimensional storage system or a three-dimensional storage system, and the following will be described taking the three-dimensional storage system as an example.

[0083] The three-dimensional storage system 2000 can include a three-dimensional memory 2100, a controller 2200 and a host 2300. The three-dimensional memory 2100 can be the same as the three-dimensional memory described in any of the embodiments above, and the present application will not be repeated here. The controller 2200 can control the three-dimensional memory 2100 through a channel CH, and the three-dimensional memory 2100 can perform operations based on the control of the controller 2200 in response to a request from the host 2300. The three-dimensional memory 2100 can receive a command CMD and an address ADDR from the controller 2300 through the channel CH and access a region selected from the memory cell array in response to the address. In other words, the three-dimensional memory 2100 can perform an internal operation corresponding to the command on the region selected by the address.

[0084] In some embodiments, the three-dimensional storage system can be implemented as a universal flash storage (UFS) device, a solid state disk (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro- MMC, a secure digital card in the form of SD, mini-SD and micro-SD, a storage device of the Personal Computer Memory Card International Association (PCMCIA) card type, a storage device of the Peripheral Component Interconnect (PCI) type, a storage device of the Peripheral Component Interconnect Express (PCI-E) type, a compact flash (CF) card, a smart media card or a memory stick, etc.

[0085] Figure 13 is a structural schematic diagram of an electronic device 3000 provided by an embodiment of the present application.

[0086] As Figure 13As shown, the present application also provides an electronic device 3000. The electronic device 3000 includes a memory 3100. The memory 3100 can be the same as the memory described in any of the embodiments above, and the present application does not repeat it. The electronic device 3000 can be a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a wearable device, a mobile power supply, and the like. Thus, other modules of the electronic device 3000, such as a controller, can be determined according to the specific type of the electronic device 3000. The other modules can control the three-dimensional memory 3100 through, for example, a channel, and the three-dimensional memory 3100 can receive commands CMD and addresses ADDR from the other modules through, for example, a channel, and access a region selected from the memory cell array in response to the address. The present application does not limit this.

[0087] The present application provides a peripheral circuit, a memory, a storage system, and an electronic device. Due to the provision of the metal interconnection structure provided by the present application, the same beneficial effects as the metal interconnection structure are achieved, which are not repeated here.

[0088] The above description is only the preferred embodiments of the present application and the explanation of the technical principles applied. Those skilled in the art should understand that the scope of the application involved in the present application is not limited to the technical solutions formed by the specific combinations of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features disclosed in the present application (but not limited to) having similar functions to form technical solutions.

Claims

1. A method for fabricating a three-dimensional memory, wherein, include: A stacked structure comprising multiple stacked layers is formed, and multiple stepped steps are formed in the stacked structure; A medium layer is formed to cover the stepped steps, and a top selection grid cutout is formed in the medium layer that is perpendicular to the stacking surface of the stacked structure; A virtual channel hole is formed that penetrates the dielectric layer and the stepped steps; as well as The top select gate cutout and the virtual channel hole are filled with insulating material to form the top select gate structure and the virtual channel structure, respectively. The virtual channel hole includes a first virtual channel hole, the projection of the first virtual channel hole on the stack layer and the projection of the top selection gate cutout on the stack layer have an overlapping area, and the extension length of the overlapping area in a first direction parallel to the top selection gate cutout is less than the maximum opening size of the first virtual channel hole in the first direction parallel to the first direction.

2. The preparation method according to claim 1, wherein, The length of the overlapping region in a second direction perpendicular to the top selection gate cutout is equal to the width of the top selection gate cutout.

3. The preparation method according to claim 1, wherein, The method further includes: A contact hole is formed that penetrates the dielectric layer and extends to the stepped step.

4. The preparation method according to claim 3, wherein, The virtual channel hole further includes: a second virtual channel hole, wherein the second virtual channel hole and the first virtual channel hole are arranged at intervals. The virtual channel structure includes a first virtual channel structure formed by the first virtual channel hole and a second virtual channel structure formed by the second virtual channel hole. The contact hole forming the contact hole penetrating the dielectric layer and extending to the stepped step includes: The contact hole is formed between the second virtual channel structure and the first virtual channel structure arranged at intervals.

5. The preparation method according to claim 4, wherein, The virtual channel hole includes two second virtual channel holes, and the two second virtual channel holes and the first virtual channel hole form a triangular structure.

6. The preparation method according to claim 4, wherein, Forming a virtual channel hole penetrating the dielectric layer and the stepped steps includes: A patterned etching mask layer is formed on the top surface of the dielectric layer; and The dielectric layer and the stepped steps are etched using the patterned etching mask layer as a mask to form the first virtual channel hole and the second virtual channel hole.

7. The preparation method according to claim 6, wherein, Forming a patterned etching mask layer on the top surface of the dielectric layer includes: forming an etching mask layer on the top surface of the dielectric layer, and forming a first virtual via pattern and a second virtual via pattern in the etching mask layer to form the patterned etching mask layer. Etching the dielectric layer and the stepped steps using the patterned etching mask layer as a mask includes: etching the dielectric layer and the stepped steps via the first virtual via pattern and the second virtual via pattern. Wherein, the extension length of the predetermined overlapping area between the first virtual channel hole pattern and the top selection gate cutout in the first direction is less than the maximum size of the first virtual channel hole pattern in the first direction, and the extension length of the predetermined overlapping area in the second direction perpendicular to the top selection gate cutout is equal to the width of the top selection gate cutout.

8. The preparation method according to any one of claims 1-7, wherein, The layered structure is divided into a step area including the stepped steps, and a core area adjacent to the step area. The method further includes: A top selection gate cutout is formed in the core region, perpendicular to the stacking planes of the stacked structure.

9. A three-dimensional memory, wherein, include: A stacked structure comprising multiple stacked layers, wherein a stepped structure is formed in the stacked structure; A dielectric layer covers the stepped platform; A top-selected gate structure is located in the dielectric layer and is perpendicular to the stacking plane of the stacked structure; as well as A virtual channel structure, penetrating the dielectric layer and the stepped steps, includes a first virtual channel structure, at least a portion of which overlaps with the top selection gate structure, wherein the at least a portion extends in a first direction parallel to the top selection gate structure, less than the maximum extension length of the first virtual channel structure in the first direction.

10. The three-dimensional memory according to claim 9, wherein, The extension length of at least a portion in a second direction perpendicular to the top selection gate structure is equal to the width of the top selection gate structure.

11. The three-dimensional memory according to claim 9, wherein, The three-dimensional memory also includes: The contact structure penetrates the dielectric layer and extends to the stepped steps.

12. The three-dimensional memory according to claim 11, wherein, The virtual channel structure further includes a second virtual channel structure, wherein the second virtual channel structure and the first virtual channel structure are located on both sides of the contact structure, respectively.

13. The three-dimensional memory according to claim 12, wherein, The virtual channel structure includes two second virtual channel structures, which are located on three sides of the contact structure and form a triangular structure.

14. The three-dimensional memory according to any one of claims 9-13, wherein, The stacked structure is divided into a step area including the stepped steps, and a core area adjacent to the step area. The three-dimensional memory also includes: The top selection gate structure is located in the core region and is perpendicular to the stacking plane of the stacked structure.

15. A storage system, characterized in that, The storage system includes a controller and a three-dimensional memory according to any one of claims 9-14, wherein the controller is coupled to the three-dimensional memory and is used to control the storage of data in the three-dimensional memory.

16. An electronic device, characterized in that, include: The storage system of claim 15.

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