Non-volatile memory element with pn diode

Abstract

A non-volatile memory element having a PN diode. The non-volatile memory element includes: an insulating layer that is electrically insulating; a PN diode formed in a monocrystalline silicon layer on the insulating layer; a write wire that is conductive and electrically connected to the front end of the PN diode; a memory cell located on the PN diode and electrically connected to the rear end of the PN diode; and a select wire located on the memory cell and electrically connected to the memory cell; wherein, when the non-volatile memory element is selected to write data, a current flows through the PN diode to write the data into the memory cell.

Description

Technical Field

[0001] This invention relates to a non-volatile memory element, and more particularly to a non-volatile memory element having a PN diode. Background Technology

[0002] Figure 1A and Figure 1B The images show a cross-sectional view and a 3D (three-dimensional) schematic diagram of a typical phase change random access memory (PCRAM) element 10. The PCRAM element 10 is a non-volatile memory element used in electronic device systems to store data. The stored data remains in the phase change region after the electronic device is turned off and the power supply is stopped, without being lost.

[0003] like Figure 1A and Figure 1B As shown, PCRAM element 10 is formed on substrate 11, and includes source / drain 12, bidirectional selector 13, metal pins 141 and 142, phase transition region 15, ground wire 16 and bit wire 17. PCRAM element 10 determines the address of a specific phase change region 15 to which data is written by addressing via bidirectional selector 13 and bit wire 17. By controlling bidirectional selector 13, the channel between source / drain 12 is turned on, and by controlling the voltage of bit wire 17, the current flowing through metal plug 141, source / drain 12 and the aforementioned channel, metal plug 142, phase change region 15 to ground wire 16 is controlled, thereby changing the crystallization state of the material in phase change region 15. Different crystallization states result in different resistance values ​​in phase change region 15, which indicate different stored data. The material in phase change region 15 is, for example, germanium-antimony-tellurium (GeSbTe, GST) alloy, which has different resistance values ​​in its crystalline and amorphous states. PCRAM element 10 writes data representing "1" and / or "0" into phase change region 15 by addressing and changing the resistance value of phase change region 15 as described above. This is well known to those skilled in the art and will not be elaborated here.

[0004] Figure 2A and Figure 2BThe images show a cross-sectional view and a 3D (three-dimensional) schematic diagram of a typical spin transfer torque (STT) magnetoresistive random access memory (MRAM) element 20. The STT-MRAM element 20 is a type of MRAM element and a non-volatile memory element used in electronic device systems to store data. The stored data remains in the magnetic region even after the electronic device is turned off and power is cut off. The MRAM element includes an upper electrode and a lower electrode, both made of ferromagnetic material, with an oxide layer (e.g., magnesium oxide) sandwiched between them. When the magnetization direction of the upper and lower ferromagnetic layers changes from parallel to antiparallel, the resistance increases; conversely, when it changes from antiparallel to parallel, the resistance decreases. This mechanism changes the resistance of the magnetic region to represent different stored data.

[0005] like Figure 2A and Figure 2B As shown, an STT-MRAM element 20 is formed on a substrate 21, including a source / drain 22, a bidirectional selector 23, metal plugs 241 and 242, a magnetic region 25, connecting wires 261 and 262, and a bit wire 27. The STT-MRAM element 20 determines the address of the magnetic region 25 to which data is written by addressing via the bidirectional selector 23 and the bit wire 27. By controlling the bidirectional selector 23, the channel between the source / drain 22 is turned on. By controlling the voltage of the bit wire 27, the current flowing through the magnetic region 25, the connecting wire 261, the metal plug 241, the channel between the source / drain 22 and the other metal plug 242 to the connecting wire 262 is controlled, thereby changing the magnetization direction of the material in the magnetic region 25. As mentioned above, the different magnetization directions of the ferromagnetic layers in the upper and lower electrodes result in different resistance values ​​in the magnetic region 25, which in turn indicate different stored data. The materials of the upper and lower electrodes are, for example, cobalt iron (CoFe) or cobalt iron boron (CoFeB). The STT-MRAM element 20 uses this mechanism to write data representing "1" and / or "0" into the magnetic region 25, which is well known to those skilled in the art and will not be described in detail here.

[0006] Figure 3A and Figure 3BThe images show a cross-sectional view and a 3D (three-dimensional) schematic diagram of a typical resistive random access memory (RRAM) element 30. The RRAM element 30 is a non-volatile memory element used in electronic device systems to store data. The stored data remains in the resistance variation region after the electronic device is turned off and power is cut off, without being lost.

[0007] like Figure 3A and Figure 3B As shown, the RRAM element 30 is formed on the substrate 31 and includes a source / drain 32, a bidirectional selector 33, metal pins 341 and 342, a resistance variation region 35, a ground wire 36, and a bit wire 37. The RRAM element 30 determines the address of the specific resistance variation region 35 to be written to by addressing via a bidirectional selector 33 and bit wire 37. By controlling the bidirectional selector 33, the channel between the source / drain 32 is turned on. By controlling the voltage of the bit wire 37, the current flowing through the metal plug 341, the channel between the source / drain 32 and the bit wire 37, another metal plug 342, the resistance variation region 35 and the ground wire 36 is controlled to change the resistance value in the resistance variation region 35, that is, to indicate different stored data. The resistance variation region 35 includes two metal layers separated by a dielectric layer. The material of the metal layers is, for example, copper telluride (CuTe) or copper germanium (CuGe) alloy. The RRAM element 30 writes data representing "1" and / or "0" into the resistance variation region 35 by addressing and changing the resistance value of the resistance variation region 35 as described above. This is well known to those skilled in the art and will not be described in detail here.

[0008] Traditionally, the selectors used to control non-volatile memory devices and write data to the storage cells are bidirectional switches, such as the aforementioned bidirectional selectors 15, 25, and 35, which are, for example, metal oxide semiconductor (MOS) devices. Therefore, using bidirectional selectors for non-volatile memory devices has at least the following disadvantages: First, taking MOS devices as bidirectional selectors as an example, because they require source, gate, and drain terminals, MOS devices have a larger area compared to diodes, such as PN diodes. This makes the fundamental conditions for miniaturization of traditional non-volatile memory devices less favorable. Second, the conduction current is also limited by the electrical characteristics of MOS devices. MOS devices have a saturation region during operation, and compared to diodes, such as PN diodes, the conduction current of MOS devices is relatively low. For example, when using MOS devices as bidirectional selectors in MRAM devices, the current for writing data to the magnetic region typically must reach 10...7 A / cm 2 To achieve this current, the area of ​​a MOS device would be relatively much larger compared to a PN diode; thirdly, the channel of a MOS device is formed in a semiconductor substrate, resulting in relatively high leakage current. As non-volatile memory technology trends towards miniaturization and increased current per unit area, the application range of traditional bidirectional selectors for controlling non-volatile memory devices is greatly limited.

[0009] Another related technology can be found in 10.1109 / IEDM.2006346905, proposed by JHOh et al., which describes a 90nm 512Mb PCRAM device. This paper discloses a PCRAM device fabricated based on standard CMOS process steps. In this prior art PCRAM device, an epitaxial silicon layer is formed on a heavily N-type doped silicon substrate, and a PN diode is formed within this epitaxial silicon layer as the selector of the PCRAM device. In this PCRAM device, because the PN diode is formed in the epitaxial silicon layer, its on-resistance is higher than that of a PN diode formed in a single-crystal silicon layer. Furthermore, the heavily N-type doped silicon substrate of this PCRAM device cannot provide effective electrical isolation from other components, resulting in relatively large leakage current. It also presents difficulties in the miniaturization processes of semiconductor technology evolution.

[0010] In view of this, the present invention addresses the shortcomings of the prior art by proposing a non-volatile memory element with a PN diode, which can reduce the area of ​​the non-volatile memory element and increase the current per unit area, thereby expanding the application range of the non-volatile memory element. Summary of the Invention

[0011] From one perspective, the present invention provides a non-volatile memory element comprising: an insulating layer that is electrically insulating; a first PN diode formed in a monocrystalline silicon layer on the insulating layer; a first write wire that is conductive and electrically connected to a first front end of the first PN diode; a memory cell located on the first PN diode and electrically connected to a first rear end of the first PN diode; and a select wire that is conductive, located on the memory cell, and electrically connected to the memory cell; when the non-volatile memory element is selected to write a first data, a first current flows through the first PN diode to write the first data into the memory cell.

[0012] From another perspective, the present invention provides a non-volatile memory device, comprising: a non-volatile memory element array composed of a plurality of non-volatile memory elements; and a control circuit for controlling the non-volatile memory element array to perform read and write operations on the non-volatile memory elements; wherein the non-volatile memory element includes: an insulating layer that is electrically insulating; a first PN diode formed in a single-crystal silicon layer on the insulating layer; a first write wire that is conductive and electrically connected to a first front end of the first PN diode; a memory cell located on the first PN diode and electrically connected to a first rear end of the first PN diode; and a selection wire that is conductive, located on the memory cell, and electrically connected to the memory cell; when the non-volatile memory element is selected to write a first data, a first current flows through the first PN diode to write the first data into the memory cell.

[0013] In a preferred embodiment, the first PN diode is stacked and connected to the insulating layer.

[0014] In a preferred embodiment, the first write wire is stacked and connected to the insulating layer, and the first PN diode is stacked and connected to the first write wire.

[0015] In a preferred embodiment, the non-volatile memory element further includes: a second PN diode located in the monocrystalline silicon layer on the insulating layer; and a second write wire having conductivity, and the second write wire being electrically connected to a second front end of the second PN diode; wherein, when the non-volatile memory element is selected to write a second data, a second current flows through the second PN diode to write the second data into the memory cell.

[0016] In a preferred embodiment, the second PN diode is stacked and connected to the insulating layer.

[0017] In a preferred embodiment, the second write wire is stacked and connected to the insulating layer, and the second PN diode is stacked and connected to the second write wire.

[0018] In a preferred embodiment, the non-volatile memory element further includes: a first conductive unit for electrically connecting the memory cell to the first rear end of the first PN diode, wherein a portion of the first conductive unit is stacked and connected to the first rear end; and a second conductive unit for electrically connecting the first conductive unit to the second rear end of the second PN diode, thereby electrically connecting the memory cell to the second rear end; wherein the first write wire is stacked and connected to the insulating layer, and the first front end is stacked and connected to the first write wire, and the first rear end is stacked and connected to the first front end; wherein a first portion of the second conductive unit is stacked and connected to... On the insulating layer, a second portion of the second conductive unit is stacked and connected to the first portion, and another portion of the first conductive unit is stacked and connected to the second portion; wherein the second rear end is stacked and connected to the first portion, and the second front end is stacked and connected to the second rear end, and the second write wire is stacked and connected to the second front end; wherein the first wire and the first portion are formed by the same metal deposition process step; wherein the first front end and the second rear end are formed by the same ion implantation process step, or by the same epitaxial process step; wherein the first rear end and the second front end are formed by the same ion implantation process step, or by the same epitaxial process step.

[0019] In a preferred embodiment, the non-volatile memory element further includes a first connection conductive unit electrically connected between the first PN diode and the memory cell, so as to electrically connect the memory cell to the first rear end of the first PN diode.

[0020] In a preferred embodiment, the non-volatile memory element further includes a second conductive connection unit electrically connected between the second PN diode and the memory cell, so as to electrically connect the memory cell to the second rear end of the second PN diode.

[0021] In a preferred embodiment, the non-volatile memory element is a phase change random access memory (PCRAM), a magnetoresistive random access memory (MRAM), or a resistive random access memory (RRAM).

[0022] In a preferred embodiment, the first writing wire is a metal wire.

[0023] In a preferred embodiment, the first write wire and the second write wire are metallic wires.

[0024] In a preferred embodiment, the non-volatile memory element is formed on a semiconductor-on-insulator (SOI) substrate or a semiconductor-on-metal (SMOI) substrate.

[0025] In a preferred embodiment, the first conductive connection unit and the second write wire are formed by the same metal deposition process step.

[0026] The following detailed description through specific embodiments will make it easier to understand the purpose, technical content, features, and effects achieved by the present invention. Attached Figure Description

[0027] Figure 1A and 1B This diagram shows a cross-sectional view and a 3D (three-dimensional) schematic diagram of a typical phase change random access memory (PCRAM) element 10.

[0028] Figure 2A and 2B The diagrams show a cross-sectional view and a 3D (three-dimensional) schematic diagram of a typical spin transfer torque (STT) magnetoresistive random access memory (MRAM) element 20.

[0029] Figure 3A and 3B The diagrams show a cross-sectional view and a 3D (three-dimensional) view of a typical resistive random access memory (RRAM) element 30.

[0030] Figure 4A and 4B A cross-sectional schematic diagram and a 3D schematic diagram showing an embodiment of a non-volatile memory element according to the present invention.

[0031] Figure 4C Display as shown Figure 4A and 4B The diagram shows a cross-sectional view of one embodiment of the non-volatile memory element 40 arranged in the same selection wire 46.

[0032] Figure 4D A cross-sectional schematic diagram showing one embodiment of the non-volatile memory element according to the present invention is shown.

[0033] Figure 4E A schematic diagram showing one embodiment of the non-volatile memory device according to the present invention is shown.

[0034] Figure 5A and 5B A cross-sectional schematic diagram and a 3D schematic diagram showing an embodiment of a non-volatile memory element according to the present invention.

[0035] Figure 6A and 6B A cross-sectional schematic diagram and a 3D schematic diagram showing an embodiment of a non-volatile memory element according to the present invention.

[0036] Figure 7A and 7B A cross-sectional schematic diagram and a 3D schematic diagram showing an embodiment of a non-volatile memory element according to the present invention.

[0037] Figure 8A , 8B The diagram shows a cross-sectional view, a 3D diagram, and an operation table of one embodiment of the non-volatile memory element according to the present invention, along with 8C.

[0038] Figure 8D A 3D schematic diagram showing one embodiment of a non-volatile memory element according to the present invention.

[0039] Figure 9A , 9B The diagram shows a cross-sectional view, a 3D diagram, and an operation table of one embodiment of the non-volatile memory element according to the present invention.

[0040] Figure 9D A schematic diagram showing one embodiment of the non-volatile memory device according to the present invention is shown.

[0041] Figure 10 A schematic diagram showing one embodiment of the non-volatile memory element according to the present invention is shown.

[0042] Figure 11A and 11B A 3D schematic diagram and operation table showing one embodiment of the non-volatile memory element according to the present invention.

[0043] Figure 11C A schematic diagram showing one embodiment of the non-volatile memory device according to the present invention is shown.

[0044] Explanation of symbols in the diagram

[0045] 10, 20, 40, 50, 60, 70, 80, 90, 90', 100: Non-volatile memory elements

[0046] 11, 21, 31, 41, 51, 61, 71, 81, 91: Semiconductor substrate

[0047] 12, 22, 32: Source / Drain

[0048] 13, 23, 33: Bidirectional selector

[0049] 15: Phase transition region

[0050] 16, 36: Grounding wires

[0051] 17, 27, 37: Position wires

[0052] 25: Magnetic region

[0053] 35: Resistance variation region

[0054] 42, 52, 62, 72, 82, 92, 102: Insulation layer

[0055] 43, 53, 631, 632, 731, 732, 831, 832, 931, 1031, 1032, 1033, 1034: PN diodes

[0056] 43a, 53a, 73a, 631a, 632a, 831a, 832a, 931a, 932a: Front-end

[0057] 43b, 53b, 73b, 631b, 632b, 831b, 832b, 931b, 932b: Backend

[0058] 44, 54, 64, 74, 841, 842, 942, 971, 1041, 1042, 1072, 1073: Write the wires

[0059] 45, 55, 65, 75, 85, 95, 105: Storage units

[0060] 46, 56, 66, 76, 86, 96, 106: Select wires

[0061] 57, 67, 77, 87, 92, 261, 262, 841, 872, 972, 1043, 1044, 1071: Connecting conductive units

[0062] 82: Conductor plug

[0063] 141, 142, 241, 242, 341, 342: metal bolt

[0064] 630: Monocrystalline silicon layer

[0065] 921: Part Two

[0066] 941: Part One

[0067] 1021, 1022: Conductor plugs

[0068] I0: First current

[0069] I1: Second current

[0070] Vr: Read voltage

[0071] Vw: Write voltage Detailed Implementation

[0072] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the accompanying drawings. The drawings in this invention are illustrative and are primarily intended to show the hierarchical relationship between the layers of the related component structures; shapes, thicknesses, and widths are not drawn to scale.

[0073] Figure 4A and 4B This diagram shows a cross-sectional view and a 3D (three-dimensional) view of one embodiment of a non-volatile memory element according to the present invention. The non-volatile memory element 40 according to the present invention is formed on a semiconductor substrate 41. The non-volatile memory element 40 includes an insulating layer 42, a PN diode 43, a write wire 44, a memory cell 45, and a select wire 46. The insulating layer 42, formed on the semiconductor substrate 41, is electrically insulating. The PN diode 43 is formed in a single-crystal silicon layer, a single-crystal germanium layer, or a single-crystal gallium arsenide layer on the insulating layer 42. For example, through an ion implantation process, P-type impurities and N-type impurities are implanted at the front end 43a and the rear end 43b, respectively, in the form of accelerated ions, to form the PN diode 43. The write wire 44 is conductive and electrically connected to the front end 43a (the P-type end in this embodiment) of the PN diode 43, and the PN diode 43 is unidirectionally conductive. Storage cell 45 is located on PN diode 43 and is electrically connected to the rear end 43b (N-type terminal in this embodiment) of PN diode 43. Select wire 46 is conductive, located on storage cell 45, and electrically connected to storage cell 45; wherein, when non-volatile memory element 40 is selected and data is written to storage cell 45 therein, a first current I0 flows through PN diode 43 to write the data to storage cell 45.

[0074] The non-volatile memory element 40 determines which memory cell 45 to write data to via select line 46 and write line 44. It adjusts the potentials of select line 46 and write line 44 to conduct PN diode 43, causing a first current to flow through write line 44, PN diode 43, memory cell 45, and select line 46 to write data to memory cell 45. The memory cell 45 can be a phase transition region of a PCRAM element, a magnetic region of an MRAM element, or a resistance change region of an RRAM element. The data, for example, represents electronic characteristics such as the crystal state, magnetization direction, or resistance of a material. This is well known to those skilled in the art and will not be elaborated upon here.

[0075] Figure 4C Display as shown Figure 4A and 4B The diagram shows a cross-sectional view of one embodiment in which the non-volatile memory elements 40 are arranged in the same select wire 46. Figure 4C As shown, multiple non-volatile memory elements 40 may be arranged consecutively on the same select line 46, and the multiple select lines 46 form a non-volatile memory element array composed of multiple non-volatile memory elements 40.

[0076] Figure 4D This diagram shows a cross-sectional view of one embodiment of a non-volatile memory element according to the present invention. This embodiment is related to... Figure 4A and 4B The difference in the illustrated embodiment is that the write wire 44 in this embodiment is stacked and connected to the front end 43a (P-type terminal in this embodiment) of the PN diode 43, instead of as shown in the example. Figure 4A As shown, the write wire 44 is connected laterally to the front end 43a of the PN diode 43. Figure 4D The purpose is to illustrate that conductor 44 can not only be as Figure 4A As shown, it is connected to the front end 43a in the horizontal direction; this indicates that wire 44 can also be connected as follows. Figure 4D As shown, it is connected to the front end 43a in the longitudinal direction.

[0077] Figure 4E A schematic diagram showing one embodiment of the non-volatile memory device according to the present invention is shown. For example... Figure 4E As shown, and see also Figures 4A-4C The non-volatile memory device 4 includes: a non-volatile memory element array 400 composed of a plurality of non-volatile memory elements 40; and a control circuit 410 for controlling the non-volatile memory element array 400 to perform read and write operations on the non-volatile memory elements 40; wherein, the non-volatile memory elements 40 are, for example, Figures 4A-4CAs shown, it includes: an insulating layer 42, which is electrically insulating; a PN diode 43, formed in a single-crystal silicon layer, a single-crystal germanium layer, or a single-crystal gallium arsenide layer on the insulating layer 42; a write wire 44, which is conductive and electrically connected to the front end 43a of the PN diode 43; a storage cell 45, located on the PN diode 43, and electrically connected to the rear end 43b of the PN diode 43; and a select wire 46, which is conductive, located on the storage cell 45, and electrically connected to the storage cell 45; when a non-volatile memory element 40 is selected to write data, a first current I0 flows through the PN diode 43 to write the data into the storage cell 45.

[0078] The advantages of this invention over the prior art are at least the following: First, according to this invention, the non-volatile memory element uses a unidirectional selector (i.e., a PN diode), eliminating the need for a bidirectional selector as in the prior art, thus saving space and reducing the area occupied by the selector; Second, according to this invention, the use of a unidirectional selector (PN diode) for the non-volatile memory element is not limited by the electrical characteristics of bidirectional selectors such as MOS elements. For example, this invention can use a PN diode as the selector, which has a higher conduction current than MOS elements and a wider range of applications; Third, according to this invention, the unidirectional selector (PN diode) for the non-volatile memory element can be directly electrically connected to the write wire 44. Compared to the prior art using bidirectional selectors such as MOS elements, the PN diode of this invention can significantly reduce leakage current; and the write wire can be further formed on the insulating layer, further reducing leakage current. For example, in this embodiment, the write wire 44 of the non-volatile memory element 40, in a preferred implementation, can be formed on an insulating layer 42, providing better electrical isolation from other conductive areas and exhibiting better insulation performance than the prior art, thus reducing leakage current during operation of the non-volatile memory element 40. In embodiments of multiple PN diodes (described in detail later), this invention can replace bidirectional channels or be applied to multidirectional control (such as SOT-MRAM elements) to make the currents in the bidirectional channels approximately equal.

[0079] Figure 5A and 5BThis diagram shows a cross-sectional view and a 3D view of one embodiment of a non-volatile memory element according to the present invention. The non-volatile memory element 50 according to the present invention is formed on a semiconductor substrate 51. The non-volatile memory element 50 includes an insulating layer 52, a PN diode 53, a write wire 54, a memory cell 55, a select wire 56, and a connecting conductive unit 57. The insulating layer 52 is formed on the semiconductor substrate 51 and is electrically insulating. The PN diode 53 is formed in a single-crystal silicon layer, a single-crystal germanium layer, or a single-crystal gallium arsenide layer on the insulating layer 52. For example, through an ion implantation process, P-type impurities and N-type impurities are implanted at the front end 53a and the rear end 53b, respectively, in the form of accelerated ions, to form the PN diode 53. The write wire 54 is conductive and is electrically connected to the front end 53a of the PN diode 53, and the PN diode 53 is unidirectionally conductive. The memory cell 55 is located on the PN diode 53 and is electrically connected to the rear end 53b of the PN diode 53. The selected wire 56 is conductive, located on the storage cell 55, and electrically connected to the storage cell 55; wherein, when the non-volatile memory element 50 is selected and data is written to the storage cell 55 therein, a first current I0 flows through the PN diode 53 to write the data to the storage cell 55.

[0080] This embodiment and Figure 4A and 4B The illustrated embodiment differs in that, in this embodiment, the non-volatile memory element 50 further includes a conductive connection unit 57, which is conductive and used to electrically connect the memory cell 55 to the rear end 53b (the N-type terminal in this embodiment) of the PN diode 53. In this embodiment, as... Figure 5A and 5B As shown, the connecting conductive unit 57 is stacked and connected to the rear end 53b of the diode 53, for example, but not limited to, and the storage unit 55 is stacked and connected to the connecting conductive unit 57.

[0081] Figure 6A and 6BThis diagram shows a cross-sectional view and a 3D view of one embodiment of a non-volatile memory element according to the present invention. The non-volatile memory element 60 according to the present invention is formed on a semiconductor substrate 61. The non-volatile memory element 60 includes an insulating layer 62, write wires 64, PN diodes 631 and 632, a memory cell 65, a select wire 66, and a connection conductive cell 67. The insulating layer 62 is formed on the semiconductor substrate 61 and is electrically insulating. The PN diode 631 is formed in a single-crystal silicon layer, a single-crystal germanium layer, or a single-crystal gallium arsenide layer on the insulating layer 62. For example, through an ion implantation process, P-type impurities and N-type impurities are implanted at the front end 631a and the rear end 631b respectively in the form of accelerated ions to form the PN diode 631. In this embodiment, the PN diodes 631 are stacked and connected on the insulating layer 62, and the front end 631a and the rear end 631b of the PN diodes 631 are, for example, but not limited to, laterally adjacent. The non-volatile memory element 60 in this embodiment further includes, for example, a PN diode 632 formed in the aforementioned single-crystal silicon layer on the insulating layer 62. The PN diode 632 is formed, for example, by an ion implantation process, where N-type impurities and P-type impurities are implanted at the front end 632a and the rear end 632b respectively in the form of accelerated ions. In this embodiment, the PN diodes 632 are stacked and connected on the insulating layer 62, and the front end 632a and the rear end 632b of the PN diodes 632 are, for example, but not limited to, laterally adjacent.

[0082] A write wire 641 is conductive and electrically connected to the front end 631a of the PN diode 631. In this embodiment, the write wire 641 is, for example, but not limited to, stacked and connected to the front end 631a. A write wire 642 is conductive and electrically connected to the front end 632a of the PN diode 632. In this embodiment, the write wire 642 is, for example, but not limited to, stacked and connected to the front end 632a. A memory cell 65 is located on the PN diodes 631 and 632, and the memory cell 65 is electrically connected to the rear ends 631b and 632b of the PN diodes 631 and 632 via a connecting conductive unit 67. In this embodiment, the connecting conductive unit 67 is laterally located between the rear ends 631b and 632b. In this embodiment, a select wire 66 is located on the memory cell 65 and electrically connected to the memory cell 65. When non-volatile memory element 60 is selected to write data, a first current I0 flows through the PN diode 631 to write the data into memory cell 65. When non-volatile memory element 60 is selected to write other data, a second current I1 flows through the PN diode 632 to write the other data into memory cell 65. It should be noted that the first current I0 and the second current I1 flow in opposite directions when passing through memory cell 65.

[0083] In a preferred embodiment, the PN diode 63 is formed in a single-crystal silicon layer 630. For example... Figure 6A As shown, in a preferred embodiment, PN diode 63 is a two-terminal device. The PN diode is formed, for example, by doping a single-crystal silicon layer with P-type and N-type impurities to form a PN junction. It should be noted that in this embodiment, the orientation of the PN junctions of PN diodes 631 and 632 can be adjusted according to the circuit design, and is not limited to the N-type region on the left and the P-type region on the right as shown in the figure; it can also be the P-type region on top and the N-type region on the bottom; or the P-type region on the bottom and the N-type region on top (i.e., arranged vertically, not horizontally). In a preferred embodiment, write wires 641 and 642 are metal wires, which are formed of, for example, but not limited to, metallic materials such as aluminum, copper, or aluminum-copper alloys. In a preferred embodiment, the select wire and write wire described in this invention are, for example, but not limited to, metal wires.

[0084] According to a preferred embodiment of the present invention, as shown in this embodiment, the non-volatile memory element is formed on a semiconductor-on-insulator (SOI) substrate or a semiconductor-on-metal-insulator (SMOI) substrate, wherein the SOI substrate and the SMOI substrate are well known to those skilled in the art and will not be described in detail here.

[0085] Figure 7A A cross-sectional schematic diagram showing one embodiment of a non-volatile memory element according to the present invention is shown. Figure 7B A 3D schematic diagram showing one embodiment of a non-volatile memory element according to the present invention is shown. Figure 7AAs shown, the non-volatile memory element 70 according to the present invention is formed on a semiconductor substrate 71. The non-volatile memory element 70 includes an insulating layer 72, a write wire 74, a PN diode 73, a memory cell 75, a select wire 76, and a connecting conductive unit 77. The insulating layer 72 is formed on the semiconductor substrate 71 and is electrically insulating. The write wire 74 is located on the first conductor layer 640 and is conductive. The PN diode 73 is located on the insulating layer 72 and is formed in a single-crystal silicon layer, a single-crystal germanium layer, or a single-crystal gallium arsenide layer. The write wire 74 is conductive and is electrically connected to the front end 73a (P-type terminal in this embodiment) of the PN diode 73, and the PN diode 73 is unidirectionally conductive. The memory cell 75 is located on the PN diode 73 and is electrically connected to the rear end 73b of the PN diode 73. The selected wire 76 is conductive, located on the storage cell 75, and electrically connected to the storage cell 75; wherein, when the non-volatile memory element 70 is selected and data is written to the storage cell 75 therein, a first current I0 flows through the PN diode 73 to write the data to the storage cell 75.

[0086] This embodiment and Figure 4A and 4B One of the differences between the illustrated embodiment and the present embodiment is that, in this embodiment, the non-volatile memory element 70 further includes a conductive connection unit 77 electrically connected between the PN diode 73 and the memory cell 75. The conductive connection unit 77 is conductive, for example, a metal wire or a metal plug, for electrically connecting the memory cell 75 to the rear end 73b of the PN diode 73. Furthermore, in this embodiment, the rear end 73b of the diode 73 is stacked and connected on the front end 73a. According to the present invention, the rear end 73b of the diode 73 can be as follows: Figure 4A and 4B As shown, it is connected to the front end 73a in the horizontal direction; it can also be as follows: Figure 7A and 7B As shown, they are stacked and connected on the front end 73a.

[0087] It should be noted that the current path of the first current I0 may differ in different applications of the non-volatile memory element 70. For example, as Figure 7A As shown, when the non-volatile memory element 70 is a PCRAM element, and the memory cell 75 is the phase transition region, the current path of the first current I0 is as follows: Figure 7AAs shown, for example, the current will flow through the PN diode 73, through the connected conductive unit 77, to the memory cell 75, thereby changing the crystallization state of the material in the memory cell 75. At this time, the selected wire 76 is electrically connected to the ground potential, for example. When the non-volatile memory element 70 is a spin orbit torque (SOT) MRAM element, and the memory cell 75 is a magnetic region, the current path of the first current I0 is as follows: Figure 7B As shown, for example, it will flow through the PN diode 73 to the connected conductive unit 77, and will not flow through the memory unit 75, thereby changing the magnetization direction of the electrodes in the memory unit 75 (e.g., Figure 7B (As indicated by the arrow), and change the resistance of the storage cell 75 to write data into the storage cell 75.

[0088] Figure 8A , 8B 8C and 8C respectively show a cross-sectional schematic diagram, a 3D schematic diagram, and an operation table of one embodiment of the non-volatile memory element according to the present invention. For example... Figure 8A and 8B As shown, the non-volatile memory element 80 according to the present invention is a three-terminal element formed on a semiconductor substrate 81. The non-volatile memory element 80 includes an insulating layer 82, write wires 841 and 842, PN diodes 831 and 832, a memory cell 85, a select wire 86, and a connecting conductive cell 87. The three terminals of the non-volatile memory element 80 are the write wires 841 and 842 and the select wire 86, respectively.

[0089] An insulating layer 82 is formed on the semiconductor substrate 81 and is electrically insulating. PN diodes 831 and 832 are formed in a single-crystal silicon layer, a single-crystal germanium layer, or a single-crystal gallium arsenide layer on the insulating layer 82. Write wires 841 and 842 are conductive and are electrically connected to the front ends 831a (P-type terminal in this embodiment) and 832a (N-type terminal in this embodiment) of PN diodes 831 and 832, respectively, and PN diodes 831 and 832 are unidirectionally conductive. A memory cell 85 is located on PN diodes 831 and 832, and the memory cell 85 is electrically connected to the rear ends 831b (N-type terminal in this embodiment) and 832b (P-type terminal in this embodiment) of PN diodes 831 and 832 via a connecting conductive unit 87. A select wire 86 is conductive, located on the memory cell 85, and is electrically connected to the memory cell 85. When a non-volatile memory element 80 is selected and data is written to its memory cell 85, a first current I0 flows through the PN diode 831 to write the data to the memory cell 85. When a non-volatile memory element 80 is selected and another data is written to its memory cell 85, a second current I1 flows through the PN diode 832 to write the other data to the memory cell 85. In this embodiment, the first current I0 and the second current I1 flow in opposite directions through the memory cell 85.

[0090] For example, such as Figure 8C As shown in the operation table, when a non-volatile memory element 80 is addressed and data representing "0" is written into memory cell 85, for example, by electrically connecting write wire 841 to a write voltage Vw and selecting wire 86 to ground potential, a first current I0 is generated. This current flows from write wire 841, through PN diode 831 (P-type region below and N-type region above), then through connecting conductive cell 87, then through memory cell 85, and finally to selecting wire 86. During this process, the crystal state of the material in memory cell 85, the magnetization direction of the magnetic region, or the resistance value of the resistance change region are changed, thus writing data representing "0" into memory cell 85. Write wire 842 is electrically floated. In other non-volatile memory elements 80 that are not selected, write wires 841 and 842 are also electrically floated with selecting wire 86, for example.

[0091] On the other hand, when a non-volatile memory element 80 is addressed and data representing "1" is written into memory cell 85, for example, by electrically connecting select wire 86 to the write voltage Vw and writing wire 842 to ground potential, a second current I1 is generated. This current flows from select wire 86 through memory cell 85, then through connecting conductive unit 87, then through PN diode 832 (N-type region below and P-type region above), and finally to writing wire 842. During this process, the crystal state of the material in memory cell 85, the magnetization direction of the magnetic region, or the resistance value of the resistance change region are changed, thus writing data representing "1" into memory cell 85. Writing wire 841 is electrically floated. In other non-volatile memory elements 80 that are not selected, writing wires 841 and 842 are also electrically floated with select wire 86, for example. The write voltage Vw is, for example, a positive voltage, and is at least higher than the forward voltage of the PN diode, such that current flows from one end electrically connected to the write voltage Vw to the other end electrically connected to the ground potential.

[0092] In a preferred embodiment, when reading data from storage unit 85, for example, the select wire 86 is electrically connected to the read voltage Vr, and the data in storage unit 85 is determined to be "0" or "1" based on the voltage of the write wire 842.

[0093] Figure 8D This illustration shows a 3D schematic diagram of one embodiment of a non-volatile memory element according to the present invention. This embodiment is related to... Figure 8A and 8B The difference in the illustrated embodiment lies in that the connecting conductive unit 87 in this embodiment includes a first part 871, a second part 872, and a third part 873. The second part 872 is stacked and connected to the rear end 831b (N-type terminal in this embodiment) of the PN diode 831, and the third part 873 is stacked and connected to the rear end 832b (P-type terminal in this embodiment) of the PN diode 832. The first part is stacked and connected to the second part 872 and the third part 873, so as to electrically connect the PN diodes 831 and 832 to the memory cell 85, respectively. Furthermore, the respective front ends 831a and 832a and rear ends 831b and 832b of the PN diodes 831 and 832 can be connected laterally, unlike... Figure 8A and 8B The vertical stacked connection is shown.

[0094] Figure 9A , 9B The diagram 9C shows a cross-sectional view, a 3D diagram, and an operation table of one embodiment of the non-volatile memory element according to the present invention. (See diagram 9C for details.) Figure 9A and 9BAs shown, the non-volatile memory element 90 according to the present invention is formed on a semiconductor substrate 91. The non-volatile memory element 90 includes an insulating layer 92, write wires 942 and 971, PN diodes 931 and 932, a memory cell 95, a select wire 96, and connecting conductive cells 94 and 972. This embodiment is applied, for example, but not limited to, STT-MRAM elements or bidirectional RRAM elements.

[0095] An insulating layer 92 is formed on the semiconductor substrate 91 and is electrically insulating. Write wires 942 and 971 are conductive and are electrically connected to the front end 931a (P-type terminal in this embodiment) of PN diode 931 and the front end 932a (N-type terminal in this embodiment) of PN diode 932, respectively. PN diodes 931 and 932 are formed in a single-crystal silicon layer, a single-crystal germanium layer, or a single-crystal gallium arsenide layer on the insulating layer 92 and the first conductor layer 940. A memory cell 95 is located above PN diodes 931 and 932 and is electrically connected to the rear ends 931b and 932b of PN diodes 931 and 932. A select wire 96 is located on the memory cell 95 and is electrically connected to the memory cell 95. When a non-volatile memory element 90 is selected to write data, a first current I0 flows through the PN diode 931 to write the data into the memory cell 95. When non-volatile memory element 90 is selected to write another data, a second current I1 flows through PN diode 932 to write the other data into memory cell 95. In this embodiment, the first current I0 and the second current I1 flow in opposite directions through memory cell 95.

[0096] In this embodiment, the connecting conductive unit 972 is used to electrically connect the storage unit 95 to the rear end 931b of the PN diode 931, wherein a portion of the connecting conductive unit 972 is stacked and connected to the rear end 931b. The connecting conductive unit 94 is used to electrically connect the connecting conductive unit 972 to the rear end 932b of the PN diode 932, thereby electrically connecting the storage unit 95 to the rear end 932b. The write wire 942 is stacked and connected to the insulating layer 92, and the front end 931a is stacked and connected to the first write wire 942, while the rear end 931b is stacked and connected to the front end 931a. The first portion 941 of the connecting conductive unit 94 is stacked and connected to the insulating layer 92, and the second portion 921 of the connecting conductive unit 94 is stacked and connected to the first portion 941, while another portion of the connecting conductive unit 972 is stacked and connected to the second portion 921. The rear end 932b of the PN diode 932 is stacked and connected to the first part 941, and the front end 932a of the PN diode 932 is stacked and connected to the rear end 932b, and the write wire 971 is stacked and connected to the front end 932a.

[0097] The write wire 942 and the first portion 941 are formed by the same metal deposition process. The front end 931a and the rear end 932b are formed by the same ion implantation process or the same epitaxial process. The rear end 931b and the front end 932a are formed by the same ion implantation process or the same epitaxial process. The connecting conductive unit 972 and the write wire 971 are formed, for example, but not limited to, by the same metal deposition process. For example, the write wire 942 and the first portion 941 connecting the conductive unit 94 are formed on the first conductor layer 940 and are conductive. The first conductor layer 940 is located on and connected to the insulating layer 92.

[0098] It should be noted that "the same metal deposition process step" refers to a metal layer formed by a single metal deposition process step, which, through the same lithography process step using the same mask, defines the wiring design (layout) of the metal layer formed by that metal deposition process step, and then through the same etching process step, forms the metal wires and areas. "The same ion implantation process step" refers to an impurity doping process step that uses the same single or group (including multiple) ion beams of the same type of impurities and the same accelerating voltage to form an impurity doping process at the same depth in a semiconductor layer. Epitaxial process step refers to the process step of growing new crystals on an existing single-crystal silicon layer to form a new semiconductor layer, also known as epitaxial growth process step. All of the above process steps are well known to those skilled in the art and will not be elaborated upon here.

[0099] For example, such as Figure 9C As shown in the operation table, when a non-volatile memory element 90 is addressed and data representing "0" is written into memory cell 95, for example, the write wire 942 is electrically connected to the write voltage Vw, and the select wire 96 is electrically connected to ground potential, generating a first current I0. This current flows from the write wire 942, through the PN diode 931 (P-type region below and N-type region above), then through the connecting conductive unit 972, then through memory cell 95, and finally to the select wire 96. During this process, the crystal state of the material in memory cell 95, the magnetization direction of the magnetic region, or the resistance value of the resistance change region are changed, thus writing data representing "0" into memory cell 95. The write wire 971 is electrically floating. In other non-volatile memory elements 90 that are not selected, the write wires 942 and 971 and the select wire 96 are, for example, electrically floating.

[0100] On the other hand, when a non-volatile memory element 90 is addressed and data representing "1" is written into memory cell 95, for example, by electrically connecting select wire 96 to the write voltage Vw and writing wire 971 to ground potential, a second current I1 is generated. This current flows from select wire 96 through memory cell 95, then through the second part 921 and the first part 941 connecting conductive unit 972 and conductive unit 94, and then through PN diode 932 (similar to PN diode 931, with the P-type region at the bottom and the N-type region at the top) to writing wire 971. During this process, the crystal state of the material of memory cell 95, the magnetization direction of the magnetic region, or the resistance value of the resistance change region are changed, thus writing data representing "1" into memory cell 95. Writing wire 942 is electrically floating, while in other non-volatile memory elements 90 that are not selected, writing wires 942 and 971 and select wire 96 are electrically floating.

[0101] In a preferred embodiment, when reading data from storage unit 95, for example, the select wire 96 is electrically connected to the read voltage Vr, and the data in storage unit 75 is determined to be "0" or "1" based on the voltage of the write wire 971.

[0102] Furthermore, for information on how to form a single-crystal silicon layer on a metal layer, please refer to US 2010 / 0044670A1. However, that application states that it can be applied to both PCRAM and MRAM devices. The statement that it can be applied to MRAM devices is incorrect, as MRAM devices require current in two different directions, which cannot be achieved with a single PN diode.

[0103] Figure 9D A schematic diagram showing one embodiment of the non-volatile memory device according to the present invention is shown. For example... Figure 9D As shown, and see also Figures 9A-9B The non-volatile memory device 9 includes: a non-volatile memory element array 900 composed of a plurality of non-volatile memory elements 90; and a control circuit 910 for controlling the non-volatile memory element array 900 to perform read and write operations on the non-volatile memory elements 90; wherein the non-volatile memory elements 90, such as Figures 9A-9BAs shown, it includes: an insulating layer 92, which is electrically insulating; PN diodes 931 and 932, formed in a single-crystal silicon layer, a single-crystal germanium layer, or a single-crystal gallium arsenide layer on the insulating layer 92; write wires 942 and 971, which are conductive and are electrically connected to the front end 931a (P-type terminal in this embodiment) of PN diode 931 and the front end 932a (N-type terminal in this embodiment) of PN diode 932, respectively; a storage cell 95, located above PN diodes 931 and 932, and electrically connected to the rear ends 931b and 932b of PN diodes 931 and 932; and a selection wire 96, which is conductive, located on the storage cell 95, and electrically connected to the storage cell 95; when a non-volatile memory element 90 is selected to write data, a first current I0 flows through PN diode 931 to write the data into the storage cell 95. When non-volatile memory element 90 is selected to write another data, a second current I1 flows through PN diode 932 to write the other data into memory cell 95. In this embodiment, the first current I0 and the second current I1 flow in opposite directions through memory cell 95.

[0104] Figure 10 This diagram illustrates one embodiment of a non-volatile memory element according to the present invention. This embodiment is intended to illustrate the arrangement and connection of multiple non-volatile memory elements. Figure 10 As shown, non-volatile memory elements 90 and 90' share write lines 942 and 971, for example.

[0105] Figure 11A and 11B A 3D schematic diagram and operation table showing one embodiment of the non-volatile memory element according to the present invention are displayed. Figure 11A As shown, the non-volatile memory element 100 according to the present invention is a five-terminal element formed on a semiconductor substrate (not shown; please refer to other embodiments, such as...). Figure 9A The semiconductor substrate 91) includes a non-volatile memory element 100 comprising an insulating layer 102, write wires 1041, 1042, 1072 and 1073, PN diodes 1031, 1032, 1033 and 1034, conductor plugs 1021 and 1022, a memory cell 105, a select wire 106, and connecting conductive cells 1071, 1043 and 1044. The five terminals of the non-volatile memory element 100 are the write wires 1041 and 1042 and the select wire 106.

[0106] An insulating layer 102 is formed on a semiconductor substrate (not shown) and is electrically insulating. Write wires 1041, 1042, 1072, and 1073 are conductive. PN diodes 1031, 1032, 1033, and 1034 are unidirectionally conductive, for example, but not limited to, the PN diodes shown in the figure. A memory cell 105 is located above the PN diodes 1031, 1032, 1033, and 1034 and the connecting conductive cell 1071. A select wire 106 is located on the memory cell 105 and is electrically connected to the memory cell 105. When a non-volatile memory element 100 is selected to write data, a first current I0 flows through the PN diodes 1031 and 1032 to write the data into the memory cell 105. In this embodiment, the non-volatile memory element 100 is, for example, but not limited to, a spin orbit torque (SOT) MRAM element. When non-volatile memory element 100 is selected to write another data, a second current I1 flows through PN diodes 1033 and 1034 to write the other data into memory cell 105. This embodiment is applied, for example but not limited to, SOT-MRAM elements.

[0107] For example, such as Figure 11B As shown in the operation table, when the non-volatile memory element 100 is addressed and data representing "0" is written into the memory cell 105, for example, the write wire 1041 is electrically connected to the write voltage Vw and the write wire 1072 is electrically connected to the ground potential, thereby generating a first current I0. This current flows from the write wire 1041 through the PN diode 1031 (P-type region below and N-type region above), then through the connecting conductive unit 1071, then through the conductor plug 1021, then through the connecting conductive unit 1043, then through the PN diode 1032, and finally to the write wire 1072. During this process, the first current I0 flows through the connecting conductive unit 1071, which is electrically connected to the electrode in the memory cell 105, to change the magnetization direction of the magnetic region, thereby writing the data representing "0" into the memory cell 105. Write lines 1042 and 1073 are electrically floated with select line 106, while in other unselected non-volatile memory elements 100, write lines 1041, 1042, 1072 and 1073 are electrically floated with select line 106, for example.

[0108] On the other hand, when the non-volatile memory element 100 is addressed and data representing "1" is written into the memory cell 105, for example, the write wire 1042 is electrically connected to the write voltage Vw and the write wire 1073 is electrically connected to the ground potential, thereby generating a second current I1. This current flows from the write wire 1042 through the PN diode 1033 (P-type region below and N-type region above), then through the connecting conductive unit 1071, then through the conductor plug 1022, then through the connecting conductive unit 1044, then through the PN diode 1034, and finally to the write wire 1073. During this process, the second current I1 flows through the connecting conductive unit 1071, which is electrically connected to the electrode in the memory cell 105, but in the opposite direction to the current direction of the aforementioned process of writing data representing "0", so as to change the magnetization direction of the magnetic region and write the data representing "1" into the memory cell 105. Write lines 1041 and 1072 are electrically floated with select line 106, while in other unselected non-volatile memory elements 100, write lines 1041, 1042, 1072 and 1073 are electrically floated with select line 106, for example.

[0109] In a preferred embodiment, when reading data from storage unit 105, for example, the select wire 106 is electrically connected to the read voltage Vr, and the data in storage unit 75 is determined to be "0" or "1" based on the voltage of the write wire 1042.

[0110] Figure 11C A schematic diagram showing one embodiment of the non-volatile memory device according to the present invention is shown. For example... Figure 11C As shown, and see also Figure 11A A non-volatile memory device 101 includes: a non-volatile memory element array 1000, composed of a plurality of non-volatile memory elements 100; and a control circuit 1100 for controlling the non-volatile memory element array 1000 to perform read and write operations on the non-volatile memory elements 100; wherein, the non-volatile memory elements 100 are, for example... Figure 11AAs shown, it includes: an insulating layer 102, which is electrically insulating; PN diodes 1031, 1032, 1033, and 1034, formed in a single-crystal silicon layer, a single-crystal germanium layer, or a single-crystal gallium arsenide layer on the insulating layer 102; and write wires 1041, 1042, 1072, and 1073, which are conductive, and the write wires 1041, 1042, 1072, and 1073 are respectively connected to the front end of PN diode 1031 (P-type terminal in this embodiment), the front end of PN diode 1033 (P-type terminal in this embodiment), and the front end of PN diode 1032 (P-type terminal in this embodiment). The N-type terminal is electrically connected to the front end (N-type terminal in this embodiment) of the PN diode 1034; the storage cell 105 is located above the PN diodes 91031, 1032, 1033 and 1034, and the storage cell 105 is electrically connected to the rear end of the PN diodes 1031 and 1033; and the selection wire 106 is conductive, located on the storage cell 105, and electrically connected to the storage cell 105; when the non-volatile memory element 105 is selected to write a data, a first current I0 flows through the PN diodes 1031 and 1032 to write the data into the storage cell 105. When the non-volatile memory element 105 is selected to write another data, a second current I1 flows through the PN diodes 1033 and 1034 to write the other data into the storage cell 105.

[0111] The present invention has been described above with reference to preferred embodiments. However, the above description is only intended to facilitate understanding of the invention by those skilled in the art and is not intended to limit the scope of the invention. Various equivalent changes can be conceived by those skilled in the art within the same spirit of the invention. For example, other process steps or structures may be added without affecting the main characteristics of the components. All such variations can be deduced by analogy from the teachings of the present invention. Furthermore, the described embodiments are not limited to individual application and can also be used in combination, such as, but not limited to, using two embodiments together. Therefore, the scope of the invention should cover the above and all other equivalent changes. Moreover, no embodiment of the invention is required to achieve all the objectives or advantages; therefore, no claim should be limited thereto.

Claims

1. A non-volatile memory element, comprising: An insulating layer, which provides electrical insulation; A first PN diode is formed in a single-crystal silicon layer, a single-crystal germanium layer, or a single-crystal gallium arsenide layer on the insulating layer; A first write wire is conductive and is electrically connected to a first front end of the first PN diode; A memory cell is located on the first PN diode, and the memory cell is electrically connected to a first rear end of the first PN diode; A selection wire, which is conductive, is located on the memory cell and is electrically connected to the memory cell; A second PN diode is located in the monocrystalline silicon layer, monocrystalline germanium layer, or monocrystalline gallium arsenide layer on the insulating layer; A second write wire is conductive and is electrically connected to a second front end of the second PN diode; A first conductive connection unit for electrically connecting the memory cell to the first rear end of the first PN diode, wherein a portion of the first conductive connection unit is stacked and connected to the first rear end; and A second conductive unit is provided for electrically connecting the first conductive unit to a second rear end of the second PN diode, thereby electrically connecting the memory cell to the second rear end. in, When the non-volatile memory element is selected to write a first data, a first current flows through the first PN diode to write the first data into the memory cell. When the non-volatile memory element is selected to write a second data, a second current flows through the second PN diode to write the second data into the memory cell. The first write wire is stacked and connected to the insulating layer, the first front end is stacked and connected to the first write wire, and the first rear end is stacked and connected to the first front end; A first portion of the second conductive unit is stacked and connected to the insulating layer, a second portion of the second conductive unit is stacked and connected to the first portion, and another portion of the first conductive unit is stacked and connected to the second portion. The second back end is stacked and connected to the first part, the second front end is stacked and connected to the second back end, and the second write wire is stacked and connected to the second front end; The first write wire and the first portion are formed by the same metal deposition process step; The first front end and the second rear end are formed by the same ion implantation process or by the same epitaxial process. The first back end and the second front end are formed by the same ion implantation process or by the same epitaxial process.

2. The non-volatile memory element as claimed in claim 1, wherein, The second PN diode is stacked and connected to the insulating layer.

3. The non-volatile memory element as claimed in claim 1, wherein the second connecting conductive unit is electrically connected between the second PN diode and the memory cell to electrically connect the memory cell to a second rear end of the second PN diode.

4. The non-volatile memory element according to any one of claims 1 to 3, wherein, The non-volatile memory element is a phase-change random access memory, a magnetoresistive random access memory, or a resistive random access memory.

5. The non-volatile memory element according to any one of claims 1 to 3, wherein, The first writing conductor is a metal conductor.

6. The non-volatile memory element according to any one of claims 1 to 2, wherein, The first write wire and the second write wire are metal wires.

7. The non-volatile memory element according to any one of claims 1 to 3, wherein, The non-volatile memory element is formed on a semiconductor substrate on an insulating layer or a semiconductor substrate on an insulating-metal layer.

8. The non-volatile memory element as claimed in claim 1, wherein, The first conductive connection unit and the second write wire are formed by the same metal deposition process step.

9. A non-volatile memory device, comprising: An array of non-volatile memory elements, consisting of multiple non-volatile memory elements; as well as A control circuit is used to control the array of non-volatile memory elements and to perform read and write operations on the non-volatile memory elements. in, The non-volatile memory element includes: An insulating layer, which provides electrical insulation; A first PN diode is formed in a single-crystal silicon layer, a single-crystal germanium layer, or a single-crystal gallium arsenide layer on the insulating layer; A first write wire is conductive and is electrically connected to a first front end of the first PN diode; A memory cell is located on the first PN diode, and the memory cell is electrically connected to a first rear end of the first PN diode; A selection wire, which is conductive, is located on the memory cell and is electrically connected to the memory cell; A second PN diode is located in the monocrystalline silicon layer, monocrystalline germanium layer, or monocrystalline gallium arsenide layer on the insulating layer; A second write wire is conductive and is electrically connected to a second front end of the second PN diode; A first conductive connection unit for electrically connecting the memory cell to the first rear end of the first PN diode, wherein a portion of the first conductive connection unit is stacked and connected to the first rear end; and A second conductive unit is provided for electrically connecting the first conductive unit to a second rear end of the second PN diode, thereby electrically connecting the memory cell to the second rear end. When the non-volatile memory element is selected to write a first data, a first current flows through the first PN diode to write the first data into the memory cell. When the non-volatile memory element is selected to write a second data, a second current flows through the second PN diode to write the second data into the memory cell. The first write wire is stacked and connected to the insulating layer, the first front end is stacked and connected to the first write wire, and the first rear end is stacked and connected to the first front end; A first portion of the second conductive unit is stacked and connected to the insulating layer, a second portion of the second conductive unit is stacked and connected to the first portion, and another portion of the first conductive unit is stacked and connected to the second portion. The second back end is stacked and connected to the first part, the second front end is stacked and connected to the second back end, and the second write wire is stacked and connected to the second front end; The first write wire and the first portion are formed by the same metal deposition process step; The first front end and the second rear end are formed by the same ion implantation process or by the same epitaxial process. The first back end and the second front end are formed by the same ion implantation process or by the same epitaxial process.

10. The non-volatile memory device of claim 9, wherein, The second PN diode is stacked and connected to the insulating layer.

11. The non-volatile memory device of claim 9, wherein the second connection conductive unit is electrically connected between the second PN diode and the memory cell to electrically connect the memory cell to a second rear end of the second PN diode.

12. The non-volatile memory device of claim 9, wherein, The non-volatile memory element is a phase-change random access memory, a magnetoresistive random access memory, or a resistive random access memory.

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