Field effect transistor device and method of improving short channel effects and output characteristics thereof

Abstract

The present application provides a field effect transistor device and a method for improving short channel effect and output characteristics using the same, wherein the field effect transistor device includes an active layer including a source region, a drain region, and a channel region between the source region and the drain region; when the device is turned on, an effective channel and an equivalent source and / or an equivalent drain away from the effective channel are formed in the channel region, and the field effect transistor device forms a working current by connecting the source region and the drain region through the effective channel, and the equivalent source and / or the equivalent drain.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a field-effect transistor device and a method for improving its short-channel effect and output characteristics. Background Technology

[0002] With the development of integrated circuit technology, the gate length (corresponding to the channel length) of field-effect transistors (FETs) is constantly shrinking. Currently, VLSI chips based on submicron or even sub-10 nanometer gate length devices are already in mass production. For these small-sized devices, how to deal with their short-channel effect is a major challenge in device technology. The short-channel effect causes a comprehensive degradation of the threshold voltage and subthreshold characteristics of small-sized devices. Specifically, the device threshold voltage is no longer constant, but decreases with decreasing channel length and decreases with increasing drain voltage; the slope of the subthreshold region of the device transfer characteristics also deteriorates simultaneously.

[0003] Currently, methods to improve the short-channel effect of field-effect transistors mainly include FinFETs, silicon-on-insulator (SOI), lightly doped drain (LDD) structures, and metal-source-drain Schottky barrier transistors (SB MOSFETs). ① FinFETs use a 3D fin-shaped channel region and a three-sided gate-around structure. The two side gates enhance the gate's control over the channel, effectively suppressing the short-channel effect. The fabrication process for this approach is much more complex than for planar devices. Currently, chips using technology nodes below 22nm mostly adopt the FinFET approach. ② SOI technology introduces a buried oxide layer between the silicon channel layer and the back substrate. Under conditions of a very thin and fully depleted channel layer, it can effectively suppress leakage current between the source and drain. The challenge of this approach lies in the very high cost of SOI silicon wafers. Currently, chips based on SOI at the 10nm technology node are already in mass production. ③ A lightly doped drain LDD is placed near the drain channel, while the source and drain regions far from the channel remain heavily doped. The drain PN junction formed by this lightly doped region reduces the impact of the drain voltage on the channel, making it the mainstream technology for submicron-level short-channel devices. In this scheme, both the on-state current and field-effect mobility of the device are reduced to some extent by the LDD. ④ The operating current of a Schottky barrier transistor is the tunneling current of the Schottky barrier between the metal source and the semiconductor channel. It is not sensitive to short-channel effects. This scheme is more difficult to fabricate, has limited choices of barrier materials, and it is difficult to simultaneously suppress the off-state current of the device.

[0004] On the other hand, the kink effect appearing on the output characteristic curve of short-channel devices has also attracted much attention. When the device operates in saturation, the high drain voltage depletes the drain terminal and forms a high electric field region. Carriers are prone to collisional ionization here and are amplified by coupling with the parasitic bipolar transistors of the MOS device. This causes the drain current to increase rapidly with the increase of the drain voltage, forming the so-called kink current. The output characteristic curve of the device is significantly warped, which seriously affects the normal output characteristics.

[0005] Common methods to mitigate the kink effect include increasing the device channel length and using lightly doped drain (LDD) structures. Increasing the channel length reduces the impact of carriers generated by drain collisional ionization on the source, weakening parasitic transistor effects and alleviating the kink effect. However, increasing the channel length will correspondingly reduce the device's output current. LDD structures can reduce the peak electric field intensity in the drain depletion region, weakening the carrier collisional ionization effect and thus suppressing the kink effect. However, LDD structures introduce additional parasitic resistance, reducing the device's field-effect mobility and on-state current. Summary of the Invention

[0006] In view of this, the object of the present invention is to provide a field-effect transistor device and a method for improving its short-channel effect and output characteristics.

[0007] To achieve the above objectives, an embodiment of the present invention provides the following technical solution:

[0008] A field-effect transistor device includes an active layer, the active layer including a source region, a drain region, and a channel region located between the source region and the drain region;

[0009] When the device is turned on, an effective channel and an equivalent source and / or equivalent drain are formed in the channel region. The field-effect transistor device connects the source region and the drain region through the effective channel and the equivalent source and / or equivalent drain to form an operating current.

[0010] In one embodiment, a conductive region that does not connect the source region and the drain region is formed in the channel region; wherein,

[0011] When the conductive region is connected to the source region, the conductive region constitutes the equivalent source; and / or,

[0012] When the conductive region is connected to the drain region, the conductive region constitutes the equivalent drain.

[0013] In one embodiment, a first gate is disposed on one surface of the active layer, the first gate and the conductive region having overlapping vertical projections onto the channel region; wherein the first gate can control the channel region and form a channel therein, and the portion of the channel that does not overlap with the vertical projection of the conductive region onto the channel region constitutes the effective channel; and / or,

[0014] The conductive region and the effective channel are spaced apart in the thickness direction of the channel region.

[0015] In one embodiment, when the device is turned on, the conductivity of the conductive region is greater than the conductivity of the remaining portion of the channel excluding the effective channel, so that at least one of the conductive region and the effective channel can inject carriers into the other; preferably, the conductivity of the conductive region is at least three times greater than the conductivity of the remaining portion of the channel excluding the effective channel;

[0016] And / or, the field-effect transistor device is a planar structure device or a vertical structure device.

[0017] In one embodiment, when the device is turned on, the conductance per unit length of the effective channel in the channel is greater than the conductance per unit length of the remaining portion of the channel excluding the effective channel; preferably,

[0018] The field-effect transistor device includes a gate insulating layer disposed between the first gate and the channel region, wherein the thickness of the portion of the gate insulating layer corresponding to the effective channel is less than the thickness of the remaining portion of the gate insulating layer; and / or,

[0019] The portion of the gate insulation layer corresponding to the effective channel and the remaining portion are made of materials with different work functions; and / or,

[0020] The portion of the first gate corresponding to the effective channel and the remaining portion of the first gate are made of materials with different work functions; preferably,

[0021] When the device is turned on, the conductivity per unit length of the effective channel in the channel is at least three times greater than the conductivity per unit length of the remaining portion of the channel excluding the effective channel.

[0022] In one embodiment, a second gate is further provided on the surface of the active layer adjacent to the conductive region, the second gate being capable of controlling the formation of the conductive region in the channel region.

[0023] In one embodiment, the conductive region is formed by carriers introduced by doping on the surface of the channel region on the side away from the effective channel.

[0024] In one embodiment, an insulating layer is further disposed on the surface of the active layer away from the effective channel, and the conductive region is composed of charge carriers generated by injected charges in the insulating layer through electrostatic induction in the channel region near the insulating layer.

[0025] In one embodiment, a semiconductor material layer is further included on the surface of the active layer away from the effective channel, the active layer and the semiconductor material layer forming a heterostructure, and the conductive region is composed of two-dimensional electron gas channels or two-dimensional hole gas channels distributed in the heterostructure; and / or,

[0026] The conductive region is formed by surface treatment of the side of the channel region away from the effective channel, creating a two-dimensional electron gas channel or a two-dimensional hole gas channel.

[0027] In one embodiment, the source and drain regions are doped semiconductor or Schottky metal source / drain regions; and / or,

[0028] The gate of the field-effect transistor device is a metal-insulator-semiconductor MOS structure gate or a Schottky junction gate; and / or,

[0029] The active layer comprises at least two semiconductor materials that vary along its thickness direction or its planar extension direction.

[0030] This application also provides a method for improving the short-channel effect and output characteristics of a field-effect transistor device. The method includes providing an equivalent source and / or equivalent drain in the channel region of the device that are far from the effective channel of the device, so that when the device is turned on, the effective channel connects the source region and the drain region of the device through the equivalent source and / or equivalent drain to form an operating current.

[0031] In the embodiments of this application, by configuring the device to form an effective channel in the channel region and an equivalent source and equivalent drain far away from the effective channel when turned on, the source region and the drain region are connected to form an operating current; in this way, the equivalent drain (source) connected to the drain (source) region is structurally far away from the effective channel, which can reduce the influence of the drain voltage on the effective channel; and reduce the peak electric field in the drain depletion region when the device is saturated, thereby suppressing the short-channel effect of the device and improving the output characteristics of the device. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 Schematic diagram of the state of forming an equivalent source, an equivalent drain, and an effective channel when a field - effect transistor device according to an embodiment of the present invention is in the on - state;

[0034] Figure 2 Schematic diagram of the structure of a field - effect transistor device according to an embodiment of the present invention when in the on - state;

[0035] Figure 3 Schematic diagram of the state of forming a conductive region of a field - effect transistor device according to an embodiment of the present invention;

[0036] Figures 4 to 8 Schematic diagrams of the structures of field - effect transistor devices according to various embodiments of the present invention

[0037] Figures 9 to 16 Schematic diagram of the principle of fabricating a conductive region in various embodiments of the present invention;

[0038] Figures 17 to 19 Schematic diagram of the structure of a SOI device applying the solution of the present invention;

[0039] Figure 20 Schematic diagram of the structure where there is a gap between the vertical projection of the effective channel and the conductive region of a field - effect transistor device according to an embodiment of the present invention in the channel region;

[0040] Figures 21 to 22 To are the comparison diagrams of the transfer characteristics between the SOI device applying the solution of the present invention and a common SOI device;

[0041] Figures 23 to 24 Comparison diagram of the output characteristics between the SOI device applying the solution of the present invention and a common SOI device. Specific embodiments

[0042] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0043] Refer Figure 1 , and a specific embodiment of the field - effect transistor device 100 of the present application will be introduced. In this embodiment, the field - effect transistor device 100 includes an active layer 10, and the active layer 10 includes a source region 101, a drain region 102, and a channel region 103.

[0044] The source region 101 and drain region 102 are located on opposite sides of the active layer 10, and the channel region 103 is located between the source region 101 and the drain region 102. Figure 1 The schematic diagram shown illustrates the device when it is turned on. At this time, an effective channel 1041 is formed in the channel region 103 of the field-effect transistor, along with an equivalent source 1051 and an equivalent drain 1052 located away from the effective channel 1041. The field-effect transistor device 100 connects the source region 101 and the drain region 102 through the effective channel 1041, the equivalent source 1051, and the equivalent drain 1052 to form an operating current.

[0045] The "distance" between the effective channel 1041 and the equivalent source 1051 and equivalent drain 1052 mentioned in this application can refer to a gap in the thickness direction of the channel region 103, or a gap in both the thickness direction of the channel region 103 and the vertical projection of the channel region 103.

[0046] In a typical field-effect transistor device 100, the source region 101 in the active region is used to provide charge carriers when the device is turned on, while the drain region 102 is used to collect the charge carriers provided by the source region 101. Correspondingly, in this application, the equivalent source 1051 refers to a structure in which the charge carriers provided by the source region 101 are directly injected into the effective channel 1041, while the equivalent drain 1052 refers to a structure in which charge carriers are directly received from the effective channel 1041 and injected into the drain region 102.

[0047] Reference Figure 2 In this application, the "effective channel 1041" refers to the channel that contributes the main carrier path when the device is turned on. Taking this embodiment as an example, a first gate 20 can be disposed on one side surface of the active layer 10, and there is no gap between the vertical projection of the first gate 20 on the active layer 10 and the source region 101 and the drain region 102. Therefore, when a gate bias voltage is applied to the first gate 20 to turn on the device, a channel 104 can be controlled to be formed below the first gate 20, and the channel 104 is structurally connected to the source region 101 and the drain region 102. However, from a functional point of view, only the part of the channel that does not overlap with the vertical projection of the equivalent source 1051 and the equivalent drain 1052 on the channel region 103 is used to transmit the operating current, and therefore only this part of the channel is called the "effective channel 1041" here.

[0048] The arrangement of the equivalent source 1051 and equivalent drain 1052 effectively shortens the length of the channel portion capable of conducting operating current, thus creating a gap between the effective channel 1041 and the source region 101 and drain region 102. Furthermore, the equivalent drain 1052, connected to the drain region 102, is structurally located away from the effective channel 1041, reducing the influence of the drain potential on the effective channel 1041. Similarly, the equivalent source 1051, connected to the source region 101, is structurally located away from the effective channel 1041, also reducing the influence of the drain potential on the effective channel 1041, thereby improving the short-channel effect of the device.

[0049] Reference Figure 3 In the specific fabrication of the equivalent source 1051 and the equivalent drain 1052, a conductive region A that does not connect the source region 101 and the drain region 102 can be formed in the channel region 103. When the conductive region A is connected to the source region 101, this part of the conductive region A constitutes the equivalent source 1051; when the conductive region A is connected to the drain region 102, this part of the conductive region A constitutes the equivalent drain 1052.

[0050] When the device is turned on, the conductivity of conductive region A is set to be greater than the conductivity of the remaining portion 1042 of channel 104 excluding the effective channel 1041, so that carriers can be injected into each other between conductive region A and the effective channel 1041. In this way, carriers in source region 101 will be attracted by the equivalent source 1051 with greater conductivity, and will not be directly injected into the remaining portion 1042 of channel 104 directly connected to source region 101; similarly, carriers transported in effective channel 1041 will also be attracted by the equivalent drain 1052, and will not continue to be transported through the remaining portion 1042 of channel 104. In the formation of the operating current in this embodiment, the charge carriers provided by the source region 101 enter the equivalent source 1051 and are injected into the effective channel 1041 from the end of the equivalent source 1051 away from the source region 101; the charge carriers flowing through the effective channel 1041 are injected into the equivalent drain 1052 at the end near the equivalent drain 1052, and finally injected into the drain region 102.

[0051] To achieve the carrier injection configuration between the equivalent source 1051, equivalent drain 1052, and effective channel 1041, the conductivity of conductive region A can be set to be at least three times greater than the conductivity of the remaining portion 1042 of channel 104 excluding effective channel 1041. Furthermore, since carriers flow through the thickness direction of channel region 103 during the aforementioned "injection" process, the spacing between conductive region A and effective channel 1041 in the thickness direction of channel region 103 in this embodiment can be set to 1 nm to 10 μm, or more preferably 3 nm to 1 μm, or more preferably 5 nm to 100 nm, depending on the specific design of different devices, to ensure normal carrier injection and device performance.

[0052] It should be noted that the "carriers" mentioned in this application refer to the charged particles that can move freely in the corresponding polar channel / conductive region A. Generally, we refer to the electrons in the N-type channel or the holes in the P-type channel as the "carriers" here. Correspondingly, the holes in the N-type channel or the electrons in the P-type channel are not referred to as the "carriers" here. Therefore, in this application, the polarities of the effective channel 1041 and the conductive region A are set to be the same, so that the carrier interaction between the two channels can ultimately substantially contribute to the working current of the device.

[0053] Refer Figure 4 , and introduce another embodiment of the field effect transistor device 200 of this application.

[0054] Different from the above embodiment, in this embodiment, when the device is turned on, an equivalent drain is not formed in the channel region 103 at this time. The field effect transistor device 200 connects the source region 101 and the drain region 102 through the effective channel 1041 and the equivalent source 1051 to form a working current.

[0055] In this embodiment, it is equivalent to only weakening the influence of the drain terminal potential on the potential near the source end of the channel region 103 through the setting of the equivalent source 1051, thereby improving the short-channel effect of the device. Correspondingly, the effective channel 1041 is directly connected to the drain region 102.

[0056] In carrier transport, the carriers provided by the source region 101 enter the equivalent source 1051, and are injected into the effective channel 1041 from the end of the equivalent source 1051 far from the source region 101; the carriers flowing through the effective channel 1041 are then injected back into the drain region 102. That is, in this embodiment, only the conductive region injects carriers into the effective channel 1041 unidirectionally.

[0057] Refer Figure 5 , and introduce another embodiment of the field effect transistor device 300 of this application.

[0058] Different from the above embodiment, in this embodiment, when the device is turned on, an equivalent source is not formed in the channel region 103 at this time. The field effect transistor device 300 connects the source region 101 and the drain region 102 through the effective channel 1041 and the equivalent drain 1052 to form a working current.

[0059] In this embodiment, it is equivalent to only weakening the influence of the drain terminal potential on the effective channel 1041 through the setting of the equivalent drain 1052, thereby improving the short-channel effect of the device. Correspondingly, the effective channel 1041 is directly connected to the source region.

[0060] In carrier transport, carriers provided by the source region 101 enter the effective channel 1041, are injected into the equivalent drain 1052 from one end of the effective channel 1041 away from the source region 101, and then injected back into the drain region 102. That is, in this embodiment, only the effective channel 1041 injects carriers into the conductive region unidirectionally.

[0061] In the above embodiment, a structure in which a part of the channel formed by gate control constitutes the effective channel has been shown. In such a structure, in order to further improve the short-channel effect of the device, the unit length conductance of the effective channel in the channel can be set to be greater than the unit length conductance of the other parts of the channel except the effective channel. Some corresponding embodiments are introduced below.

[0062] Refer Figure 6 , and introduce another embodiment of the field effect transistor device 400 of the present application.

[0063] The field effect transistor device 400 includes an active layer 10, and the active layer includes a source region 101, a drain region 102, and a channel region 103. The source region 101 and the drain region 102 are respectively located on both sides of the active layer 10, and the channel region 103 is located between the source region 101 and the drain region 102.

[0064] An insulating layer 30 and a first gate 20 are sequentially provided above the channel region, and the thickness of the gate insulating layer 1041 corresponding to the effective channel 104 is less than the thickness of the gate insulating layer 1042 of the other parts. That is, the gate insulating layer 1042 corresponding to the equivalent source 1051 and the equivalent drain 1052 is thickened. In this way, the modulation ability of the gate corresponding to the other parts of the channel 1042 outside the effective channel 1041 to the corresponding part of the channel 1042 can be weakened, so that the unit length conductance of the corresponding part of the channel 1042 increases.

[0065] Cooperatively, the unit length conductance of the effective channel in the channel can also be made greater than the unit length conductance of the other parts by adjusting the materials (work functions) of the insulating layer corresponding to the effective channel part and the other parts of the insulating layer.

[0066] Refer Figure 7 , and introduce another embodiment of the field effect transistor device 500 of the present application.

[0067] The field effect transistor device 500 includes an active layer 10, and the active layer 10 includes a source region 101, a drain region 102, and a channel region 103. The source region 101 and the drain region 102 are respectively located on both sides of the active layer 10, and the channel region 103 is located between the source region 101 and the drain region 102.

[0068] Above the channel region 103, a first gate 20 is provided. Moreover, the portion 201 of the first gate 20 corresponding to the effective channel 1041 and the remaining portion 202 are made of different materials, so that the portion 201 of the first gate 20 corresponding to the effective channel 201 and the remaining portion 202 have different modulation capabilities for the corresponding formed channel, and the unit length conductance of the effective channel 1041 is greater than the unit length conductance of the remaining portion 1042 of the channel 104 except the effective channel 1041.

[0069] Specifically, if it is an N-type device, the portion 201 of the first gate 20 corresponding to the effective channel 1041 can use a metal with a smaller work function such as aluminum, hafnium, titanium, or N-type doped (n+) polysilicon, or Ru-Hf, WN, HfN, TiN, TaN, TaSiN, etc. with a smaller work function obtained by adjusting the compound composition as the gate material; the remaining portion 202 can use a metal with a larger work function such as gold, platinum, or P-type doped (P+) polysilicon, or ITO, RuO2, WN, MoN, etc. with a larger work function obtained by adjusting the compound composition as the gate material. If it is a P-type device, the portion 201 of the first gate 20 corresponding to the effective channel 1041 can use a metal with a larger work function such as gold, platinum, or P-type doped (P+) polysilicon, or ITO, RuO2, WN, MoN, etc. with a larger work function obtained by adjusting the compound composition as the gate material; the remaining portion 202 can use a metal with a smaller work function such as aluminum, hafnium, titanium, or N-type doped (n+) polysilicon, or Ru-Hf, WN, HfN, TiN, TaN, TaSiN, etc. with a smaller work function obtained by adjusting the compound composition as the gate material.

[0070] Refer Figure 8 , in some alternative embodiments, the first gate 20 can also be provided only on one surface of the channel region between the equivalent source 1051 and the equivalent drain 1052. In this way, even when a bias voltage that can turn on the device is applied to the first gate 20, a channel that structurally connects the source region and the drain region will not be formed below the first gate 20 (as Figure 8 shown, the channel 1041 controlled by the first gate 20 at this time does not connect the source region 101 and the drain region 102). That is, the channel 1041 formed by the first gate 20 in the channel region 103 is the above-mentioned "effective channel".

[0071] In the above embodiments, when the device is turned on, the unit length conductance of the effective channel in the channel can preferably be set to be at least three times greater than the unit length conductance of the remaining portion of the channel except the effective channel.

[0072] The following introduces the formation method of the conductive region in this application with some specific embodiments:

[0073] Example 1

[0074] The conductive region A is formed by carriers introduced by surface doping of the channel region 103A on the side away from the effective channel 1041A.

[0075] Correspondingly, refer to Figure 9 If it is an N-type silicon-based device 100A, the doping concentration at the interface can be changed by doping the surface of the channel region 103A away from the effective channel 1041A with donor atoms, such as phosphorus or arsenic; refer to Figure 10 If it is a P-type silicon-based device 100A, the doping concentration at the interface can be changed by doping acceptor atoms, such as boron, on the surface of the channel region 103A away from the effective channel 1041A.

[0076] Example 2

[0077] Coordination Figure 11 and Figure 12 The field-effect transistor device 100B also includes an insulating layer 40B disposed on the surface of the active layer 10B away from the effective channel 1041B. The conductive region A is formed on one side surface of the channel region by the injected charge in the insulating layer 40B through electrostatic induction.

[0078] Correspondingly, participants Figure 11 If it is an N-type device, positive charges can be injected locally into the insulating layer 40B, such as H. + Hole realization; reference Figure 12 If it is a P-type device, negative charges can be injected locally into the insulating layer 40B, for example, F. - Cl - This is achieved through methods such as electron transport. In this way, a high density of fixed charges is formed in the insulating layer 40B, and through electrostatic induction, charge carriers for the conductive region A are generated in the channel region 103B adjacent to the insulating layer 40B. It should be noted that "local" here refers to the portion of the insulating layer 40B corresponding to the channel region where the conductive region A needs to be formed.

[0079] In the specific charge injection process, it is preferable to inject the charge into the insulating layer 40B at a position closer to the channel region 103B, so that the conductive region A formed in the channel region 103B can store more charge carriers. Of course, in some other alternative embodiments, a "double insulating layer" structure can also be adopted, specifically including a charge trapping layer disposed on the surface of the channel region 103B and a conventional insulating layer covering the charge trapping layer. The charge trapping layer can be made of a material that is easier to store charge, or metal or semiconductor nanoparticles can be introduced therein to store charge more stably, thereby ensuring the stability and controllability of charge carriers in the conductive region.

[0080] Example 3

[0081] Reference Figure 13 Figure 13 , the field effect transistor device 100C includes a semiconductor material layer 40C disposed on the active layer 10C. The semiconductor material layer 40C and the active layer 10C form a heterostructure, and the conductive region A is formed by a two-dimensional electron gas channel or a two-dimensional hole gas channel distributed in the heterostructure.

[0082] Specifically, the semiconductor material layer 40C and the active layer 10C have different bandgap widths. The semiconductor material layer 40C can be divided into two parts respectively connected to the source region 101C and the drain region 102C, so that the formed two-dimensional electron gas channel does not conduct the source and drain regions.

[0083] Of course, in some alternative embodiments, for example, the channel region 103C can be surface-treated to form a two-dimensional electron gas channel or a two-dimensional hole gas channel. These alternative embodiments of forming a two-dimensional electron gas channel or a two-dimensional hole gas channel known to those skilled in the art should all fall within the protection scope of this application. And, the semiconductor material layer 40C mentioned here can be a barrier layer, and the barrier layer can be doped or intrinsic.

[0084] Embodiment 4

[0085] Reference Figure 14 Figure 14 , the field effect transistor device 100D is fabricated as a device having at least two gates. Specifically, the field effect transistor device 100D includes a first gate insulating layer 30D and a first gate 20D sequentially disposed on one surface of the active layer 10D, and a second gate insulating layer 40D and a second gate 50D sequentially disposed on the surface of the active layer 10D adjacent to the conductive region A.

[0086] The second gate 50D is correspondingly divided into two parts. One part is connected to the source region 101D by the vertical projection on the active layer 10D, and the other part is connected to the drain region 102D by the vertical projection on the active layer 10D. Thus, when appropriate bias voltages are applied to these two parts of the second gate 50D, conductive regions A connecting the source region 101D and the conductive region A connecting the drain region 102D can be respectively formed at corresponding positions in the channel region 103D.

[0087] In this embodiment, the absolute value of the bias voltage applied to the second gate 50D should be greater than the absolute value of the turn-on voltage applied to the device. Correspondingly, if it is an N-type device, a positive bias voltage greater than the first gate 20D is applied to the second gate 50D; if it is a P-type device, a negative bias voltage with an absolute value greater than the first gate 20D is applied to the second gate 50D.

[0088] Embodiment 5

[0089] Reference Figure 15, the field-effect transistor device 100E is fabricated to include at least two gates similar to Example 4. However, the difference is that in this embodiment, in order to make the conductance of the conductive region A greater than that of the portion 1042E of the channel 104E other than the effective channel 1041E, the first gate 20E and the second gate 50E with different work function gate materials can be adopted. That is: the work function difference between the first gate 20E and the active layer 10E, and the work function difference between the second gate 50E and the active layer 10E are not equal to achieve this.

[0090] Correspondingly, if it is an N-type device, the first gate 20E can adopt metals with a larger work function such as gold, platinum, or P-type doped (P+) polysilicon, or ITO, RuO2, WN, MoN, etc. with a larger work function obtained by adjusting the compound composition as the gate material; the second gate 50E can adopt metals with a smaller work function such as aluminum, hafnium, titanium, or N-type doped (n+) polysilicon, or Ru-Hf, WN, HfN, TiN, TaN, TaSiN, etc. with a smaller work function obtained by adjusting the compound composition as the gate material. If it is a P-type device, the first gate 20E can adopt metals with a smaller work function such as aluminum, hafnium, titanium, or N-type doped (n+) polysilicon, or Ru-Hf, WN, HfN, TiN, TaN, TaSiN, etc. with a smaller work function obtained by adjusting the compound composition as the gate material; the second gate 50E can adopt metals with a larger work function such as gold, platinum, or P-type doped (P+) polysilicon, or ITO, RuO2, WN, MoN, etc. with a larger work function obtained by adjusting the compound composition as the gate material.

[0091] Preferably, in an N-type device, the work function difference between the first gate 20E and the active layer 10E can be set to be greater than zero (Φms > 0V), so that the channel 104E is an enhancement-mode channel; at the same time, the work function difference between the second gate 50E and the active layer 10E is set to be less than zero (Φms < 0V), so that when the device is in the off state, a certain number of carriers can be formed in the conductive region A under the action of the bias voltage applied thereto. In a P-type device, the work function difference between the first gate 20E and the active layer can be set to be less than zero (Φms < 0V), so that the channel 104E is an enhancement-mode channel; at the same time, the work function difference between the second gate 50E and the active layer 10E is set to be greater than zero (Φms > 0V), so that when the device is in the off state, a certain number of carriers can be formed in the conductive region A under the action of the bias voltage applied thereto.

[0092] Example 6

[0093] Refer Figure 16, the field effect transistor device 100F is fabricated to include at least two gates 20F and 50F similar to those in Embodiment 4. However, the difference is that in this embodiment, in order to make the conductance of the conductive region A greater than that of the part 1042F in the channel 104F except the effective channel 1041F, the capacitance per unit area of the second gate insulating layer 40F can be set to be greater than that of the first gate insulating layer 30F.

[0094] Specifically, it can be achieved by regulating the dielectric constants of the first gate insulating layer 30F and the second gate insulating layer 40F, or the thicknesses of the first gate insulating layer 30F and the second gate insulating layer 40F.

[0095] For example, when the thicknesses of the first gate insulating layer 30F and the second gate insulating layer 40F are equal, only the dielectric constant factor of the gate insulating layer needs to be considered, and it is only necessary to set the dielectric constant of the second gate insulating layer 40F to be higher than that of the first gate insulating layer 30F. Demonstratively, the first gate insulating layer 30F can be made of silicon dioxide, and the second gate insulating layer 40F can be made of a high-k dielectric such as hafnium dioxide, aluminum oxide, etc.

[0096] Also, for example, when the materials of the first gate insulating layer 30F and the second gate insulating layer 40F are the same, only the thickness factor of the gate insulating layer needs to be considered, and the thickness of the second gate insulating layer 40F can be set to be less than that of the first gate insulating layer 30F.

[0097] In specific device applications, the second gate in the above Embodiments 4 to 6 can also be directly floating or grounded to avoid increasing the complexity of device applications due to excessive device connection terminals.

[0098] Moreover, the methods of forming the conductive regions in the above embodiments can also be applied in combination with each other to achieve better implementation effects.

[0099] The field effect transistor devices introduced in the above embodiments / mode of implementation can be planar structure devices or vertical structure devices. Hereinafter, taking a SOI device (TFT device) as an example, the specific settings of the solution of the present application when applied to a SOI device will be demonstratively described.

[0100] Embodiment 7

[0101] Refer Figure 17 , it is a planar top-gate structure TFT device 100G, and includes a light-transmissive insulating substrate 40G, and an active layer 10G, a gate dielectric layer 30G, and a gate 20G sequentially disposed on the substrate 40G. Source regions 101G and drain regions 102G are respectively doped on both sides of the active layer 10G, and source electrodes and drain electrodes are respectively externally connected; a channel region 103G is located between the source regions 101G and the drain regions 10G.

[0102] On the substrate 40G, positive charge regions 60G are formed on both sides of the source region 101G and the drain region 102G by means of ion implantation or the like. There is an overlapping portion between the vertical projection of the positive charge region 60G and the gate 20G in the channel region 103G. Correspondingly, the positive charge region in this overlapping portion can form a two-dimensional electron gas 70G that is respectively connected to the source region 101G and the drain region 102G in the channel region 103G. Here, the two-dimensional electron gas 70G constitutes the conducting region.

[0103] When the device is turned on, a channel is formed under the gate 20G, and the portion of the channel whose vertical projection is located between the conducting regions constitutes the actual effective channel.

[0104] Example 8

[0105] See Figure 18 , for a planar bottom-gate structure TFT device 100H, which includes a light-transmitting insulating substrate 40H, and a gate 20H, a gate dielectric layer 30H, and an active layer 10H that are sequentially disposed on the substrate 40H. In this embodiment, an upper-layer metal source electrode 501H and a metal drain electrode 502H are respectively disposed on both sides of the active layer 10H. The active layer 10H can adopt an amorphous IGZO metal oxide semiconductor layer, and an ohmic contact is formed between the source electrode 501H and the drain electrode 502H and the active layer 10H. The portions of the active layer below the source electrode 501H and the drain electrode 502H respectively constitute the source region and the drain region, and the channel region is located between the source region and the drain region.

[0106] Positive charge regions 60H that are respectively connected to the source electrode 501H and the drain electrode 502H are formed by ion implantation in the passivation layer covering the upper layer of the device. There is an overlapping portion between the vertical projection of the positive charge region 60H and the gate 20H in the channel region. Correspondingly, the positive charge region in this overlapping portion can form a two-dimensional electron gas 70H that is respectively connected to the source region and the drain region in the channel region. Here, the two-dimensional electron gas 70H constitutes the conducting region.

[0107] When the device is turned on, a channel is formed above the gate 20H, and the portion of the channel whose vertical projection is located between the conducting regions 70H constitutes the actual effective channel.

[0108] Example 9

[0109] See Figure 19The device is a vertical SOI device 100I, comprising a substrate 60I, a buried insulating layer 50I and an active layer 10I sequentially disposed on the substrate 60I, a gate insulating layer 30I disposed on one side of the active layer 10I, and a gate 20I. In a direction away from the substrate 60I, a source region 101I and a drain region 102I are located below and above the active layer 10I, respectively. An equivalent source 1051I connected to the active region 101I and an equivalent drain 1052I connected to the drain region 102I are formed in the channel region 103I.

[0110] When a bias voltage is applied to the gate 20I of the device to turn it on, the gate 20I controls the formation of a channel 104I in the channel region 103I of the device, which connects the source region 101I and the drain region 102I. However, only the portion of the channel 104I that does not overlap with the equivalent source 1051I and the equivalent drain 1052I in the vertical projection on the channel region 103I constitutes an effective channel 1041I for transmitting the operating current when the device is turned on. That is, the remaining portion 1042I in the channel 104I is not used to transmit the operating current when the device is turned on.

[0111] In the above embodiments / examples, the source and drain regions in the device can be common heavily doped semiconductor sources and drains, or Schottky metal sources and drains of metal-semiconductor structures; the gate can be a common metal-insulator-semiconductor MOS structure gate, or a Schottky junction gate of a metal-semiconductor structure; the active layer can be composed of a single semiconductor material, or it can include at least two semiconductor materials that vary along its thickness direction or planar extension direction to form a composite channel.

[0112] Furthermore, the equivalent source and equivalent drain can be formed spontaneously or controlled by the gate structure of the corresponding structure.

[0113] In general, in the above embodiments, the vertical projection of the effective channel, equivalent source, and / or equivalent drain onto the channel region connects the source and drain regions, thereby ensuring that carriers from the effective channel and the equivalent source and / or equivalent drain can be injected unidirectionally or bidirectionally, at least in the thickness direction, and constructing a carrier pathway from the source region to the drain region. Of course, referring to... Figure 20This application does not exclude the possibility that, in some particular embodiments, if the vertical projection of the effective channel, equivalent source, and / or equivalent drain superimposed on the channel region 103J does not connect the source region 101J and the drain region 102J of the device 100J, but has an "appropriate gap" that does not completely cut off the flow of charge carriers from the equivalent source 1051J to the effective channel 1041J and from the effective channel 1041J to the equivalent drain 1052J, and the injection direction of charge carriers between the effective channel 1041J, the equivalent source 1051J, and the equivalent drain 1052J forms an angle with the thickness direction of the channel region 103J, such an implementation should also fall within the protection scope of this application.

[0114] This application also provides a specific embodiment of a method for improving the short-channel effect and output characteristics of a field-effect transistor device. In this embodiment, the method includes providing an equivalent source and / or equivalent drain in the channel region of the device, away from the effective channel of the device, so that when the device is turned on, the effective channel connects the source region and the drain region of the device through the equivalent source and / or equivalent drain to form an operating current.

[0115] Since the methods for improving short-channel effect and output characteristics described here are substantially the same as the structural implementation of the field-effect transistor device described above, they can be partially or wholly adapted from the content of the above structural implementation, and will not be repeated here.

[0116] The following are the simulation results of SOI devices using the embodiments / exemplifications described above in this application. In the simulation, devices with only an equivalent source, only an equivalent drain, and both equivalent source and equivalent drain are referred to as equivalent source devices, equivalent drain devices, and equivalent source-drain devices, respectively. In the simulation examples, the comparison objects for the above devices are conventional SOI devices, whose channel length is the same as the effective channel length of the device of this invention, and whose channel material and gate and other related parameters are kept consistent.

[0117] Simulation Example 1

[0118] Simulation software: Silvaco TCAD;

[0119] The schematic diagram of the device structure in the simulation is as follows: Figure 21 As shown, the specific parameters are as follows:

[0120] ①The channel region is made of Si with a thickness of 0.05μm;

[0121] ② The P-type doping concentration in the channel region is 1E17cm -3 ;

[0122] ③ The gate insulating layer material is SiO2, with a thickness of 17nm;

[0123] ④Conventional SOI device, channel length L = 0.1 μm;

[0124] ⑤Apparent gate length L of the inventive device g = 0.2 μm;

[0125] ⑥Effective channel length L of the inventive device eff = 0.1 μm;

[0126] ⑦Equivalent source device, equivalent source length 0.1 μm;

[0127] ⑧Equivalent drain device, equivalent source length 0.1 μm;

[0128] ⑨Equivalent source-drain device, both equivalent source and equivalent drain lengths are 0.05 μm;

[0129] ⑩N-type doping concentration in the source and drain regions is 1E20 cm -3 ;

[0130] The fixed positive charge surface density at the back interface of the channel forming the equivalent source-drain is 1E14 cm -2 ;

[0131] Drain terminal voltage Vd = 2 V or 0.1 V;

[0132] See Figure 21 and Figure 22 , which is a comparison chart of the transfer characteristics between the inventive device and the conventional SOI device. As can be seen from Figure 21 , when Vd = 2 V, the subthreshold swing SS of the conventional SOI device is 479 mV / dec. In comparison, the subthreshold swings of both the equivalent drain device (SS = 291 mV / dec) and the equivalent source device (SS = 308 mV / dec) are significantly reduced, and the improvement of the subthreshold swing of the equivalent source-drain device (SS = 245 mV / dec) is particularly significant. Comparing Figure 21 and Figure 22It can be found that due to the short-channel effect in conventional SOI devices, when Vd = 2V, the threshold voltage of the device decreases significantly (the threshold voltage at Vd = 2V is -0.36V, which is 0.53V lower than the threshold voltage of 0.17V at Vd = 0.1V). In contrast, the change in the threshold voltage of the device of the present invention is much smaller (the decreases in the threshold voltages of the equivalent drain, equivalent source, and equivalent source-drain devices are only 0.18V, 0.14V, and 0.04V respectively). At the same time, compared with the conventional SOI device, the field-effect mobility of the device of the present invention only decreases slightly (the mobilities of the equivalent drain, equivalent source, and equivalent source-drain devices at Vd = 2V are 99.7%, 94.9%, and 96.1% of the mobility of the conventional SOI device respectively). Therefore, the various embodiments provided in the present application can effectively improve the short-channel effect of the device almost without sacrificing the device performance.

[0133] Reference Figure 23 and Figure 24 , is a comparison diagram of the output characteristics of the device of the present invention and the conventional SOI device. As can be seen from the figure, whether Vg = 2V or 4V, the output characteristic curve of the device of the present invention is flatter and the working range is wider. The Vd value corresponding to the significant occurrence of the KINK current in the output characteristics is V kink , V kink The larger it is, the weaker the carrier impact ionization effect in the drain depletion region of the device is, and the more difficult it is for the device to exhibit the kink current effect. Taking Vg = 4V as an example ( Figure 24 ), the V kink of the conventional SOI device is 0.60V, while the V kink of the equivalent drain, equivalent source, and equivalent source-drain devices are 1.10V, 0.99V, and 1.26V respectively, indicating that the device of the present invention can effectively reduce the carrier impact ionization effect during device operation, suppress the KINK current, and improve the output characteristics of the device. At the same time, from Figure 23 and 24 observations, the output current of the device of the present invention is equivalent to that of the conventional SOI device without any decrease.

[0134] Through the above embodiments, the present application has the following beneficial technical effects:

[0135] 1) By setting the device to be able to form an effective channel in the channel region and an equivalent source electrode and an equivalent drain electrode far from the effective channel when turned on, so as to connect the source region and the drain region to form a working current; in this way, the equivalent drain (source) electrode connected to the drain (source) region is structurally far from the effective channel, which can reduce the influence of the drain-end voltage on the effective channel, thereby improving the short-channel effect of the device.

[0136] 2) By setting equivalent source and equivalent drain, the device of the present invention reduces the peak electric field in the channel drain depletion region under saturation operation, significantly reduces the carrier collision ionization effect in the drain depletion region, suppresses the kink current in the device output characteristics, and improves the output characteristics of the device. At the same time, the device of the present invention can suppress the hot carrier degradation effect and improve the reliability of the device.

[0137] It should be understood that although the terms first, second, etc., may be used herein to describe various elements or structures, the objects being described should not be limited by these terms. These terms are only used to distinguish these objects from one another. For example, a first channel may be referred to as a second channel, and similarly, a second channel may be referred to as a first channel, without departing from the scope of protection of this application.

[0138] Furthermore, the same reference numerals or markings may be used in different implementations, but this does not represent a structural or functional connection, but is merely for the convenience of description.

[0139] The terms used in this invention, such as “above,” “over,” “below,” and “under,” indicating spatial relative position, are for illustrative purposes to describe the relationship of one unit or feature relative to another unit or feature as shown in the accompanying drawings. These terms may be intended to include different orientations of the device in use or operation other than those shown in the figures. For example, if the device in the figures is flipped, a unit described as being “below” or “under” other units or features would be located “above” other units or features. Therefore, the exemplary term “under” can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or otherwise) and the spatially related descriptive terms used in this invention will be interpreted accordingly.

[0140] When a component or layer is referred to as being "on" or "connected" to another component or layer, it can be directly on or connected to that other component or layer, or there can be intermediate components or layers. Conversely, when a component is referred to as being "directly on" or "directly connected to" another component or layer, there cannot be intermediate components or layers.

[0141] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0142] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style of the specification is merely for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A field-effect transistor device, comprising an active layer, characterized in that, The active layer includes a source region, a drain region, and a channel region located between the source region and the drain region. When the device is turned on, an effective channel and an equivalent source and / or equivalent drain are formed in the channel region. The field-effect transistor device connects the source region and the drain region through the effective channel and the equivalent source and / or equivalent drain to form an operating current. The channel region contains a conductive region that does not connect the source region and the drain region. When the conductive region is connected to the source region, the conductive region constitutes the equivalent source; and / or, When the conductive region is connected to the drain region, the conductive region constitutes the equivalent drain.

2. The field-effect transistor device according to claim 1, characterized in that, Includes a first gate disposed on one surface of the active layer, wherein the first gate and the conductive region overlap in their vertical projections onto the channel region; wherein the first gate controls the channel region and forms a channel therein, and the portion of the channel that does not overlap with the vertical projection of the conductive region onto the channel region constitutes the effective channel; and / or, The conductive region and the effective channel are spaced apart in the thickness direction of the channel region.

3. The field-effect transistor device according to claim 2, characterized in that, When the device is turned on, the conductivity of the conductive region is greater than the conductivity of the remaining portion of the channel excluding the effective channel, so that at least one of the conductive region and the effective channel can inject carriers into the other. And / or, the field-effect transistor device is a planar structure device or a vertical structure device.

4. The field-effect transistor device according to claim 3, characterized in that, The conductivity of the conductive region is at least three times greater than the conductivity of the remaining portion of the channel excluding the effective channel.

5. The field-effect transistor device according to claim 2, characterized in that, When the device is turned on, the conductivity per unit length of the effective channel in the channel is greater than the conductivity per unit length of the remaining portion of the channel excluding the effective channel.

6. The field-effect transistor device according to claim 5, characterized in that, The field-effect transistor device includes a gate insulating layer disposed between the first gate and the channel region, wherein the thickness of the portion of the gate insulating layer corresponding to the effective channel is less than the thickness of the remaining portion of the gate insulating layer; and / or, The portion of the gate insulation layer corresponding to the effective channel and the remaining portion of the gate insulation layer are made of different materials; and / or, The portion of the first gate corresponding to the effective channel and the remaining portion of the first gate are made of materials with different work functions.

7. The field-effect transistor device according to claim 5, characterized in that, When the device is turned on, the conductivity per unit length of the effective channel in the channel is at least three times greater than the conductivity per unit length of the remaining portion of the channel excluding the effective channel.

8. The field-effect transistor device according to any one of claims 1 to 7, characterized in that, It also includes a second gate disposed on the surface of the active layer adjacent to the conductive region, the second gate being able to control the formation of the conductive region in the channel region.

9. The field-effect transistor device according to any one of claims 1 to 7, characterized in that, The conductive region is formed by carriers introduced by doping on the surface of the channel region on the side away from the effective channel.

10. The field-effect transistor device according to any one of claims 1 to 7, characterized in that, It also includes an insulating layer disposed on the surface of the active layer away from the effective channel, wherein the conductive region is composed of charge carriers generated by the injected charge in the insulating layer through electrostatic induction in the channel region near the insulating layer.

11. The field-effect transistor device according to any one of claims 1 to 7, characterized in that, It also includes a semiconductor material layer disposed on the surface of the active layer away from the effective channel, the active layer and the semiconductor material layer forming a heterostructure, and the conductive region being composed of two-dimensional electron gas channels or two-dimensional hole gas channels distributed in the heterostructure; and / or, The conductive region is formed by surface treatment of the side of the channel region away from the effective channel, creating a two-dimensional electron gas channel or a two-dimensional hole gas channel.

12. The field-effect transistor device according to any one of claims 1 to 7, characterized in that, The source and drain regions are doped semiconductor or Schottky metal source / drain regions; and / or, The gate of the field-effect transistor device is a metal-insulator-semiconductor MOS structure gate or a Schottky junction gate; And / or, The active layer comprises at least two semiconductor materials that vary along its thickness direction or its planar extension direction.

13. A method for improving the short-channel effect and output characteristics of a field-effect transistor device, characterized in that, The method includes setting an equivalent source and / or equivalent drain in the channel region of the device away from the effective channel of the device, so that when the device is turned on, the effective channel connects the source region and the drain region of the device through the equivalent source and / or equivalent drain to form an operating current. The channel region contains a conductive region that does not connect the source region and the drain region; when the conductive region is connected to the source region, the conductive region constitutes the equivalent source; and / or, when the conductive region is connected to the drain region, the conductive region constitutes the equivalent drain.

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