Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, comprising: an opening exposing a portion of a first fin, a portion of a second fin, and a portion of a third region, the second direction being perpendicular to the first direction; a first isolation structure being provided on the third region within the opening, the first isolation structure comprising a first isolation layer and a second isolation layer located above the first isolation layer, the first isolation layer being larger in the second direction than the second isolation layer; a first gate being formed on the first region within the opening; and a second gate being formed on the second region within the opening. The opening having a larger top than bottom dimension along the second direction facilitates filling of the opening with gate material, avoids premature sealing of the top of the opening before the bottom of the opening, and improves the performance of the first and second gates formed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] In the existing semiconductor field, fin field-effect transistor (FinFET) is an emerging multi-gate device. Compared with planar metal-oxide semiconductor field-effect transistor (MOSFET), fin field-effect transistor has stronger short-channel suppression capability and higher operating current, and is now widely used in various semiconductor devices.

[0003] Currently, the semiconductor industry uses metal gates to replace polysilicon gate electrodes to solve problems such as threshold voltage Vt drift, polysilicon gate depletion effect, excessive gate resistance, and Fermi level pinning. The technology of using high-K dielectric materials to replace SiON and using metal gates to replace polysilicon gates is called HKMG process technology. With the continuous development of semiconductor technology, the gate size of FinFET devices is also constantly decreasing. In HKMG technology, in the process of replacing polysilicon gates with metal gates, due to the three-dimensional structure and small size of FinFET devices, it is not easy to fill the metal gate material, resulting in unstable performance of the formed gate structure, which is not conducive to improving device performance.

[0004] In summary, the technology of existing FinFET devices needs to be further improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a base, the base comprising a first region, a second region, and a third region, the third region being located between the first region and the second region, and adjacent to the first region and the second region on both sides of the third region, the substrate further comprising a plurality of first fins located on the first region, and a plurality of second fins located on the second region, the first fins and the second fins both extending along a first direction; an interlayer dielectric layer located on the substrate, the interlayer dielectric layer having an opening extending from the first region to the second region along a second direction, the opening exposing a portion of the first fins, a portion of the second fins, and a portion of the third region, the second direction being perpendicular to the first direction; a first isolation structure located on the third region in the opening, the first isolation structure comprising a first isolation layer and a second isolation layer located on the first isolation layer, the first isolation layer having a size in the second direction larger than a size of the second isolation layer in the second direction; a first gate located on the first region in the opening, the first gate located on a portion of the sidewalls and top surface of the first fin; and a second gate located on the second region in the opening, the second gate located on a portion of the sidewalls and top surface of the second fin.

[0007] Optionally, the substrate also includes a second isolation structure located on the base, the second isolation structure is located on a portion of the side wall surface of the first fin and the second fin, and the top surface of the second isolation structure is lower than the top surface of the first fin and the second fin; the first gate and the second gate are also located on a portion of the surface of the second isolation structure; the first isolation structure is located on the surface of the second isolation structure.

[0008] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a base, the base including a first region, a second region and a third region, the third region being located between the first region and the second region, and the third region being adjacent to the first region and the second region on both sides, the substrate also including a plurality of first fins located on the first region, and a plurality of second fins located on the second region, the first fins and the second fins both extending along a first direction; forming an interlayer dielectric layer and a first isolation structure on the substrate, the interlayer dielectric layer having an opening extending from the first region to the second region along a second direction, the opening exposing a portion of the first fins, a portion of the second fins and a portion of the third region, the second direction being perpendicular to the first direction, the third region in the opening having a first isolation structure, the first isolation structure including a first isolation layer and a second isolation layer located on the first isolation layer, the size of the first isolation layer in the second direction being larger than the size of the second isolation layer in the second direction; forming a first gate on the first region in the opening; forming a second gate on the second region in the opening.

[0009] Optionally, the method for forming the interlayer dielectric layer and the opening includes: forming a dummy gate structure spanning the first fin and the second fin, the dummy gate structure being located at part of the sidewalls and top surfaces of the first fin and the second fin, the dummy gate structure including a dummy gate; forming an interlayer dielectric layer on the substrate, the interlayer dielectric layer being located at the sidewalls of the dummy gate structure and exposing the top surface of the dummy gate; etching and removing the dummy gate on the third region, forming an initial opening in the dummy gate and the interlayer dielectric layer, the bottom of the initial opening exposing the substrate surface; forming the first isolation structure in the initial opening; after forming the first isolation structure, removing the dummy gate, and forming the opening and the first isolation structure located in the opening in the interlayer dielectric layer.

[0010] Optionally, the process of forming the initial opening includes a dry etching process.

[0011] Optionally, the method for forming the first isolation structure includes: forming a first isolation layer in the initial opening; after forming the first isolation layer, forming a first side wall on the side wall of the initial opening exposed by the first isolation layer; after forming the first side wall, forming the second isolation layer in the initial opening, and the first isolation structure and the first side wall fill the initial opening.

[0012] Optionally, after forming the first isolation structure and before forming the first gate and the second gate, the first sidewall spacer is removed.

[0013] Optionally, the method for forming the first isolation layer includes: forming an initial first isolation layer in the initial opening, the initial first isolation layer filling the first opening; and etching back the initial first isolation layer until the top surface of the initial first isolation layer is lower than the top surfaces of the first fin and the second fin.

[0014] Optionally, a size range of the top surface of the first isolation layer lower than the top surface of the first fin is 30 nanometers to 150 nanometers; a size range of the top surface of the first isolation layer and the top surface of the second fin is 20 nanometers to 100 nanometers.

[0015] Optionally, the method for forming the initial first isolation layer includes: forming a first dielectric material layer in the initial opening, on the surface of the pseudo gate, and on the surface of the interlayer dielectric layer, wherein the first dielectric material layer fills the initial opening; and flattening the first dielectric material layer until the surface of the pseudo gate and the surface of the interlayer dielectric layer are exposed.

[0016] Optionally, the method for forming the first sidewall includes: after the first isolation layer, forming a first sidewall material layer in the initial opening, the interlayer dielectric layer and the surface of the pseudo gate; etching back the first sidewall material layer until the top surfaces of the first isolation layer, the interlayer dielectric layer and the pseudo gate are exposed.

[0017] Optionally, the substrate also includes a second isolation structure located on the base, the second isolation structure is located on a portion of the side wall surface of the first fin and the second fin, and the top surface of the second isolation structure is lower than the top surface of the first fin and the second fin; the first gate and the second gate are also located on a portion of the surface of the first isolation structure; the bottom of the opening exposes a portion of the top surface of the second isolation structure.

[0018] Optionally, the dummy gate structure further includes a dummy gate oxide layer located between the first fin, the second fin and the dummy gate; the dummy gate structure further includes a second sidewall spacer located on a sidewall of the dummy gate.

[0019] Optionally, after forming the first isolation structure and before forming the first gate and the second gate, the method further includes: removing the dummy gate oxide layer.

[0020] Optionally, the method for forming the first gate includes: forming a first gate oxide layer on the surface of the first fin exposed by the opening on the first region; forming a first work function layer on the first gate oxide layer; forming a first metal material layer on the first work function layer, and the first metal material layer, the first work function layer and the first gate oxide layer fill the opening on the first region.

[0021] Optionally, the method for forming the second gate includes: forming a second gate oxide layer on the surface of the second fin exposed by the opening on the second region; forming a second work function layer on the second gate oxide layer; forming a second metal material layer on the second work function layer, and the second metal material layer, the second work function layer and the second gate oxide layer fill the opening on the second region.

[0022] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0023] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a first gate is formed on a first region within the opening, a second gate is formed on a second region within the opening, and a first isolation structure is provided on a third region within the opening. The first isolation structure is used to isolate the first gate from the second gate. The first isolation structure includes a first isolation layer and a second isolation layer located on the first isolation layer. The size of the first isolation layer in the second direction is larger than the size of the second isolation layer in the second direction. The size of the opening along the second direction is larger at the top than at the bottom, which facilitates the filling of the gate material within the opening, avoids the situation where the top of the opening is prematurely closed before the bottom of the opening, and improves the performance of the formed first and second gates. In addition, the first isolation layer plays a primary role in isolating the first and second gates, does not change the size of the first isolation layer in the second direction, and therefore does not affect the isolation performance between different devices.

[0024] Furthermore, the top surface of the first isolation layer is lower than the top surface of the first fin by a dimension ranging from 30 nanometers to 150 nanometers; and the top surface of the first isolation layer and the top surface of the second fin are in a dimension ranging from 20 nanometers to 100 nanometers. The significance of selecting this dimension range is that the top surface of the first isolation layer is lower than the top surface of the first fin, which facilitates the width of the opening between the first fin and the first isolation structure to be larger, facilitating the filling of gate material, while also not affecting the isolation performance of the first isolation structure for the first and second gates.

[0025] In the semiconductor structure provided by the technical solution of the present invention, the first isolation structure is used to isolate the first gate from the second gate. The opening has a larger top than bottom dimension along the second direction, which facilitates the filling of the opening with gate material, avoids premature sealing of the top of the opening before the bottom of the opening, and improves the performance of the first and second gates formed. In addition, the first isolation layer primarily isolates the first and second gates, and the dimension of the first isolation layer in the second direction is not changed, thereby not affecting the isolation performance between different devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figures 1 to 5 It is a cross-sectional schematic diagram of the formation process of a semiconductor structure;

[0027] Figures 6 to 14 1 is a schematic structural diagram of each step of a method for forming a semiconductor structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0029] As described in the background art, the performance of semiconductor structures formed using existing FinFET technology urgently needs to be improved. This is now explained and analyzed using a semiconductor structure.

[0030] Figures 1 to 5 It is a schematic diagram of the semiconductor structure formation process.

[0031] Please refer to Figure 1 and Figure 2 , Figure 1 It is a top view. Figure 2 It is along Figure 1 A schematic diagram of a cross-sectional structure in the XY direction provides a substrate, wherein the substrate includes a base 100, the base 100 includes a first region I and a second region II adjacent to the first region I, a plurality of first fins 101 located on the first region I, a plurality of second fins 102 located on the second region II, and an isolation region 103 located on the base 100, the isolation region 103 is located on a portion of the sidewall surface of the first fin 101 and the second fin 102, and the top surface of the isolation structure 103 is lower than the top surface of the first fin 101 and the second fin 102; a first dummy gate 104 is formed across the first fin 101, and the first dummy gate 104 is located on a portion of the sidewall and top surface of the first fin 101; a second dummy gate 105 is formed across the second fin 102, and the second dummy gate 105 is located on a portion of the sidewall and top surface of the second fin 102.

[0032] Please refer to Figure 3 and Figure 4 , Figure 3 It is a top view. Figure 4 It is along Figure 3A schematic diagram of the cross-sectional structure in the XY direction is shown, in which an interlayer dielectric layer 106 is formed on the substrate, and the interlayer dielectric layer 106 is located on the side walls of the first dummy gate 104 and the second dummy gate 105, and exposes the top surfaces of the first dummy gate 104 and the second dummy gate 105; the first dummy gate 104 is removed to form a first trench 107 in the interlayer dielectric layer 106; the second dummy gate 105 is removed to form a second trench 108 in the interlayer dielectric layer 106.

[0033] Please refer to Figure 5 , Figure 5 The viewing direction is the same as Figure 4 , a first gate 109 is formed in the first trench 107 ; and a second gate 110 is formed in the second trench 108 .

[0034] In the above method, the dielectric wall A (eg, Figure 3 and Figure 4 As shown in FIG, the first trench 107 is located in the first opening a (as shown in FIG) between the first fin 101 and the dielectric wall A. Figure 4 As shown in FIG, the width of the first trench 107 is also getting smaller and smaller, which results in the top of the first opening a being easily closed before the bottom of the first opening a when the gate material is filled in the first trench 107 to form the first gate 109, thereby causing the formed first gate 109 to have more defects, thereby reducing the performance of the first gate 109. Similarly, the second trench 108 is located between the second fin 102 and the dielectric wall A. The second opening b (as shown in FIG. Figure 4 The width of the dielectric wall A (shown) also becomes smaller and smaller, affecting the performance of the second gate 110. In another embodiment, by reducing the width of the dielectric wall A to increase the widths of the first opening a and the second opening b, this method reduces the isolation effect of the dielectric wall A on the devices on the first region I and the devices on the second region II. Overall, this is not conducive to improving device performance.

[0035] It should be noted that the width refers to the dimension perpendicular to the extending direction of the first fin 101 (or the second fin 102 ).

[0036] To solve the above technical problem, the present invention provides a method for forming a semiconductor structure, wherein a first gate is formed on a first region within the opening, a second gate is formed on a second region within the opening, and a first isolation structure is provided on a third region within the opening. The first isolation structure is used to isolate the first gate from the second gate. The first isolation structure includes a first isolation layer and a second isolation layer located on the first isolation layer. The first isolation layer has a larger dimension in the second direction than the second isolation layer. The top of the opening is larger than the bottom along the second direction, which facilitates the filling of the gate material within the opening, avoids the situation where the top of the opening is prematurely closed before the bottom of the opening, and improves the performance of the formed first and second gates. In addition, the first isolation layer plays a primary role in isolating the first and second gates, does not change the dimension of the first isolation layer in the second direction, and thus does not affect the isolation performance between different devices.

[0037] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] Figures 6 to 14 1 is a schematic structural diagram of each step of a method for forming a semiconductor structure in an embodiment of the present invention.

[0039] Please refer to Figure 6 and Figure 7 , Figure 6 It is a top view. Figure 7 It is along Figure 6 A schematic diagram of the cross-sectional structure taken along the MN direction is provided, wherein a substrate is provided, the substrate comprising a base 200, the base 200 comprising a first region I, a second region II and a third region III, the third region III being located between the first region I and the second region II, and the third region III being adjacent to the first region I and the second region II on both sides, the substrate further comprising a plurality of first fins 201 located on the first region I, and a plurality of second fins 202 located on the second region II, the first fins 201 and the second fins 202 both extending along the first direction X.

[0040] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate 200 may also be a silicon-on-insulator (SOI) structure or a germanium-on-insulator structure.

[0041] In this embodiment, the materials of the first fin 201 and the second fin 202 are both silicon. In other embodiments, the materials of the first fin 201 and the second fin 202 can also be semiconductor materials such as single crystal germanium, silicon germanium, and gallium arsenide.

[0042] The first region I and the second region II are used to form different devices, and the third region III is used to form a first isolation structure that isolates different devices on the first region I and the second region II.

[0043] In this embodiment, the substrate also includes a second isolation structure 203 located on the base 200, and the second isolation structure 203 is located on a portion of the side wall surface of the first fin 201 and the second fin 201, and the top surface of the second isolation structure 203 is lower than the top surface of the first fin 201 and the second fin 202.

[0044] The material of the second isolation structure 203 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the second isolation structure 203 is silicon oxide. The second isolation structure 203 is used to achieve electrical isolation between different devices.

[0045] Subsequently, an interlayer dielectric layer and a first isolation structure are formed on the substrate. The interlayer dielectric layer has an opening extending from the first region I to the second region II along the second direction Y. The opening exposes a portion of the first fin 201, a portion of the second fin 202, and a portion of the third region III. The second direction Y is perpendicular to the first direction X. A first isolation structure is provided on the third region III in the opening. The first isolation structure includes a first isolation layer and a second isolation layer located on the first isolation layer. The size of the first isolation layer in the second direction Y is larger than the size of the second isolation layer in the second direction Y. For the method of forming the interlayer dielectric layer and the opening, please refer to Figures 6 to 13 .

[0046] Please continue to refer to Figure 6 and Figure 7 , forming a dummy gate structure (not marked in the figure) spanning the first fin 201 and the second fin 202, the dummy gate structure is located on part of the sidewalls and top surfaces of the first fin 201 and the second fin 202, and the dummy gate structure includes a dummy gate 204.

[0047] In this embodiment, the dummy gate structure further includes a dummy gate oxide layer 206 located between the first fin 201 , the second fin 202 and the dummy gate 204 ; the dummy gate structure further includes a second spacer 205 located on the sidewall of the dummy gate 204 .

[0048] In this embodiment, the dummy gate 204 is made of polysilicon. In other embodiments, the dummy gate may be made of amorphous silicon, silicon carbide, etc. The dummy gate 204 is used to occupy a position for the subsequent formation of the first gate, the second gate, and the first isolation structure.

[0049] Please refer to Figure 8 and Figure 9 , Figure 8 It is a top view. Figure 9 It is along Figure 8 Schematic diagram of the cross-sectional structure in the MN direction, an interlayer dielectric layer 207 is formed on the substrate, the interlayer dielectric layer 207 is located on the sidewall of the pseudo gate structure and exposes the top surface of the pseudo gate 204; the pseudo gate 204 on the third region III is etched away, and an initial opening 208 is formed in the pseudo gate 204 and the interlayer dielectric layer 207, and the bottom of the initial opening 208 exposes the substrate surface.

[0050] Specifically, in this embodiment, the bottom of the opening 208 exposes a portion of the top surface of the second isolation structure 203 .

[0051] The material of the interlayer dielectric layer 207 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the interlayer dielectric layer 207 is silicon oxide. The interlayer dielectric layer 207 is used to isolate metal interconnects from devices during subsequent device manufacturing processes, reduce parasitic capacitance between the metal and the substrate, and prevent parasitic field-effect transistors from forming when metal crosses different regions.

[0052] In this embodiment, specifically, the dummy gate structure is also located on a portion of the surface of the first isolation structure 203 .

[0053] The initial opening 208 is formed by a dry etching process. In this embodiment, the initial opening 208 is formed by a dry etching process, which facilitates forming the initial opening 208 with a better morphology. Process parameters for the dry etching process include: an etching gas comprising one or a combination of CF4 and CHF3, with a power ranging from 300 watts to 1000 watts. The initial opening 208 is used to form the first isolation structure.

[0054] Subsequently, the first isolation structure is formed in the initial opening 208. The method for forming the first isolation structure includes: Figures 10 to 12 .

[0055] Please refer to Figure 10 , Figure 10 The viewing direction is the same as Figure 9 , forming a first isolation layer 209 in the initial opening 208 .

[0056] The method for forming the first isolation layer 209 includes: forming an initial first isolation layer (not marked in the figure) in the initial opening 208, wherein the initial first isolation layer fills the initial opening 208; and etching back the initial first isolation layer until the top surface of the initial first isolation layer is lower than the top surface of the first fin 201 and the second fin 202.

[0057] The method for forming the initial first isolation layer 209 includes: forming a first dielectric material layer (not shown in the figure) in the initial opening 208, on the surface of the dummy gate 204, and on the surface of the interlayer dielectric layer 207, wherein the first dielectric material layer fills the initial opening 208; and planarizing the first dielectric material layer until the surface of the dummy gate 204 and the surface of the interlayer dielectric layer 207 are exposed.

[0058] The material of the first dielectric material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the first dielectric material layer is silicon oxide, and the first isolation layer 209 is formed from the first dielectric material layer. Therefore, the material of the first isolation layer 209 is also silicon oxide.

[0059] The first dielectric material layer is formed by a chemical vapor deposition process. In this embodiment, the first dielectric material layer is formed by a fluid chemical vapor deposition process. The fluid chemical vapor deposition process is advantageous in reducing defects such as voids within the formed first dielectric material layer and has excellent filling performance.

[0060] The size range of the top surface of the first isolation layer 209 below the top surface of the first fin 201 is 30 nanometers to 150 nanometers; the size range of the top surface of the first isolation layer 209 and the top surface of the second fin 202 is 20 nanometers to 100 nanometers. The significance of selecting these size ranges will be described in detail later. Figure 12 Description.

[0061] Please refer to Figure 11 , Figure 11 The viewing direction is the same as Figure 9 After the first isolation layer 209 is formed, a first sidewall spacer 210 is formed on the sidewall of the initial opening 208 exposed by the first isolation layer 209 .

[0062] The method for forming the first sidewall spacer 210 includes: after the first isolation layer 209, forming a first sidewall material layer (not shown in the figure) in the initial opening 208, on the surface of the interlayer dielectric layer 207 and the dummy gate 204; etching back the first sidewall material layer until the top surfaces of the first isolation layer 209, the interlayer dielectric layer 207 and the dummy gate 204 are exposed.

[0063] The material of the first sidewall spacer 210 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride oxycarbonate. In this embodiment, the material of the first sidewall spacer 210 is silicon nitride. The material of the first sidewall spacer 210 is different from the material of the first isolation layer 209 and the subsequently formed second isolation layer. This allows for the subsequent removal of the first sidewall spacer 210 using a process with a high etch selectivity for the first sidewall spacer 210, thereby reducing etching damage to the first isolation layer 209 and the second isolation layer.

[0064] In this embodiment, the size of the second isolation layer along the second direction Y can be adjusted by adjusting the size of the first spacer 210 along the second direction Y, that is, the thickness of the first spacer material layer.

[0065] Please refer to Figure 12 , Figure 12 The viewing direction is the same as Figure 9 After forming the first sidewall 210 , the second isolation layer 211 is formed in the initial opening 208 , and the first isolation structure and the first sidewall 210 completely fill the initial opening 208 .

[0066] The first isolation structure includes a first isolation layer 209 and a second isolation layer 211 located on the first isolation layer 209. The first isolation layer 209 has a larger dimension in the second direction Y than the second isolation layer 211. Subsequently, the dummy gate 204 is removed, forming an opening in the interlayer dielectric layer 207 and the first isolation structure located within the opening. A first gate is formed in the first region I within the opening, and a second gate is formed in the second region II within the opening. The top of the opening in the first region I (the second region II) is larger than the bottom along the second direction Y, which facilitates filling the opening in the first region I (the second region II) with the first gate material (the second gate material), avoids premature sealing of the top of the opening before the bottom of the opening, and improves the performance of the formed first and second gates.

[0067] The thickness of the second isolation layer 211 ranges from 25 nanometers to 150 nanometers; the thickness of the first isolation layer 209 ranges from 35 nanometers to 200 nanometers. The thickness refers to the dimension perpendicular to the substrate. The first isolation layer 209 primarily isolates the first and second gates. Unchanging the dimension of the first isolation layer 209 in the second direction does not affect the isolation performance between different devices.

[0068] The top surface of the first isolation layer 209 is lower than the top surface of the first fin 201 by a dimension ranging from 30 nanometers to 150 nanometers; the top surface of the first isolation layer 209 and the top surface of the second fin 202 are in a dimension ranging from 20 nanometers to 100 nanometers. The significance of selecting this dimension range is that the top surface of the first isolation layer 209 is lower than the top surface of the first fin 201 (the second fin 202), which facilitates a larger width of the opening between the first fin 201 and the first isolation structure, facilitating filling with gate material, while also not affecting the isolation performance of the first isolation structure for the first and second gates.

[0069] Please refer to Figure 13 , Figure 13 The viewing direction is the same as Figure 9 After forming the first isolation structure, the dummy gate 204 is removed, and the opening 212 and the first isolation structure located in the opening 212 are formed in the interlayer dielectric layer 207 .

[0070] In this embodiment, the process for removing the dummy gate 204 is a wet etching process. The solution used in the wet etching process includes a tetramethylammonium hydroxide solution. Since the tetramethylammonium hydroxide solution has a larger etching ratio for polysilicon material than for silicon and silicon oxide, the dummy gate 204 has a larger etching selectivity with respect to the substrate, the first isolation structure, and the interlayer dielectric layer 207 during the process of removing the dummy gate 204, thereby reducing damage to the substrate, the first isolation structure, and the interlayer dielectric layer 207 during the process of removing the dummy gate 204.

[0071] In this embodiment, after forming the first isolation structure and before forming the first gate and the second gate, the first sidewall spacer 210 is removed.

[0072] The process for removing the first sidewall spacer 210 includes one or a combination of a dry etching process and a wet etching process. In this embodiment, the process for removing the first sidewall spacer 210 is a wet etching process. The solution used in the wet etching process includes a phosphoric acid solution. Because phosphoric acid has a high selectivity for the first sidewall spacer 210, the wet etching process reduces etching damage to the first isolation layer 209 and the second isolation layer.

[0073] In this embodiment, after forming the first isolation structure and before forming the first gate and the second gate, the process further includes: removing the dummy gate oxide layer 206 .

[0074] Please refer to Figure 14 , Figure 14 The viewing direction is the same as Figure 9, a first gate 213 is formed on the first region I in the opening 212 ; and a second gate 214 is formed on the second region II in the opening 212 .

[0075] In this embodiment, the method for forming the first gate 213 includes: forming a first gate oxide layer (not marked in the figure) on the surface of the first fin 201 exposed by the opening 212 on the first region I; forming a first work function layer (not marked in the figure) on the first gate oxide layer; forming a first metal material layer (not marked in the figure) on the first work function layer, and the first metal material layer, the first work function layer and the first gate oxide layer fill the opening 212 on the first region I.

[0076] In this embodiment, the material of the first metal material layer is tungsten. In other embodiments, the first metal material layer can also be made of copper, aluminum, etc.

[0077] In this embodiment, the method for forming the second gate 214 includes: forming a second gate oxide layer (not marked in the figure) on the surface of the second fin 202 exposed by the opening 212 on the second region II; forming a second work function layer (not marked in the figure) on the second gate oxide layer; forming a second metal material layer (not marked in the figure) on the second work function layer, and the second metal material layer, the second work function layer and the second gate oxide layer fill the opening 212 on the second region II.

[0078] In this embodiment, the material of the second metal material layer is tungsten. In other embodiments, the second metal material layer can also be made of copper, aluminum, etc.

[0079] Specifically, the first gate 201 and the second gate 202 are also located on a portion of the surface of the first isolation structure 203 .

[0080] Correspondingly, another embodiment of the present invention also provides an embodiment of a semiconductor structure formed by the above-mentioned forming method, please continue to refer to Figure 14 , comprising: a substrate, the substrate comprising a base 200, the base 200 comprising a first region I, a second region II, and a third region III, the third region III being located between the first region I and the second region II, and adjacent to the first region I and the second region II on both sides of the third region III, the substrate further comprising a plurality of first fins 201 located on the first region I, and a plurality of second fins 202 located on the second region II, the first fins 201 and the second fins 202 both extending along a first direction X; an interlayer dielectric layer 207 located on the substrate, the interlayer dielectric layer 207 having an opening 212 extending from the first region I to the second region II along a second direction Y (as shown in FIG. Figure 13), the opening 212 exposes a portion of the first fin 201, a portion of the second fin 202 and a portion of the third region III, and the second direction Y is perpendicular to the first direction X; a first isolation structure located on the third region III in the opening 212, the first isolation structure comprising a first isolation layer 209 and a second isolation layer 211 located on the first isolation layer 209, the size of the first isolation layer 209 in the second direction Y being larger than the size of the second isolation layer 211 in the second direction Y; a first gate 213 located on the first region I in the opening 212, the first gate 213 being located on a portion of the sidewall and top surface of the first fin 201; a second gate 214 located on the second region II in the opening 212, the second gate 214 being located on a portion of the sidewall and top surface of the second fin 202.

[0081] Since the size of the first isolation layer 209 in the second direction Y is larger than the size of the second isolation layer 211 in the second direction Y, the size of the top of the opening on the first region I (the second region II) along the second direction Y is larger than the bottom, which is conducive to the filling of the first gate material (the second gate material) in the opening on the first region I (the second region II), avoiding the situation where the top of the opening is closed before the bottom of the opening, and improving the performance of the first gate 213 and the second gate 214 formed.

[0082] The substrate also includes a second isolation structure located on the base 200, the second isolation structure is located on a portion of the sidewall surface of the first fin 201 and the second fin 202, and the top surface of the second isolation structure is lower than the top surface of the first fin 201 and the second fin 202; the first gate 213 and the second gate 214 are also located on a portion of the surface of the second isolation structure 203; the first isolation structure is located on the surface of the second isolation structure 203.

[0083] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate, the substrate comprising a base, the substrate comprising a first region, a second region, and a third region, the third region being located between the first region and the second region, and adjacent to the first region and the second region on both sides of the third region, the substrate further comprising a plurality of first fins located on the first region, and a plurality of second fins located on the second region, the first fins and the second fins both extending along a first direction; an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer has an opening extending from the first region to the second region along a second direction, wherein the opening exposes a portion of the first fin, a portion of the second fin, and a portion of the third region, wherein the second direction is perpendicular to the first direction; a first isolation structure located on the third region in the opening, the first isolation structure comprising a first isolation layer and a second isolation layer located on the first isolation layer, a dimension of the first isolation layer in the second direction being greater than a dimension of the second isolation layer in the second direction, and a thickness of the first isolation layer being greater than a thickness of the second isolation layer; a first gate located on a first region within the opening, the first gate being located on a portion of a sidewall and a top surface of the first fin; A second gate is located on the second region in the opening, and the second gate is located on a portion of a sidewall and a top surface of the second fin.

2. The semiconductor structure according to claim 1, wherein The substrate further includes a second isolation structure located on the base, the second isolation structure being located on a portion of sidewall surfaces of the first fin and the second fin, and a top surface of the second isolation structure being lower than a top surface of the first fin and the second fin; The first gate and the second gate are also located on a portion of the surface of the second isolation structure; and the first isolation structure is located on the surface of the second isolation structure.

3. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a base, the substrate comprising a first region, a second region, and a third region, the third region being located between the first region and the second region, and adjacent to the first region and the second region on both sides of the third region, the substrate further comprising a plurality of first fins located on the first region, and a plurality of second fins located on the second region, wherein both the first fins and the second fins extend along a first direction; An interlayer dielectric layer and a first isolation structure are formed on the substrate, wherein the interlayer dielectric layer has an opening extending from the first region to the second region along a second direction, the opening exposing a portion of the first fin, a portion of the second fin, and a portion of the third region, the second direction being perpendicular to the first direction, a first isolation structure is provided on the third region in the opening, the first isolation structure comprising a first isolation layer and a second isolation layer located on the first isolation layer, a size of the first isolation layer in the second direction being larger than a size of the second isolation layer in the second direction, and a thickness of the first isolation layer being larger than a thickness of the second isolation layer; forming a first gate on the first region in the opening; A second gate is formed on the second region in the opening.

4. The method for forming a semiconductor structure according to claim 3, wherein: The method for forming the interlayer dielectric layer and the opening includes: forming a dummy gate structure spanning the first fin and the second fin, the dummy gate structure being located on part of the sidewalls and top surfaces of the first fin and the second fin, and the dummy gate structure including a dummy gate; forming an interlayer dielectric layer on the substrate, the interlayer dielectric layer being located on the sidewalls of the dummy gate structure and exposing the top surface of the dummy gate; etching and removing the dummy gate on the third region to form an initial opening in the dummy gate, the initial opening cutting off the dummy gate, and exposing the substrate surface at the bottom of the initial opening; forming the first isolation structure in the initial opening; after forming the first isolation structure, removing the dummy gate to form the opening and the first isolation structure located in the opening in the interlayer dielectric layer.

5. The method for forming a semiconductor structure according to claim 4, wherein: The process of forming the initial opening includes a dry etching process.

6. The method for forming a semiconductor structure according to claim 4, wherein: The method for forming the first isolation structure includes: forming a first isolation layer in the initial opening; after forming the first isolation layer, forming a first sidewall on the sidewall of the initial opening exposed by the first isolation layer; after forming the first sidewall, forming the second isolation layer in the initial opening, and the first isolation structure and the first sidewall fill the initial opening.

7. The method for forming a semiconductor structure according to claim 6, wherein: After forming the first isolation structure and before forming the first gate and the second gate, the first sidewall spacer is removed.

8. The method for forming a semiconductor structure according to claim 6, wherein: The method for forming the first isolation layer includes: forming an initial first isolation layer in the initial opening, wherein the initial first isolation layer fills the initial opening; and etching back the initial first isolation layer until a top surface of the initial first isolation layer is lower than top surfaces of the first fin and the second fin.

9. The method for forming a semiconductor structure according to claim 8, wherein: A dimension of the first isolation layer top surface lower than the first fin top surface ranges from 30 nanometers to 150 nanometers; a dimension of the first isolation layer top surface and the second fin top surface ranges from 20 nanometers to 100 nanometers.

10. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the initial first isolation layer includes: forming a first dielectric material layer in the initial opening, on the surface of the dummy gate, and on the surface of the interlayer dielectric layer, wherein the first dielectric material layer fills the initial opening; and flattening the first dielectric material layer until the surface of the dummy gate and the surface of the interlayer dielectric layer are exposed.

11. The method for forming a semiconductor structure according to claim 6, wherein: The method for forming the first sidewall includes: forming a first sidewall material layer in the initial opening, the interlayer dielectric layer and the surface of the dummy gate after the first isolation layer; and etching back the first sidewall material layer until the top surfaces of the first isolation layer, the interlayer dielectric layer and the dummy gate are exposed.

12. The method for forming a semiconductor structure according to claim 3, wherein: The substrate further includes a second isolation structure located on the base, the second isolation structure being located on a portion of sidewall surfaces of the first fin and the second fin, and a top surface of the second isolation structure being lower than a top surface of the first fin and the second fin; The first gate and the second gate are also located on a portion of the surface of the first isolation structure; the bottom of the opening exposes a portion of the top surface of the second isolation structure.

13. The method for forming a semiconductor structure according to claim 4, wherein: The dummy gate structure further includes a dummy gate oxide layer located between the first fin, the second fin and the dummy gate; the dummy gate structure further includes a second spacer located on a sidewall of the dummy gate.

14. The method for forming a semiconductor structure according to claim 13, wherein: After forming the first isolation structure and before forming the first gate and the second gate, the method further includes: removing the dummy gate oxide layer.

15. The method for forming a semiconductor structure according to claim 3, wherein: The method for forming the first gate includes: forming a first gate oxide layer on the surface of the first fin exposed by the opening on the first region; forming a first work function layer on the first gate oxide layer; forming a first metal material layer on the first work function layer, and the first metal material layer, the first work function layer and the first gate oxide layer fill the opening on the first region.

16. The method for forming a semiconductor structure according to claim 3, wherein: The method for forming the second gate includes: forming a second gate oxide layer on the surface of the second fin exposed by the opening on the second region; forming a second work function layer on the second gate oxide layer; forming a second metal material layer on the second work function layer, and the second metal material layer, the second work function layer and the second gate oxide layer fill the opening on the second region.

Images