Flash memory and method of making the same

Abstract

The application discloses a flash memory and a manufacturing method thereof. The flash memory comprises a substrate, two gate structures arranged on the substrate, each of the gate structures comprising a floating gate and a control gate, the control gate being arranged on the floating gate, an erase gate being arranged between the two gate structures, and two word lines being arranged on one side of the two gate structures respectively, wherein the upper surface of each of the word lines comprises a first concave surface and a sharp corner, the sharp corner is close to a side wall of the word line where the sharp corner is located, the side wall is away from each of the gate structures, and the sharp corner is connected with the first concave surface.

Description

Technical Field

[0001] This invention relates to a method and structure for forming character lines of a flash memory using a self-alignment method. Background Technology

[0002] Flash memory is a type of non-volatile memory that can retain stored information even without an external power supply. In recent years, due to its advantages such as rewritability and electrical erasure, flash memory has been widely used in electronic products such as mobile phones, digital cameras, game consoles, and personal digital assistants, as well as in the developing system-on-a-chip (SoC).

[0003] However, currently, the character lines of flash memory are defined using photoresist. However, due to the error of the equipment itself, the position of the photoresist is deviated, resulting in inconsistent widths of the character lines formed subsequently. Summary of the Invention

[0004] In view of this, the present invention provides a method for defining character line positions using a self-alignment approach to improve the consistency of character line widths.

[0005] According to a preferred embodiment of the present invention, a flash memory includes a substrate, two gate structures disposed on the substrate, each gate structure including a floating gate and a control gate, the control gate being disposed on the floating gate, an erase gate being disposed between the two gate structures, and two character lines disposed on the substrate, one of which is disposed on one side of one of the gate structures, and the other character line being disposed on one side of the other gate structure, wherein the upper surface of each character line includes a first concave surface and a sharp corner, the sharp corner being close to a side wall of the character line it is located on, the side wall being away from each gate structure, and the sharp corner being connected to the first concave surface.

[0006] According to another preferred embodiment of the present invention, a method for manufacturing a flash memory includes providing a substrate, wherein two gate structures are disposed on the substrate, and a conductive layer is formed compliantly covering the two gate structures and the substrate. The conductive layer includes a first mountain-shaped profile, a second mountain-shaped profile, a first flat profile, and a second flat profile. The first mountain-shaped profile connects to the second mountain-shaped profile. The first flat profile is on one side of the first mountain-shaped profile, and the second flat profile is on one side of the second mountain-shaped profile. The first mountain-shaped profile and the second mountain-shaped profile each cover one of the two gate structures, and the first flat profile and the second flat profile cover the substrate. The first and second mountain-shaped profiles each include a mountain peak and two slopes. A sacrificial layer is then formed to conformally cover the conductive layer. A first anisotropic etching process is then performed to remove the sacrificial layers located on the mountain peak of the first and second mountain-shaped profiles, as well as on the first and second flat profiles, while retaining the sacrificial layers located on the slopes of the first and second mountain-shaped profiles. Finally, after the first anisotropic etching process, a second anisotropic etching process is performed to etch the conductive layer and the sacrificial layer until the first and second flat profiles are completely removed.

[0007] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. However, the following preferred embodiments and drawings are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0008] Figures 1 to 4 This is a schematic diagram illustrating a method for manufacturing a flash memory according to a preferred embodiment of the present invention.

[0009] Explanation of main component symbols

[0010] 10: Base

[0011] 12: Gate Structure

[0012] 14: Floating gate

[0013] 16: Control Gate

[0014] 18: Hard Mask

[0015] 20: Doped region

[0016] 22: Insulation layer

[0017] 24: Conductive layer

[0018] 26: First mountain outline

[0019] 26a: Mountain Top

[0020] 26b: Slope

[0021] 28: Second mountain shape outline

[0022] 28a: Mountain Top

[0023] 28b: Slope

[0024] 30: First flat profile

[0025] 32: Second flat profile

[0026] 34: First Anisotropic Etching Fabrication Process

[0027] 36: Second Anisotropic Etching Fabrication Process

[0028] 38: Character line

[0029] 38a: Concave surface

[0030] 38b: Sharp angle

[0031] 42: Spacer wall

[0032] 44: Doped region

[0033] 46: Sidewall

[0034] 48: Concave surface

[0035] 100: Flash memory

[0036] 126: Sacrifice Layer

[0037] W: Width

[0038] X: Horizontal direction Detailed Implementation

[0039] Figures 1 to 4 This is a method for manufacturing a flash memory according to a preferred embodiment of the present invention.

[0040] like Figure 1As shown, a substrate 10 is first provided, and two gate structures 12 are disposed on the substrate 10. Each gate structure 12 includes a floating gate 14, a control gate 16, and a hard mask 18. The control gate 16 is disposed on the floating gate 14, and the hard mask 18 is disposed on the control gate 16. A doped region 20 is disposed in the substrate 10 between the two gate structures 12. The doped region 20 will subsequently serve as the source line of the flash memory. An insulating layer 22 covers the substrate 10 and is disposed between the substrate 10 and the gate structures 12. In addition, the insulating layer 22 is also disposed between the control gate 16 and the floating gate 14, and on both sides of each gate structure 12. Next, a conductive layer 24 is formed to cover each gate structure 12 and the substrate 10. The conductive layer 24 is preferably doped polysilicon. Since the gate structure 12 forms two raised contours on the substrate 10, after the conductive layer 24 covers the gate structure 12 and the substrate 10, the conductive layer 24 will form a first mountain-shaped contour 26, a second mountain-shaped contour 28, a first flat contour 30 and a second flat contour 32 along the gate structure 12. The positions of the first flat contour 30 and the second flat contour 32 are indicated by dashed lines in the figure. The first mountain-shaped profile 26 connects to the second mountain-shaped profile 28. A first flat profile 30 is on one side of and connected to the first mountain-shaped profile 26. A second flat profile 32 is on one side of and connected to the second mountain-shaped profile 28. The first mountain-shaped profile 26 and the second mountain-shaped profile 28 each cover one of the two gate structures 12. The first flat profile 30 and the second flat profile 32 cover the substrate 10. The first mountain-shaped profile 26 includes a peak 26a and two slopes 26b. The second mountain-shaped profile 28 includes a peak 26a and two slopes 26b. 8b, the first mountain-shaped profile 26 and the second mountain-shaped profile 28 do not overlap each other, the first flat profile 30 and the second flat profile 32 both cover the substrate 10, one slope 26b of the first mountain-shaped profile 26 and one slope 28b of the second mountain-shaped profile 28 are connected, the first flat profile 30 and the other slope 26b of the first mountain-shaped profile 26 are connected, the second flat profile 32 and the other slope 28b of the second mountain-shaped profile 28 are connected, and the upper surface of the first flat profile 30, the upper surface of the second flat profile 32 and the upper surface of the substrate 10 are parallel to each other. According to a preferred embodiment of the invention, the thickness of the conductive layer 24 is between 500 angstroms and 1500 angstroms. Then a sacrificial layer 126 is formed to conformally cover the conductive layer 24, the sacrificial layer 126 comprising silicon oxide or silicon nitride. According to a preferred embodiment of the invention, the thickness of the sacrificial layer 126 is between 30 angstroms and 300 angstroms.

[0041] like Figure 2As shown, a first anisotropic etching process 34 is performed to remove the sacrificial layer 126 located on the summit 26a of the first mountain-shaped contour 26, the summit 28a of the second mountain-shaped contour 28, and on the first flat contour 30 and the second flat contour 32, while retaining the sacrificial layer 126 located on the two slopes 26b of the first mountain-shaped contour 26 and the two slopes 28b of the second mountain-shaped contour 28. In short, the first anisotropic etching process 34 removes the sacrificial layer 126 in the horizontal direction X. The first anisotropic etching process 34 is preferably dry etching. The horizontal direction X is parallel to the upper surface of the substrate 10.

[0042] like Figure 3 As shown, a second anisotropic etching process 36 is performed to etch the conductive layer 24 and the sacrificial layer 126 until the first flat contour 30 and the second flat contour 32 are completely removed. The second anisotropic etching process 34 is then stopped. After the second anisotropic etching process 34 stops, the upper surfaces of each gate structure 12 are exposed, i.e., the hard mask 18 is exposed. It is worth noting that during the etching of the conductive layer 24, the conductive layer 24 at the slope 26b / 28b positions covered by the sacrificial layer 126 is etched later because the second anisotropic etching process 34 must remove the sacrificial layer 126 first. The conductive layer 24 at the peak 26a / 26b positions not covered by the sacrificial layer 26, the first flat contour 30, and the second flat contour 32 are etched from the beginning of the second anisotropic etching process 36. This results in less of the conductive layer 24 at the slope 26b / 28b positions being etched within the same etching time. The conductive layer 24 at the summit positions 26a / 28b, the first flat contour 30, and the second flat contour 32 will be etched extensively. Therefore, when the first flat contour 30 and the second flat contour 32 are completely removed, some conductive layer 24 will remain at the slope positions 26b / 28b. This remaining conductive layer 24 is divided into three unconnected conductive blocks, which serve as two character lines 38 and one erase gate 40. One character line 38 is located on one side of one gate structure 12, and the other character line 38 is located on the other side of the other gate structure 12. Since the sacrificial layer 126 can affect the amount of conductive layer 24 etched, the width of the character lines 38 can be controlled by adjusting the thickness of the sacrificial layer 126.

[0043] like Figure 4As shown, the remaining sacrificial layer 126 is completely removed. At this point, each of the two character lines 38 includes a concave surface 38a and a sharp corner 38b. The sharp corner 38b is connected to the concave surface 38a and is located away from the gate structure 12. Then, a spacer wall 42 is formed on the sidewall 46 of each of the two character lines 38. Then, a doped region 44 is formed in the substrate 10 on the side of each character line 38 away from the erase gate 40. The doped region 44 will later serve as the bit line of the flash memory 100. At this point, the flash memory 100 of the present invention has been completed.

[0044] like Figure 4 As shown, the flash memory 100 of the present invention includes a substrate 10, two gate structures 12 disposed on the substrate 10, each gate structure 12 including a floating gate 14, a control gate 16 and a hard mask 18, the control gate 16 being disposed on the floating gate 14, the hard mask 18 being disposed on the control gate 16, an erase gate 40 being disposed between the two gate structures 12, and two character lines 38 being disposed on the side of the two gate structures 12 opposite to the erase gate 40, that is, one of the character lines 38 is disposed on the side of one gate structure 12 away from the erase gate 40, and the other character line 38 is disposed on the side of the other gate structure 12 away from the erase gate 40. Each character line 38 has a concave surface 38a and a sharp corner 38b on its upper surface. The sharp corner 38b is close to a sidewall 46 of the character line 38 it belongs to. The sidewall 46 is away from the two gate structures 12, and the sharp corner 38b is connected to the concave surface 38a. The sharp corner 38b points away from the substrate 10, and the concave surface 38a is lower than the upper surface of the gate structure 12. Furthermore, the two character lines 38 formed by the manufacturing process of the present invention each have a width W, which is parallel to the upper surface of the substrate 10, and the width W of the two character lines 38 is the same. According to another preferred embodiment of the present invention, the difference between the widths W of the two character lines 38 formed by the manufacturing process of the present invention is smaller than the difference between the widths W of the two character lines formed by defining character lines using photoresist.

[0045] Furthermore, the upper surface of the erase gate 40 includes a concave surface 48, which is lower than the upper surface of the gate structure 12. An insulating layer 22 is disposed between the substrate 10 and the character line 38, between the substrate 10 and the gate structure 12, between the gate structure 12 and the erase gate 40, between the control gate 16 and the floating gate 14, and between the character line 38 and the gate structure 12. A doped region 20 is located in the substrate 10 between the two gate structures 12, that is, in the substrate 10 directly below the erase gate 40. The doped region 20 serves as the source line of the flash memory 100. Two other doped regions 44 are each located in the substrate 10 on one side of the two character lines 38. Each doped region 44 serves as a bit line of the flash memory 100. The insulating layer 22 comprises silicon oxide, silicon nitride, silicon carbide nitride, silicon oxynitride, or silicon carbide nitride, etc. The control gate 16, the erase gate 40, and the character line 38 comprise conductive materials, such as doped polysilicon. The floating gate 14 comprises silicon nitride or polysilicon. The hard mask 18 comprises silicon oxide, silicon nitride, silicon carbide nitride, silicon oxynitride, or silicon carbide oxynitride. The substrate 10 comprises a silicon substrate, germanium substrate, gallium arsenide substrate, silicon germanium substrate, indium phosphide substrate, gallium nitride substrate, silicon carbide substrate, or silicon-coated insulating substrate.

[0046] Because this invention uses a self-aligned method to form character lines and control gates, it eliminates the need for patterned photoresist to define the character line positions, thus saving a photomask. Furthermore, this invention specifically uses a sacrificial layer to control the etching degree of the conductive layer at different locations. Compared to anisotropic etching without a sacrificial layer, the fabrication process using a sacrificial layer to etch the conductive layer allows control over the character line width and the erase gate thickness by adjusting the thickness of both the sacrificial and conductive layers. In contrast, the fabrication process without a sacrificial layer relies solely on adjusting the thickness of the conductive layer to control the character line width and the erase gate thickness, but controlling the character line width using only a single material (conductive layer) offers limited variability. Moreover, to fabricate wider character lines, the process without a sacrificial layer requires forming a very thick conductive layer for etching. With a sacrificial layer, a thinner conductive layer can be formed to achieve wider character lines, thereby reducing manufacturing costs.

[0047] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for manufacturing a flash memory, comprising: A substrate is provided, wherein two gate structures are disposed on the substrate; A conductive layer is formed to conformally cover the two gate structures and the substrate, wherein the conductive layer includes a first mountain-shaped profile, a second mountain-shaped profile, a first flat profile and a second flat profile, the first mountain-shaped profile is connected to the second mountain-shaped profile, the first flat profile is on one side of the first mountain-shaped profile, the second flat profile is on one side of the second mountain-shaped profile, the first mountain-shaped profile and the second mountain-shaped profile each cover one of the two gate structures, the first flat profile and the second flat profile cover the substrate, and the first mountain-shaped profile and the second mountain-shaped profile each include a mountain peak and two slopes; A sacrificial layer is formed to conformably cover the conductive layer; A first anisotropic etching process is performed to remove the sacrificial layer located on the summit of the first mountain profile, the summit of the second mountain profile, and on the first flat profile and the second flat profile, while retaining the sacrificial layer located on the two slopes of the first mountain profile and the two slopes of the second mountain profile. Following the first anisotropic etching process, a second anisotropic etching process is performed to etch the conductive layer and the sacrificial layer until the first flat contour and the second flat contour are completely removed. This results in the remaining conductive layer being divided into three unconnected conductive blocks. These three blocks serve as two character lines and an erase gate, respectively. Each character line is located on either side of the erase gate. The upper surface of each character line includes a concave surface and a sharp corner. The sharp corner is located away from the two gate structures and is connected to the concave surface. After removing the first flat profile and the second flat profile, completely remove the remaining sacrificial layer.

2. The method of manufacturing a flash memory as claimed in claim 1, further comprising: after forming each of the character lines, forming a gap wall that contacts the entire sidewall of each of the character lines.

3. The method for manufacturing a flash memory as claimed in claim 2, further comprising: forming a source line in the substrate between the two gate structures before forming the conductive layer; and Two bit lines are formed, each located in the substrate on the side of the character line away from the erase gate.

4. The method for manufacturing a flash memory as claimed in claim 1, wherein the thickness of the conductive layer is between 500 angstroms and 1500 angstroms, and the thickness of the sacrificial layer is between 30 angstroms and 300 angstroms.

5. The method for manufacturing a flash memory as claimed in claim 1, wherein the sacrificial layer comprises silicon oxide or silicon nitride.

6. The method of manufacturing a flash memory as claimed in claim 1, wherein the upper surface of the first flat profile, the upper surface of the second flat profile, and the upper surface of the substrate are parallel to each other.

7. The method for manufacturing a flash memory as claimed in claim 1, wherein the upper surface of each of the gate structures is exposed after the second anisotropic etching process.

8. A flash memory device manufactured by the method according to any one of claims 1-7, characterized in that, Include: Base; Two gate structures are disposed on the substrate, each gate structure including a floating gate and a control gate, the control gate being disposed on the floating gate; The gate is erased and positioned between the two gate structures; and Two character lines are disposed on the substrate, wherein one of the two character lines is disposed on one side of one of the two gate structures, and the other of the two character lines is disposed on the other side of the two gate structures. The upper surface of each character line includes a first concave surface and a sharp corner. The sharp corner is close to the sidewall of the character line where it is located, the sidewall is away from the two gate structures, and the sharp corner is connected to the first concave surface.

9. The flash memory of claim 8, wherein the sharp corner points away from the substrate.

10. The flash memory of claim 8, wherein the upper surface of the erase gate includes a second concave surface.

11. The flash memory of claim 10, wherein the second concave surface is lower than the upper surface of each of the gate structures.

12. The flash memory of claim 8, wherein the first concave surface is lower than the upper surface of each of the gate structures.

13. The flash memory of claim 8, further comprising: an insulating layer disposed between the substrate and the two character lines, between the substrate and the two gate structures, between each gate structure and the erase gate, between the control gate and the floating gate, and between each character line and each gate structure.

14. The flash memory of claim 8, further comprising: The source line is disposed in the substrate directly below the erased gate; and Two bit lines are respectively set in the base on one side of each character line.

Images