Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

A semiconductor structure includes an optical component and a thermal control mechanism adjacent to the optical component and configured to control a temperature of the optical component. The thermal control mechanism includes an electrically conductive structure, a first thermoelectric member, and a second thermoelectric member opposite the first thermoelectric member. The first thermoelectric member and the second thermoelectric member are electrically connected to the electrically conductive structure. The first thermoelectric member and the second thermoelectric member have opposite conductivity types. The semiconductor structure further includes a first dielectric layer surrounding the optical component and portions of the thermal control mechanism, wherein the electrically conductive structure is above the first dielectric layer and the first thermoelectric member and the second thermoelectric member are surrounded by the first dielectric layer. The semiconductor structure further includes a first via extending through the first dielectric layer and electrically connected to the electrically conductive structure. Embodiments of the invention also relate to methods of manufacturing a semiconductor structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present invention relate to a semiconductor structure and a method of manufacturing a semiconductor structure. BACKGROUND

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various components (e.g., optoelectronic devices, electronic components, etc.). To accommodate the miniaturization of semiconductor devices, various techniques and applications have been developed for wafer level packaging involving a greater number of different components with different functions. Improvements in integration density have resulted in iterative reductions in the minimum feature size, which allows for more components to be integrated into a given area.

[0003] As such, the manufacturing of semiconductor devices involves many steps and operations on such small and thin semiconductor devices. Therefore, the manufacturing of miniaturized semiconductor devices becomes more complicated. Moreover, involving a greater number of different components with different materials, due to the high power density of semiconductor devices, results in higher requirements for thermal management and heat dissipation efficiency. SUMMARY

[0004] Embodiments of the present invention provide a semiconductor structure, comprising: an optical component; a thermal control mechanism adjacent to the optical component and configured to control a temperature of the optical component, wherein the thermal control mechanism comprises an electrically conductive structure, a first thermoelectric member, and a second thermoelectric member opposite to the first thermoelectric member, the first thermoelectric member and the second thermoelectric member are electrically connected to the electrically conductive structure, the first thermoelectric member and the second thermoelectric member have opposite conduction types; a first dielectric layer surrounding the optical component and part of the thermal control mechanism, wherein the electrically conductive structure is above the first dielectric layer, and the first thermoelectric member and the second thermoelectric member are surrounded by the first dielectric layer; and a first via extending through the first dielectric layer and electrically connected to the electrically conductive structure.

[0005] Another embodiment of the present invention provides a semiconductor structure, comprising: an optical component; an electronic component adjacent to the optical component; a thermal control mechanism between the electronic component and the optical component; a thermal sensing circuit between the thermal control mechanism and the optical component, wherein the thermal sensing circuit is configured to control a current direction of a current flowing through the thermal control mechanism, the thermal sensing circuit is electrically connected to the thermal control mechanism, and the thermal sensing circuit is closer to the optical component relative to the electronic component; and a first dielectric layer surrounding the optical component, at least part of the electronic component, at least part of the thermal control mechanism, and at least part of the thermal sensing circuit.

[0006] Yet another embodiment of the present invention provides a method of fabricating a semiconductor structure, comprising: forming a first dielectric layer surrounding an optical component; forming a thermal control mechanism adjacent to the optical component and at least partially surrounded by the first dielectric layer, wherein forming the thermal control mechanism comprises: forming a first thermoelectric member having a first conductivity type, forming a second thermoelectric member having a second conductivity type opposite the first conductivity type, wherein the second thermoelectric member is opposite the first thermoelectric member; and forming a conductive structure electrically connected to the thermal control mechanism over the thermal control mechanism; and forming a second dielectric layer over the first dielectric layer surrounding the conductive structure. BRIEF DESCRIPTION OF DRAWINGS

[0007] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to common practice, the various features are not necessarily drawn to scale. Indeed, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 is a cross-sectional view of a semiconductor structure in accordance with some embodiments of the present invention.

[0009] Figure 2 is an enlarged top view of a portion of the semiconductor structure in Figure 1

[0010] Figure 3 is a cross-sectional view of a semiconductor structure in accordance with some embodiments of the present invention.

[0011] Figure 4 is a cross-sectional view of a semiconductor structure in accordance with some embodiments of the present invention.

[0012] Figure 5 is a cross-sectional view of a semiconductor structure in accordance with some embodiments of the present invention.

[0013] Figure 6 is a cross-sectional view of a semiconductor structure in accordance with some embodiments of the present invention.

[0014] Figure 7 is a cross-sectional view of a semiconductor structure in accordance with some embodiments of the present invention.

[0015] Figure 8 is a cross-sectional view of a semiconductor structure in accordance with some embodiments of the present invention.

[0016] Figure 9 is a cross-sectional view of a semiconductor structure in accordance with some embodiments of the present invention.

[0017] Figure 10A and Figure 10B is a cross-sectional view of a semiconductor structure in accordance with some embodiments of the present invention. Figure 9 ​an enlarged perspective view of a portion of the semiconductor structure in

[0018] Figure 11 is a flowchart of a method of fabricating a semiconductor structure according to some embodiments of the invention.

[0019] Figures 12 to 19 are cross-sectional views of a semiconductor structure during various stages of fabrication according to some embodiments of the invention. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the application in any way. For example, the formation of a first part over or on a second part can include embodiments where the first part and the second part are formed in direct contact, and where additional parts can be formed between the first part and the second part, such that the first part and the second part can not be in direct contact. Moreover, the application can be repeated with variations and permutations of the examples described. This repetition can be appropriate for the particular structure and can depend on the variation and permutation. Similarly, the applicant can be a given name, corporate name, cross- referenced name, and the like. Such names can be used in the same sentence for convenience purposes.

[0021] Also, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or component's or portion's relationship to another element, component or portion as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0022] As used herein, although terms such as "first", "second" and "third" describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can be used only to distinguish one element, component, region, layer or section from another. Unless the context clearly indicates otherwise, as used herein, terms such as "first", "second" and "third" do not imply a sequence or order.

[0023] While the numerical ranges and parameters setting forth the broad scope of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Moreover, as used herein, the terms "substantially", "approximately" and "about" are understood to encompass a value or range of values that one of ordinary skill in the art can consider as a reasonable alternative under the circumstances. Optionally, the terms "substantially", "approximately" and "about" indicate an acceptable standard error, when considered by one of ordinary skill in the art. Those of ordinary skill in the art will appreciate that the acceptable standard error can vary depending on the different techniques.

[0024] Except in operating / working examples, or unless otherwise expressly specified, all of the numerical ranges disclosed herein are approximations. Although the numerical ranges and parameters setting forth the broad scope of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Moreover, as used herein, the terms "substantially", "approximately" and "about" are understood to encompass a value or range of values that one of ordinary skill in the art can consider as a reasonable alternative under the circumstances. Optionally, the terms "substantially", "approximately" and "about" indicate an acceptable standard error, when considered by one of ordinary skill in the art. Those of ordinary skill in the art will appreciate that the acceptable standard error can vary depending on the different techniques.

[0025] Other components and processes can also be included. For example, test structures can be included to assist in verification testing of the 3D package or 3DIC device. The test structures can include, for example, test pads formed in the redistribution layers or on the substrate that allow testing of the 3D package or 3DIC using probes and / or probe cards, etc. Verification testing can be performed on the intermediate structures as well as the final structures. Further, the structures and methods disclosed herein can be used in conjunction with test methods that incorporate intermediate verification of known good dies to improve yield and reduce cost.

[0026] A semiconductor structure is manufactured using a plurality of operations. During the manufacture of the semiconductor structure, components such as semiconductor chips or dies having different functions and sizes are stacked on each other and integrated into a single module. The components are disposed on a substrate or another component, and a mold is formed to encapsulate the components. During the operations of the semiconductor structure, each component in some cases emits heat. If the heat accumulated inside the semiconductor structure reaches a certain temperature, the performance of the components is reduced in some cases, especially when the components are heat-sensitive optical components. The reliability and performance of the semiconductor structure can be adversely affected. Therefore, heat dissipation mechanisms included in the semiconductor structure help to dissipate heat to the surrounding environment and maintain the operational efficiency of the semiconductor structure.

[0027] This invention provides a semiconductor structure and a method for manufacturing the semiconductor structure. Specifically, a semiconductor structure including an optical component, a thermal control mechanism, a first dielectric layer, and a first via is disclosed below. A semiconductor structure including an optical component, an electronic component, a thermal control mechanism, a thermal sensing circuit, and a first dielectric layer is also disclosed below. Furthermore, a method for manufacturing a semiconductor structure including an optical component and a thermal control mechanism is disclosed below. In some embodiments, other components and processes are also included. The semiconductor structure includes a thermal control mechanism configured to control the temperature of the optical component to improve its performance.

[0028] The thermal control mechanism directs heat from the optical components to the periphery of the semiconductor structure. This heat is then effectively and efficiently dissipated into the surrounding environment, thus maintaining or enhancing the performance of the semiconductor structure.

[0029] Figure 1 This is a cross-sectional view of a semiconductor structure 100 according to some embodiments of the present invention. Figure 2 yes Figure 1 An enlarged top view of the thermal control mechanism 120. In some embodiments, reference is made to... Figure 1 and Figure 2 The semiconductor structure 100 includes an optical component 111, a thermal control mechanism 120, a first dielectric layer 101, and a first through-hole 130.

[0030] In some embodiments, the optical component 111 is surrounded by a first dielectric layer 101. In some embodiments, the optical component 111 is configured to transmit optical signals or light signals. In some embodiments, the optical component 111 includes a first surface 111a and a second surface 111b opposite to the first surface 111a. In some embodiments, the first surface 111a of the optical component 111 is at the same level as the third surface 101a of the first dielectric layer 101. In some embodiments, the first surface 111a of the optical component 111 is exposed through the third surface 101a of the first dielectric layer 101. In some embodiments, the first surface 111a of the optical component 111 is below the third surface 101a of the first dielectric layer 101. In some embodiments, the first surface 111a of the optical component 111 is the front side of the optical component 111. In some embodiments, the second surface 111b is the back side of the optical component 111. The optical component 111 is capable of performing various operations, such as transmitting or processing optical signals. In some embodiments, optical component 111 includes optoelectronic devices such as modulators, phase shifters, photodiodes, waveguides, detectors, gratings, and / or couplers. In some embodiments, optical component 111 includes silicon, etc.

[0031] In some embodiments, the first dielectric layer 101 surrounds the optical component 111. In some embodiments, the first dielectric layer 101 is in contact with a sidewall of the optical component 111. In some embodiments, the first dielectric layer 101 is not in contact with the first surface 111a of the optical component 111.

[0032] In some embodiments, the first dielectric layer 101 comprises a low-k dielectric material. The low-k dielectric material has a dielectric constant (k-value) lower than 3.0, or lower than about 2.5, and is also referred to as an extremely low-k (ELK) dielectric material. In some embodiments, the first dielectric layer 101 comprises a dielectric material having a refractive index lower than that of the optical component 111. In some embodiments, the first dielectric layer 101 comprises silicon dioxide or the like. In some embodiments, the first dielectric layer 101 comprises a polymer such as polyimide, polybenzoxazole (PBO), or the like. In some embodiments, the first dielectric layer 101 comprises a single layer film or a composite stack comprising a plurality of dielectric sub-layers. In some embodiments, the dielectric sub-layers are composed of the same material or different materials.

[0033] In some embodiments, the second dielectric layer 102 is disposed over the optical component 111 and the first dielectric layer 101. In some embodiments, the second dielectric layer 102 is in contact with the first surface 111a of the optical component 111. In some embodiments, the second dielectric layer 102 is disposed on the third surface 101a of the first dielectric layer 101. In some embodiments, the second dielectric layer 102 is not in contact with the first surface 111a of the optical component 111.

[0034] In some embodiments, the second dielectric layer 102 comprises a low-k dielectric material. In some embodiments, the second dielectric layer 102 comprises a dielectric material having a refractive index lower than that of the optical component 111. In some embodiments, the second dielectric layer 102 comprises silicon dioxide or the like. In some embodiments, the second dielectric layer 102 comprises a polymer such as polyimide, polybenzoxazole (PBO), or the like. In some embodiments, the second dielectric layer 102 comprises a single layer film or a composite stack comprising a plurality of dielectric sub-layers. In some embodiments, the dielectric sub-layers are composed of the same material or different materials. In some embodiments, the first dielectric layer 101 and the second dielectric layer 102 are composed of the same material or different materials.

[0035] In some embodiments, the first via 130 extends through the first dielectric layer 101. In some embodiments, a plurality of first vias 130 extend through the first dielectric layer 101. In some embodiments, the first via 130 is disposed within the first dielectric layer 101. In some embodiments, an end of the first via 130 extends at least partially outside of the first dielectric layer 101. In some embodiments, the first via 130 protrudes from the first dielectric layer 101. In some embodiments, the second dielectric layer 102 surrounds the protruding portion of the first via 130. In some embodiments, the thermal control mechanism 120 is disposed between the first via 130 and the optical assembly 111.

[0036] In some embodiments, the first via 130 comprises an electrically conductive material such as gold, silver, copper, nickel, tungsten, aluminum, tin, and / or alloys thereof. In some embodiments, the first via 130 is a through-dielectric via (TDV). In some embodiments, the height of the first via 130 is substantially equal to the thickness of the first dielectric layer 101. In some embodiments, the height of the first via 130 is substantially greater than the thickness of the first dielectric layer 101.

[0037] In some embodiments, the diameter of the first via 130 is between about 2 pm and about 50 pm. When the diameter of the first via 130 is greater than 50 pm, the cost of the semiconductor structure 100 is too high; when the diameter of the first via 130 is less than 2 pm, the electrical resistance of the first via 130 is too high. In some embodiments, the diameter of the first via 130 is between about 10 pm and about 25 pm. In some embodiments, the length of the first via 130 is between about 5 pm and about 500 pm. When the length of the first via 130 is greater than 500 pm, the cost of the semiconductor structure 100 is too high; when the length of the first via 130 is less than 5 pm, the first dielectric layer 101 is too thin to be manufactured. In some embodiments, the length of the first via 130 is between about 20 pm and about 250 pm.

[0038] In some embodiments, the thermal control mechanism 120 is disposed adjacent to the optical assembly 111 and is configured to dissipate heat from the optical assembly 111 to the periphery or surroundings of the semiconductor structure 100. In some embodiments, the thermal control mechanism 120 is configured to transfer heat from the optical assembly 111 to another portion or another assembly of the semiconductor structure 100. In some embodiments, the thermal control mechanism 120 comprises a thermoelectric cooler (TEC). In some embodiments, the thermal control mechanism 120 is disposed in the first dielectric layer 101 and / or the second dielectric layer 102.

[0039] In some embodiments, the distance Dl between the thermal control mechanism 120 and the optical assembly 111 is between about 0.01 pm and about 1.0 pm. When the distance Dl is less than 0.01 pm, the cost of the semiconductor structure 100 is too high; when the distance Dl is greater than 1.0 pm, the efficiency of the thermal control mechanism 120 to transfer heat from the optical assembly 111 is too low. In some embodiments, as shown in Figure 1 and Figure 2 , the thermal control mechanism 120 and the optical assembly 111 are disposed along the X direction. In some embodiments, as shown in Figure 2 , the thermal control mechanism 120 surrounds the optical assembly 111 in a top view. In some embodiments, the thermal control mechanism 120 and the optical assembly 111 are laterally offset in a top view.

[0040] In some embodiments, as shown in Figure 1 and Figure 2 , the thermal control mechanism 120 includes a conductive structure 121 that is electrically connected to the first via 130 and disposed above the first dielectric layer 101. In some embodiments, the conductive structure 121 includes a conductive material such as copper or the like. In some embodiments, the thermal control mechanism 120 is electrically connected to a plurality of first vias 130. In some embodiments, the thermal control mechanism 120 further includes a first thermoelectric member 124 and a second thermoelectric member 125 opposite the first thermoelectric member 124. In some embodiments, the first thermoelectric member 124 and the second thermoelectric member 125 are surrounded by the first dielectric layer 101 and electrically connected to the conductive structure 121 and have different conduction types. In some embodiments, the first thermoelectric member 124 and the second thermoelectric member 125 have opposite conduction types.

[0041] In some embodiments, the first thermoelectric member 124 and the second thermoelectric member 125 have different Seebeck coefficients. In some embodiments, the first thermoelectric member 124 includes a p-type thermoelectric material and the second thermoelectric member 125 includes an n-type thermoelectric material. In some embodiments, the first thermoelectric member 124 includes an n-type thermoelectric material and the second thermoelectric member 125 includes a p-type thermoelectric material. In some embodiments, the first thermoelectric member 124 is a P-junction and the second thermoelectric member 125 is an N-junction. In some embodiments, the first thermoelectric member 124 includes copper or the like. In some embodiments, the second thermoelectric member 125 includes bismuth telluride (Bi2Te3), lead telluride (PbTe), or the like.

[0042] In some embodiments, the electrically conductive structure 121 is disposed above the first and second thermoelectric members 124, 125. In some embodiments, the electrically conductive structure 121 is disposed above the first via 130. In some embodiments, the electrically conductive structure 121 is disposed on the third surface 101a of the first dielectric layer 101. In some embodiments, the electrically conductive structure 121 is surrounded by the second dielectric layer 102. In some embodiments, the electrically conductive structure 121 is configured to be connected to a power source.

[0043] In some embodiments, the electrically conductive structure 121 includes a first electrically conductive member 122 and a second electrically conductive member 123 opposite the first electrically conductive member 122. In some embodiments, the first and second thermoelectric members 124, 125 are disposed between the first and second electrically conductive members 122, 123. In some embodiments, the first and second electrically conductive members 122, 123, the first and second thermoelectric members 124, 125 are connected in series. In some embodiments, the second dielectric layer 102 surrounds the first and second electrically conductive members 122, 123. In some embodiments, the first and second electrically conductive members 122, 123 extend laterally within the second dielectric layer 102.

[0044] In some embodiments, the first and second electrically conductive members 122, 123 extend parallel to each other. In some embodiments, the first and second electrically conductive members 122, 123 are disposed above the first and second thermoelectric members 124, 125. In some embodiments, the first and second electrically conductive members 122, 123 are disposed above the first via 130, and one of the first and second electrically conductive members 122, 123 is electrically connected to the first via 130. In some embodiments, the first and second electrically conductive members 122, 123 include an electrically conductive material, such as gold, silver, copper, nickel, tungsten, aluminum, tin, and / or alloys thereof.

[0045] In some embodiments, the width Wl of the first thermoelectric member 124 is between about 0.04 μm and about 100 μm. When the width Wl is greater than 100 μm, the cost of the semiconductor structure 100 is too high; when the width Wl is less than 0.04 μm, the electrical resistance of the first thermoelectric member 124 is too high. In some embodiments, the width Wl of the first thermoelectric member 124 is between about 0.04 μm and about 10 μm. In some embodiments, the width W2 of the second thermoelectric member 125 is between about 0.04 μm and about 100 μm. Similarly, when the width W2 is greater than 100 μm, the cost of the semiconductor structure 100 is too high; when the width W2 is less than 0.04 μm, the electrical resistance of the second thermoelectric member 125 is too high. In some embodiments, the width W2 of the second thermoelectric member 125 is between about 0.04 μm and about 10 μm. In some embodiments, the width Wl of the first thermoelectric member 124 is substantially equal to the width W2 of the second thermoelectric member 125. In some embodiments, the width Wl of the first thermoelectric member 124 is different from the width W2 of the second thermoelectric member 125.

[0046] In some embodiments, the first thickness Tl of the first thermoelectric member 124 and the second thickness T2 of the second thermoelectric member 125 are substantially greater than about 0.2 μm. In some embodiments, the first thickness Tl and the second thickness T2 are between about 0.2 μm and about 50 μm. When the thicknesses Tl, T2 are higher than 50 μm, the cost of the semiconductor structure 100 is too high; when the thicknesses Tl, T2 are less than 0.2 μm, the electrical resistance of the first thermoelectric member 124 and the second thermoelectric member 125 is too high. In some embodiments, the first thickness Tl and the second thickness T2 are between about 0.2 μm and about 2 μm. In some embodiments, the first thickness Tl of the first thermoelectric member 124 and the second thickness T2 of the second thermoelectric member 125 are substantially orthogonal to the third surface 101a of the first dielectric layer 101. In some embodiments, the length L of the first thermoelectric member 124 or the length L of the second thermoelectric member 125 is substantially greater than the first thickness Tl and the second thickness T2. In some embodiments, the first thickness Tl is substantially equal to the second thickness T2.

[0047] In some embodiments, the first and second thermoelectric members 124 and 125 are disposed between the first and second conductive members 122 and 123 in a top view. In some embodiments, portions of the first and second thermoelectric members 124 and 125 overlap the first and second conductive members 122 and 123 in a top view. In some embodiments, the first and second thermoelectric members 124 and 125 are adjacent to each other. In some embodiments, the first and second conductive members 122 and 123 extend between the first and second thermoelectric members 124 and 125. In some embodiments, the first and second thermoelectric members 124 and 125 are exposed through the third surface 101a of the first dielectric layer 101.

[0048] In some embodiments, the first thermoelectric member 124 includes a diffusion barrier layer at each end of the first thermoelectric member 124. In some embodiments, the second thermoelectric member 125 also includes a diffusion barrier layer at each end of the second thermoelectric member 125. In some embodiments, the diffusion barrier layer includes titanium, gold, copper, or the like. In some embodiments, the diffusion barrier layer is disposed between the first thermoelectric member 124 and the first conductive member 122, or between the first thermoelectric member 124 and the second conductive member 123. In some embodiments, the diffusion barrier layer is disposed between the second thermoelectric member 125 and the first conductive member 122, or between the second thermoelectric member 125 and the second conductive member 123.

[0049] In some embodiments, the first thermoelectric member 124 is separated from the second thermoelectric member 125 by a second distance D2. In some embodiments, the second distance D2 between the first and second thermoelectric members 124 and 125 is substantially between about 0.04 μιη and about 10 μιη. When the distance D2 is greater than 10 μιη, the size of the semiconductor structure 100 must be expanded; when the distance D2 is less than 0.04 μιη, it is a challenge to form a reliable semiconductor device. In some embodiments, the second distance D2 is between about 0.04 μιη and about 1 μιη. In some embodiments, the second distance D2 is less than the length L of the first thermoelectric member 124 or the length L of the second thermoelectric member 125.

[0050] In some embodiments, the third thickness T3 of the first thermoelectric member 124 and the fourth thickness T4 of the second thermoelectric member 125 are substantially normal to the third surface 101a of the first dielectric layer 101. In some embodiments, the length L is substantially greater than the third thickness T3 and the fourth thickness T4. In some embodiments, the first thickness T1 and the second thickness T2 are substantially greater than the third thickness T3 or the fourth thickness T4. In some embodiments, the third thickness T3 is substantially equal to the fourth thickness T4. In some embodiments, the first thickness T1 is substantially greater than the third thickness T3 and the fourth thickness T4. In some embodiments, the second thickness T2 is substantially greater than the third thickness T3 and the fourth thickness T4. In some embodiments, a width W3 of the first conductive member 122 or the second conductive member 123 is substantially equal to a width W1 of the first thermoelectric member 124 or a width W2 of the second thermoelectric member 125.

[0051] In some embodiments, the conductive structure 121 further includes a second via 126a and a third via 126b electrically connected to the first thermoelectric member 124 and the second thermoelectric member 125, respectively. In some embodiments, the second dielectric layer 102 surrounds the second via 126a and the third via 126b. In some embodiments, the second via 126a is disposed between the first conductive member 122 and the first thermoelectric member 124, or between the second conductive member 123 and the first thermoelectric member 124. In some embodiments, the third via 126b is disposed between the first conductive member 122 and the second thermoelectric member 125, or between the second conductive member 123 and the second thermoelectric member 125. In some embodiments, the conductive structure 121 includes a plurality of second vias 126a and a plurality of third vias 126b. In some embodiments, a diffusion barrier layer is disposed between the first thermoelectric member 124 and the second via 126a. In some embodiments, a diffusion barrier layer is disposed between the second thermoelectric member 125 and the third via 126b. In some embodiments, the second via 126a and the third via 126b are omitted, and the first conductive member 122 and the second conductive member 123 are attached to the first thermoelectric member 124 and the second thermoelectric member 125. As such, the thermal control mechanism 120 is configured to have a minimized thickness.

[0052] In some embodiments, the thermal control mechanism 120 is operated by applying a voltage. In some embodiments, the voltage is applied through the conductive structure 121. When the voltage is applied to the thermal control mechanism 120, a temperature difference exists between the first conductive member 122 and the second conductive member 123. As such, heat can be transferred and dissipated from the first conductive member 122 and the second conductive member 123 through the first thermoelectric member 124 and the second thermoelectric member 125. For example, heat generated from the optical assembly 111 or heat surrounding the optical assembly 111 can be dissipated by the thermal control mechanism 120. In some embodiments, heat is directed from the first conductive member 122 to the second conductive member 123. Thus, heat can be dissipated to the periphery of the semiconductor structure 100 or to the environment surrounding the thermal control mechanism 120. In some embodiments, the optical assembly 111 is heat sensitive, and thus, the thermal control mechanism 120 can draw heat away from the optical assembly 111 in order to prevent the optical assembly 111 from being thermally damaged.

[0053] In some embodiments, a heat spreader 140 is thermally and / or electrically connected to the first via 130 and is configured to spread heat emanating from or surrounding the optical assembly 111. In some embodiments, the heat spreader 140 is disposed below the first dielectric layer 101. In some embodiments, the first thermoelectric member 124 and the second thermoelectric member 125 are electrically connected to the heat spreader 140 through the first via 130 and the conductive structure 121. In some embodiments, the heat spreader 140 is disposed above the fourth surface 101b of the first dielectric layer 101. In some embodiments, the heat spreader 140 overlaps the thermal control mechanism 120 and the optical assembly 111 in a top view. In some embodiments, the heat spreader 140 comprises a conductive material, such as gold, silver, copper, nickel, tungsten, aluminum, tin, and / or alloys thereof.

[0054] In some embodiments, the semiconductor structure 100 further includes a fourth via 150 configured to transport a signal. In some embodiments, the fourth via 150 extends through the first dielectric layer 101. In some embodiments, the fourth via 150 is disposed within the first dielectric layer 101. In some embodiments, an end of the fourth via 150 is at least partially exposed by the first dielectric layer 101. In some embodiments, the fourth via 150 protrudes from the first dielectric layer 101. In some embodiments, the second dielectric layer 102 surrounds a portion of the fourth via 150 that protrudes from the first dielectric layer 101. In some embodiments, the fourth via 150 is electrically isolated from the heat spreader 140. In some embodiments, the fourth via 150 is disposed adjacent to the first via 130. In some embodiments, the fourth via 150 is disposed adjacent to the thermal control mechanism 120. In some embodiments, the first via 130 is disposed between the fourth via 150 and the thermal control mechanism 120. In some embodiments, a length of the first via 130 is substantially equal to a length of the fourth via 150. In some embodiments, the fourth via 150 is a dielectric via (TDV).

[0055] In some embodiments, the first interconnect structure 103 surrounded by the second dielectric layer 102 is electrically connected to the thermal control mechanism 120 and the first via 130. In some embodiments, the first interconnect structure 103 surrounded by the second dielectric layer 102 is electrically connected to the fourth via 150. In some embodiments, the first interconnect structure 103 includes a plurality of conductive patterns distributed in and surrounded by the second dielectric layer 102. In some embodiments, the plurality of conductive patterns includes via portions 103a and pad portions 103b. In some embodiments, the fourth via 150 is electrically connected to one of the pad portions 103b of the first interconnect structure 103. In some embodiments, the thermal control mechanism 120 is electrically connected to at least one of the via portions 103a and at least one of the pad portions 103b. In some embodiments, the first conductive member 122 and the second conductive member 123 are substantially flush with at least one of the pad portions 103b. In some embodiments, the first interconnect structure 103 includes a conductive material such as gold, silver, copper, nickel, tungsten, aluminum, tin, and / or alloys thereof.

[0056] In some embodiments, a passivation layer 104 is disposed over the second dielectric layer 102 and the first interconnect structure 103. In some embodiments, the passivation layer 104 is configured to provide a trench over the first interconnect structure 103, where the trench defines an exposed portion of the first interconnect structure 103. In some embodiments, some pad portions 103b of the first interconnect structure 103 are exposed by the passivation layer 104. In some embodiments, the passivation layer 104 comprises a dielectric material, such as polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), silicon nitride (SiN), silicon carbide (SiC), silicon oxide (SiO), silicon oxynitride (SiON), a low-k dielectric (such as carbon-doped oxide), an ultra-low-k dielectric (such as porous carbon-doped silicon dioxide), or a combination thereof.

[0057] Figure 3 is a cross-sectional view of a semiconductor structure 200 according to some embodiments of the present application. In some embodiments, the semiconductor structure 200 is similar to the semiconductor structure 100, and further comprises an electronic component 112. In some embodiments, the electronic component 112 is disposed adjacent to the optical component 111. In some embodiments, the electronic component 112 is electrically connected to the optical component 111. In some embodiments, a thermal control mechanism 120 is disposed between the optical component 111 and the electronic component 112. In some embodiments, the electronic component 112 is electrically connected to the thermal control mechanism 120. In some embodiments, the electronic component 112 is electrically connected to the thermal control mechanism 120 by the first interconnect structure 103. In some embodiments, the electronic component 112 is disposed adjacent to the thermal control mechanism 120. In some embodiments, the electronic component 112 is surrounded by the first dielectric layer 101 and / or the second dielectric layer 102.

[0058] In some embodiments, the thermal control mechanism 120 is disposed between the optical component 111 and the electronic component 112. In some embodiments, the electronic component 112 is laterally offset from the thermal control mechanism 120 and the optical component 111 in a top view. In some embodiments, the optical component 111 and the electronic component 112 are electrically connected.

[0059] In some embodiments, the electronic component 112 is configured to transmit electrical signals. In some embodiments, the electronic component 112 is a die, such as a logic device die, a central processing unit (CPU) die, a system on a chip (SoC), etc. In some embodiments, the electronic component 112 comprises a plurality of electrically conductive members 112a, such as pads or vias. In some embodiments, the electrically conductive members 112a form an electrical circuit within the electronic component 112. In some embodiments, the electrically conductive members 112a comprise gold, silver, copper, nickel, tungsten, aluminum, palladium, and / or alloys thereof.

[0060] In some embodiments, the semiconductor structure 200 includes an optical portion 210 and an electronic portion 220 adjacent to the optical portion 210. In some embodiments, the optical portion 210 is laterally offset from the electronic portion 220 in a top view. As the optical components 111 are more sensitive to heat than the electronic components 112, in some embodiments, the optical portion 210 includes the optical components 111 and the thermal control mechanism 120, and the electronic portion 220 includes the electronic components 112. In some embodiments, the heat spreader 140 is disposed in the optical portion 210. In some embodiments, the heat spreader 140 is disposed in the optical portion 210 and the electronic portion 220. In some embodiments, the optical components 111, the electronic components 112, and the thermal control mechanism 120 are disposed on the heat spreader 140.

[0061] Figure 4 is a cross-sectional view of a semiconductor structure 300 according to some embodiments of the present application. In some embodiments, the semiconductor structure 300 is similar to the semiconductor structure 100, and further includes the electronic components 112 disposed below the optical components 111 and the molding 160 surrounding the thermal control mechanism 120, the optical components 111, and the electronic components 112. In some embodiments, the semiconductor structure 300 further includes the RDL 106 disposed on the second dielectric layer 102, and the bump pads 107 and the first conductive bumps 108 disposed on the RDL 106.

[0062] In some embodiments, the electronic components 112 are disposed between the heat spreader 140 and the optical components 111. In some embodiments, the thermal control mechanism 120 surrounds the optical components 111 and the electronic components 112 in a top view. In some embodiments, the thermal control mechanism 120 and the electronic components 112 overlap in a top view.

[0063] In some embodiments, the electronic components 112 are disposed above the fourth surface 101b of the first dielectric layer 101. In some embodiments, the electronic components 112 are disposed below the first dielectric layer 101. In some embodiments, the electronic components 112 are in contact with the fourth surface 101b of the first dielectric layer 101. In some embodiments, the heat spreader 140 is disposed below the electronic components 112. In some embodiments, the first via 130 extends through the electronic components 112. In some embodiments, the first via 130 extends through the first dielectric layer 101 and the electronic components 112. In some embodiments, the fourth via 150 is electrically connected to the pad portion 103b disposed in the second dielectric layer 102 and the electronic components 112. In some embodiments, the electronic components 112 include a substrate.

[0064] In some embodiments, the semiconductor structure 300 includes a redistribution layer (RDL) 106 disposed on the second dielectric layer 102 and the first interconnect structure 103. In some embodiments, the RDL 106 includes a fourth dielectric layer 106a and a second interconnect structure 106b surrounded by the fourth dielectric layer 106a. In some embodiments, the RDL 106 is a front-side RDL.

[0065] In some embodiments, the fourth dielectric layer 106a is a single dielectric layer. In some embodiments, the fourth dielectric layer 106a is composed of multiple dielectric layers. In some embodiments, the fourth dielectric layer 106a includes a dielectric material, such as silicon oxide, silicon nitride, undoped silicon glass, or the like. In some embodiments, the fourth dielectric layer 106a includes a polymeric material, such as polyimide (PI), polybenzoxazole (PBO), or the like. In some embodiments, the fourth dielectric layer 106a includes several dielectric layers that are different or the same from each other in dielectric material.

[0066] In some embodiments, the second interconnect structure 106b is surrounded by the fourth dielectric layer 106a. In some embodiments, the second interconnect structure 106b extends within the fourth dielectric layer 106a. In some embodiments, the second interconnect structure 106b extends through one or more layers of the fourth dielectric layer 106a. In some embodiments, the second interconnect structure 106b is electrically connected to the first interconnect structure 103, the first via 130, and the thermal control mechanism 120. In some embodiments, the second interconnect structure 106b is directly coupled with the first interconnect structure 103. In some embodiments, the second interconnect structure 106b is electrically connected to the electronic component 112. In some embodiments, the second interconnect structure 106b is electrically connected to the fourth via 150. In some embodiments, the second interconnect structure 106b includes a conductive material, such as gold, silver, copper, nickel, tungsten, aluminum, tin, and / or alloys thereof.

[0067] In some embodiments, bump pads 107 are disposed on RDL 106. In some embodiments, bump pads 107 are disposed on fourth dielectric layer 106a and electrically connected to second interconnect structures 106b. In some embodiments, bump pads 107 are configured to receive conductive members or the like. In some embodiments, bump pads 107 comprise under bump metallization (UBM) pads. In some embodiments, bump pads 107 are electrically connected to thermal control mechanism 120 through first interconnect structures 103 and second interconnect structures 106b. In some embodiments, bump pads 107 are electrically connected to optical assembly 111. In some embodiments, bump pads 107 are electrically connected to electronic assembly 112. In some embodiments, bump pads 107 are electrically connected to first vias 130 and heat spreader 140 through first interconnect structures 103 and second interconnect structures 106b. In some embodiments, bump pads 107 comprise gold, silver, copper, nickel, tungsten, aluminum, palladium, and / or alloys thereof. In some embodiments, bump pads 107 are omitted.

[0068] In some embodiments, first conductive bumps 108 are disposed on RDL 106 and electrically connected to first interconnect structures 103 and second interconnect structures 106b. In some embodiments, first conductive bumps 108 are disposed on bump pads 107. In some embodiments, first conductive bumps 108 comprise conductive materials such as solder, copper, nickel, gold, or the like. In some embodiments, first conductive bumps 108 are solder balls, ball grid array (BGA) balls, controlled collapse chip connection (C4) bumps, posts, or the like. In some embodiments, first conductive bumps 108 are spherical, semi-spherical, or cylindrical.

[0069] In some embodiments, semiconductor structure 300 is a semiconductor package. In some embodiments, semiconductor structure 300 is part of a semiconductor package. In some embodiments, semiconductor structure 300 is an integrated fan-out (InFO) package, in which I / O terminals of electronic assembly 112 are fan-out and redistributed over a larger area. In some embodiments, semiconductor structure 300 is a three-dimensional integrated circuit (3DIC). In some embodiments, semiconductor structure 300 is a chip-on-wafer-on-substrate (CoWoS) structure.

[0070] In some embodiments, mold 160 surrounds first dielectric layer 101, second dielectric layer 102, and electronic assembly 112. In some embodiments, mold 160 is in contact with sidewalls of first dielectric layer 101, second dielectric layer 102, and electronic assembly 112. In some embodiments, mold 160 is in contact with sidewalls of heat spreader 140 and exposes at least portions of heat spreader 140. In some embodiments, mold 160 comprises a single layer of film or a composite stack. In some embodiments, RDL 106 is disposed on mold 160.

[0071] In some embodiments, the mold 160 has high thermal conductivity, low moisture absorption, and high flexural strength. In some embodiments, the mold 160 includes various materials, such as molding compound, mold underfill, epoxy, resin, etc.

[0072] Figure 5 is a cross-sectional view of a semiconductor structure 400 according to some embodiments of the present application. In some embodiments, the semiconductor structure 400 is similar to the semiconductor structure 300 and further includes a die 113 disposed below the heat spreader 140 and a second conductive bump 114 electrically connected to the die 113. In some embodiments, the die 113 is disposed below the heat spreader 140 and electrically connected to the second interconnect structure 106b of the RDL 106. In some embodiments, the die 113 is disposed below the electronic assembly 112. In some embodiments, the mold 160 surrounds the die 113. In some embodiments, portions of the die 113 are exposed by the mold 160.

[0073] In some embodiments, the die 113 is fabricated with predetermined functional circuitry located within the die 113, where the predetermined functional circuitry is produced by a photolithography operation. In some embodiments, the die 113 is a memory die, a dynamic random access memory (DRAM) die, a high bandwidth memory (HBM) die, etc. In some embodiments, the die 113 is a chip or a package. In some embodiments, the die 113 is electrically connected to the electronic assembly 112.

[0074] In some embodiments, the die 113 includes a fifth surface 113a and a sixth surface 113b opposite the fifth surface 113a. In some embodiments, the fifth surface 113a is a front side or an active side of the die 113. In some embodiments, the sixth surface 113b is a back side or a passive side of the die 113. In some embodiments, the fifth surface 113a is directly coupled to the heat spreader 140. In some embodiments, the sixth surface 113b is exposed by the mold 160.

[0075] In some embodiments, the die 113 includes a plurality of second pads 113c disposed above or within the die 113. In some embodiments, the second pads 113c are electrically connected to the second interconnect structure 106b of the RDL 106 through the fifth via 131. In some embodiments, the fifth via 131 is disposed between the RDL 106 and the die 113. In some embodiments, the mold 160 surrounds the fifth via 131. In some embodiments, the second pads 113c are electrically connected to the thermal control mechanism 120 and the first via 130 through the second conductive bump 114, the fifth via 131, and the second interconnect structure 106b. In some embodiments, the second pads 113c are electrically connected to the fourth via 150.

[0076] In some embodiments, the second pad 113c is disposed above the fifth surface 113a of the die 113. In some embodiments, the second pad 113c is electrically connected to circuitry above or within the die 113. In some embodiments, the second pad 113c is configured to be electrically connected to circuitry external to the die 113. In some embodiments, the second pad 113c is configured to be electrically connected to a conductive trace or conductive structure. In some embodiments, the second pad 113c comprises gold, silver, copper, nickel, tungsten, aluminum, palladium, and / or alloys thereof. For the sake of clarity and simplicity, Figure 5 Only two second pads 113c above the die 113 are shown, however, one of ordinary skill in the art will readily understand that one or more second pads 113c are present above the die 113 in some embodiments.

[0077] Figure 6 is a cross-sectional view of a semiconductor structure 500 in accordance with some embodiments of the present application. In some embodiments, the semiconductor structure 500 is similar to the semiconductor structure 100 and further comprises an electronic component 112 disposed below the heat spreader 140, and a mold 160 surrounding the first dielectric layer 101, the second dielectric layer 102, the electronic component 112, and the heat spreader 140. In some embodiments, the semiconductor structure 500 further comprises an RDL 106 disposed below the electronic component 112, wherein the bump pad 107 and the first conductive bump 108 are disposed below the RDL 106. In some embodiments, the RDL 106 is electrically connected to the electronic component 112.

[0078] In some embodiments, the heat spreader 140 is disposed between the optical component 111 and the electronic component 112. In some embodiments, the heat spreader 140 is electrically isolated from the electronic component 112. In some embodiments, the second interconnect structure 106b is electrically connected to the first interconnect structure 103.

[0079] In some embodiments, the fourth via 150 comprises a first portion 151 disposed in the first dielectric layer 101 and the second dielectric layer 102, and a second portion 152 disposed in the electronic component 112. In some embodiments, the third conductive bump 109 is disposed between and electrically connected to the first portion 151 and the second portion 152. In some embodiments, the third conductive bump 109 comprises a conductive material such as solder, copper, nickel, gold, etc. In some embodiments, the first conductive bump 108 is a solder ball, a ball grid array (BGA) ball, a controlled collapse chip connection (C4) bump, a post, etc. In some embodiments, the third conductive bump 109 is spherical, semi-spherical, or cylindrical.

[0080] Figure 7is a cross-sectional view of a semiconductor structure 600 according to some embodiments of the application. In some embodiments, semiconductor structure 600 is similar to semiconductor structure 500 and further includes a die 113 disposed above passivation layer 104 and a fourth conductive bump 115 electrically connecting die 113 to first interconnect structure 103. In some embodiments, die 113 is disposed above second dielectric layer 102. In some embodiments, at least a portion of thermal control mechanism 120 is disposed between die 113 and electronic component 112.

[0081] In some embodiments, fourth conductive bump 115 is surrounded by molding 160. In some embodiments, molding 160 is disposed between passivation layer 104 and die 113. In some embodiments, fourth conductive bump 115 is disposed between first interconnect structure 103 and die 113. In some embodiments, fourth conductive bump 115 includes a conductive material such as solder, copper, nickel, gold, etc. In some embodiments, fourth conductive bump 115 is a solder ball, a ball grid array (BGA) ball, a controlled collapse chip connection (C4) bump, a post, etc. In some embodiments, fourth conductive bump 115 is spherical, semi-spherical, or cylindrical.

[0082] Figure 8 is a cross-sectional view of a semiconductor structure 700 according to some embodiments of the application. In some embodiments, semiconductor structure 700 is similar to semiconductor structure 100 and further includes electronic component 112 adjacent to thermal control mechanism 120. In some embodiments, electronic component 112 is disposed adjacent to the stack of first dielectric layer 101 and second dielectric layer 102. In some embodiments, the thickness of electronic component 112 is substantially equal to the total thickness of first dielectric layer 101 and second dielectric layer 102. In some embodiments, electronic component 112 is electrically connected to second interconnect structure 106b.

[0083] In some embodiments, heat spreader 140 is disposed below first via 130, thermal control mechanism 120, and optical component 111. In some embodiments, passivation layer 104 is disposed adjacent to heat spreader 140 and heat spreader 140 is exposed by passivation layer 104. In some embodiments, passivation layer 104 is disposed below electronic component 112.

[0084] In some embodiments, the molding 160 surrounds the optical portion 210 and the electronic portion 220. In some embodiments, the portion 162 of the molding 160 is disposed between the optical portion 210 and the electronic portion 220. In some embodiments, the portion 162 of the molding 160 separates the optical portion 210 from the electronic portion 220. In some embodiments, the portion 162 of the molding 160 is disposed between the electronic assembly 112 and the stack of the first dielectric layer 101 and the second dielectric layer 102. In some embodiments, the portion 162 of the molding 160 is disposed between the RDL 103 and the passivation layer 104.

[0085] In some embodiments, the RDL 106 is disposed on the second dielectric layer 102 and the electronic assembly 112. In some embodiments, the passivation layer 104 is disposed under the first dielectric layer 101 and the electronic assembly 112.

[0086] In some embodiments, the molding surrounds the RDL 106 and the passivation layer 104.

[0087] Figure 9 is a cross-sectional view of a semiconductor structure 800 according to some embodiments of the present application. In some embodiments, referring to Figure 9 , the semiconductor structure 800 includes the optical assembly 111, the electronic assembly 112 adjacent to the optical assembly 111, the thermal control mechanism 120 between the optical assembly 111 and the electronic assembly 112, the first dielectric layer 101, and the thermal sensing circuit 170. The thermal sensing circuit 170 is disposed between the thermal control mechanism 120 and the optical assembly 111 and is configured to control the current direction of the current flowing through the thermal control mechanism 120. In some embodiments, the first via 130 and the heat sink 140 are omitted.

[0088] In some embodiments, the thermal control mechanism 120, the thermal sensing circuit 170, and the optical assembly 111 are disposed in the optical portion 210. The thermal sensing circuit 170 is electrically connected to the thermal control mechanism 120 and is closer to the optical assembly 111 than to the electronic assembly 112. In some embodiments, a third distance D3 between the thermal sensing circuit 170 and the optical assembly 111 is between about 0.01 pm and about 1.0 pm for optimal thermal sensing. When the distance D3 is less than 0.01 pm, the cost of the semiconductor structure 100 is too high; when the distance D3 is greater than 1.0 pm, the thermal sensing circuit 170 cannot accurately sense the state of the optical assembly 111. In some embodiments, the third distance D3 is between about 0.02 pm and about 0.5 pm. In some embodiments, the thermal sensing circuit 170 includes a bandgap temperature sensor.

[0089] In some embodiments, the first dielectric layer 101 surrounds at least a portion of the thermal sensing circuit 170. In some embodiments, the second dielectric layer 102 surrounds at least a portion of the thermal sensing circuit 170. In some embodiments, in a top view, the thermal control mechanism 120 surrounds the thermal sensing circuit 170 and the optical assembly 111.

[0090] In some embodiments, the thermal sensing circuit 170 is electrically connected to the thermal control mechanism 120 through the conductive structure 121. In some embodiments, the thermal sensing circuit 170 is electrically connected to the thermal control mechanism 120 through the first conductive member 122 and the second conductive member 123. In some embodiments, the thermal sensing circuit 170 is electrically connected to the electronic assembly 112 through the first interconnect structure 103.

[0091] Figure 10A and Figure 10B is Figure 9 an enlarged perspective view of a portion of the semiconductor structure 800 in . The thermal sensing circuit 170 controls the current direction of the current flowing through the thermal control mechanism 120 to transfer heat from the optical assembly 111 to the electronic assembly 112 to cool the optical assembly 111. As such, the thermal control mechanism 120 is capable of adjusting the temperature of the optical assembly 111 and the electronic assembly 112. In some embodiments, by controlling the current direction, the optical assembly 111 is cooled. In some embodiments, the thermal control mechanism 120 is capable of transferring heat from the electronic assembly 112 to the optical assembly 111 while keeping the temperature of the optical assembly 111 or the temperature surrounding the optical assembly 111 below a predetermined threshold temperature and ensuring no adverse effect on the performance or function of the optical assembly 111. As such, the thermal control mechanism 120 is capable of adjusting the temperature of the optical assembly 111 and the electronic assembly 112. In some embodiments, by controlling the current direction, the electronic assembly 112 is capable of dissipating heat while the temperature of the optical assembly 111 is controllable.

[0092] In some embodiments, referring to Figure 10A , the current 181 flows through the thermal control mechanism 120 and the heat 182 is transferred from the optical assembly 111 to the electronic assembly 112. In some embodiments, the current 181 flows from the second conductive member 123 to the first thermoelectric member 124 and from the first conductive member 122 to the second thermoelectric member 125 and the heat is dissipated from the optical assembly 111 to the electronic assembly 112. In some embodiments, the thermal control mechanism 120 surrounds the thermal sensing circuit 170 and the optical assembly 111, the current flows counterclockwise, and the heat is dissipated from the optical assembly 111 to the electronic assembly 112.

[0093] In some embodiments, referring to Figure 10BCurrent 181 flows through thermal control mechanism 120 and heat 182 is transferred from electronic component 112 to optical component 111. In some embodiments, current 181 flows from second conductive member 123 to second thermoelectric member 125 and from first conductive member 122 to first thermoelectric member 124 and heat is dissipated from electronic component 112. In some embodiments, thermal control mechanism 120 surrounds thermal sensing circuit 170 and optical component 111, current flows clockwise and heat is dissipated from electronic component 112 to optical component 111.

[0094] Figure 11 is a flowchart of a method M10 for fabricating a semiconductor structure according to some embodiments of the present application. As shown in Figure 11 , method M10 comprises several operations: (O101) forming an optical component surrounded by a first dielectric layer; (O102) forming a thermal control mechanism adjacent to the optical component and surrounded by the first dielectric layer; and (O103) forming a conductive structure disposed over the thermal control mechanism and electrically connected to the thermal control mechanism and surrounded by a second dielectric layer over the first dielectric layer. The forming of the thermal control mechanism comprises forming a first thermoelectric member of a first conductivity type and forming a second thermoelectric member of a second conductivity type, wherein the first conductivity type is opposite to the second conductivity type, and the first thermoelectric member is disposed opposite to the second thermoelectric member.

[0095] Figures 12 to 19 is a schematic cross-sectional view of a semiconductor structure during various stages of fabrication according to some embodiments of the present application. In some embodiments, method M10 can be used to form semiconductor structure 100 as shown in Figure 1 .

[0096] As shown in Figure 12 , in operation O101, an optical component 111 is formed surrounded by a first dielectric layer 101. In some embodiments, optical component 111 is embedded in first dielectric layer 101. In some embodiments, first dielectric layer 101 is formed by a suitable fabrication technique, such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc. In some embodiments, first dielectric layer 101 is composed of a single layer or multiple layers stacked on each other.

[0097] In some embodiments, operation O101 further comprises adjusting a first surface 111a of optical component 111 to be coplanar with a third surface 101a of first dielectric layer 101. In some embodiments, operation O101 further comprises exposing first surface 111a of optical component 111 through third surface 101a of first dielectric layer 101.

[0098] In some embodiments, in operation O102, a thermal control mechanism 120 is formed adjacent to the optical component 111 and surrounded by the first dielectric layer 101. Figure 13 and Figures 15 to 17 Formation of the thermal control mechanism 120 is shown. In some embodiments, the formation of the thermal control mechanism 120 and the formation of the first RDL 103 are performed simultaneously or separately.

[0099] In some embodiments, referring to Figure 13 , the first thermoelectric member 124 and the second thermoelectric member 125 are disposed within the first dielectric layer 101. In some embodiments, the second thermoelectric member 125 is disposed adjacent to the first thermoelectric member 124. In some embodiments, the first thermoelectric member 124 and the second thermoelectric member 125 are formed by doping a first thermoelectric material and a second thermoelectric material different from the first thermoelectric material within an opening of the first dielectric layer 101. In some embodiments, the first thermoelectric member 124 and the second thermoelectric member 125 are formed by an electroplating operation. In some embodiments, the first thermoelectric member 124 and the second thermoelectric member 125 are in a configuration as described above or as shown in Figure 1 and Figure 2 In some embodiments, the top surfaces of the first thermoelectric member 124 and the second thermoelectric member 125 are substantially flush or substantially coplanar with the third surface 101a of the first dielectric layer 101.

[0100] In some embodiments, referring to Figure 14 , the electrically conductive member 112a of the electronic component 112 is disposed adjacent to the first thermoelectric member 124 and the second thermoelectric member 125. In some embodiments, the formation of the first thermoelectric member 124 and the second thermoelectric member 125 and the disposition of the electrically conductive member 112a are performed simultaneously or separately. In some embodiments, the electrically conductive member 112a of the electronic component 112 is formed by photolithography, electroplating, or any other suitable operation. In some embodiments, the disposition of the electronic component 112 includes placing the electronic component 112, such as a die, over the first dielectric layer 101. In some embodiments, the electronic component 112 is in a configuration as described above or as shown in Figure 3 .

[0101] In some embodiments, referring to Figure 15 , the first via 130 is formed. In some embodiments, the first via 130 is formed by removing a portion of the first dielectric layer 101 to form an opening and then disposing an electrically conductive material in the opening. In some embodiments, the removing of the portion of the first dielectric layer 101 includes photolithography, etching, or any other suitable operation. In some embodiments, the disposing of the electrically conductive material includes sputtering, electroplating, or any other suitable operation. In some embodiments, the first via 130 is in a configuration as described above or as shown in Figure 1 and Figure 3 .

[0102] In some embodiments, referring to Figure 16 , a second dielectric layer 102 is formed over the first dielectric layer 101. In some embodiments, the second dielectric layer 102 is formed by suitable fabrication techniques, such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc. In some embodiments, the second dielectric layer 102 consists of a single layer or multiple layers stacked with each other.

[0103] In some embodiments, the electrically conductive structure 121, the first interconnect structure 103 are formed within the second dielectric layer 102. In some embodiments, the electrically conductive structure 121 and the first interconnect structure 103 are in a configuration as described above or as shown in Figure 1 and Figure 3 In some embodiments, the second via 126a, the third via 126b, and a portion of the first via 130 protruding from the first dielectric layer 101 are surrounded by the second dielectric layer 102. In some embodiments, the electronic component 112 is surrounded by the first dielectric layer 101 and / or the second dielectric layer 102. In some embodiments, the first via 130, the first thermoelectric member 124, and the second thermoelectric member 125 are disposed between the electronic component 112 and the optical component 111.

[0104] In some embodiments, the first interconnect structure 103 is electrically connected to the thermal control mechanism 120 and the electronic component 112. In some embodiments, some pad portions 103b of the interconnect structure 103 are exposed by the second dielectric layer 102.

[0105] In some embodiments, referring to Figure 17 , the method M10 further includes forming a heat spreader 140 electrically connected to the first via 130. In some embodiments, the heat spreader 140 is formed under the optical component 111, the thermal control mechanism 120, the first via 130, and the electronic component 112. In some embodiments, the heat spreader 140 is formed by suitable fabrication techniques, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc. In some embodiments, the heat spreader 140 is in a configuration as described above or as shown in Figure 1 and Figure 3 In some embodiments, referring to

[0106] In some embodiments, referring to Figure 18 , the method M10 further includes forming a passivation layer 104 over the second dielectric layer 102 and the first interconnect structure 103. In some embodiments, some pad portions 103b are exposed by the passivation layer 104. In some embodiments, the passivation layer 104 is in a configuration as described above or as shown in Figure 1 and Figure 3 In some embodiments, referring to

[0107] In some embodiments, with reference to Figure 19 instead of forming the first via 130 and the heat spreader 140, the method M10 further includes forming a thermal sensing circuit 170 disposed between the thermal control mechanism 120 and the optical assembly 111. In some embodiments, the thermal sensing circuit 170 is in a configuration as described above or shown in FIG. 2B. Figure 9

[0108] In some embodiments, the thermal sensing circuit 170 is electrically connected to the thermal control mechanism 120 and the electronic assembly 112 through the first interconnect structure 103. In some embodiments, the thermal sensing circuit 170 is surrounded by the thermal control mechanism 120 in a top view. In some embodiments, the forming of the thermal control mechanism 120 and the forming of the thermal sensing circuit 170 are performed simultaneously or separately.

[0109] In some embodiments, a passivation layer 104 is formed over the second dielectric layer 102 and the first interconnect structure 103. In some embodiments, some pad portions 103b electrically connected to the thermal sensing circuit 170 are exposed by the passivation layer 104. In some embodiments, the passivation layer 104 is in a configuration as described above or shown in FIG. 2B. Figure 9

[0110] ​​Aspects of the present disclosure relate to a semiconductor structure. The semiconductor structure includes an optical component. The semiconductor structure also includes a thermal control mechanism adjacent to the optical component and configured to control a temperature of the optical component. The thermal control mechanism includes an electrically conductive structure, a first thermoelectric member, and a second thermoelectric member opposite the first thermoelectric member. The first thermoelectric member and the second thermoelectric member are electrically connected to the electrically conductive structure. The first thermoelectric member and the second thermoelectric member have opposite conductivity types. The semiconductor structure also includes a first dielectric layer surrounding the optical component and a portion of the thermal control mechanism, where the electrically conductive structure is above the first dielectric layer and the first thermoelectric member and the second thermoelectric member are surrounded by the first dielectric layer. The semiconductor structure also includes a first via extending through the first dielectric layer and electrically connected to the electrically conductive structure. In some embodiments, the semiconductor structure also includes a heat spreader electrically connected to the first via, where the heat spreader is above the first dielectric layer. In some embodiments, the heat spreader is above a first surface of the first dielectric layer and the electrically conductive structure is above a second surface of the first dielectric layer opposite the first surface. In some embodiments, the electrically conductive structure includes a second via and a third via, where the second via is electrically connected to the first thermoelectric member and the third via is electrically connected to the second thermoelectric member. In some embodiments, the semiconductor structure also includes a second dielectric layer above the optical component and the first dielectric layer, where the electrically conductive structure is surrounded by the second dielectric layer. In some embodiments, the first thermoelectric member and the second thermoelectric member are electrically connected to the heat spreader through the first via and the electrically conductive structure. In some embodiments, the thermal control mechanism surrounds the optical component. In some embodiments, the semiconductor structure also includes an electronic component electrically connected to the thermal control mechanism. In some embodiments, the thermal control mechanism is between the electronic component and the optical component. In some embodiments, the semiconductor structure also includes the electronic component between the heat spreader and the optical component. In some embodiments, the semiconductor structure also includes the electronic component, where the heat spreader is between the electronic component and the optical component. In some embodiments, a distance between the thermal control mechanism and the optical component is in a range from about 0.01 pm to about 1.0 pm.

[0111] One aspect of the specification relates to a semiconductor structure. The semiconductor structure includes an optical component. The semiconductor structure also includes an electronic component adjacent to the optical component. The semiconductor structure also includes a thermal control mechanism between the electronic component and the optical component. The semiconductor structure also includes a thermal sensing circuit between the thermal control mechanism and the optical component, where the thermal sensing circuit is configured to control a current direction of a current flowing through the thermal control mechanism, the thermal sensing circuit is electrically connected to the thermal control mechanism, and the thermal sensing circuit is closer to the optical component than the electronic component. The semiconductor structure also includes a first dielectric layer surrounding the optical component, at least a portion of the electronic component, at least a portion of the thermal control mechanism, and at least a portion of the thermal sensing circuit. In some embodiments, the thermal control mechanism includes a conductive structure electrically connected to the first via and located above the first dielectric layer; a first thermoelectric member and a second thermoelectric member opposite the first thermoelectric member, where the first and second thermoelectric members are surrounded by the first dielectric layer, electrically connected to the conductive structure, and have opposite conduction types. In some embodiments, a distance between the thermal sensing circuit and the optical component is in a range from about 0.01 pm to about 1.0 pm.

[0112] One aspect of the specification relates to a method of manufacturing a semiconductor structure. The method includes forming a first dielectric layer surrounding an optical component. The method also includes forming a thermal control mechanism adjacent to the optical component and at least partially surrounded by the first dielectric layer. Forming the thermal control mechanism includes forming a first thermoelectric member having a first conduction type, forming a second thermoelectric member having a second conduction type opposite the first conduction type, where the second thermoelectric member is opposite the first thermoelectric member, and forming a conductive structure above the thermal control mechanism electrically connected to the thermal control mechanism. The method also includes forming a second dielectric layer above the first dielectric layer surrounding the conductive structure. In some embodiments, forming the conductive structure includes forming a first conductive member extending between the first and second thermoelectric members, where the first conductive member is surrounded by the second dielectric layer; and forming a second conductive member extending between the first and second thermoelectric members and adjacent to the first conductive member, where the second conductive member is surrounded by the second dielectric layer. In some embodiments, each of the first and second thermoelectric members is formed by electroplating. In some embodiments, the method also includes forming a via extending through the first dielectric layer and electrically connected to the thermal control mechanism; and forming a heat spreader electrically connected to the via. In some embodiments, the method also includes disposing an electronic component adjacent to the thermal control mechanism, where the electronic component is surrounded by the first or second dielectric layer, and the thermal control mechanism is between the electronic component and the optical component; and forming a thermal sensing circuit between the thermal control mechanism and the optical component.

[0113] The foregoing summary of some embodiments has been presented with sufficient particularity by way of example to convey the spirit and scope of the application to persons skilled in the art. It is clear that other embodiments can be drawn from the foregoing description that fall within the scope of the invention. Those skilled in the art will appreciate that they can readily use the conception disclosed with the present invention as a basis for the designing or modifying of other processes and / or structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will realize that such equivalent constructions do not depart from the spirit and scope of the invention, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present invention in its broadest form.

Claims

1. A semiconductor structure, comprising: an optical component; a thermal control mechanism adjacent to the optical component and configured to control a temperature of the optical component, wherein, the thermal control mechanism includes an electrically conductive structure, a first thermoelectric member, and a second thermoelectric member opposite the first thermoelectric member, the first thermoelectric member and the second thermoelectric member are electrically connected to the electrically conductive structure, the first thermoelectric member and the second thermoelectric member have opposite conduction types; a first dielectric layer surrounding the optical component and a portion of the thermal control mechanism, wherein the electrically conductive structure is above the first dielectric layer, and the first thermoelectric member and the second thermoelectric member are surrounded by the first dielectric layer; and a first via extending through the first dielectric layer and electrically connected to the electrically conductive structure.

2. The semiconductor structure of claim 1, further comprising: a heat sink electrically connected to the first via, wherein the heat sink is above the first dielectric layer.

3. The semiconductor structure of claim 2, wherein, the heat sink is above a first surface of the first dielectric layer, and the electrically conductive structure is above a second surface of the first dielectric layer opposite the first surface.

4. The semiconductor structure of claim 1, wherein, the electrically conductive structure includes a second via and a third via, wherein the second via is electrically connected to the first thermoelectric member, and the third via is electrically connected to the second thermoelectric member.

5. The semiconductor structure of claim 1, further comprising: a second dielectric layer above the optical component and the first dielectric layer, wherein the electrically conductive structure is surrounded by the second dielectric layer.

6. The semiconductor structure of claim 2, wherein, the first thermoelectric member and the second thermoelectric member are electrically connected to the heat sink through the first via and the electrically conductive structure.

7. The semiconductor structure of claim 1, wherein, the thermal control mechanism surrounds the optical component.

8. The semiconductor structure of claim 1, further comprising: an electronic component electrically connected to the thermal control mechanism.

9. The semiconductor structure of claim 8, wherein, the thermal control mechanism is between the electronic component and the optical component.

10. The semiconductor structure of claim 2, further comprising: an electronic component between the heat sink and the optical component.

11. The semiconductor structure of claim 2, further comprising: an electronic component, wherein the heat sink is between the electronic component and the optical component.

12. The semiconductor structure of claim 1, wherein, a distance between the thermal control mechanism and the optical component is in a range from 0.01 pm to 1.0 pm.

13. A semiconductor structure, comprising: an optical component; an electronic component adjacent to the optical component; a thermal control mechanism between the electronic component and the optical component; a thermal sensing circuit between the thermal control mechanism and the optical component, wherein the thermal sensing circuit is configured to control a current direction of a current flowing through the thermal control mechanism, the thermal sensing circuit is electrically connected to the thermal control mechanism, and the thermal sensing circuit is closer to the optical component relative to the electronic component; and a first dielectric layer surrounding the optical component, at least a portion of the electronic component, at least a portion of the thermal control mechanism, and at least a portion of the thermal sensing circuit; wherein the thermal control mechanism includes: a conductive structure electrically connected to the first via and positioned above the first dielectric layer, a first thermoelectric member, and a second thermoelectric member, opposite the first thermoelectric member, wherein the first and second thermoelectric members are surrounded by the first dielectric layer, electrically connected to the conductive structure, and have opposite conductive types.

14. The semiconductor structure of claim 13, wherein, The first thermoelectric member is separated from the second thermoelectric member by a distance between 0.04 pm and 10 pm.

15. The semiconductor structure of claim 13, wherein, A distance between the thermal sensing circuit and the optical assembly is in a range from 0.01 pm to 1.0 pm.

16. A method of fabricating a semiconductor structure, comprising: forming a first dielectric layer surrounding an optical assembly; forming a thermal control mechanism adjacent to the optical assembly and at least partially surrounded by the first dielectric layer, wherein forming the thermal control mechanism comprises: forming a first thermoelectric member having a first conductive type, forming a second thermoelectric member having a second conductive type opposite the first conductive type, wherein the second thermoelectric member is opposite the first thermoelectric member; and forming a conductive structure above the thermal control mechanism electrically connected to the thermal control mechanism; and forming a second dielectric layer above the first dielectric layer surrounding the conductive structure.

17. The method of claim 16, wherein, The forming of the conductive structure comprises: forming a first conductive member extending between the first and second thermoelectric members, wherein the first conductive member is surrounded by the second dielectric layer; and forming a second conductive member extending between the first and second thermoelectric members and adjacent to the first conductive member, wherein the second conductive member is surrounded by the second dielectric layer.

18. The method of claim 16, wherein, Each of the first and second thermoelectric members is formed by electroplating.

19. The method of claim 16, further comprising: forming a via extending through the first dielectric layer and electrically connected to the thermal control mechanism; and forming a heat spreader electrically connected to the via.

20. The method of claim 16, further comprising: positioning an electronic assembly adjacent to the thermal control mechanism, wherein the electronic assembly is surrounded by the first or second dielectric layer and the thermal control mechanism is positioned between the electronic assembly and the optical assembly; and forming a thermal sensing circuit between the thermal control mechanism and the optical assembly.

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