Electrostatic discharge circuit and electrostatic discharge control system

Abstract

The present application relates to an electrostatic discharge circuit, which can include a control voltage generation circuit, an electrostatic detection circuit, a drive control circuit, and a discharge drive circuit. The control voltage generation circuit can generate first to third control voltages by a voltage division operation on a supply voltage. The electrostatic detection circuit can set a first set voltage based on the first control voltage, and detect electrostatic transmitted through the first set voltage. The drive control circuit can set a second set voltage based on the second control voltage, and generate a drive control signal. The discharge drive circuit can set a third set voltage based on the third control voltage, and perform a discharge operation on electrostatic.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0012351, filed on January 28, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] The various embodiments generally relate to an electrostatic discharge circuit and an electrostatic discharge control system, and more particularly, to an electrostatic discharge circuit and an electrostatic discharge control system capable of protecting the internal circuitry of an integrated circuit from the effects of static electricity contained in power. Background Technology

[0004] Typically, integrated circuits, including semiconductor devices, receive power and perform various circuit operations. For these operations to function stably, integrated circuits require a stable power supply. However, the power applied to an integrated circuit may contain unwanted static electricity with higher voltages.

[0005] Recently, with technological advancements, the size of internal circuits mounted on integrated circuits has gradually decreased, and their integration density has become increasingly higher. In this context, high-voltage static electricity contained in the power supply can have a potentially destructive effect on the internal circuits. Specifically, high-voltage static electricity can damage the gate dielectric layer of metal-oxide-semiconductor (MOS) transistors included in the internal circuits. Therefore, integrated circuits include ESD (electrostatic discharge) circuits to protect the internal circuits from the effects of high-voltage static electricity. Summary of the Invention

[0006] In an embodiment, an electrostatic discharge circuit may include: a control voltage generation circuit configured to generate a first control voltage, a second control voltage, and a third control voltage by dividing a supply voltage; an electrostatic discharge detection circuit configured to set a first setting voltage based on the first control voltage and generate an electrostatic discharge detection signal by detecting electrostatic discharge contained in the first setting voltage; a drive control circuit configured to set a second setting voltage based on the second control voltage and generate a drive control signal based on the electrostatic discharge detection signal; and a discharge drive circuit configured to set a third setting voltage based on the third control voltage and perform a discharge operation on the electrostatic discharge contained in the third setting voltage based on the drive control signal.

[0007] In an embodiment, an electrostatic discharge control system can include: a first electrostatic discharge circuit configured to perform a discharge operation on electrostatic contained in a first supply voltage; a second electrostatic discharge circuit configured to perform a discharge operation on electrostatic contained in a second supply voltage, the first supply voltage having a higher voltage level than the second supply voltage; and a selection control circuit configured to selectively control the first electrostatic discharge circuit or the second electrostatic discharge circuit based on a selected supply voltage among the first supply voltage and the second supply voltage, the selected supply voltage being applied to a supply voltage terminal.

[0008] In an embodiment, an electrostatic discharge control system can include: a control signal generation circuit configured to generate a selection control signal based on a selected supply voltage among a first supply voltage and a second supply voltage, the selected supply voltage being applied to a supply voltage terminal; a control voltage generation circuit that is enabled in response to the selection control signal when the selected supply voltage is the first supply voltage, and that is configured to generate a first control voltage, a second control voltage, and a third control voltage by dividing the selected supply voltage; a first setting circuit configured to receive the selected supply voltage and generate a first setting voltage based on one of the first control voltage and the selection control signal; a detection circuit configured to detect electrostatic contained in the first setting voltage and output an electrostatic detection signal; a second setting circuit configured to receive the selected supply voltage and generate a second setting voltage based on one of the second control voltage and the selection control signal; a drive circuit configured to generate a drive control signal based on the electrostatic detection signal; a third setting circuit configured to receive the selected supply voltage and generate a third setting voltage based on one of the third control voltage and the selection control signal; and a discharge circuit configured to form a discharge path for the third setting voltage based on the drive control signal.

[0009] In an embodiment, an electrostatic discharge circuit can include: a bias generation circuit configured to generate a bias voltage; an electrostatic sensing circuit configured to sense electrostatic contained in a supply voltage and generate a drive control signal; and a discharge drive circuit configured to set a setting voltage based on the bias voltage and perform a discharge operation on electrostatic contained in the setting voltage based on the drive control signal. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a block diagram illustrating an electrostatic discharge circuit according to an embodiment.

[0011] Figure 2 is a circuit diagram illustrating Figure 1 an electrostatic discharge circuit of

[0012] Figure 3An electrostatic discharge control system according to an embodiment is shown.

[0013] Figure 4 An electrostatic discharge control system according to an embodiment is shown. Figure 3 A selection control circuit.

[0014] Figure 5 A selection control circuit. Figure 3 A second electrostatic discharge circuit.

[0015] Figure 6 A control voltage generation circuit according to another embodiment is shown.

[0016] Figure 7 An electrostatic discharge control system according to another embodiment is shown.

[0017] Figure 8 A control signal generation circuit. Figure 7 A control signal generation circuit.

[0018] Figure 9 A block diagram showing an electrostatic discharge circuit according to another embodiment. DETAILED DESCRIPTION

[0019] The description of the present application is merely directed to the embodiments of the structural and / or functional description. The scope of the right of the present application should not be construed as being limited to the embodiments described in the specification. That is, because the embodiments can be modified in various ways and can have various forms, the scope of the right of the present application should be understood to include equivalent solutions that can achieve the technical spirit. In addition, the objects or effects proposed in the present disclosure do not mean that the specific embodiments should include all objects or effects or only such effects. Therefore, the scope of the right of the present disclosure should not be construed as being limited as such.

[0020] The meanings of the terms described in the present application should be understood as follows.

[0021] The terms such as "first" and "second" are used to distinguish one element from another element, and the scope of the present disclosure should not be limited by these terms. For example, a first element can be named as a second element. Likewise, a second element can be named as a first element.

[0022] Unless explicitly stated otherwise in the context, a singular expression should be understood to include a plural expression. The terms such as "include" or "have" should be understood to indicate the presence of a group of characteristics, numbers, steps, operations, elements, components, or combinations thereof, and do not exclude the possibility of the presence or addition of one or more other characteristics, numbers, steps, operations, elements, components, or combinations thereof.

[0023] In each of the steps, symbols (e.g., a, b, and c) are used for ease of description, and the symbols do not describe the order of the steps. Unless a specific order is clearly described in the context, the steps can be performed in an order different from the order described in the context. That is, the steps can be performed according to the described order, can be performed substantially simultaneously with the described order, or can be performed in the reverse order of the described order.

[0024] Unless otherwise defined, all terms used herein, including technical terms or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms defined in commonly used dictionaries should be interpreted as having a same meaning as those defined in the context of a relevant art, and should not be interpreted in an ideal or overly formal sense unless clearly defined in the application.

[0025] Various embodiments relate to an electrostatic discharge circuit including a low-voltage transistor and capable of protecting internal circuits of an integrated circuit from static electricity contained in a supply voltage.

[0026] Also, various embodiments further relate to an electrostatic discharge control system capable of protecting internal circuits of an integrated circuit from static electricity contained in a plurality of supply voltages.

[0027] Figure 1 is a block diagram illustrating an electrostatic discharge circuit 300 according to an embodiment.

[0028] Referring to Figure 1 , the electrostatic discharge circuit 300 can be configured to sense and discharge static electricity contained in a supply voltage VDDH. More specifically, the electrostatic discharge circuit 300 can include a control voltage generation circuit 310, an electrostatic detection circuit 320, a driving control circuit 330, and a discharge driving circuit 340.

[0029] The control voltage generation circuit 310 can be configured to generate the first to third control voltages V_CTR1 to V_CTR3 by dividing the supply voltage VDDH. The supply voltage VDDH can have a relatively high voltage level. For example, the supply voltage VDDH can be higher than an allowable voltage of a low voltage transistor included in the electrostatic discharge circuit 300. For example, the supply voltage VDDH can be one of about 3.3 V ± 10%, about 2.5 V ± 10%, and about 1.8 V ± 10%. For reference, a supply voltage (to be described below) having a relatively low voltage level can include the allowable voltage of the low voltage transistor. For example, the supply voltage having a relatively low voltage level can be one of about 1.8 V ± 10%, about 1.2 V ± 10%, and about 0.8 V ± 10%. The control voltage generation circuit 310 can be coupled between a supply voltage terminal to which the supply voltage VDDH is applied and a ground voltage terminal to which the ground voltage VSS is applied.

[0030] The first to third control voltages V_CTR1 to V_CTR3 generated by the control voltage generation circuit 310 can have the same voltage level. Also, at least one of the first to third control voltages V_CTR1 to V_CTR3 can have a different voltage level from the other control voltages among the first to third control voltages V_CTR1 to V_CTR3. Figure 2 The first to third control voltages V_CTR1 to V_CTR3 having different voltage levels from each other are illustrated.

[0031] The electrostatic detection circuit 320 can be configured to set a first setup voltage based on the first control voltage V_CTR1 and detect electrostatic contained in the first setup voltage. The electrostatic detection circuit 320 can generate an electrostatic detection signal DET by detecting the electrostatic. The electrostatic detection circuit 320 can be coupled between the supply voltage terminal and the ground voltage terminal. More specifically, the electrostatic detection circuit 320 can include a first setup circuit 321 and a detection circuit 322.

[0032] The first setup circuit 321 can be configured to receive the supply voltage VDDH and generate the first setup voltage based on the first control voltage V_CTR1. The detection circuit 322 can be configured to detect the electrostatic contained in the first setup voltage and output the electrostatic detection signal DET. Detailed circuit configurations of the first setup circuit 321 and the detection circuit 322 will be described below with reference to Figure 2

[0033] ​The drive control circuit 330 can be configured to set the second set voltage based on the second control voltage V_CTR2 and generate the drive control signal DRV based on the electrostatic detection signal DET. The drive control circuit 330 can be coupled between the supply voltage terminal and the ground voltage terminal. More specifically, the drive control circuit 330 can include a second set circuit 331 and a drive circuit 332.

[0034] The second set circuit 331 can be configured to receive the supply voltage VDDH and generate the second set voltage based on the second control voltage V_CTR2. The drive circuit 332 can be configured to generate the drive control signal DRV based on the electrostatic detection signal DET. Detailed circuit configurations of the second set circuit 331 and the drive circuit 332 will be described below with reference to Figure 2

[0035] The discharge drive circuit 340 can be configured to set a third set voltage based on a third control voltage V_CTR3 and perform a discharge operation on electrostatic contained in the third set voltage based on the drive control signal DRV. The discharge drive circuit 340 can be coupled between the supply voltage terminal and the ground voltage terminal. More specifically, the discharge drive circuit 340 can include a third set circuit 341 and a discharge circuit 342.

[0036] The third set circuit 341 can be configured to receive the supply voltage VDDH and generate the third set voltage based on the third control voltage V_CTR3. The discharge circuit 342 can be configured to form a discharge path for the third set voltage based on the drive control signal DRV. Detailed circuit configurations of the third set circuit 341 and the discharge circuit 342 will be described below with reference to Figure 2

[0037] Figure 2 is a circuit diagram illustrating the electrostatic discharge circuit 300 of Figure 1

[0038] Referring to Figure 2 , the electrostatic discharge circuit 300 can include a control voltage generation circuit 310, an electrostatic detection circuit 320, a drive control circuit 330, and a discharge drive circuit 340.

[0039] The control voltage generation circuit 310 can include first to fourth resistors R1 to R4 coupled in series between the supply voltage terminal and the ground voltage terminal.

[0040] ​​​The first to fourth resistors R1 to R4 can generate the first to third control voltages V_CTR1 to V_CTR3 by dividing the supply voltage VDDH. The third control voltage V_CTR3 can be output from a node to which the first resistor R1 and the second resistor R2 are commonly coupled, the second control voltage V_CTR2 can be output from a node to which the second resistor R2 and the third resistor R3 are commonly coupled, and the first control voltage V_CTR1 can be output from a node to which the third resistor R3 and the fourth resistor R4 are commonly coupled. Accordingly, the first to third control voltages V_CTR1 to V_CTR3 can have different voltage levels. In addition, the first to third control voltages V_CTR1 to V_CTR3 can have voltage levels sequentially decreasing from the voltage level of the supply voltage VDDH. That is, among the first to third control voltages V_CTR1 to V_CTR3, the third control voltage V_CTR3 can have the highest voltage level, the second control voltage V_CTR2 can have the next highest voltage level, and the first control voltage V_CTR1 can have the lowest voltage level.

[0041] The control voltage generation circuit 310 having the above-described configuration can generate the first to third control voltages V_CTR1 to V_CTR3 by dividing the supply voltage VDDH.

[0042] According to another embodiment, the control voltage generation circuit 310 can include first to third resistors R1 to R3 coupled in series between a supply voltage terminal and a ground voltage terminal. The first to third resistors R1 to R3 can generate the first to third control voltages V_CTR1 to V_CTR3 by dividing the supply voltage VDDH. In an embodiment, the first control voltage V_CTR1 and the second control voltage V_CTR2 can have the same voltage level. In another embodiment, the second control voltage V_CTR2 and the third control voltage V_CTR3 can have the same voltage level.

[0043] The static electricity detection circuit 320 can include a detection circuit 322 and a first setting circuit 321. The static electricity detection circuit 320 can include a fifth resistor R5, a first NMOS transistor NM1, and a capacitor C coupled in series between a supply voltage terminal and a ground voltage terminal. The first NMOS transistor NM1 can be included in the first setting circuit 321. The fifth resistor R5 and the capacitor C can be included in the detection circuit 322.

[0044] The first NMOS transistor NM1 can be coupled between the fifth resistor R5 and the first node N1, and configured to receive the first control voltage V_CTR1 through a gate terminal thereof. The first NMOS transistor NM1 can be turned on in response to the first control voltage V_CTR1. Accordingly, when the first NMOS transistor NM1 is turned on, the supply voltage VDDH can be transmitted to the first node N1 as the first set voltage through the fifth resistor R5 and the first NMOS transistor NM1. Accordingly, the first node N1 can receive the first set voltage.

[0045] The capacitor C can be coupled between the first node N1 and a ground voltage terminal. The capacitor C can be open-circuited or short-circuited according to a current characteristic of the first set voltage transmitted to the first node N1. In other words, the capacitor C can be open-circuited when the first set voltage of the first node N1 has a DC characteristic, and can be short-circuited when the first set voltage of the first node N1 has an AC characteristic. That is, the capacitor C can be open-circuited or short-circuited according to a characteristic of a current flowing through the first node N1.

[0046] More specifically, when the static electricity is not included in the supply voltage VDDH, the first set voltage of the first node N1 can have a DC characteristic. At this time, the capacitor C can be open-circuited. Accordingly, the first node N1 can have a voltage level corresponding to the supply voltage VDDH or a voltage level similar to the supply voltage VDDH. On the other hand, when the static electricity is included in the supply voltage VDDH, the voltage level of the supply voltage VDDH is instantaneously changed due to a higher voltage of the static electricity. Accordingly, the first set voltage of the first node N1 can have an AC characteristic. At this time, the capacitor C can be short-circuited. Accordingly, the first node N1 can have a voltage level corresponding to the ground voltage VSS or a voltage level similar to the ground voltage VSS.

[0047] That is, the first node N1 can have a voltage level changed according to whether the static electricity is included in the supply voltage VDDH. The changed voltage level at the first node N1 is output as the static electricity detection signal DET, and thus the static electricity detection signal DET indicates whether the static electricity is included in the supply voltage VDDH.

[0048] The static electricity detection circuit 320 having the above-described configuration can provide the first set voltage to the first node N1 in response to the first control voltage V_CTR1. The static electricity detection circuit 320 can generate the static electricity detection signal DET by detecting the static electricity included in the first set voltage on the first node N1.

[0049] The drive control circuit 330 can include a second setting circuit 331 and a drive circuit 332. The drive control circuit 330 can include a second NMOS transistor NM2, a third NMOS transistor NM3, a first PMOS transistor PM1, and a fourth NMOS transistor NM4 coupled in series between the supply voltage terminal and the ground voltage terminal. The second NMOS transistor NM2 and the third NMOS transistor NM3 can be included in the second setting circuit 331. The first PMOS transistor PM1 and the fourth NMOS transistor NM4 can be included in the drive circuit 332.

[0050] The second NMOS transistor NM2 and the third NMOS transistor NM3 can be coupled in series between the second node N2 and the supply voltage terminal, and receive the second control voltage V_CTR2 through a gate terminal thereof. The second NMOS transistor NM2 and the third NMOS transistor NM3 can be turned on in response to the second control voltage V_CTR2. Accordingly, the supply voltage VDDH can be transmitted to the second node N2 as the second setting voltage through the second NMOS transistor NM2 and the third NMOS transistor NM3. Accordingly, the second node N2 can receive the second setting voltage.

[0051] The first PMOS transistor PM1 and the fourth NMOS transistor NM4 can be coupled in series between the second node N2 and the ground voltage terminal, and receive the static electricity detection signal DET through a gate terminal thereof. Accordingly, when the static electricity detection signal DET has a voltage level corresponding to a logic high level, the fourth NMOS transistor NM4 can be turned on. On the other hand, when the static electricity detection signal DET has a voltage level corresponding to a logic low level, the first PMOS transistor PM1 can be turned on.

[0052] As described above, when static electricity is not detected, the static electricity detection signal DET can have a voltage level corresponding to the supply voltage VDDH. That is, when static electricity is not detected, the static electricity detection signal DET can have a logic high level. Accordingly, the fourth NMOS transistor NM4 can be turned on in response to the static electricity detection signal DET having the logic high level. At this time, the drive control signal DRV can have a logic low level corresponding to the ground voltage VSS.

[0053] On the other hand, when static electricity is detected, the static electricity detection signal DET can have a voltage level corresponding to the ground voltage VSS. That is, the static electricity detection signal DET can have a logic low level. Accordingly, the first PMOS transistor PM1 can be turned on in response to the static electricity detection signal DET having the logic low level. At this time, the drive control signal DRV can have a logic high level corresponding to the second setting voltage.

[0054] The drive control circuit 330 having the above configuration can supply the second set voltage to the second node N2 in response to the second control voltage V_CTR2. Further, the drive control circuit 330 can generate the drive control signal DRV based on the electrostatic detection signal DET.

[0055] The discharge drive circuit 340 can include a third setting circuit 341 and a discharge circuit 342. The discharge drive circuit 340 can include a fifth NMOS transistor NM5 and a sixth NMOS transistor NM6 coupled in series between the power supply voltage terminal and the ground voltage terminal. The fifth NMOS transistor NM5 can be included in the third setting circuit 341. The sixth NMOS transistor NM6 can be included in the discharge circuit 342.

[0056] The fifth NMOS transistor NM5 can be coupled between the third node N3 and the power supply voltage terminal, and receive the third control voltage V_CTR3 through its gate terminal. The fifth NMOS transistor NM5 can be turned on in response to the third control voltage V_CTR3. The power supply voltage VDDH can be transmitted to the third node N3 through the fifth NMOS transistor NM5 as the third set voltage. Accordingly, the third node N3 can receive the third set voltage.

[0057] The sixth NMOS transistor NM6 can be coupled between the third node N3 and the ground voltage terminal, and receive the drive control signal DRV through its gate terminal. The sixth NMOS transistor NM6 can be turned off when the drive control signal DRV has a logic low level. On the other hand, the sixth NMOS transistor NM6 can be turned on when the drive control signal DRV has a logic high level. Accordingly, when the sixth NMOS transistor NM6 is turned on, the third node N3 and the ground voltage terminal can be coupled to each other. That is, the sixth NMOS transistor NM6 can form a discharge path for the third set voltage on the third node N3 in response to the drive control signal DRV.

[0058] As described above, the drive control signal DRV can have a logic low level when no electrostatic is detected. The sixth NMOS transistor NM6 can be turned off in response to the drive control signal DRV having a logic low level. On the other hand, the drive control signal DRV can have a logic high level when electrostatic is detected. The sixth NMOS transistor NM6 can be turned on in response to the drive control signal DRV having a logic high level. At this time, the sixth NMOS transistor NM6 can form a discharge path. Accordingly, electrostatic contained in the power supply voltage VDDH can be discharged to the ground voltage terminal through the discharge path.

[0059] The discharge drive circuit 340 having the above configuration can supply the third set voltage to the third node N3 in response to the third control voltage V_CTR3. Further, the discharge drive circuit 340 can perform a discharge operation on the static electricity included in the supply voltage VDDH based on the drive control signal DRV.

[0060] The static electricity discharge circuit 300 according to the present embodiment can use a supply voltage VDDH corresponding to a higher voltage (for example, 3.3 V). The first to sixth NMOS transistors NM1 to NM6 and the first PMOS transistor PM1 included in the static electricity discharge circuit 300 can all be implemented with low-voltage transistors. The low-voltage transistors can be transistors used when implementing an integrated circuit using a lower supply voltage (for example, 1.8 V).

[0061] Generally, low-voltage transistors can occupy a smaller area and require a lower design cost compared to high-voltage transistors. As described above, the static electricity discharge circuit 300 can detect and discharge static electricity included in a supply voltage VDDH corresponding to a higher voltage, although using low-voltage transistors. In other words, the static electricity discharge circuit 300 according to the present embodiment can not only perform a discharge operation on static electricity included in the supply voltage VDDH, but also reduce the area occupied by the static electricity discharge circuit 300.

[0062] The reason for using low-voltage transistors in the static electricity discharge circuit 300 according to the present embodiment can be described as follows.

[0063] Generally, a transistor can have a reliability guarantee condition depending on its operating characteristics. A low-voltage transistor can perform a normal circuit operation only when the voltage levels of the source, drain, and gate terminals of the transistor satisfy the reliability guarantee condition. In an integrated circuit using a lower supply voltage (for example, 1.8 V), the voltage difference Vgd between the gate terminal and the drain terminal, the voltage difference Vgs between the gate terminal and the source terminal, and the voltage difference Vds between the drain terminal and the source terminal of the low-voltage transistor need to be 1.98 V or less to satisfy the reliability guarantee condition. The static electricity discharge circuit 300 according to the present embodiment can receive a supply voltage VDDH of 3.3 V corresponding to a higher voltage, and the first to sixth NMOS transistors NM1 to NM6 and the first PMOS transistor PM1 can each maintain the reliability guarantee condition of a low-voltage transistor.

[0064] Hereinafter, for ease of description, it is assumed that the first control voltage V_CTR1, the second control voltage V_CTR2, and the third control voltage V_CTR3 obtained by dividing the supply voltage VDDH of 3.3 V are 2.3 V, 2.4 V, and 2.5 V, respectively. Further, it is assumed that the threshold voltages of the first to sixth NMOS transistors NM1 to NM6 and the first PMOS transistor PM1 are 0.5 V.

[0065] The first NMOS transistor NM1 can receive a first control voltage V_CTR1 of 2.3 V through its gate terminal. Thus, assuming that the fifth resistor R5 is ignored, a voltage difference Vgd between the gate terminal and the drain terminal can become 1 V (= 3.3 V - 2.3 V), a voltage difference Vgs between the gate terminal and the source terminal can become 0.5 V (= 2.3 V - 1.8 V), and a voltage difference Vds between the drain terminal and the source terminal can become 1.5 V (= 3.3 V - 1.8 V). That is, the above-described voltage differences between the gate, drain, and source terminals of the first NMOS transistor NM1 can have voltage levels in a range of 1.98 V or less, which corresponds to a reliability guarantee condition of a low-voltage transistor.

[0066] The second NMOS transistor NM2 can receive a second control voltage V_CTR2 of 2.4 V through its gate terminal. Thus, a voltage difference Vgd between the gate terminal and the drain terminal can become 0.9 V (= 3.3 V - 2.4 V), a voltage difference Vgs between the gate terminal and the source terminal can become 0.5 V (= 2.4 V - 1.9 V), and a voltage difference Vds between the drain terminal and the source terminal can become 1.4 V (= 3.3 V - 1.9 V). That is, the above-described voltage differences between the gate, drain, and source terminals of the second NMOS transistor NM2 can have voltage levels in a range of 1.98 V or less, which corresponds to a reliability guarantee condition of a low-voltage transistor. Similarly, the voltage differences between the gate, drain, and source terminals of each of the third NMOS transistor NM3, the first PMOS transistor PM1, and the fourth NMOS transistor NM4 can have voltage levels in a range of 1.98 V or less, which corresponds to a reliability guarantee condition of a low-voltage transistor.

[0067] The fifth NMOS transistor NM5 can receive a third control voltage V_CTR3 of 2.5 V through its gate terminal. Thus, a voltage difference Vgd between the gate terminal and the drain terminal can become 0.8 V (= 3.3 V - 2.5 V), a voltage difference Vgs between the gate terminal and the source terminal can become 0.5 V (= 2.5 V - 2 V), and a voltage difference Vds between the drain terminal and the source terminal can become 1.3 V (= 3.3 V - 2 V). That is, the above-described voltage differences between the gate, drain, and source terminals of the fifth NMOS transistor NM5 can have voltage levels in a range of 1.98 V or less, which corresponds to a reliability guarantee condition of a low-voltage transistor. Similarly, the voltage differences between the gate, drain, and source terminals of the sixth NMOS transistor NM6 can have voltage levels in a range of 1.98 V or less, which corresponds to a reliability guarantee condition of a low-voltage transistor.

[0068] In particular, in the case of the fifth NMOS transistor NM5, since the voltage level of the third control voltage V_CTR3 is 2.5 V, the current Ids flowing from the drain terminal to the source terminal can be maximized. That is, the electrostatic discharge circuit 300 according to the present embodiment can maximize the current Ids flowing from the drain terminal to the source terminal of the fifth NMOS transistor NM5, thereby maximizing the discharge efficiency of static electricity.

[0069] The electrostatic discharge circuit 300 according to the present embodiment can further include a reverse discharge circuit 350.

[0070] Referring to Figure 2 , the reverse discharge circuit 350 can be configured to discharge static electricity contained in the ground voltage VSS to the supply voltage terminal. The reverse discharge circuit 350 can be configured as a diode D coupled between the ground voltage terminal and the supply voltage terminal.

[0071] The electrostatic discharge circuit 300 according to the present embodiment can not only perform a discharge operation on static electricity contained in the supply voltage VDDH, but also perform a discharge operation on static electricity contained in the ground voltage VSS.

[0072] Figure 3 is a block diagram illustrating an electrostatic discharge control system 400 according to an embodiment.

[0073] Referring to Figure 3 , the electrostatic discharge control system 400 can be configured to perform a discharge operation on static electricity contained in a plurality of supply voltages in an integrated circuit. Hereinafter, for convenience of description, a case in which the supply voltage terminal VDD receives a first supply voltage VDDH having one of about 3.3 V ± 10%, about 2.5 V ± 10%, and about 1.8 V ± 10% corresponding to a higher voltage and a second supply voltage VDDL having one of about 1.8 V ± 10%, about 1.2 V ± 10%, and about 0.8 V ± 10% corresponding to a lower voltage will be described as an example. When the first supply voltage VDDH of 3.3 V is applied to the supply voltage terminal VDD, the electrostatic discharge control system 400 can perform a discharge operation on static electricity contained in the first supply voltage VDDH. In addition, when the second supply voltage VDDL of 1.8 V is applied to the supply voltage terminal VDD, the electrostatic discharge control system 400 can perform a discharge operation on static electricity contained in the second supply voltage VDDL. More specifically, the electrostatic discharge control system 400 can include a selection control circuit 410, a first electrostatic discharge circuit 420, and a second electrostatic discharge circuit 430.

[0074] The selection control circuit 410 can be configured to selectively control the first electrostatic discharge circuit 420 and the second electrostatic discharge circuit 430 based on a supply voltage applied to the supply voltage terminal VDD between the first supply voltage VDDH and the second supply voltage VDDL. The selection control circuit 410 can be designed to selectively enable the first electrostatic discharge circuit 420 and the second electrostatic discharge circuit 430. For example, the selection control circuit 410 can selectively supply the first supply voltage VDDH and the second supply voltage VDDL to the first electrostatic discharge circuit 420 and the second electrostatic discharge circuit 430. That is, the selection control circuit 410 can supply the first supply voltage VDDH to the first electrostatic discharge circuit 420 and supply the second supply voltage VDDL to the second electrostatic discharge circuit 430. The first electrostatic discharge circuit 420 can be enabled based on the first supply voltage VDDH supplied thereto. The second electrostatic discharge circuit 430 can be enabled based on the second supply voltage VDDL supplied thereto.

[0075] Figure 4 The selection control circuit 410 of FIG. 1 is illustrated. Figure 3

[0076] Referring to FIG. 1, Figure 4 The selection control circuit 410 can include a first comparison circuit 411, a second comparison circuit 412, a control circuit 413, and an output circuit 414.

[0077] The first comparison circuit 411 can be configured to compare a supply voltage transmitted to the supply voltage terminal VDD with a first reference voltage VREF1 corresponding to the first supply voltage VDDH. When the supply voltage applied to the supply voltage terminal VDD is lower than the first supply voltage VDDH, the first comparison circuit 411 can generate a first comparison signal having a logic low level. When the first supply voltage VDDH is applied to the supply voltage terminal VDD, the first comparison circuit 411 can generate a first comparison signal having a logic high level.

[0078] The second comparison circuit 412 can be configured to compare a supply voltage transmitted to the supply voltage terminal VDD with a second reference voltage VREF2 corresponding to the second supply voltage VDDL. When the supply voltage applied to the supply voltage terminal VDD is lower than the second supply voltage VDDL, the second comparison circuit 412 can generate a second comparison signal having a logic low level. When the second supply voltage VDDL is applied to the supply voltage terminal VDD, the second comparison circuit 412 can generate a second comparison signal having a logic high level.

[0079] ​The control circuit 413 can be configured to generate a selection control signal CTR_S based on the first and second comparison signals of the first and second comparison circuits 411 and 412. The control circuit 413 can include a NAND gate. The NAND gate can receive the first and second comparison signals of the first and second comparison circuits 411 and 412, perform a NAND operation on the received signals, and output the selection control signal CTR_S.

[0080] The output circuit 414 can selectively output the first supply voltage VDDH or the second supply voltage VDDL as an output voltage in response to the selection control signal CTR_S. More specifically, the output circuit 414 can include a first PMOS transistor PM1, an inverter INV, and a second PMOS transistor PM2.

[0081] The first PMOS transistor PM1 can receive the selection control signal CTR_S through its gate terminal. When the selection control signal CTR_S has a logic low level, the first PMOS transistor PM1 can be turned on. When the first PMOS transistor PM1 is turned on, the first supply voltage VDDH applied to the supply voltage terminal VDD can be output as an output voltage. The inverter INV can invert the selection control signal CTR_S and output the inverted selection control signal. Then, the second PMOS transistor PM2 can receive the inverted selection control signal through its gate terminal. When the inverted selection control signal has a logic low level, the second PMOS transistor PM2 can be turned on. When the second PMOS transistor PM2 is turned on, the second supply voltage VDDL applied to the supply voltage terminal VDD can be output as an output voltage.

[0082] Hereinafter, a circuit operation of the selection control circuit 410 will be described with reference to Figure 4 The circuit operation of the selection control circuit 410 will be described.

[0083] In the following description, a case in which the second supply voltage VDDL corresponding to a lower voltage is applied to the supply voltage terminal VDD will be exemplified.

[0084] The second comparison circuit 412 can receive the second supply voltage VDDL, compare the second supply voltage VDDL with the second reference voltage VREF2, and output a second comparison signal having a logic high level. At this time, because the first reference voltage VREF1 has a higher voltage level than the second supply voltage VDDL applied to the supply voltage terminal VDD, the first comparison circuit 411 can generate a first comparison signal having a logic low level. Then, the NAND gate NAND can output a selection control signal CTR_S having a logic high level based on the first comparison signal having a logic low level and the second comparison signal having a logic high level. Accordingly, the second PMOS transistor PM2 can turn on in response to the selection control signal CTR_S having a logic high level, and output the second supply voltage VDDL as an output voltage. At this time, the first PMOS transistor PM1 can maintain an off state.

[0085] Next, a case in which the first supply voltage VDDH corresponding to a higher voltage is applied to the supply voltage terminal VDD will be described as follows.

[0086] The first comparison circuit 411 can receive the first supply voltage VDDH, compare the first supply voltage VDDH with the first reference voltage VREF1, and output a first comparison signal having a logic high level. At this time, because the first supply voltage VDDH applied to the supply voltage terminal VDD has a higher voltage level than the second reference voltage VREF2, the second comparison circuit 412 can generate a second comparison signal having a logic high level. Then, the NAND gate NAND can output a selection control signal CTR_S having a logic low level based on the first comparison signal having a logic high level and the second comparison signal having a logic high level. Accordingly, the first PMOS transistor PM1 can turn on in response to the selection control signal CTR_S having a logic low level, and output the first supply voltage VDDH as an output voltage. At this time, the second PMOS transistor PM2 can maintain an off state.

[0087] When the first supply voltage VDDH is applied to the supply voltage terminal VDD, the selection control circuit 410 having the above-described configuration can provide the first supply voltage VDDH to the first electrostatic discharge circuit 420 of Figure 3 , on the other hand, when the second supply voltage VDDL is applied to the supply voltage terminal VDD, the selection control circuit 410 can provide the second supply voltage VDDL to the second electrostatic discharge circuit 430 of Figure 3 .

[0088] Referring back to Figure 3The first electrostatic discharge circuit 420 can be enabled by the first supply voltage VDDH received from the selection control circuit 410. The first electrostatic discharge circuit 420 can perform a discharge operation on electrostatic contained in the first supply voltage VDDH. The first electrostatic discharge circuit 420 can correspond to Figure 1 and Figure 2 the electrostatic discharge circuit 300 described with reference to Figure 1 and Figure 2 The first electrostatic discharge circuit 420 can include the control voltage generation circuit 310, the electrostatic detection circuit 320, the drive control circuit 330, and the discharge drive circuit 340 described with reference to

[0089] On the other hand, the second electrostatic discharge circuit 430 can be enabled by the second supply voltage VDDL received from the selection control circuit 410. The second electrostatic discharge circuit 430 can perform a discharge operation on electrostatic contained in the second supply voltage VDDL.

[0090] Figure 5 is a circuit diagram illustrating the second electrostatic discharge circuit 430 of Figure 3

[0091] With reference to Figure 5 , the second electrostatic discharge circuit 430 can include a detection circuit 431, a drive circuit 432, and a discharge circuit 433. The second electrostatic discharge circuit 430 can receive the second supply voltage VDDL through the supply voltage terminal VDD.

[0092] The detection circuit 431 can be configured to detect electrostatic contained in the second supply voltage VDDL. The detection circuit 431 can include a resistor R and a capacitor C serially coupled between the supply voltage terminal VDD and the ground voltage terminal.

[0093] The drive circuit 432 can be configured to generate a control signal CTR based on an output signal of the detection circuit 431. The drive circuit 432 can include a first PMOS transistor PM1 and a first NMOS transistor NM1 serially coupled between the supply voltage terminal VDD and the ground voltage terminal.

[0094] The discharge circuit 433 can be configured to form a discharge path for the second supply voltage VDDL in response to the control signal CTR. The discharge circuit 433 can include a second NMOS transistor NM2 coupled between the supply voltage terminal VDD and the ground voltage terminal.

[0095] The second electrostatic discharge circuit 430 can receive the second supply voltage VDDL and perform a discharge operation on the second supply voltage VDDL. The first NMOS transistor NM1 and the second NMOS transistor NM2 and the first PMOS transistor PM1 can be low-voltage transistors. ​

[0096] Hereinafter, overall circuit operations of the electrostatic discharge control system 400 will be described with reference to Figure 3 to Figure 5 Figure 3

[0097] First, a case where a first supply voltage VDDH corresponding to a higher voltage is applied to the supply voltage terminal VDD will be described as follows.

[0098] As described above, when the first supply voltage VDDH is applied to the supply voltage terminal VDD, Figure 4 the selection control circuit 410 can output the first supply voltage VDDH as the output voltage. Accordingly, the first electrostatic discharge circuit 420 can be enabled, and the second electrostatic discharge circuit 430 can be disabled. Then, the first electrostatic discharge circuit 420 of the Figure 3 Figure 2 may perform the discharge operation described with reference to

[0099] Next, a case where a second supply voltage VDDL corresponding to a lower voltage is applied to the supply voltage terminal VDD will be described as follows.

[0100] As described above, when the second supply voltage VDDL is applied to the supply voltage terminal VDD, Figure 4 the selection control circuit 410 can output the second supply voltage VDDL as the output voltage. Accordingly, the first electrostatic discharge circuit 420 can be disabled, and the second electrostatic discharge circuit 430 can be enabled.

[0101] Figure 5 When no electrostatic is contained in the second supply voltage VDDL, because the capacitor C is open, the first node N1 of the detection circuit 431 can have a voltage level corresponding to the second supply voltage VDDL. That is, the first node N1 can have a logic high level. Then, the driving circuit 432 can generate a control signal CTR having a logic low level in response to the logic high level on the first node N1 as an output signal of the detection circuit 431. At this time, the second NMOS transistor NM2 of the discharge circuit 433 can maintain an off state in response to the control signal CTR having the logic low level.

[0102] ​​​​When static electricity is included in the second supply voltage VDDL, the first node N1 of the detection circuit 431 can have a voltage level corresponding to the ground voltage VSS due to the shorting of the capacitor C. That is, the first node N1 can have a logic low level. Then, the driving circuit 432 can generate a control signal CTR having a logic high level in response to the logic low level on the first node N1 which is an output signal of the detection circuit 431. Then, the second NMOS transistor NM2 of the discharging circuit 433 can be turned on in response to the control signal CTR having a logic high level. Accordingly, the static electricity included in the second supply voltage VDDL can be discharged to the ground voltage terminal.

[0103] As described above, when the second supply voltage VDDL corresponding to a lower voltage is applied to the supply voltage terminal VDD, the second static discharge circuit 430 can be enabled. In this case, the first static discharge circuit 420 can be disabled. For this operation, the control voltage generation circuit 310 of Figure 2 may be modified to have the same configuration as Figure 6 Before description, the control voltage generation circuit 310 can be disabled when the second supply voltage VDDL is applied to the supply voltage terminal VDD.

[0104] Figure 6 is a circuit diagram illustrating a control voltage generation circuit 310' according to another embodiment.

[0105] Referring to Figure 6 , the control voltage generation circuit 310' can include a transmission circuit 311 and a voltage division circuit 312.

[0106] The transmission circuit 311 can be configured to transmit the first supply voltage VDDH received through the supply voltage terminal VDD in response to a selection control signal CTR_S. The transmission circuit 311 can include a PMOS transistor PM having a source terminal and a drain terminal coupled between the supply voltage terminal VDD and the voltage division circuit 312 and a gate terminal configured to receive the selection control signal CTR_S. The selection control signal CTR_S can correspond to the selection control signal CTR_S of Figure 4 .

[0107] The voltage division circuit 312 can be configured to receive a voltage transmitted through the transmission circuit 311 and generate first to third control voltages V_CTR1 to V_CTR3. The voltage division circuit 312 can include first to fourth resistors R1 to R4 coupled in series between the PMOS transistor PM and the ground voltage terminal.

[0108] Referring to Figure 4 and Figure 6 , the circuit operation of the control voltage generation circuit 310' will be described as follows.

[0109] When the first supply voltage VDDH corresponding to a higher voltage is applied to the supply voltage terminal VDD, Figure 4 The control circuit 413 can generate the selection control signal CTR having a logic low level. Then, Figure 6 The PMOS transistor PM of the control circuit 413 can be turned on in response to the selection control signal CTR_S having a logic low level. Thus, when the first supply voltage VDDH is applied to the supply voltage terminal VDD, the control voltage generation circuit 310' can generate the first to third control voltages V_CTR1 to V_CTR3 by the voltage division operation. Since it is described in detail with reference to Figure 2 The voltage division operation for generating the first to third control voltages V_CTR1 to V_CTR3 and the discharge operation using the first to third control voltages V_CTR1 to V_CTR3 have been sufficiently described, and thus detailed description thereof will be omitted here.

[0110] When the second supply voltage VDDL corresponding to a lower voltage is applied to the supply voltage terminal VDD, the selection control signal CTR can have a logic high level. Figure 6 The PMOS transistor PM of the control circuit 413 can be turned off in response to the selection control signal CTR_S having a logic high level. Thus, when the second supply voltage VDDL is applied to the supply voltage terminal VDD, the control voltage generation circuit 310' can be deactivated. Since the first to third control voltages V_CTR1 to V_CTR3 become a logic low level when the control voltage generation circuit 310' is deactivated, the first to third control voltages V_CTR1 to V_CTR3 are not applied to the Figure 3 The PMOS transistor PM of the control circuit 413 can be turned off in response to the selection control signal CTR_S having a logic high level. Thus, when the second supply voltage VDDL is applied to the supply voltage terminal VDD, the control voltage generation circuit 310' can be deactivated. Since the first to third control voltages V_CTR1 to V_CTR3 become a logic low level when the control voltage generation circuit 310' is deactivated, the first to third control voltages V_CTR1 to V_CTR3 are not applied to the Figure 2 The static detection circuit 320, the drive control circuit 330, and the discharge drive circuit 340 of the control circuit 413 can also be deactivated.

[0111] Figure 7 is a block diagram illustrating an electrostatic discharge control system 700 according to another embodiment.

[0112] Referring to Figure 7 , the electrostatic discharge control system 700 can be configured to control a discharge operation of static electricity contained in a plurality of supply voltages in an integrated circuit receiving a plurality of supply voltages through a supply voltage terminal VDD. In the electrostatic discharge control system 700, as in the Figure 3 The first supply voltage VDDH or the second supply voltage VDDL can be applied to the supply voltage terminal VDD in the electrostatic discharge control system 700 as in the electrostatic discharge control system 400.

[0113] The electrostatic discharge control system 700 can include a control signal generation circuit 710, a control voltage generation circuit 720, a first setting circuit 721, a first transmission circuit 722, a common detection circuit 723, a second setting circuit 724, a second transmission circuit 725, a common drive circuit 726, a third setting circuit 727, a third transmission circuit 728, and a common discharge circuit 729.

[0114] The control signal generation circuit 710 can be configured to generate a first selection control signal CTR_S1 and a second selection control signal CTR_S2 based on one of a first supply voltage VDDH and a second supply voltage VDDL applied to a supply voltage terminal VDD. The first selection control signal CTR_S1 and the second selection control signal CTR_S2 can have opposite relationships. The first selection control signal CTR_S1 and the second selection control signal CTR_S2 can be transmitted through signal lines separated from each other. In another embodiment, the first selection control signal CTR_S1 and the second selection control signal CTR_S2 can be transmitted through the same signal line, and the second selection control signal CTR_S2 can be an inverted signal of the first selection control signal CTR_S1, or vice versa.

[0115] Figure 8 The control signal generation circuit 710 of FIG. 1 is illustrated. Figure 7

[0116] Referring to FIG. 1, Figure 8 The control signal generation circuit 710 can include a first comparison circuit 711, a second comparison circuit 712, and a control circuit 713. Except for a first PMOS transistor PM1 and a second PMOS transistor PM2, the control signal generation circuit 710 can have a similar configuration to the selection control circuit 410 of FIG. 1. Figure 4

[0117] When the first supply voltage VDDH is applied to the supply voltage terminal VDD, the control signal generation circuit 710 can generate the first selection control signal CTR_S1 having a logic low level and the second selection control signal CTR_S2 having a logic high level. On the other hand, when the second supply voltage VDDL is applied to the supply voltage terminal VDD, the control signal generation circuit 710 can generate the first selection control signal CTR_S1 having a logic high level and the second selection control signal CTR_S2 having a logic low level.

[0118] Referring back to Figure 7 ​​, the control voltage generation circuit 720 can be enabled or disabled in response to the first selection control signal CTR_S1, and generate the first to third control voltages V_CTR1 to V_CTR3 by performing a voltage division operation on a supply voltage transmitted through the supply voltage terminal VDD. The control voltage generation circuit 720 can correspond to Figure 6 the control voltage generation circuit 310' of FIG. 10. However, unlike the control voltage generation circuit 310' of FIG. 10, Figure 6 the control voltage generation circuit 720 can receive the first selection control signal CTR_S1 instead of the selection control signal CTR_S.

[0119] As described above, when the first supply voltage VDDH is applied to the supply voltage terminal VDD, the first selection control signal CTR_S1 can have a logic low level. Accordingly, when the first supply voltage VDDH is applied to the supply voltage terminal VDD, the control voltage generation circuit 720 can be enabled. Thus, the control voltage generation circuit 720 can generate the first to third control voltages V_CTR1 to V_CTR3 by performing a voltage division operation on the first supply voltage VDDH. On the other hand, when the second supply voltage VDDL is applied to the supply voltage terminal VDD, the first selection control signal CTR_S1 can have a logic high level. Accordingly, the control voltage generation circuit 720 can be disabled.

[0120] The first setting circuit 721, the common detection circuit 723, the second setting circuit 724, the common drive circuit 726, the third setting circuit 727, and the common discharge circuit 729 can correspond to Figure 2 the first setting circuit 321, the detection circuit 322, the second setting circuit 331, the drive circuit 332, the third setting circuit 341, and the discharge circuit 342 of FIG. 10, respectively.

[0121] However, when the first supply voltage VDDH and the second supply voltage VDDL are applied to the supply voltage terminal VDD, the common detection circuit 723, the common drive circuit 726, and the common discharge circuit 729 can be commonly used. That is, the common detection circuit 723, the common drive circuit 726, and the common discharge circuit 729 can be used to perform a discharge operation on the first supply voltage VDDH and a discharge operation on the second supply voltage VDDL. Accordingly, the electrostatic discharge control system 700 according to the present embodiment can minimize the circuit area occupied by the circuits required to perform a discharge operation on a plurality of supply voltages including the first supply voltage VDDH and the second supply voltage VDDL.

[0122] The first transmission circuit 722 can be coupled in parallel with the first setting circuit 721, and transmit a supply voltage applied through the supply voltage terminal VDD as a first setting voltage in response to a second selection control signal CTR_S2. The first transmission circuit 722 can include a first PMOS transistor PM1. The first PMOS transistor PM1 can be coupled between the fifth resistor R5 and the first node N1, and receive the second selection control signal CTR_S2 through its gate terminal.

[0123] As described above, when the second supply voltage VDDL is applied to the supply voltage terminal VDD, the second selection control signal CTR_S2 can have a logic low level. The first PMOS transistor PM1 can be turned on in response to the second selection control signal CTR_S2 having the logic low level. At this time, the first NMOS transistor NM1 of the first setting circuit 721 can be turned off in response to the first control voltage V_CTR1 having the logic low level. Accordingly, the second supply voltage VDDL can be transmitted to the first node N1 through the fifth resistor R5 and the first PMOS transistor PM1.

[0124] The second transmission circuit 725 can be coupled in parallel with the second setting circuit 724, and transmit a supply voltage applied through the supply voltage terminal VDD as a second setting voltage in response to a second selection control signal CTR_S2. The second transmission circuit 725 can include a second PMOS transistor PM2. The second PMOS transistor PM2 can be coupled between the supply voltage terminal VDD and the second node N2, and receive the second selection control signal CTR_S2 through its gate terminal. Accordingly, when the second supply voltage VDDL is applied to the supply voltage terminal VDD, the second PMOS transistor PM2 can be turned on in response to the second selection control signal CTR_S2 having a logic low level. At this time, the second NMOS transistor NM2 and the third NMOS transistor NM3 can be turned off in response to the second control voltage V_CTR2 having the logic low level. Accordingly, the second supply voltage VDDL can be transmitted to the second node N2 through the second PMOS transistor PM2.

[0125] The third transfer circuit 728 can be coupled in parallel with the third setting circuit 727, and transfer a supply voltage applied through the supply voltage terminal VDD as a third setting voltage in response to a second selection control signal CTR_S2. The third transfer circuit 728 can include a third PMOS transistor PM3. The third PMOS transistor PM3 can be coupled between the supply voltage terminal VDD and the third node N3, and receive the second selection control signal CTR_S2 through its gate terminal. Accordingly, when the second supply voltage VDDL is applied to the supply voltage terminal VDD, the third PMOS transistor PM3 can be turned on in response to the second selection control signal CTR_S2 having a logic low level. At this time, the fifth NMOS transistor NM5 can be turned off based on the third control voltage V_CTR3 having a logic low level. Accordingly, the second supply voltage VDDL can be transferred to the third node N3 through the third PMOS transistor PM3.

[0126] As with the NMOS transistors included in the electrostatic discharge control system 700, the first to third PMOS transistors PM1 to PM3 can each have a reliability guarantee condition depending on their operating characteristics. That is, low-voltage transistors can be used as the first to third PMOS transistors PM1 to PM3.

[0127] In short, the NMOS transistors and the PMOS transistors in the electrostatic discharge control system 700 according to the present embodiment can be low-voltage transistors. Furthermore, even if the first supply voltage VDDH or the second supply voltage VDDL is applied to the supply voltage terminal VDD, the electrostatic discharge control system 700 can perform a discharge operation on the electrostatic contained in the first supply voltage VDDH or the second supply voltage VDDL. The electrostatic discharge control system 700 can further include a common detection circuit 723, a common driving circuit 726, and a common discharge circuit 729 used when either of the first supply voltage VDDH and the second supply voltage VDDL is applied to the supply voltage terminal VDD.

[0128] As described above, the electrostatic discharge control system 700 can perform a discharge operation on both the first supply voltage VDDH and the second supply voltage VDDL. Accordingly, the electrostatic discharge control system 700 can be implemented with a minimum circuit area.

[0129] Figure 9 is a block diagram illustrating an electrostatic discharge circuit 900 according to another embodiment.

[0130] Referring to Figure 9 The electrostatic discharge circuit 900 can be configured to sense and discharge electrostatic contained in a supply voltage VDDH. More specifically, the electrostatic discharge circuit 900 can include a bias generation circuit 910, an electrostatic sensing circuit 920, and a discharge driving circuit 930.

[0131] The bias generation circuit 910 can be configured to generate a bias voltage V_B. The bias generation circuit 910 can be coupled between a supply voltage terminal to which a supply voltage VDDH is applied and a ground voltage terminal to which a ground voltage VSS is applied. The bias generation circuit 910 can correspond to Figure 1 the control voltage generation circuit 310 of FIG. 1. Accordingly, the bias voltage V_B can correspond to one of the first to third control voltages V_CTR1 to V_CTR3 of FIG. 1. Figure 1

[0132] The electrostatic sensing circuit 920 can be configured to sense electrostatic contained in the supply voltage VDDH and generate a drive control signal DRV. The electrostatic sensing circuit 920 can include Figure 1 the electrostatic detection circuit 320 and the drive control circuit 330 of FIG. 1.

[0133] The discharge driving circuit 930 can be configured to set a set voltage based on the bias voltage V_B and perform a discharge operation on electrostatic contained in the set voltage based on the drive control signal DRV. The discharge driving circuit 930 can correspond to Figure 1 the discharge driving circuit 340 of FIG. 1. However, unlike the discharge driving circuit 340 of FIG. 1, Figure 1 the discharge driving circuit 930 of FIG. 9 can receive the bias voltage V_B instead of Figure 9 the third control voltage V_CTR3 of FIG. 1. Figure 1

[0134] The electrostatic discharge circuit 900 according to the present embodiment can set a set voltage of the discharge driving circuit 930 in response to the bias voltage V_B. In addition, the electrostatic discharge circuit 900 can perform a discharge operation on electrostatic contained in the set voltage.

[0135] According to the above-described embodiments, the electrostatic discharge circuit and the electrostatic discharge control system can protect internal circuits of an integrated circuit from electrostatic contained in a supply voltage, thereby guaranteeing stable circuit operation.

[0136] In addition, the electrostatic discharge circuit and the electrostatic discharge control system can be implemented using low-voltage transistors. Accordingly, it is possible to minimize a circuit area of the electrostatic discharge circuit and the electrostatic discharge control system.

[0137] Although various embodiments are described above, it will be understood by those skilled in the art that the described embodiments are merely examples. Accordingly, the electrostatic discharge circuit and the electrostatic discharge control system described herein should not be limited based on the described embodiments.​​

Claims

1. An electrostatic discharge circuit comprising: a control voltage generation circuit that generates a first control voltage, a second control voltage, and a third control voltage by dividing a supply voltage; an electrostatic detection circuit that sets a first setting voltage based on the first control voltage, and generates an electrostatic detection signal by detecting electrostatic contained in the first setting voltage; a drive control circuit that sets a second setting voltage based on the second control voltage, and generates a drive control signal based on the second setting voltage and the electrostatic detection signal; and a discharge drive circuit that sets a third setting voltage based on the third control voltage, and performs a discharge operation on electrostatic contained in the third setting voltage based on the drive control signal.

2. The electrostatic discharge circuit according to claim 1, wherein one or more of the first control voltage to the third control voltage have different voltage levels.

3. The electrostatic discharge circuit according to claim 1, wherein the first control voltage to the third control voltage have voltage levels that sequentially decrease from a voltage level of the supply voltage.

4. The electrostatic discharge circuit according to claim 1, wherein the electrostatic detection circuit includes: a first setting circuit that receives the supply voltage, and generates the first setting voltage based on the first control voltage; and a detection circuit that detects the electrostatic contained in the first setting voltage, and outputs the electrostatic detection signal.

5. The electrostatic discharge circuit according to claim 1, wherein the drive control circuit includes: a second setting circuit that receives the supply voltage, and generates the second setting voltage based on the second control voltage; and a drive circuit that generates the drive control signal based on the electrostatic detection signal.

6. The electrostatic discharge circuit according to claim 1, wherein the discharge drive circuit includes: a third setting circuit that receives the supply voltage, and generates the third setting voltage based on the third control voltage; and a discharge circuit that forms a discharge path for the third setting voltage based on the drive control signal.

7. The electrostatic discharge circuit according to claim 1, wherein the electrostatic detection circuit includes a first low voltage transistor that receives the first control voltage through a gate terminal of the first low voltage transistor, the drive control circuit includes a second low voltage transistor that receives the second control voltage through a gate terminal of the second low voltage transistor, and a third low voltage transistor that receives the electrostatic detection signal through a gate terminal of the third low voltage transistor, and the discharge drive circuit includes a fourth low voltage transistor that receives the third control voltage through a gate terminal of the fourth low voltage transistor, and a fifth low voltage transistor that receives the drive control signal through a gate terminal of the fifth low voltage transistor. ​ ​ ​ ​ 8. The electrostatic discharge circuit according to claim 1, further comprising a reverse discharge circuit that discharges electrostatics contained in a ground voltage to a power supply voltage terminal to which the power supply voltage is applied.

9. An electrostatic discharge control system comprising: a first electrostatic discharge circuit that performs a discharge operation on electrostatics contained in a first power supply voltage; a second electrostatic discharge circuit that performs a discharge operation on electrostatics contained in a second power supply voltage, the first power supply voltage having a higher voltage level than the second power supply voltage; and a selection control circuit that selectively controls the first electrostatic discharge circuit or the second electrostatic discharge circuit based on a selected power supply voltage between the first power supply voltage and the second power supply voltage, the selected power supply voltage being applied to a power supply voltage terminal, wherein the first electrostatic discharge circuit includes: a control voltage generation circuit that generates a first control voltage, a second control voltage, and a third control voltage by dividing the first power supply voltage; an electrostatic detection circuit that sets a first setting voltage based on the first control voltage and generates an electrostatic detection signal by detecting electrostatics contained in the first setting voltage; a drive control circuit that sets a second setting voltage based on the second control voltage and generates a drive control signal based on the second setting voltage and the electrostatic detection signal; and a discharge drive circuit that sets a third setting voltage based on the third control voltage and performs a discharge operation on electrostatics contained in the third setting voltage based on the drive control signal.

10. The electrostatic discharge control system according to claim 9, wherein the selection control circuit selectively supplies the first power supply voltage or the second power supply voltage to the first electrostatic discharge circuit or the second electrostatic discharge circuit, respectively.

11. The electrostatic discharge control system according to claim 9, wherein the selection control circuit includes: a first comparison circuit that compares the selected power supply voltage with a first reference voltage corresponding to the first power supply voltage; a second comparison circuit that compares the selected power supply voltage with a second reference voltage corresponding to the second power supply voltage; a control circuit that generates a selection control signal based on output signals of the first comparison circuit and the second comparison circuit; and an output circuit that selectively outputs the first power supply voltage or the second power supply voltage in response to the selection control signal.

12. The electrostatic discharge control system according to claim 9, wherein the electrostatic detection circuit includes a first low-voltage transistor that receives the first control voltage through a gate terminal of the first low-voltage transistor, the drive control circuit includes a second low-voltage transistor that receives the second control voltage through a gate terminal of the second low-voltage transistor and a third low-voltage transistor that receives the electrostatic detection signal through a gate terminal of the third low-voltage transistor, and ​ ​ The discharge drive circuit includes a fourth low voltage transistor that receives the third control voltage through a gate terminal of the fourth low voltage transistor, and a fifth low voltage transistor that receives the drive control signal through a gate terminal of the fifth low voltage transistor.

13. The electrostatic discharge control system according to claim 9, wherein the second electrostatic discharge circuit includes: a detection circuit that detects electrostatic included in the second power supply voltage; a drive circuit that generates a control signal based on an output signal of the detection circuit; and a discharge circuit that forms a discharge path for the second power supply voltage based on the control signal.

14. The electrostatic discharge control system according to claim 9, wherein the control voltage generation circuit includes: a transfer circuit that transfers the first power supply voltage in response to a selection control signal; and a voltage division circuit that receives a voltage transferred by the transfer circuit, and generates the first control voltage to the third control voltage by voltage dividing the received voltage.

15. An electrostatic discharge control system comprising: a control signal generation circuit that generates a selection control signal based on a selected power supply voltage among a first power supply voltage and a second power supply voltage, the selected power supply voltage being applied to a power supply voltage terminal; a control voltage generation circuit that is enabled in response to the selection control signal when the selected power supply voltage is the first power supply voltage, and generates a first control voltage, a second control voltage, and a third control voltage by voltage dividing the selected power supply voltage; a first setting circuit that receives the selected power supply voltage, and generates a first setting voltage based on one of the first control voltage and the selection control signal; a detection circuit that detects electrostatic included in the first setting voltage, and outputs an electrostatic detection signal; a second setting circuit that receives the selected power supply voltage, and generates a second setting voltage based on one of the second control voltage and the selection control signal; a drive circuit that generates a drive control signal based on the second setting voltage and the electrostatic detection signal; a third setting circuit that receives the selected power supply voltage, and generates a third setting voltage based on one of the third control voltage and the selection control signal; and a discharge circuit that forms a discharge path for the third setting voltage based on the drive control signal.

16. The electrostatic discharge control system according to claim 15, wherein the control signal generation circuit includes: a first comparison circuit that compares the selected power supply voltage with a first reference voltage corresponding to the first power supply voltage; a second comparison circuit that compares the selected power supply voltage with a second reference voltage corresponding to the second power supply voltage; and a control circuit that generates the selection control signal based on output signals of the first comparison circuit and the second comparison circuit. ​ ​ 17. The electrostatic discharge control system of claim 15, wherein the first setting circuit includes a first low voltage NMOS transistor that receives the first control voltage through a gate terminal of the first low voltage NMOS transistor, the second setting circuit includes a second low voltage NMOS transistor that receives the second control voltage through a gate terminal of the second low voltage NMOS transistor, and the third setting circuit includes a third low voltage NMOS transistor that receives the third control voltage through a gate terminal of the third low voltage NMOS transistor.

18. The electrostatic discharge control system of claim 17, wherein the first setting circuit further includes a first low voltage PMOS transistor that is coupled in parallel with the first low voltage NMOS transistor and receives the selection control signal through a gate terminal of the first low voltage PMOS transistor, the second setting circuit further includes a second low voltage PMOS transistor that is coupled in parallel with the second low voltage NMOS transistor and receives the selection control signal through a gate terminal of the second low voltage PMOS transistor, and the third setting circuit further includes a third low voltage PMOS transistor that is coupled in parallel with the third low voltage NMOS transistor and receives the selection control signal through a gate terminal of the third low voltage PMOS transistor.

19. An electrostatic discharge circuit comprising: a bias generation circuit that generates a bias voltage; an electrostatic sensing circuit that senses electrostatics contained in a supply voltage and generates a drive control signal; and a discharge drive circuit that sets a setting voltage based on the bias voltage and performs a discharge operation on electrostatics contained in the setting voltage based on the drive control signal, wherein the electrostatic sensing circuit includes: an electrostatic detection circuit that detects electrostatics contained in the supply voltage and generates an electrostatic detection signal; and a drive control circuit that generates the drive control signal based on the setting voltage and the electrostatic detection signal.

20. The electrostatic discharge circuit of claim 19, wherein the bias generation circuit generates the bias voltage by dividing the supply voltage.

21. The electrostatic discharge circuit of claim 20, wherein the electrostatic detection circuit includes: a first setting circuit that receives the supply voltage and generates a first setting voltage based on the bias voltage; and a detection circuit that detects electrostatics contained in the first setting voltage and outputs the electrostatic detection signal.

22. The electrostatic discharge circuit of claim 20, wherein the drive control circuit includes: a second setting circuit that receives the supply voltage and generates a second setting voltage based on the bias voltage; and a drive circuit that generates the drive control signal based on the electrostatic detection signal. ​ ​ ​ ​ 23. The electrostatic discharge circuit according to claim 19, wherein the discharge driving circuit includes: a setting circuit that receives the power supply voltage and generates the setting voltage based on the bias voltage; and a discharge circuit that forms a discharge path for the setting voltage based on the drive control signal.

24. The electrostatic discharge circuit according to claim 19, wherein the discharge driving circuit includes: a first low-voltage transistor that receives the bias voltage through a gate terminal of the first low-voltage transistor; and a second low-voltage transistor that receives the drive control signal through a gate terminal of the second low-voltage transistor.

25. The electrostatic discharge circuit according to claim 19, further comprising a reverse discharge circuit that discharges electrostatic contained in a ground voltage to a power supply voltage terminal to which the power supply voltage is applied.

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