Transmitter with overvoltage protection

Abstract

Embodiments of the present application disclose a transmitter with overvoltage protection, which comprises a level conversion circuit, an edge adjustment circuit and a driver. The level conversion circuit generates a plurality of first signals and a plurality of second signals based on an input signal, wherein voltage ranges of the input signal, the plurality of first signals and the plurality of second signals are different from each other. The edge adjustment circuit adjusts levels of a first node and a second node according to the plurality of first signals and the plurality of second signals, and provides an overvoltage protection in the process of adjusting the levels of the first node and the second node. The driver generates an output signal according to the levels of the first node and the second node.

Description

TECHNICAL FIELD

[0001] The present application relates to a transmitter, in particular to a transmitter with over-voltage protection, which can be implemented by transistors with relatively low withstand voltage. BACKGROUND

[0002] Due to the progress of manufacturing process, the size of transistors is getting smaller and smaller, and the withstand voltage of the transistors is getting lower and lower. However, in the existing applications, the transmitter still needs to transmit signals with high level. If the existing transmitter is directly implemented by transistors with low withstand voltage, the transistors will be damaged by excessive voltage, resulting in the reduction of reliability of the transmitter. SUMMARY

[0003] In some embodiments, the present application provides a transmitter with over-voltage protection, which can be implemented by transistors with relatively low withstand voltage.

[0004] In some embodiments, the transmitter includes a level conversion circuit, an edge adjustment circuit, and a driver. The level conversion circuit generates a plurality of first signals and a plurality of second signals based on an input signal, wherein the voltage range of the input signal, the voltage range of the plurality of first signals, and the voltage range of the plurality of second signals are different from each other. The edge adjustment circuit adjusts the level of a first node and the level of a second node according to the plurality of first signals and the plurality of second signals, and provides over-voltage protection in the process of adjusting the level of the first node and the level of the second node. The driver generates an output signal according to the level of the first node and the level of the second node.

[0005] The transmitter in some embodiments of the present application can use transistors with low withstand voltage to transmit output signals with high level, and use over-voltage protection and short-circuit current protection to ensure that the transistors will not be damaged, so as to improve the reliability of the transmitter.

[0006] The features, implementations, and effects of the present application will be described in detail below with reference to the preferred embodiments and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0007] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0008] Figure 1 A schematic diagram of a transmitter according to some embodiments of the present application;

[0009] Figure 2 A schematic diagram of a transmitter according to some embodiments of the present application;Figure 1 schematic diagram of a circuit in the level shifting circuit of

[0010] Figure 3A schematic diagram of a circuit in the edge adjustment circuit of Figure 1

[0011] Figure 3B schematic diagram of another circuit in the edge adjustment circuit of Figure 1

[0012] Figure 4 schematic diagram of a driver in the driver of Figure 1

[0013] Figure 5A schematic diagram of the operation of the circuit of Figure 3A when the input signal is switched from a low level to a high level and the level of the control node has not yet changed according to some embodiments of the present application;

[0014] Figure 5B schematic diagram of the operation of the circuit of Figure 3B when the input signal is switched from a low level to a high level and the level of the control node has not yet changed according to some embodiments of the present application;

[0015] Figure 6A schematic diagram of the operation of the circuit of Figure 3A when the input signal is switched from a low level to a high level and the level of the control node has changed according to some embodiments of the present application; and

[0016] Figure 6B schematic diagram of the operation of the circuit of Figure 3B when the input signal is switched from a low level to a high level and the level of the control node has changed according to some embodiments of the present application.

[0017]

Symbol Explanation

[0018] 100: transmitter

[0019] 110: level shifting circuit

[0020] 120: edge adjustment circuit

[0021] 130: driver

[0022] 210, 220: comparison circuit

[0023] 230, 240, 250, 260: inverter

[0024] 300A, 300B: circuit

[0025] 310: pull-down circuit​​​

[0026] 315, 335: current source circuit

[0027] 320, 340: protection circuit

[0028] 330: pull-up circuit

[0029] 340: protection circuit

[0030] AVDDH, AVDDL, AVSSH, AVSS: voltage

[0031] C: capacitor

[0032] D1, D2: data signal

[0033] DBH, DH, DBL, DL: signal

[0034] DIN: input signal

[0035] DO: output signal

[0036] d1 ~ d10: node

[0037] dc: control node

[0038] do: output node

[0039] R: resistor

[0040] T3 ~ T4, N1 ~ N13: N-type transistor

[0041] T1 ~ T, P1 ~ P13: P-type transistor

[0042] VO: output signal DETAILED DESCRIPTION

[0043] All words used herein are intended to be given their ordinary meaning. Definitions of the above words in the commonly used dictionaries are hereby incorporated into the content of this application as if affixed thereto. Also, the use of "or" means "and / or" unless stated otherwise. Furthermore, the use of the term "including" as well as other forms such as "include", is intended to cover non-exclusive inclusions, such that any process, method, article, or apparatus that includes other non-specified elements or steps is within the scope of the application. Also, the use of the term "coupled" or "connected" is intended to be used in its broadest sense, meaning either an indirect or direct electrical or mechanical connection.

[0044] As used herein, the term "coupled" or "connected" can mean either an indirect or direct electrical or mechanical connection between two or more components, or can mean two or more components that are operatively or functionally associated with each other. As used herein, the term "circuit" can be a device that includes at least one transistor and / or at least one active or passive component connected in a manner to process a signal.

[0045] Figure 1A schematic diagram of a transmitter 100 according to some embodiments of the present application. In some embodiments, the transmitter 100 can be implemented by transistors with low voltage tolerance, and configured to have over-voltage protection to be able to output signals with high voltage level.

[0046] The transmitter 100 includes a level conversion circuit 110, an edge adjustment circuit 120, a driver 130, and a capacitor C. The level conversion circuit 110 generates a signal DH, a signal DBH, a signal DL, and a signal DBL based on an input signal DIN. In some embodiments, the signal DH and the signal DBH have opposite levels, and the signal DL and the signal DBL have opposite levels. For example, when the signal DH has a high level, the signal DBH has a low level; and vice versa.

[0047] In some embodiments, the voltage range of the input signal DIN, the voltage range of the signal DH and the signal DBH, and the voltage range of the signal DL and the signal DBL are different from each other. In this example, the voltage range of the input signal DIN is greater than the voltage range of the signal DH and the signal DBH, and greater than the voltage range of the signal DL and the signal DBL. For example, the voltage range of the input signal DIN can be determined by a voltage AVSS and a voltage AVDDH, where the voltage AVSS is the lower limit of the voltage range of the input signal DIN, and the voltage AVDDH is the upper limit of the voltage range of the input signal DIN. The voltage range of the signal DH and the signal DBH can be determined by a voltage AVSSH and a voltage AVDDH, where the voltage AVSSH is the lower limit of the voltage range of the signal DH and the signal DBH, and the voltage AVDDH is the upper limit of the voltage range of the signal DH and the signal DBL. The voltage range of the signal DL and the signal DBL can be determined by a voltage AVSS and a voltage AVDDL, where the voltage AVSS is the lower limit of the voltage range of the signal DL and the signal DBL, and the voltage AVDDL is the upper limit of the voltage range of the signal DL and the signal DBL. Figure 2 Figure 2 Figure 2

[0048] ​​​For example, the voltage AVDDH can be about 3.3 volts, the voltage AVDDL can be about 1.8 volts, the voltage AVSSH can be about 1.5 volts, and the voltage AVSS can be about 0 volts. Accordingly, it should be understood that the upper limit of the voltage range of the signal DH and the signal DBH (i.e., the voltage AVDDH) is higher than the upper limit of the voltage range of the signal DL and the signal DBL (i.e., the voltage AVSSH), and the lower limit of the voltage range of the signal DH and the signal DBH (i.e., the voltage AVSSH) is higher than the lower limit of the voltage range of the signal DL and the signal DBL (i.e., the voltage AVSS). The numerical values of the voltages described above are merely for example, and the present application is not limited thereto. In other embodiments, the voltage AVDDL and the voltage AVSSH can be set to be half of the voltage AVDDH.

[0049] The edge adjustment circuit 120 adjusts the level of the first node (e.g., the node dl of the Figure 3A edge adjustment circuit 120) and the level of the second node (e.g., the node d3 of the Figure 3A edge adjustment circuit 120) according to the signal DH, the signal DBH, the signal DL, and the signal DBL, and provides an over-voltage protection during the adjustment of the levels of the first node and the second node. In some embodiments, each of the level conversion circuit 110, the edge adjustment circuit 120, and the driver 130 can be implemented by a plurality of transistors, wherein the withstand voltage of the plurality of transistors is lower than the upper limit of the voltage range of the input signal DIN (e.g., the voltage AVDDH). For example, as previously described, the voltage AVDDH can be about 3.3 volts, and the withstand voltage of the plurality of transistors described above can be about 1.8 volts. In order to avoid damage to the transistors in the edge adjustment circuit 120 during the level adjustment, the edge adjustment circuit 120 can provide an over-voltage protection to the transistors therein. On the other hand, the level conversion circuit 110 and the driver 130 can avoid damage by the circuit connection relationship.

[0050] The driver 130 is coupled to a node (e.g., the control node in the Figure 3A edge adjustment circuit 120) of the edge adjustment circuit 120 via the capacitor C, and generates the output signal VO according to the level of the first node and the level of the second node. In some embodiments, by the edge adjustment circuit 120, the driver 130 does not generate an excessive short-circuit current (or a shoot-through current) to avoid damage to the driver 130. In some embodiments, by adjusting the bias current in the edge adjustment circuit 120, the rising edge and the falling edge of the output signal VO can be adjusted. The detailed arrangement and operation of the circuits described above will be explained later with reference to the drawings.

[0051] Figure 2 The waveforms of the signals in some embodiments according to the present application are shown in FIG. 1. Figure 1FIG. 2 is a schematic diagram of a level shifting circuit 110. The level shifting circuit 110 includes a comparison circuit 210, a comparison circuit 220, a plurality of inverters 230, 240, 250, and 260. The comparison circuit 210 outputs one of the input signal DIN and a voltage AVSSH having a higher level as a data signal Dl. The comparison circuit 220 outputs one of the input signal DIN and a voltage AVDDL having a lower level as a data signal D2. The inverter 230 and the inverter 240 are coupled in series to sequentially generate a signal DBH and a signal DH from the data signal Dl, wherein the inverter 230 and the inverter 240 operate in a voltage range of the signal DBH and the signal DH, i.e., the inverter 230 and the inverter 240 operate between a voltage AVDDH and the voltage AVSSH. The inverter 250 and the inverter 260 are coupled in series to sequentially generate a signal DBL and a signal DL from the data signal D2, wherein the inverter 250 and the inverter 260 operate in a voltage range of the signal DBL and the signal DL, i.e., the inverter 250 and the inverter 260 operate between the voltage AVDDL and a voltage AVSS.

[0052] In detail, the comparison circuit 210 includes a plurality of P-type transistors Tl and T2. The first end (e.g., source) of the P-type transistor Tl receives the input signal DIN, the second end (e.g., drain) of the P-type transistor Tl outputs the data signal Dl, the control end (e.g., gate) of the P-type transistor Tl receives the voltage AVSSH, and the fourth end (e.g., base) of the P-type transistor Tl receives the voltage AVDDH. The first end of the P-type transistor T2 receives the voltage AVSSH, the second end of the P-type transistor T2 is coupled to the second end of the P-type transistor Tl, the control end of the P-type transistor T2 receives the input signal DIN, and the fourth end of the P-type transistor T2 receives the voltage AVDDH. The P-type transistor Tl can selectively conduct according to the voltage AVSSH and the input signal DIN to output the voltage AVSSH as the data signal Dl. The P-type transistor T2 can selectively conduct according to the voltage AVSSH and the input signal DIN to output the input signal DIN as the data signal Dl. For example, if the voltage AVSSH is higher than the input signal DIN, the P-type transistor Tl conducts and the P-type transistor T2 does not conduct. In this condition, the P-type transistor Tl can output the voltage AVSSH as the data signal Dl. Alternatively, if the input signal DIN is higher than the voltage AVSSH, the P-type transistor T2 conducts and the P-type transistor Tl does not conduct. In this condition, the P-type transistor T2 can output the input signal DIN as the data signal Dl. Furthermore, by the above connection, the voltage across any two ends of each of the P-type transistors Tl and T2 does not exceed the aforementioned voltage withstand (e.g., 1.8 volts).

[0053] Similarly, the comparator circuit 220 includes multiple N-type transistors T3 and T4. The first terminal (e.g., the drain) of N-type transistor T3 receives the input signal DIN, the second terminal (e.g., the source) outputs the data signal D2, the control terminal (e.g., the gate) receives the voltage AVDDL, and the fourth terminal (e.g., the base) receives the voltage AVSS. The first terminal of N-type transistor T4 receives the voltage AVDDL, the second terminal of N-type transistor T4 is coupled to the second terminal of N-type transistor T3, the control terminal of N-type transistor T4 receives the input signal DIN, and the fourth terminal of N-type transistor T4 receives the voltage AVSS. N-type transistor T3 can be selectively turned on based on the voltage AVDDL and the input signal DIN to output the input signal DIN as the data signal D2. N-type transistor T4 can also be selectively turned on based on the voltage AVDDL and the input signal DIN to output the voltage AVDDL as the data signal D2. For example, if the voltage AVDDL is higher than the input signal DIN, N-type transistor T3 is turned on and N-type transistor T4 is not turned on. Under these conditions, N-type transistor T3 can output the input signal DIN as the data signal D1. Alternatively, if the input signal DIN is higher than the voltage AVDDL, N-type transistor T4 is turned on and N-type transistor T3 is not turned on. Under these conditions, N-type transistor T4 can output the voltage AVDDL as the data signal D2. Through the above connection method, the voltage across either end of N-type transistors T3 and T4 can be ensured not to exceed the aforementioned withstand voltage.

[0054] In some embodiments, Figure 1 Edge adjustment circuit 120 includes Figure 3A 300A circuit and Figure 3B Circuit 300B. Circuit 300A can adjust the level of the first node according to signal DL (i.e., the corresponding signal between signal DL and signal DBL), signal DH, and signal DBH to adjust the rising edge of the output signal VO. Circuit 300B can adjust the level of the second node according to signal DH (i.e., the corresponding signal between signal DH and signal DBH), signal DL, and signal DBL to adjust the falling edge of the output signal VO. For ease of understanding, the following will refer to... Figure 3A and Figure 3B The setup of each of the above circuits will be explained in sequence.

[0055] Figure 3A Drawings based on some embodiments of this application Figure 1FIG. 3A is a schematic diagram of the circuit 300A in the edge adjustment circuit 120 of FIG. 1. The circuit 300A includes a pull-down circuit 310 and a protection circuit 320. The pull-down circuit 310 adjusts the level of a node dl according to a signal DL, a signal DH, and a signal DBH, and adjusts the level of a control node dc. The protection circuit 320 provides overvoltage protection to the pull-down circuit 310 according to the level of the control node dc, a voltage AVSSH, and a voltage AVDDL.

[0056] In detail, the pull-down circuit 310 includes a plurality of P-type transistors P1-P3, a plurality of N-type transistors N1-N2, and a current source circuit 315. The first end of the P-type transistor P1 receives the voltage AVDDH, the second end of the P-type transistor P1 is coupled to the node dl, and the control end of the P-type transistor P1 receives the signal DH. The P-type transistor P1 selectively conducts according to the signal DH to transmit the voltage AVDDH to the node dl. In other words, when the P-type transistor P1 is turned on, the level of the node dl can be pulled up to the voltage AVDDH. The first end of the P-type transistor P2 is coupled to the node dl, the second end of the P-type transistor P2 is coupled to the node d3, and the control end of the P-type transistor P2 receives the signal DBH. The P-type transistor P2 selectively conducts according to the signal DBH to couple the node dl to the node d3. The first end of the P-type transistor P3 is coupled to the node d3, the second end of the P-type transistor P3 is coupled to the control node dc, and the control end of the P-type transistor P3 receives the voltage AVSSH. The P-type transistor P3 selectively conducts according to the voltage AVSSH and the level of the node d3 to couple the node d3 to the control node dc.

[0057] The first end of the N-type transistor N1 is coupled to the control node dc, the second end of the N-type transistor N1 is coupled to the node d4, and the control end of the N-type transistor N1 receives the voltage AVDDL. The N-type transistor N1 selectively conducts according to the voltage AVDDL and the level of the node d4 to couple the control node dc to the node d4. The first end of the N-type transistor N2 is coupled to the node d4, the second end of the N-type transistor N2 is coupled to a voltage source providing the voltage AVSS via the current source circuit 315, and the control end of the N-type transistor N2 receives the signal DL. The N-type transistor N2 selectively conducts according to the level of the signal DL to pull down the level of the node d4 to the voltage AVSS via the current source circuit 315. Through the above arrangement, it should be understood that in the pull-down circuit 310, if the P-type transistor P1 is not turned on and the remaining transistors are all turned on, the node dl can be pulled down to the voltage AVSS via the current source circuit 315. In some embodiments, the current source circuit 315 is a variable current source. The greater the current of the current source circuit 315, the higher the pull-down capability, so that the node dl can be pulled down to the voltage AVSS more quickly. In this way, the rising time of the output signal VO from the low level to the high level (i.e., adjusting the rising edge of the output signal VO) can be accelerated.

[0058] The protection circuit 320 includes multiple N-type transistors N3 to N5 and multiple P-type transistors P4 to P6. The first terminal of N-type transistor N3 is coupled to node d1, the second terminal of N-type transistor N3 is coupled to node d5, and the control terminal of N-type transistor N3 receives signal DH. N-type transistor N3 is selectively turned on according to signal DH to couple nodes d1 to d5. The first terminal of N-type transistor N4 receives voltage AVSSH, the second terminal of N-type transistor N4 is coupled to node d5, and the control terminal of N-type transistor N4 receives signal DBH. N-type transistor N4 is selectively turned on according to signal DBH to transmit voltage AVSSH to node d5. The first terminal of P-type transistor P4 receives voltage AVSSH, the second terminal of P-type transistor P4 is coupled to node d5, and the control terminal of P-type transistor P4 is coupled to control node dc. P-type transistor P4 is selectively turned on according to the level of control node dc to transmit voltage AVSSH to node d5. The first terminal of P-type transistor P5 is coupled to node d3, the second terminal of P-type transistor P5 receives voltage AVSSH, and the control terminal of P-type transistor P5 is coupled to control node dc. P-type transistor P5 selectively conducts according to the level of control node dc to transmit voltage AVSSH to node d3. The first terminal of N-type transistor N5 is coupled to node d6, the second terminal of N-type transistor N5 receives voltage AVDDL, and the control terminal of N-type transistor N5 is coupled to control node dc. N-type transistor N5 selectively conducts according to the level of control node dc to transmit voltage AVDDH to node d6. The first terminal of P-type transistor P6 is coupled to node d4, the second terminal of P-type transistor P6 is coupled to node d6, and the control terminal of P-type transistor P6 receives signal DL. P-type transistor P6 selectively conducts according to signal DL to couple node d6 to node d4. The operation of protection circuit 320 will be described later. Figure 5A and Figure 6A illustrate.

[0059] Figure 3B Drawings based on some embodiments of this application Figure 1 A schematic diagram of circuit 300B in the edge adjustment circuit 120. Circuit 300B includes a pull-up circuit 330 and a protection circuit 340. The pull-up circuit 330 pulls up the level of node d2 based on signals DH, DL, and DBL, and adjusts the level of control node dc. The protection circuit 340 provides overvoltage protection to the pull-up circuit 330 based on the level of control node dc, voltage AVSSH, and voltage AVDDL.

[0060] In detail, the pull-up circuit 330 includes a current source circuit 335, a plurality of P-type transistors P7-P8, and a plurality of N-type transistors N6-N8. The first end of the P-type transistor P7 receives the voltage AVDDH via the current source circuit 335, the second end of the P-type transistor P7 is coupled to a node d7, and the control end of the P-type transistor P7 receives a signal DH. The P-type transistor P7 selectively conducts according to the signal DH to transmit the voltage AVDDH from the current source circuit 335 to the node d7. The first end of the P-type transistor P8 is coupled to the node d7, the second end of the P-type transistor P8 is coupled to a control node dc, and the control end of the P-type transistor P8 receives a voltage AVSSH. The P-type transistor P8 selectively conducts according to the voltage AVSSH and the level of the node d7 to couple the node d7 to the control node dc.

[0061] The first end of the N-type transistor N6 is coupled to the control node dc, the second end of the N-type transistor N6 is coupled to a node d8, and the control end of the N-type transistor N6 receives a voltage AVDDL. The N-type transistor N6 selectively conducts according to the voltage AVDDL and the level of the node d8 to couple the control node dc to the node d8. The first end of the N-type transistor N7 is coupled to the node d8, the second end of the N-type transistor N7 is coupled to the node d2, and the control end of the N-type transistor N7 receives a signal DBL. The N-type transistor N7 selectively conducts according to the signal DBL to couple the node d8 to the node d2. The first end of the N-type transistor N8 is coupled to the node d2, the second end of the N-type transistor N8 receives a voltage AVSS, and the control end of the N-type transistor N8 receives a signal DL. The N-type transistor N8 selectively conducts according to the signal DL to transmit the voltage AVSS to the node d2. Through the above arrangement, it can be understood that in the pull-up circuit 330, if the N-type transistor N8 is not conducting and the remaining transistors are all conducting, the node d2 can be pulled up to the voltage AVDDH via the current source circuit 335. In some embodiments, the current source circuit 335 is a variable current source. The greater the current of the current source circuit 335, the higher the pull-up capability, so that the node d2 can be pulled up to the voltage AVDDH more quickly. In this way, the falling time of the output signal VO from the high level to the low level (i.e., adjusting the falling edge of the output signal VO) can be accelerated.

[0062] The protection circuit 340 includes multiple N-type transistors N9 to N11 and multiple P-type transistors P9 to P11. The first terminal of P-type transistor P9 is coupled to node d9, the second terminal of P-type transistor P9 is coupled to node d2, and the control terminal of P-type transistor P9 receives a signal DL. P-type transistor P9 is selectively turned on according to signal DL to couple node d9 to node d2. The first terminal of P-type transistor P10 is coupled to node d9, the second terminal of P-type transistor P10 receives a voltage AVDDL, and the control terminal of P-type transistor P10 receives a signal DBL. P-type transistor P10 is selectively turned on according to signal DBL to transmit the voltage AVDDL to node d9. The first terminal of N-type transistor N9 is coupled to node d9, the second terminal of N-type transistor N9 receives a voltage AVDDL, and the control terminal of N-type transistor N9 is coupled to control node dc. N-type transistor N9 is selectively turned on according to the level of control node dc to transmit the voltage AVDDL to node d9. N-type transistor N10 receives voltage AVDDL at its first terminal, is coupled to node d8 at its second terminal, and is coupled to control node dc at its control terminal. N-type transistor N10 selectively conducts according to the level of control node dc to transmit voltage AVDDL to node d8. P-type transistor P11 receives voltage AVSSH at its first terminal, is coupled to node d10 at its second terminal, and is coupled to control node dc at its control terminal. P-type transistor P11 selectively conducts according to the level of control node dc to transmit voltage AVSSH to node d10. N-type transistor N11 is coupled to node d10 at its first terminal, is coupled to node d7 at its second terminal, and receives signal DH at its control terminal. N-type transistor N11 selectively conducts according to signal DH to couple node d10 to node d7. The operation of protection circuit 340 will be described later. Figure 5B and Figure 6B illustrate.

[0063] Figure 4 Drawings based on some embodiments of this application Figure 1 A schematic diagram of driver 130 is shown. Driver 130 includes multiple P-type transistors P12-P13 and multiple N-type transistors N12-N13. The first terminal of P-type transistor P12 receives voltage AVDDH, the second terminal of P-type transistor P12 is coupled to the first terminal of P-type transistor P13, and the control terminal of P-type transistor P12 is coupled to... Figure 3A In the circuit, node d1 is used. P-type transistor P12 is selectively turned on according to the level of node d1 to transfer voltage AVDDH to the first terminal of P-type transistor P13. The second terminal of P-type transistor P13 is coupled to the output node do, and the control terminal of P-type transistor P13 receives voltage AVSSH.

[0064] The first terminal of the N-type transistor N12 is coupled to the output node do, the second terminal of the N-type transistor N12 is coupled to the first terminal of the N-type transistor N13, and the control terminal of the N-type transistor N12 receives the voltage AVDDH. The second terminal of the N-type transistor N13 receives the voltage AVSS, and the control terminal of the N-type transistor N13 is coupled to the node d2 in Figure 3B The N-type transistor N13 selectively turns on according to the level of the node d2, and pulls down the level of the output node do to the voltage AVSS. The output node do is coupled to the Figure 1 through the capacitor C, and is coupled to the output terminal (not shown) through the resistor R to transmit the output signal VO. Figure 3A and the control node dc in Figure 3B , and is coupled to the output terminal (not shown) through the resistor R to transmit the output signal VO.

[0065] When the level of the node d1 becomes low, the P-type transistor P12 can turn on to pull up the level of the output node do. In this way, the output signal VO can be switched to the high level. Alternatively, when the level of the node d2 becomes high, the N-type transistor N13 can turn on to pull down the level of the output node do. In this way, the output signal VO can be switched to the low level. On the other hand, by the edge adjustment circuit 120, the turn-on period of the P-type transistor P12 can not overlap with the turn-on period of the N-type transistor N13 (i.e., the two transistors will not turn on at the same time). In this way, the driver 130 can be ensured not to generate short-circuit current, so as to improve the reliability of the transmitter 100.

[0066] Figure 5A The operation of the circuit 300A when the input signal DIN is switched from the low level to the high level and the level of the control node dc has not been changed yet is shown in FIG. 3B. Referring to FIG. 3B, Figure 3A Figure 2 ​This is understandable. When the input signal DIN switches from a low level to a high level, the level of signal DH is the same as the voltage AVDDH, the level of signal DBH is the same as the voltage AVSSH, and the level of signal DL is the same as the voltage AVDDL. As a result, P-type transistors P1 and P6, and N-type transistor N4, are not conducting, while P-type transistors P2-P3 and transistors N1-N3 are conducting. Furthermore, because the input signal DIN was at a low level in the previous cycle, the level of control node dc was at a high level (equivalent to voltage AVDDH). Therefore, during the initial period after the input signal DIN switches to a high level, the level of control node dc remains at a high level, causing P-type transistors P4 and P5 to be non-conducting and N-type transistor N5 to be conducting. Based on the above conditions, the level of node d1 is pulled down to the sum of the critical voltages of signal DBH and transistor P2 via transistors P2 and P3, N-type transistors N1 and N2 and current source circuit 315, and the level of control node dc is pulled down via multiple N-type transistors N1 and N2 and current source circuit 315.

[0067] In the above process, N-type transistor N7 can be coupled from node d1 to node d5. As mentioned earlier, the level of node d1 is adjusted to the sum of the signal DBH and the critical voltage of transistor P2. This ensures that the voltage across any of the N-type transistors N4, P4, and P5 does not exceed their withstand voltage. Furthermore, N-type transistor N5 can transfer voltage AVDDL to node d6 to ensure that the voltage across the P-type transistor P6 does not exceed its withstand voltage. Additionally, when the level of node d1 decreases, Figure 4 The P-type transistor P12 will start to conduct and pull up the level of the output node do to start generating an output signal VO with a high level.

[0068] Figure 5B Drawings based on some embodiments of this application Figure 3B The circuit 300B operates as follows: when the input signal DIN switches from a low level to a high level while the level of the control node dc remains unchanged. (Refer to...) Figure 2 This is understandable. When the input signal DIN switches from a low level to a high level, the level of signal DBL is the same as that of voltage AVSS. As mentioned earlier, during the initial period after the input signal DIN switches to a high level, the level of control node dc is still at a high level. Under this condition, P-type transistors P7, P9, and P11 are not conducting, and N-type transistor N8 is conducting. Thus, N-type transistor N8 can quickly pull down the level of node d2 to voltage AVSS. Figure 4The N-type transistor N13 will be quickly turned off to avoid short-circuit current. On the other hand, N-type transistors N9-N10 and P-type transistor P10 are turned on, making the levels of nodes d9 and d8 both equal to voltage AVDDL. Furthermore, N-type transistor N11 and P-type transistor P8 are turned on, making the levels of nodes d7 and d10 close to the level of control node dc. This arrangement ensures that the voltage across any transistor in circuit 300B does not exceed its withstand voltage.

[0069] Figure 6A Drawings based on some embodiments of this application Figure 3A The circuit diagram for circuit 300A is shown when the input signal DIN switches from a low level to a high level and the level of the control node dc changes. (Continued) Figure 5A In this operation, when the level of control node DC is pulled down to a low level (e.g., voltage AVSS) via N-type transistors N1 and N2 and current source circuit 315, P-type transistors P4 and P5 are turned on while N-type transistor N5 is turned off. Under this condition, the levels of nodes d5 and d3 are both voltage AVSSH, making P-type transistors P2 and P3 turn off. Thus, N-type transistor N3 can fully pull down the level of node d1 to voltage AVSSH. In this way, Figure 4 The P-type transistor P12 can be fully turned on. With the above configuration, the level of each internal node of circuit 300A can be fixed at a specific voltage to ensure that the voltage across any two ends of any transistor in circuit 300A will not exceed its withstand voltage value.

[0070] Figure 6B Drawings based on some embodiments of this application Figure 3B The diagram illustrates the operation of circuit 300B when the input signal DIN switches from a low level to a high level and the level of control node dc changes. (Continued) Figure 5B The operation, when the level of the control node DC is via Figure 6A When N-type transistors N1 and N2 and current source circuit 315 are pulled down to a low level (e.g., voltage AVSS), P-type transistor P11 is turned on while N-type transistors N9 and N10 are not turned on. Under this condition, the levels of nodes d10 and d7 are both voltage AVSSH, causing P-type transistor P8 to be off. Since P-type transistor P10 remains on, the level of node d9 does not change (remaining at voltage AVDDL). Since multiple N-type transistors N6 and N7 remain off, the level of node d8 also does not change. In this way, the levels of the internal nodes of circuit 300B can all be fixed at a specific voltage to ensure that the voltage across any two terminals of any transistor in circuit 300B will not exceed its withstand voltage value.

[0071] pass Figure 5A , Figure 5B ,Figure 6A With Figure 6B understanding that during the process of input signal DIN switching from low level to high level, circuit 300A gradually pulls the level of node d1 down to voltage AVSSH in the operation of Figure 5A and Figure 6A to gradually turn on P-type transistor P12 of Figure 4 . On the contrary, circuit 300B can quickly pull the level of node d2 down to voltage AVSSH in the operation of Figure 5B to quickly turn off N-type transistor N13 of Figure 4 . In this way, it can be ensured that P-type transistor P12 and N-type transistor N13 of Figure 4 cannot be fully turned on at the same time to ensure that driver 130 will not generate excessive short-circuit current.

[0072] Similarly, when input signal DIN switches from high level to low level, if the level of control node dc has not changed yet (maintained at the low level of the previous period), according to the levels of signals DH, DBL, and DL, pull-up circuit 330 can pull the level of node d2 up to the level of signal DBL minus the threshold voltage of N-type transistor N7. Meanwhile, P-type transistor P1 in pull-down circuit 310 is turned on to quickly pull the level of node d1 up to voltage AVDDH to ensure that P-type transistor P12 of Figure 4 can be quickly turned off. Then, when the level of control node dc is pulled up to voltage AVDDH, pull-up circuit 330 can completely pull the level of node d2 up to voltage AVDDH to ensure that N-type transistor N13 of Figure 4 can be fully turned on. In this way, it can be ensured that during the process of input signal DIN switching from high level to low level, P-type transistor P12 and N-type transistor N13 of Figure 4 cannot be fully turned on at the same time to ensure that driver 130 will not generate excessive short-circuit current.

[0073] Since circuit 300A and circuit 300B have similar mirror-symmetrical structures, there are also corresponding relationships between the operations of circuit 300A and circuit 300B. Therefore, the relevant operations performed by circuit 300A and circuit 300B during the process of input signal DIN switching from high level to low level can be understood according to the operation processes of Figure 5A , Figure 5B , Figure 6A and Figure 6B , which will not be repeated here. Through the above description, it should be understood that during the process of the level of input signal DIN switching, protection circuit 320 and protection circuit 340 can fix the levels of multiple internal nodes in pull-down circuit 310 and pull-up circuit 330 to provide the above-mentioned overvoltage protection to ensure that the voltage across any transistor of the above-mentioned two will not be too high.

[0074] It should be noted that, in the embodiments of the present application, "a plurality of" refers to "two or more than two"

[0075] In summary, the transmitter in some embodiments of the present application can use transistors with low voltage resistance to transmit output signals with high level, and use overvoltage protection and short circuit current protection to ensure that the transistors will not be damaged, so as to improve the reliability of the transmitter.

[0076] The above describes in detail the transmitter with overvoltage protection provided by the embodiments of the present application. The principles and implementation manners of the present application are described by applying specific examples in this paper, and the above description of the embodiments is only used to help understand the method of the present application and its core idea; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation manner and application range will be changed, and in summary, the content of the present description should not be understood as a limitation of the present application.

Claims

1. A transmitter, characterized by The method comprises: generating a plurality of first signals and a plurality of second signals based on an input signal, wherein voltage ranges of the input signal, the plurality of first signals and the plurality of second signals are different from each other; adjusting a level of a first node and a level of a second node according to the plurality of first signals and the plurality of second signals, and providing an overvoltage protection during the adjusting of the level of the first node and the level of the second node; and generating an output signal according to the level of the first node and the level of the second node; wherein the adjusting of the level of the first node and the level of the second node comprises: adjusting the level of the first node according to a corresponding one of the plurality of second signals and the plurality of first signals to adjust a rising edge of the output signal; and adjusting the level of the second node according to a corresponding one of the plurality of first signals and the plurality of second signals to adjust a falling edge of the output signal. The adjusting of the level of the first node and the level of the second node comprises: pulling down the level of the first node and adjusting a level of a control node according to the corresponding one of the plurality of second signals and the plurality of first signals; and providing an overvoltage protection to the pulling down according to the level of the control node, a first voltage and a second voltage, wherein the first voltage is a lower limit of a voltage range of the plurality of first signals, and the second voltage is an upper limit of a voltage range of the plurality of second signals.

2. The transmitter of claim 1, wherein, The adjusting of the level of the first node and the level of the second node comprises a plurality of transistors, each of which has a withstand voltage less than the upper limit of the voltage range of the input signal, and the adjusting of the level of the first node and the level of the second node provides an overvoltage protection to the plurality of transistors.

3. The transmitter of claim 1, wherein, The pulling down of the level of the first node and the adjusting of the level of the control node comprises: a first P-type transistor selectively turned on according to one of the plurality of first signals to transmit a third voltage to the first node, wherein the third voltage is an upper limit of the voltage range of the plurality of first signals; a second P-type transistor selectively turned on according to another one of the plurality of first signals to couple the first node to a third node; a third P-type transistor selectively turned on according to the first voltage and a level of the third node to couple the third node to the control node; a first N-type transistor selectively turned on according to the second voltage and a level of a fourth node to couple the control node to the fourth node; a current source circuit; and a second N-type transistor selectively turned on according to the corresponding one of the plurality of second signals to pull down the level of the fourth node to a fourth voltage via the current source circuit, wherein the fourth voltage is a lower limit of the voltage range of the plurality of second signals.

4. The transmitter of claim 3, wherein, The providing of the overvoltage protection to the pulling down comprises: a third N-type transistor selectively turned on according to the one of the plurality of first signals to couple the first node to a fifth node; a fourth N-type transistor selectively turned on according to the another one of the plurality of first signals to transmit the first voltage to the fifth node; and a fifth N-type transistor selectively turned on according to the corresponding one of the plurality of second signals to transmit the second voltage to the fourth node. a fourth P-type transistor selectively turned on according to a level of the control node to transmit the first voltage to the fifth node; a fifth P-type transistor selectively turned on according to a level of the control node to transmit the first voltage to the third node; a fifth N-type transistor selectively turned on according to a level of the control node to transmit the second voltage to a sixth node; and a sixth P-type transistor selectively turned on according to the corresponding one of the second signals to couple the sixth node to the third node.

5. The transmitter of claim 1, wherein, The second circuit includes: a pull-up circuit to pull up a level of the second node according to the corresponding one of the first signals and the second signals and to adjust a level of a control node; a protection circuit to provide overvoltage protection to the pull-up circuit according to a level of the control node, a first voltage and a second voltage, wherein the first voltage is a lower limit of a voltage range of the first signals and the second voltage is an upper limit of a voltage range of the second signals.

6. The transmitter of claim 5, wherein, The pull-up circuit includes: a current source circuit; a first P-type transistor selectively turned on according to the corresponding one of the first signals to transmit a third voltage from the current source circuit to a third node, wherein the third voltage is an upper limit of a voltage range of the first signals; a second P-type transistor selectively turned on according to a level of the first voltage and the third node to couple the third node to the control node; a first N-type transistor selectively turned on according to a level of the second voltage and a fourth node to couple the control node to the fourth node; a second N-type transistor selectively turned on according to one of the second signals to couple the fourth node to the second node; and a third N-type transistor selectively turned on according to another one of the second signals to transmit a fourth voltage to the second node, wherein the fourth voltage is a lower limit of a voltage range of the second signals.

7. The transmitter of claim 6, wherein, The protection circuit includes: a third P-type transistor selectively turned on according to the another one of the second signals to couple the second node to a fifth node; a fourth P-type transistor selectively turned on according to the one of the second signals to transmit the second voltage to the fifth node; a fourth N-type transistor selectively turned on according to a level of the control node to transmit the second voltage to the fifth node; a fifth N-type transistor selectively turned on according to a level of the control node to transmit the second voltage to the fourth node; a fifth P-type transistor selectively turned on according to a level of the control node to transmit the first voltage to a sixth node; and a sixth N-type transistor selectively turned on according to the corresponding one of the first signals to couple the sixth node to the third node.

8. The transmitter of claim 1, wherein, The first signals have opposite levels to each other, and the second signals have opposite levels to each other.

9. The transmitter of claim 1, wherein, The voltage range of the input signal is greater than the voltage range of the first signals and greater than the voltage range of the second signals, an upper limit of the voltage range of the first signals is higher than an upper limit of the voltage range of the second signals, and a lower limit of the voltage range of the first signals is higher than a lower limit of the voltage range of the second signals.

10. The transmitter of claim 1, wherein, The level conversion circuit includes: a first comparison circuit outputting a first data signal having a higher level of one of the input signal and a first voltage, wherein the first voltage is a lower limit of the voltage range of the first signals; a second comparison circuit outputting a second data signal having a lower level of one of the input signal and a second voltage, wherein the second voltage is an upper limit of the voltage range of the second signals; a plurality of first inverters generating the first signals according to the first data signal; and a plurality of second inverters generating the second signals according to the second data signal.

11. The transmitter of claim 10, wherein, The first comparison circuit includes: a first P-type transistor selectively conducting according to the first voltage and the input signal to output the input signal as the first data signal; and a second P-type transistor selectively conducting according to the first voltage and the input signal to output the first voltage as the first data signal, wherein a base of each of the first P-type transistor and the second P-type transistor receives a third voltage, and the third voltage is an upper limit of the voltage range of the first signals or the input signal.

12. The transmitter of claim 10, wherein, The second comparison circuit includes: a first N-type transistor selectively conducting according to the second voltage and the input signal to output the input signal as the second data signal; and a second N-type transistor selectively conducting according to the first voltage and the input signal to output the second voltage as the second data signal, wherein a base of each of the first N-type transistor and the second N-type transistor receives a fourth voltage, and the fourth voltage is a lower limit of the voltage range of the second signals or the input signal.

13. The transmitter of claim 1, wherein, The driver includes a P-type transistor and an N-type transistor, the P-type transistor selectively conducting according to the level of the first node and the N-type transistor selectively conducting according to the level of the second node to generate the output signal, and the P-type transistor and the N-type transistor are not simultaneously conducting.

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