vibrating device

Abstract

Vibration device. A vibration device capable of suppressing variation in oscillation characteristics is provided. The vibration device includes a semiconductor substrate, a base, a vibration element, and a cover. The semiconductor substrate has a first surface and a second surface in an opposite relationship to the first surface. The base includes an integrated circuit disposed on the first surface or the second surface. The vibration element is electrically connected to the integrated circuit and is disposed on the first surface side. The cover is joined to the base at a joining portion of the base in a manner that accommodates the vibration element. The integrated circuit includes a passive element, and the passive element is disposed so that, when viewed from a direction orthogonal to the first surface, at least a portion of the passive element overlaps the joining portion.

Description

Technical Field

[0001] This invention relates to vibration devices, etc. Background Technology

[0002] Previously, oscillators and other vibrating devices were known as devices that used vibrating elements. Patent Document 1 discloses the following technology: a piezoelectric vibrating plate, which serves as a vibrating element, is mounted on a semiconductor substrate such as a silicon substrate on which an integrated circuit circuit pattern is formed, and the piezoelectric vibrating plate is sealed by the semiconductor substrate and a cover, thereby achieving encapsulation.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2013-126052

[0004] The materials constituting the device and package have different coefficients of thermal expansion, thus stress is applied during packaging. Furthermore, stress arises during the soldering and mounting of the package to an external circuit board due to the difference in thermal expansion coefficients between the package and the circuit board, as well as stress caused by the underfill material used to fix the package and the circuit board. When these stresses cause warping or other deformations in the integrated circuit, they affect the device's characteristics. The manner in which stress is generated depends on the package structure; therefore, it is necessary to consider the stresses generated by the package structure when designing the layout of the integrated circuit. This situation was not considered in Patent Document 1. Summary of the Invention

[0005] One aspect of the present invention relates to a vibration device comprising: a base including a semiconductor substrate and an integrated circuit, the semiconductor substrate having a first surface and a second surface opposite to the first surface, the integrated circuit being disposed on the first surface or the second surface; a vibration element electrically connected to the integrated circuit and disposed on the first surface side; and a cover engaging with the base at a joint of the base to receive the vibration element, the integrated circuit including passive elements configured such that at least a portion of the passive elements overlaps with the joint when viewed from a direction orthogonal to the first surface.

[0006] Furthermore, one aspect of the present invention relates to a vibration device comprising: a base including a semiconductor substrate and an integrated circuit, the semiconductor substrate having a first surface and a second surface opposite to the first surface, the integrated circuit being disposed on the first surface or the second surface; a vibration element electrically connected to the integrated circuit and disposed on the first surface side; and a cover engaging with the base at a joint of the base to receive the vibration element, the integrated circuit including at least one of a reference voltage generating circuit for generating a reference voltage used in the integrated circuit or a regulator circuit for generating a regulating power supply voltage used in the integrated circuit, wherein at least a portion of a passive element or an active element included in the reference voltage generating circuit or the regulator circuit is configured to overlap the joint when viewed from a direction orthogonal to the first surface.

[0007] Furthermore, one aspect of the present invention relates to a vibration device comprising: a base including a semiconductor substrate and an integrated circuit, the semiconductor substrate having a first surface and a second surface opposite to the first surface, the integrated circuit being disposed on the first surface or the second surface; a vibration element electrically connected to the integrated circuit and disposed on the first surface side; and a cover engaging with the base at a joint of the base to receive the vibration element, the integrated circuit including at least one of a temperature sensor for detecting temperature or a temperature compensation circuit for temperature compensation of the oscillation frequency of the vibration element, wherein at least a portion of a passive element or an active element included in the temperature sensor or the temperature compensation circuit is configured to overlap the joint when viewed from a direction orthogonal to the first surface. Attached Figure Description

[0008] Figure 1 This is a cross-sectional view showing a structural example of the vibration device according to this embodiment.

[0009] Figure 2 This is a cross-sectional view showing a specific structural example of the vibration device according to this embodiment.

[0010] Figure 3 This is a top view showing an example of a vibrating element of a vibrating device.

[0011] Figure 4 This is a block diagram illustrating an example of an integrated circuit structure.

[0012] Figure 5 This is a cross-sectional view showing another structural example of the vibration device of this embodiment.

[0013] Figure 6 This is a diagram illustrating the effect of stress on a vibrating device.

[0014] Figure 7 This is a diagram showing an example of the structure of a resistor.

[0015] Figure 8 This is a diagram showing an example of the structure of a capacitor.

[0016] Figure 9 This is a cross-sectional view showing an example of the structure of a bipolar transistor.

[0017] Figure 10 This is a top view showing an example of the configuration of through electrodes, external connection terminals, integrated circuits, etc.

[0018] Figure 11 This is a diagram showing an example of the structure of an oscillating circuit.

[0019] Figure 12 This is a diagram illustrating an example of the structure of a reference voltage generation circuit.

[0020] Figure 13 This is a diagram showing an example of the structure of a regulator circuit.

[0021] Figure 14 This is a diagram showing an example of the structure of a temperature sensor.

[0022] Figure 15 This is a diagram showing an example of the structure of a temperature compensation circuit.

[0023] Figure 16 This is a diagram showing an example of the structure of a high-order correction circuit.

[0024] Figure 17 This is a top view showing another configuration example of through electrodes, external connection terminals, integrated circuits, etc.

[0025] Label Explanation

[0026] 1. 101: Vibrating device; 2. 102: Base; 5. 105: Vibrating element; 7. 107: Cover; 8. 108: Reconfiguration wiring layer; 10. 110: Integrated circuit; 11: Oscillating circuit; 12: Output circuit; 13: Control circuit; 14A: Power supply circuit; 14B: Regulator circuit; 15: Temperature compensation circuit; 16: Temperature sensor; 17: Storage unit; 18: PLL circuit; 20: Semiconductor substrate; 21. 121: First surface; 22. 122: Second surface; 23. 24: Transistor; 25: Component separation film; 27: Guard ring; 30: Wiring layer; 31. 32: Metal layer; 33. 34. 35: Insulating layer; 36. 37. 38. 39: Contact pads; 40. 41, 140, 141: Through-electrode; 44: Insulating layer; 50: Vibrating substrate; 52, 53: Excitation electrode; 54: Wiring; 56: Terminal; 60, 61, 160, 161: Connecting components; 62, 162: Bumps; 64: Terminal; 68, 69: Contact pads; 71, 72: Connecting components; 80, 180: Insulating layer; 82, 182: Wiring; 84: First metal layer; 86: Second metal layer; 91, 92, 191, 192: External connection terminals; 132: Drive circuit; 134: Reference voltage supply circuit; 136: First variable capacitor circuit; 137: Second variable capacitor circuit; 152: Zero-order calibration circuit; 154: First-order calibration circuit; 156: High-order calibration circuit. Positive circuit; 158: Current-to-voltage conversion circuit; 159: Reference voltage supply line; 171, 172: 3rd metal layer; 173, 174: 4th metal layer; 176: 5th metal layer; 177, 178: 6th metal layer; 210A, 210B: Conductor layer; 220: Insulating layer; 230: Base region; 232: Crystal defect; BP, BP0, BP1, BP2, BP3, BP4, BP51, BP52, BP5(2N), BP5(2N+1), BP61, BP62, BP6(2N), BP6(2N+1): Bipolar transistor; C, C1, C2, C31, C3n, C4, C5, C6, C7, C8, CA: Capacitor; CK: Time Clock signal; IA, IB1, IB2, IB(2N), IB(2N+1): constant current; ISA, ISB, ISC1, ISC2, ISC(2N), ISC(2N+1): current source; JA: junction; LA, LB: wiring; N1: first node; NR1, NR2, NRn, NS1, NS2: supply node; OE: output enable signal; OPA: operational amplifier; OSC: oscillation signal; R, RA1, RA2, RA3, RB, RC1, RC2, RD1, RD2, RD3, RE1, RF1, RF2, RF(2N), RF(2N+1), RG1, RG2, RG(2N), RG(2N+1), RQ: resistor;REA: Variable resistor circuit; SD1: Side 1; SD2: Side 2; SD3: Side 3; SD4: Side 4; SDA: Data signal; SP: Storage space; TA1, TD1, TD2, TD3: Transistors; TE3, TE4, TE5, TE7: External terminals; TL: Cover thickness; TCK, TGND, TOE, TVC, TVDD, TXA, TXB: Terminals; VDD: Power supply voltage; VG, VR1, VRB, VREF, VRn, VS1, VS2, VS(2N), VS(2N+1): Reference voltage; VCP: Temperature compensation voltage; VREG: Adjustable power supply voltage; VT: Temperature detection voltage. Detailed Implementation

[0027] The following describes this embodiment. It should be noted that the following description of this embodiment does not unduly limit the scope of the claims. Furthermore, the structures described in this embodiment are not necessarily all essential structural elements. Additionally, for ease of explanation, some structural elements are sometimes omitted in the following figures. Furthermore, for ease of understanding, the dimensional ratios of the structural elements in the figures differ from the actual dimensions.

[0028] Figure 1 This is a cross-sectional view showing a structural example of the vibration device 1 according to this embodiment. Figure 1 As shown, the vibration device 1 of this embodiment includes a base 2, a vibration element 5, and external connection terminals 91 and 92. Furthermore, the vibration device 1 may include a cover 7 and a reconfigured wiring layer 8. The base 2 includes a semiconductor substrate 20 and a through electrode 40. The semiconductor substrate 20 has a first surface 21 and a second surface 22 opposite to the first surface 21. The first surface 21 is, for example, the upper surface of the semiconductor substrate 20, and the second surface 22 is, for example, the lower surface of the semiconductor substrate 20. The through electrode 40 is an electrode that penetrates the first surface 21 and the second surface 22 of the semiconductor substrate 20. The vibration element 5 is disposed on the first surface 21 side of the semiconductor substrate 20. For example, the vibration element 5 is disposed at a position separated from the first surface 21 of the semiconductor substrate 20 by a given separation distance. Specifically, the vibration element 5 is fixed to the first surface 21 of the semiconductor substrate 20, for example, via a conductive bonding member 60. The external connection terminals 91 and 92 are disposed on the second surface 22 side of the semiconductor substrate 20 via an insulating layer 80 or the like. Insulating layer 80 is, for example, the insulating layer that constitutes the reconfiguration wiring layer 8.

[0029] Furthermore, in the figures described in this embodiment, the X-axis, Y-axis, and Z-axis are illustrated as three mutually orthogonal axes. The direction along the X-axis is referred to as the "X-axis direction," the direction along the Y-axis as the "Y-axis direction," and the direction along the Z-axis as the "Z-axis direction." Additionally, the end of the arrow in each axis direction is referred to as the "positive side," the base side as the "negative side," the positive side of the Z-axis direction as "up," and the negative side of the Z-axis direction as "down." For example, the Z-axis direction is along the vertical direction, and the XY plane is along the horizontal plane. Figure 1 This is a cross-sectional view of the vibrating device 1 taken from the Y-axis direction. Furthermore, the first surface 21 and the second surface 22 of the semiconductor substrate 20 are surfaces along the XY plane, and are orthogonal to the Z-axis. In addition to the case of intersection at 90°, "orthogonal" also includes the case of intersection at an angle slightly inclined relative to 90°.

[0030] Vibration device 1 is, for example, an oscillator. Specifically, vibration device 1 is an oscillator such as a simple packaged quartz oscillator (SPXO), a voltage-controlled quartz oscillator (VCXO), a temperature-compensated quartz oscillator (TCXO), a quartz oscillator with a thermostatic bath (OCXO), a SAW (Surface Acoustic Wave) oscillator, a voltage-controlled SAW oscillator, or a MEMS (Micro Electro Mechanical Systems) oscillator. MEMS oscillators can be implemented using a MEMS vibration element with a piezoelectric film and electrodes disposed on a substrate such as a silicon substrate. However, vibration device 1 can also be an inertial sensor such as an accelerometer or angular velocity sensor, or a force sensor such as a tilt sensor.

[0031] The base 2 is composed of a semiconductor substrate 20. The semiconductor substrate 20 is, for example, a silicon substrate. In addition, the semiconductor substrate 20 is not limited to a silicon substrate, but may also be a semiconductor substrate of Ge, GaP, GaAs, InP, etc. However, it is preferable that the relationship with the cover 7 described later can be taken into account.

[0032] Furthermore, the base 2 includes an integrated circuit 10. The integrated circuit 10, as a semiconductor circuit, is formed on the second surface 22 of the semiconductor substrate 20. The integrated circuit 10 is composed of multiple circuit elements. These circuit elements are, for example, active elements such as transistors, or passive elements such as capacitors and resistors. Specifically, the integrated circuit 10 is composed of multiple circuit blocks, each containing multiple circuit elements. Furthermore, the integrated circuit 10 is formed from impurity regions (diffusion regions) formed by doping the semiconductor substrate 20 with impurities, and wiring layers formed by stacking metal layers and insulating layers. The source and drain regions of the circuit elements (transistors) of the integrated circuit 10 are formed through the diffusion regions, and wiring connecting the circuit elements is formed through the wiring regions.

[0033] Furthermore, the base 2 includes a through electrode 40. The through electrode 40 is made of a conductive material that penetrates the first surface 21 and the second surface 22 of the semiconductor substrate 20. For example, a through hole is formed in the semiconductor substrate 20, and the through hole is filled with a conductive material, thereby forming the through electrode 40. The conductive material can be a metal such as copper, or a conductive polysilicon such as polysilicon. The conductive polysilicon is, for example, polysilicon that is doped with impurities such as phosphorus (P), boron (B), and arsenic (As) to impart conductivity. When polysilicon is used as the conductive material, a through electrode 40 that is sufficiently resistant to the heat applied during the formation process of the integrated circuit 10 can be achieved.

[0034] One end of the through electrode 40 is electrically connected to the vibrating element 5 via a conductive connecting member 60. Figure 1 In this embodiment, the conductive bonding member 60 is implemented by a bump 62, one end of which is electrically connected to the vibrating element 5 and the other end of which is electrically connected to the through electrode 40. Specifically, the other end of the bump 62 is connected to the through electrode 40 via a terminal 64. The bump 62 is a conductive bump, specifically a metal bump. Alternatively, the conductive bonding member 60 can also be implemented using a conductive adhesive material or the like.

[0035] The other end of the through electrode 40 is electrically connected to the integrated circuit 10. Specifically, the other end of the through electrode 40 is connected to the circuit elements of the integrated circuit 10 via the contact pad 36 formed on the integrated circuit 10. Thus, the vibration element 5 and the integrated circuit 10 can be electrically connected via the through electrode 40.

[0036] The cover 7 is joined to the base 2 via the joining parts JA of the joining parts 71 and 72. Furthermore, the base 2 and the cover 7, which serves as the cover body, form an airtight storage space SP, within which the vibrating element 5 is housed. The storage space SP is airtightly sealed, and for example, it is in a depressurized state. This effectively protects the vibrating element 5 from impacts, dust, heat, or moisture, enabling stable operation. Moreover, the state within the storage space SP is not limited to a depressurized state; for example, the storage space SP can also be in an inert gas environment such as argon or nitrogen.

[0037] Similar to the base 2, the cover 7 can be made of a silicon substrate. Therefore, the base 2 and the cover 7 have the same coefficient of thermal expansion, which can suppress thermal stress caused by thermal expansion. Furthermore, both the base 2 and the cover 7 can be formed using semiconductor manufacturing processes. Therefore, the vibrating device 1 can be manufactured with high precision and its miniaturization can be achieved. Additionally, the cover 7 is not limited to a silicon substrate and can also be made of semiconductor substrates such as Ge, GaP, GaAs, and InP. However, in this embodiment, it is preferable that the cover 7 and the base 2 are made of the same material or have the same coefficient of thermal expansion. "Same" includes substantially the same material.

[0038] A redistributable wiring layer 8 is disposed on the second surface 22 side of the semiconductor substrate 20, and includes an insulating layer 80 and wiring 82 for redistribution wiring. The insulating layer 80 is implemented, for example, with a resin such as polyimide or epoxy glass, and the wiring 82 is implemented, for example, with a metal wiring such as copper foil. The insulating layer 80 needs to have heat resistance to withstand the soldering during the mounting of the vibrating device 1, and polyimide is preferred. In addition to copper, aluminum, silver, and other metal materials can also be used for the wiring 82. Furthermore, the thickness of the wiring layer and terminals in the redistributable wiring layer 8 is, for example, about 10 to 20 μm. By providing the redistributable wiring layer 8, the contact pads 38 and 39 formed on the integrated circuit 10 and the external connection terminals 91 and 92 can be electrically connected. Moreover, by mounting the external connection terminals 91 and 92 of the vibrating device 1 to the terminals and wiring of the circuit board on which the vibrating device 1 is mounted, the vibrating device 1 can be incorporated into an electronic device. Furthermore, by setting up this reconfigured wiring layer 8, mechanical protection can be provided for parts of the integrated circuit 10, and thermal protection can be provided for the integrated circuit 10, etc., so that it is not affected by the heat during the soldering process when the vibration device 1 is installed.

[0039] Figure 2 This is a cross-sectional view showing a specific structural example of the vibrating device 1. Figure 3 This is a top view showing an example of the vibrating element 5 of the vibrating device 1. First, using... Figure 3 The details of the vibrating element 5 are explained below.

[0040] Vibrating element 5 is a component that generates mechanical vibration through electrical signals. For example, such as... Figure 3 As shown, the vibration element 5 has a vibration substrate 50 and electrodes disposed on the surface of the vibration substrate 50. The vibration substrate 50 has a thickness shear vibration mode and, in this embodiment, is formed from an AT-cut quartz substrate. The AT-cut quartz substrate has a three-dimensional frequency-temperature characteristic, thus becoming a vibration element 5 with excellent temperature characteristics. Furthermore, the electrodes have an excitation electrode 52 disposed on the upper surface of the vibration substrate 50 and an excitation electrode 53 disposed on the lower surface opposite to the excitation electrode 52. The upper surface is the surface on the positive side in the Z-axis direction, and the lower surface is the surface on the negative side in the Z-axis direction. Furthermore, one of the excitation electrodes 52 and 53 is a first excitation electrode, and the other of the excitation electrodes 52 and 53 is a second excitation electrode. In addition, the electrodes have a pair of terminals 56 and 57 disposed on the lower surface of the vibration substrate 50, a wiring 54 electrically connecting the terminals 56 and the excitation electrode 52, and a wiring 55 electrically connecting the terminals 57 and the excitation electrode 53.

[0041] Furthermore, the structure of the vibrating element 5 is not limited to the structure described above. For example, the vibrating element 5 may be a mesa type where the vibration region sandwiched by the excitation electrodes 52 and 53 protrudes from its surroundings; conversely, it may be an inverted mesa type where the vibration region is recessed from its surroundings. Additionally, it may be possible to perform bevel machining by grinding around the vibrating substrate 50, or convex machining to make the upper and lower surfaces convex curved surfaces. Furthermore, the vibrating element 5 is not limited to vibrating in a thickness shear vibration mode. For example, the vibrating element 5 may be a tuning fork type vibrating element in which multiple vibrating arms bend in the in-plane direction, a tuning fork type vibrating element in which multiple vibrating arms bend in the out-of-plane direction, a gyroscope sensor element having a driving arm for driving vibration and a detection arm for detecting vibration to detect angular velocity, or an acceleration sensor element having a detection section for detecting acceleration. Furthermore, the vibrating substrate 50 is not limited to being formed from an AT-cut quartz substrate, but may also be formed from quartz substrates other than AT-cut quartz substrates, such as X-cut quartz substrates, Y-cut quartz substrates, Z-cut quartz substrates, BT-cut quartz substrates, SC-cut quartz substrates, ST-cut quartz substrates, etc. In this embodiment, the vibrating substrate 50 is made of quartz, but is not limited to this; for example, it may also be made of piezoelectric single crystals such as lithium niobate, lithium tantalate, lithium tetraborate, potassium niobate, gallium phosphate, etc., or other piezoelectric single crystals. Furthermore, the vibrating element 5 is not limited to a piezoelectrically driven vibrating element, but may also be an electrostatically driven vibrating element using electrostatic force.

[0042] Moreover, such as Figure 2 , Figure 3 As shown, the vibrating element 5 is fixed to the upper surface, i.e., the first surface 21, of the semiconductor substrate 20 via conductive bonding members 60 and 61. Furthermore, in Figure 2 There is no illustration in the text, but, as shown... Figure 3 As shown, for example, two joining parts 60 and 61 are provided along the Y-axis direction. Furthermore, as described later... Figure 10 As shown, two through electrodes 40 and 41 are provided on the semiconductor substrate 20, for example, along the Y-axis direction. These through electrodes 40 and 41 are electrically connected to the vibrating element 5 via conductive bonding members 60 and 61. One of the through electrodes 40 and 41 is a first through electrode, and the other is a second through electrode. Specifically, one end of the through electrode 40 is electrically connected to the excitation electrode 52 of the vibrating element 5 via the bonding member 60, the terminal 56 of the vibrating element 5, and the wiring 54. Furthermore, one end of the through electrode 41 is electrically connected to the excitation electrode 53 of the vibrating element 5 via the bonding member 61, the terminal 57 of the vibrating element 5, and the wiring 55. Moreover, the other end of the through electrodes 40 and 41 is electrically connected to the integrated circuit 10. Thus, the vibrating element 5 and the integrated circuit 10 are electrically connected via the through electrodes 40 and 41. Specifically, the other end of the through electrodes 40 and 41 is connected via... Figure 2 , Figure 10 The contact pads 36 and 37 shown are electrically connected to the oscillation circuit 11 of the integrated circuit 10. Thus, the oscillation element 5 and the oscillation circuit 11 are electrically connected via through electrodes 40 and 41.

[0043] The bonding components 60 and 61 only need to have both conductivity and bonding properties, and there are no particular limitations. For example, they can be implemented using various conductive bumps 62, such as gold bumps, silver bumps, copper bumps, solder bumps, and resin core bumps. Alternatively, conductive adhesives, such as those made by dispersing conductive fillers such as silver fillers in various adhesives based on polyimide, epoxy, silicone, or acrylic, can also be used as bonding components 60 and 61.

[0044] Furthermore, after forming the through-hole, the semiconductor substrate 20 is thermally oxidized, thereby forming an insulating film, i.e., an insulating layer 44, made of, for example, silicon oxide (SiO2), on the first surface 21 of the semiconductor substrate 20 and the inner surface of the through-hole. By forming the insulating layer 44 through thermal oxidation, a dense and homogeneous insulating layer 44 can be formed on the surface of the semiconductor substrate 20. Furthermore, the difference in the coefficients of linear expansion between the insulating layer 44 and the semiconductor substrate 20 can be reduced. Therefore, a vibrating device 1 that is less prone to thermal stress and has excellent oscillation characteristics can be realized. The material constituting the insulating layer 44 is not particularly limited; for example, it can be made of silicon nitride (SiN) or resin. Furthermore, the method of forming the insulating layer 44 is not limited to thermal oxidation; for example, it can also be formed by CVD (Chemical Vapor Deposition).

[0045] Furthermore, conductive materials such as copper or conductive polysilicon are filled inside the insulating layer 44 of the through-hole to form through electrodes 40 and 41. That is, conductive materials are used to fill the through-hole to form through electrodes 40 and 41. One end of the through electrodes 40 and 41 is electrically connected to the vibrating element 5. Specifically, one end of the through electrodes 40 and 41 is electrically connected to the excitation electrodes 52 and 53 of the vibrating element 5. On the other hand, the other end of the through electrodes 40 and 41 is electrically connected to the integrated circuit 10. Specifically, the other end of the through electrodes 40 and 41 is electrically connected to the oscillation circuit 11 of the integrated circuit 10 via contact pads 36 and 37.

[0046] like Figure 2As shown, the integrated circuit 10 is composed, for example, of an N-type transistor 23 or a P-type transistor 24. These transistors 23 and 24 are formed from a diffusion region (source and drain regions), a gate electrode, and a gate oxide film formed on the semiconductor substrate 20. Furthermore, the transistors 23 and 24 are separated by a device separation film 25 called LOCOS (Local Oxidation of Silicon). In addition, the integrated circuit 10 includes a wiring layer 30 that implements the interconnections between multiple circuit elements such as transistors 23 and 24. For example, Figure 2 The wiring layer 30 includes metal layers 31 and 32, and insulating layers 33, 34, and 35. Metal layers 31 and 32 are the first and second metal layers, respectively, and insulating layers 33, 34, and 35 are the first, second, and third insulating layers, respectively. Metal layer 31 is formed between insulating layers 33 and 34, and metal layer 32 is formed between insulating layers 34 and 35. These metal layers 31 and 32 are implemented using metals such as aluminum or copper. Furthermore, metal layers 31 and 32 are electrically connected through contacts called via contacts, and metal layer 31 is electrically connected to the source and drain regions of transistors 23 and 24 through these contacts. Moreover, as... Figure 2 As shown, the contact pads 36 electrically connected to the other ends of the through electrodes 40 and 41 are formed by the lower metal layer 31. Furthermore, the contact pads 38 and 39 electrically connected to the external connection terminals 91 and 92 are formed by the upper metal layer 32. Additionally, in the wiring layer 30, the layer closest to transistors 23 and 24 in the integrated circuit 10 is designated as the lower layer, and the layer furthest from transistors 23 and 24 is designated as the upper layer. Furthermore, in... Figure 2 The diagram shows a wiring layer 30 with two metal layers 31 and 32. However, this embodiment is not limited to this, and the wiring layer 30 may also have three or more metal layers. In this case, contact pads 36 and 37 are formed by the lowest metal layer among the multiple metal layers, and contact pads 38 and 39 are formed by the highest metal layer. Furthermore, a passivation film is formed by the highest insulating layer 35, which is made of an insulating resin such as polyimide.

[0047] Furthermore, the reconfigured wiring layer 8 includes an insulating layer 80 implemented with resin layers such as polyimide and epoxy glass, and wiring 82 implemented with copper foil, etc. Moreover, the contact pad 38 is electrically connected to the external connection terminal 91, and the contact pad 39 is electrically connected to the external connection terminal 92 via the wiring 82.

[0048] In addition, Figure 2In this configuration, external connection terminals 91 and 92 are respectively constructed with a first metal layer 84 and a second metal layer 86. The first metal layer 84, serving as the side of the insulating layer 80, is, for example, a titanium-tungsten layer to improve the tightness of contact with the insulating layer 80. The second metal layer 86 is, for example, a metal layer such as copper or gold that is easy to solder to external terminals or wiring.

[0049] Figure 4 An example of the structure of the integrated circuit 10 of this embodiment is shown. The integrated circuit 10 of this embodiment may include terminals TXA, TXB, TCK, TVDD, TGND, TOE, an oscillation circuit 11, an output circuit 12, a control circuit 13, a reference voltage generation circuit 14A, a regulator circuit 14B, a temperature compensation circuit 15, a temperature sensor 16, and a storage unit 17. Furthermore, the vibration device 1 of this embodiment includes a vibration element 5 and the integrated circuit 10. The oscillation circuit 11 is a circuit that oscillates the vibration element 5. For example, the oscillation circuit 11 is electrically connected to terminals TXA and TXB to cause the vibration element 5 to oscillate, thereby generating an oscillation signal OSC. For example, the oscillation circuit 11 drives the vibration element 5 via wiring LA and wiring LB connected to terminals TXA and TXB, causing the vibration element 5 to oscillate. For example, the oscillation circuit 11 includes an oscillation drive circuit disposed between terminals TXA and TXB. Further details are available using… Figure 11 As will be described later, however, the oscillation circuit 11 can be implemented using transistors such as bipolar transistors that implement the drive circuit 132, as well as passive components such as capacitors and resistors. The drive circuit 132 is the core circuit of the oscillation circuit 11; it drives the vibrating element 5 with current or voltage, thereby causing the vibrating element 5 to oscillate. The oscillation circuit 11 can, for example, use various types of oscillation circuits such as Pierce type, Colpitts type, Inverter type, or Hartley type. Further details will be provided using… Figure 11 As will be described later, a variable capacitor circuit or the like can also be provided in the oscillation circuit 11, and the oscillation frequency can be adjusted by adjusting the capacitance of the variable capacitor circuit. More specifically, the oscillation circuit 11 may also have a first variable capacitor circuit 136 electrically connected to the wiring LA connected to the terminal TXA, and a second variable capacitor circuit 137 electrically connected to the wiring LB connected to the terminal TXB. In addition, the connection in this embodiment is an electrical connection. An electrical connection is a connection that can transmit electrical signals, and is a connection that can transmit information using electrical signals. An electrical connection may also be a connection via passive components or the like.

[0050] Output circuit 12 outputs clock signal CK based on the oscillation signal OSC from oscillation circuit 11. For example, output circuit 12 buffers the oscillation signal OSC from oscillation circuit 11 and outputs clock signal CK. For example, output circuit 12 can also perform waveform shaping of oscillation signal OSC, voltage level shifting, etc. The signal form of the clock signal output by output circuit 12 can be, for example, single-ended CMOS, clipped sine wave, etc., but is not limited to these. For example, it can also be LVDS (Low Voltage Differential Signaling), PECL (Positive Emitter Coupled Logic), HCSL (High Speed ​​Current Steering Logic), or differential CMOS (Complementary MOS), etc.

[0051] The control circuit 13 performs various control processes. For example, the control circuit 13 controls the overall operation of the integrated circuit 10. For example, the control circuit 13 controls the operating sequence of the integrated circuit 10. In addition, the control circuit 13 performs various processes for controlling the oscillation circuit 11. Furthermore, the control circuit 13 can also control the output circuit 12, etc. The control circuit 13 can be implemented, for example, using an ASIC (Application Specific Integrated Circuit) circuit based on automatic configuration routing, such as a gate array.

[0052] Temperature sensor 16 is a sensor for detecting temperature. Specifically, temperature sensor 16 outputs a temperature-dependent voltage, VT, which varies according to the ambient temperature. For example, temperature sensor 16 generates the temperature detection voltage VT using temperature-dependent circuit elements. Specifically, temperature sensor 16 uses the temperature dependence of the forward voltage of a PN junction to output a temperature detection voltage VT whose voltage value varies with temperature. The forward voltage of the PN junction can be, for example, the base / emitter voltage of a bipolar transistor.

[0053] The temperature compensation circuit 15 performs temperature compensation for the oscillation frequency of the oscillation circuit 11. For example, the temperature compensation circuit 15 generates a temperature compensation voltage VCP based on the temperature detection voltage VT from the temperature sensor 16, and outputs the temperature compensation voltage VCP to the oscillation circuit 11, thereby performing temperature compensation for the oscillation frequency of the oscillation circuit 11. For example, the temperature compensation circuit 15 outputs the temperature compensation voltage VCP, which becomes the capacitor control voltage of the variable capacitor circuit in the oscillation circuit 11, thereby performing temperature compensation. Temperature compensation is a process that compensates for changes in the oscillation frequency caused by temperature variations.

[0054] For example, the temperature compensation circuit 15 performs analog temperature compensation based on polynomial approximation. For instance, when the temperature compensation voltage VCP, which compensates for the frequency-temperature characteristics of the vibrating element 5, is approximated by a polynomial, the temperature compensation circuit 15 performs analog temperature compensation based on the coefficient information of that polynomial. Analog temperature compensation is achieved, for example, by adding analog signals, such as current signals and voltage signals. For instance, when the temperature compensation voltage VCP is approximated by a high-order polynomial, the 0th-order coefficient, 1st-order coefficient, and high-order coefficients of the polynomial are stored in the storage unit 17 as 0th-order correction data, 1st-order correction data, and high-order correction data, respectively. For example, the storage unit 17 is implemented using non-volatile memory. High-order coefficients are, for example, coefficients of orders greater than 1st order, and high-order correction data are correction data corresponding to the high-order coefficients. For example, when the temperature compensation voltage VCP is approximated by a fifth-order polynomial, the 0th, 1st, 2nd, 3rd, 4th, and 5th-order coefficients of the polynomial are stored in the storage unit 17 as 0th-order correction data, 1st-order correction data, 2nd-order correction data, 3rd-order correction data, 4th-order correction data, and 5th-order correction data.

[0055] Then, the temperature compensation circuit 15 performs temperature compensation based on the 0th to 5th order correction data. Alternatively, temperature compensation based on the 2nd or 4th order correction data can be omitted. Furthermore, the degree of the polynomial approximation is arbitrary; for example, a 3rd order polynomial approximation or a polynomial approximation of a degree greater than 5 can be performed. Additionally, the temperature sensor 16 can also be calibrated to the 0th order. Alternatively, the temperature sensor 16 can be omitted from the integrated circuit 10, and the temperature compensation circuit 15 performs temperature compensation based on temperature detection signals such as temperature detection voltage input from an external source.

[0056] Alternatively, the temperature compensation circuit 15 can also perform temperature compensation digitally. In this case, the temperature compensation circuit 15 is implemented, for example, by a logic circuit. Specifically, the temperature compensation circuit 15 performs digital temperature compensation processing based on the temperature detection information, i.e., temperature detection data, from the temperature sensor 16. For example, the temperature compensation circuit 15 calculates frequency adjustment data based on the temperature detection data. Then, the capacitance value of the variable capacitor circuit of the oscillation circuit 11 is adjusted according to the calculated frequency adjustment data, thereby achieving temperature compensation processing of the oscillation frequency of the oscillation circuit 11. In this case, the variable capacitor circuit of the oscillation circuit 11 is implemented by a capacitor array having multiple capacitors weighted in a binary manner and a switch array. Furthermore, the storage unit 17 stores a lookup table representing the correspondence between the temperature detection data and the frequency adjustment data, and the temperature compensation circuit 15 uses the lookup table read from the storage unit 17 by the control circuit 13 to perform temperature compensation processing to calculate the frequency adjustment data based on the temperature data.

[0057] In addition, when performing digital temperature compensation processing, the temperature sensor 16 measures the ambient temperature and other temperatures, and outputs the result as temperature detection data. The temperature detection data is data that increases or decreases monotonically relative to temperature, for example. As the temperature sensor 16 in this case, a temperature sensor utilizing the temperature-dependent characteristics of the oscillation frequency of a ring oscillator can be used. Specifically, the temperature sensor 16 includes a ring oscillator and a counter circuit. The counter circuit counts the oscillation signal of the ring oscillator, i.e., the output pulse signal, during a counting period defined by a clock signal based on the oscillation signal OSC from the oscillation circuit 11, and outputs its count value as temperature detection data.

[0058] Control circuit 13 controls temperature compensation circuit 15. Furthermore, control circuit 13 can also control oscillation circuit 11, output circuit 12, regulator circuit 14B, or storage unit 17. For example, control circuit 13 has a register; at the start of normal operation, when the oscillating element 5 oscillates and outputs clock signal CK, information stored in storage unit 17 is read and transferred to the register of control circuit 13 for storage. Then, various control signals are generated based on the information stored in the register and output to each circuit of integrated circuit 10 to control each circuit. Therefore, during normal operation, control circuit 13 does not need to perform high-speed operation, thus reducing the noise generated by control circuit 13. Additionally, integrated circuit 10 may have a first mode with temperature compensation enabled and a second mode with temperature compensation disabled. In this case, control circuit 13 can switch between the first and second modes.

[0059] The reference voltage generation circuit 14A generates a reference voltage VREF based on the power supply voltage VDD. For example, it generates a reference voltage VREF that remains constant even when there are fluctuations in the power supply voltage or temperature. The reference voltage generation circuit 14A can be implemented, for example, by a bandgap reference circuit that generates the reference voltage VREF based on the bandgap voltage.

[0060] The regulator circuit 14B generates an adjustable power supply voltage based on the power supply voltage VDD. For example, the regulator circuit 14B generates the adjustable power supply voltage based on the power supply voltage VDD from terminal TVDD and the reference voltage VREF from the reference voltage generation circuit 14A. By using the reference voltage VREF, which remains constant even in the presence of power supply voltage fluctuations and temperature variations, an adjustable power supply voltage that is stepped down from the power supply voltage VDD can be generated, i.e., a constant voltage even in the presence of power supply voltage fluctuations and temperature variations. The regulator circuit 14B then supplies the generated adjustable power supply voltage to each circuit block of the integrated circuit 10. In this case, the regulator circuit 14B, for example, makes the voltage values ​​of the adjustable voltage supplied to the temperature compensation circuit 15 different from those supplied to the control circuit 13, supplying an appropriate adjustable power supply voltage corresponding to each circuit block.

[0061] The output enable signal OE is input to the terminal TOE. The terminal TOE is electrically connected to the external terminal TE7 of the vibrating device 1. The control circuit 13 performs output enable control processing based on the output enable signal OE input from the terminal TOE. Additionally, in test mode, a test signal for the vibrating element 5 can also be input via the terminal TOE. In this case, a switching circuit is provided to connect the terminal TOE and the wiring LA, and the test signal input from the terminal TOE is input to one end of the vibrating element 5 via the switching circuit and the wiring LA. This allows for testing and inspection of the vibrating element 5, such as overdrive. Furthermore, if the storage unit 17 is implemented using non-volatile memory, when writing information to the non-volatile memory, a high voltage for memory writing can be input via the terminal TOE and supplied to the storage unit 17, i.e., the non-volatile memory.

[0062] The storage unit 17 is a circuit that stores various types of information and can be implemented using a semiconductor memory or the like. Specifically, the storage unit 17 can be implemented using a non-volatile memory. Examples of non-volatile memories include electrically erasable EEPROMs (Electrically Erasable Programmable Read-Only Memory) and OTP (One-Time Programmable) memories using FAMOS (Floating Gate Avalanche Injection MOS). Alternatively, the non-volatile memory can also be a memory using fuse cells. When the temperature compensation circuit 15 performs temperature compensation based on a polynomial approximation, the storage unit 17, implemented using a non-volatile memory or the like, stores the coefficient information of the polynomial approximation. For example, the storage unit 17 stores the aforementioned 0th-order correction data, 1st-order correction data, and higher-order correction data as the coefficient information of the polynomial approximation. This coefficient information is written into the storage unit 17, implemented using a non-volatile memory or the like, and stored, for example, during the manufacturing of the integrated circuit 10 and the vibration device 1, or at the time of shipment. Therefore, the temperature compensation coefficient information can be set according to the model of the integrated circuit 10 and the vibration device 1.

[0063] Next, the manufacturing method of the vibration device 1 according to this embodiment will be described. Although process diagrams are omitted, the vibration device 1 can be manufactured, for example, by the following method. First, a wafer-shaped semiconductor substrate 20 with a standard thickness is prepared. Specifically, the standard thickness is 625–775 μm. This allows for stable processing of the semiconductor substrate 20 during the manufacturing process of the integrated circuit 10. Then, the integrated circuit 10 is formed on the lower surface, i.e., the second surface 22. The thickness of the integrated circuit 10 is 5–20 μm. Then, a redistribution wiring layer 8 having an insulating layer 80 and wiring 82, as well as external connection terminals 91, 92, are formed on the second surface 22, electrically connecting the contact pads 38, 39, etc. of the integrated circuit 10 to the external connection terminals 91, 92, etc. The thickness of the redistribution wiring layer 8 is 10–20 μm. Then, the side of the semiconductor substrate 20 on which the vibration element 5 is mounted, i.e., the first surface 21, is ground using a back-side grinder or the like. That is, the thickness of the base 2 is reduced to a predetermined thickness. The specified thickness is the thickness that allows for the formation of the vias described later by dry etching, specifically 20 μm to 100 μm. Then, the desired area of ​​the substrate 2 is removed from the first surface 21 side by dry etching. Next, the desired area of ​​the element separation film 25 is removed by wet etching. This forms a via through the metal layer 31 extending from the first surface 21 to the wiring layer 30. Then, an insulating film, i.e., an insulating layer 44, is formed on the surface of the semiconductor substrate 20, particularly on the inner surface of the via. Then, a conductive material such as copper is used to fill the via, thereby forming through electrodes 40 and 41. Then, a vibrating element 5 is prepared and bonded to the first surface 21 of the semiconductor substrate 20 via bonding members 60 and 61. Then, a wafer of the same size as the semiconductor substrate 20 with a cover 7 is prepared. Then, under reduced pressure, the wafer containing the substrate 2 and the wafer containing the cover 7 are bonded via bonding members 71 and 72. Then, the bonded wafer is cut using a dicing machine or the like, thereby monolithizing the vibrating device 1. Thus, the vibrating device 1, which includes the vibrating element 5 and the integrated circuit 10, can be manufactured simultaneously through wafer-level batch processing, enabling the production of vibrating devices 1 with high output and low cost. That is, the vibrating device 1 in this embodiment is a WLP (Wafer Level Package).

[0064] Furthermore, the above description is a structural example of the vibration device 1 in which the integrated circuit 10 is formed on the second surface 22. However, this embodiment is not limited to this and various modified embodiments are possible. For example, such as Figure 5As shown, a vibrating device 101 may also be configured to form an integrated circuit 110 on the first surface 121. The vibrating device 101 includes a base 102, a vibrating element 105, and external connection terminals 191 and 192. Furthermore, the vibrating device 101 may include a redistribution wiring layer 108. The base 102 includes through electrodes 140 and 141. The vibrating element 105 is disposed on the first surface 121 side. For example, the vibrating element 105 is disposed at a position separated from the first surface 121 by a given separation distance. The vibrating element 105 is fixed to the first surface 121, for example, via a conductive bonding member 160. The external connection terminals 191 and 192 are disposed on the second surface 122 side via an insulating layer 180, wiring 182, etc. The insulating layer 180 is an insulating layer constituting the redistribution wiring layer 108. They can be formed by appropriately using the method described above.

[0065] Furthermore, the vibrating device 101 may include a cover 107. A third metal layer 171, 172 is provided on the first surface 121. The third metal layer 171, 172 is, for example, gold with a thickness of 100 nm, but may also be a metal such as copper. A fourth metal layer 173, 174 is provided on the surface of the cover 107 that abuts against the third metal layer 171, 172. The fourth metal layer 173, 174 is, for example, gold with a thickness of 20 nm, but may also be a metal such as copper. The third metal layer 171, 172 and the fourth metal layer 173, 174 are joined by activated bonding, thereby joining the cover 107 to the first surface 121. The activation bonding is performed as follows: after activating the surfaces of the third metal layers 171, 172 and the fourth metal layers 173, 174 by irradiating them with a neutral argon ion beam or the like, bonding is achieved by bringing the third metal layers 171, 172 and the fourth metal layers 173, 174 into contact. This allows bonding of the third metal layers 171, 172 and the fourth metal layers 173, 174 at room temperature without the need for pressure. Furthermore, a fifth metal layer 176 can be further formed on the bottom surface of the recess in the cover 107. Additionally, a sixth metal layer 177, 178 can be further formed on the side surface of the recess in the cover 107. The fifth metal layer 176 and the sixth metal layers 177, 178 are, for example, gold with a thickness of 20 nm, but can also be metals such as copper. Therefore, the fifth metal layer 176 and the sixth metal layers 177 and 178 can act as shielding layers to protect the integrated circuit 110 and the vibrating element 105 from external interference such as unnecessary radiation. Furthermore, by making the thickness of the fifth metal layer 176 and the sixth metal layers 177 and 178 approximately 20 nm, infrared light can pass through. Thus, for example, by making the cover 107 made of silicon, infrared light can be used to inspect the vibrating element 105 inside the vibrating device 101. Additionally, although not shown in the figure, a close-fitting layer of titanium or the like can be formed between the third metal layers 171 and 172, the fourth metal layers 173 and 174, the fifth metal layer 176, and the sixth metal layers 177 and 178 and the cover 107.

[0066] As described above, the vibration device 1 of this embodiment includes a semiconductor substrate 20, a base 2, a vibration element 5, and a cover 7. The semiconductor substrate 20 has a first surface 21 and a second surface 22 opposite to the first surface 21. The base 2 includes an integrated circuit 10 disposed on either the first surface 21 or the second surface 22. The vibration element 5 is electrically connected to the integrated circuit 10 and is disposed on the first surface 21 side. The cover 7 is engaged with the base 2 at the joint JA of the base 2 to accommodate the vibration element 5. Furthermore, the case where the integrated circuit 10 is disposed on either the first surface 21 or the second surface 22 includes the case where the integrated circuit 10 is disposed on both the first surface 21 and the second surface 22.

[0067] The following specific problems arise in the WLP such as the vibration device 1 of this embodiment. Figure 6 The effect of stress generated in the vibration device 1 of this embodiment is schematically shown. Additionally, in Figure 6 For simplicity, illustrations of the vibrating element 5, external connection terminals 91, 92, etc., are omitted. The coefficients of thermal expansion of the materials constituting the device differ, thus stress is applied through encapsulation. For example, the coefficient of thermal expansion of silicon, the material of the base 2, is approximately 3 ppm / K, while that of copper, the wiring material, is approximately 17 ppm / K. Therefore, during the manufacturing process, the thermal shrinkage of the integrated circuit 10 and the redistribution wiring layer 8 is greater than that of the base 2, resulting in stress based on the difference in thermal shrinkage. At this time, if the thickness of the base 2 is the standard thickness, it is much thicker than the thickness of the integrated circuit 10 and the redistribution wiring layer 8; therefore, even with applied stress, the base 2 will not deform and will maintain flatness. However, as described above, during the manufacturing process, the base 2 is thinned to 20 μm to 100 μm; therefore, the base 2 loses rigidity, and the effect of stress cannot be ignored. Specifically, as shown in B3, the base 2, integrated circuit 10, and redistribution wiring layer 8 cannot maintain flatness and warp. This causes distortion in the passive and active components constituting the integrated circuit 10, affecting their characteristics. However, detailed information can be obtained by utilizing... Figure 7 , Figure 8 , Figure 9 This will be discussed later. Additionally, this issue may arise when the package is soldered onto an external circuit board, and when an underfill is used to secure the package and the circuit board. On the other hand, Figure 6 The regions shown in A1 and A2 are the areas that join with the cover 7, i.e., the areas containing the joint JA. Assuming that both the base 2 and the cover 7 are made of silicon, their coefficients of thermal expansion are the same. Therefore, in the regions shown in A1 and A2, the thickness of the base 2 plus the cover thickness TL is essentially the thickness of the base 2. That is, compared to the region shown in A3, the regions shown in A1 and A2 are equivalent to forming the integrated circuit 10 and the reconfigured wiring layer 8 on the more rigid base 2. Therefore, as shown in B1 and B2, the regions shown in A1 and A2, i.e., the regions containing the joint JA, are flat or have minimal warping.

[0068] Figure 7The structure of the resistor R in this embodiment is schematically shown. When the resistor R is a cuboid with length RL, width RW, and thickness RT, its resistance value is (ρ×RL) / (RW×RT). Here, ρ is the resistivity. Furthermore, due to the influence of stress, the resistor R deforms into a cuboid with length (RL+ΔRL), width (RW+ΔRW), and thickness (RT+ΔRT), thus changing its resistance value. The specific effects on the integrated circuit 10 caused by the change in the resistance value of the resistor R will be described later.

[0069] Figure 8 A schematic example of the construction of capacitor C according to this embodiment is shown. Capacitor C includes conductor layers 210A and 210B, and an insulating layer 220 between conductor layers 210A and 210B. When the length of conductor layers 210A and 210B is CL, the width is CW, and the thickness of the insulating layer 220 is CD, the electrostatic capacitance of capacitor C is (ε × CL × CW) / CD. ε is the dielectric constant. Furthermore, due to the influence of stress, the length of conductor layers 210A and 210B changes to (CL + ΔCL), and the width changes to (CW + ΔCW). In addition, the thickness of the insulating layer 220 changes to (CD + ΔCD). Therefore, the electrostatic capacitance of capacitor C changes. The specific effects on the circuit caused by the change in the electrostatic capacitance of capacitor C will be described later.

[0070] Figure 9 A schematic example of the construction of the bipolar transistor BP according to this embodiment is shown. When stress is applied to the bipolar transistor BP, a crystal defect 232 is generated in the base region 230 of the bipolar transistor BP. As a result, the leakage recombination current increases, and the characteristics of the bipolar transistor BP change.

[0071] Figure 10 This is a top view showing an example of the configuration of the through electrodes 40, 41, terminals TCK, TGND, TOE, TVC, TVDD, TXA, TXB, and integrated circuit 10 in the vibration device 1 of this embodiment. Figure 10 The diagram shows the relationship between the arrangement of each circuit of integrated circuit 10 and the arrangement of through electrodes 40, 41, terminals TCK, TGND, TOE, TVC, TVDD, TXA, and TXB. Figure 10 This is a top view of the base 2 viewed from the negative side of the Z-axis. The outlines of the through electrodes 40 and 41 located on the positive side of the Z-axis relative to the base 2 where the integrated circuit 10 is formed are shown by dashed lines. Furthermore, the inner wall line 9L of the cover 7, indicating the position of the inner wall portion 9, is shown by dashed lines. That is, the area between the inner wall line 9L and the outer perimeter line 2L of the base corresponds to the aforementioned joint JA.

[0072] In addition, Figure 10In the diagram, the area enclosed by the product area line 3L is the product area, and the area between the product area line 3L and the base outer perimeter line 2L, which represents the outer perimeter of the base 2, is the scribing area. The scribing area is where accessory patterns are arranged; furthermore, it is also the cutting area used for monolithic assembly from the wafer into individual vibrating devices 1. The accessory patterns are patterns composed of evaluation elements for verifying the electrical characteristics of components, electrode pads for supplying power to these evaluation elements, etc.

[0073] A protective ring 27 is formed around the perimeter of the product area, surrounding the integrated circuit 10. The protective ring 27 is formed, for example, by... Figure 2 The metal layers 31 and 32, and insulating layers 33 and 34 of the wiring layer 30 are formed by creating dummy metal layers and making them in contact to prevent moisture and other substances from entering from the outside. This protects the entire integrated circuit 10. Furthermore, the protective ring 27 is not limited to... Figure 10 There could be two sticks, or one stick, or even three or more sticks.

[0074] Furthermore, in this embodiment, such as Figure 10 As shown, the base 2 has a first side SD1 and a second side SD2 opposite to the first side SD1. That is, the integrated circuit 10 has a first side SD1 and a second side SD2 opposite to the first side SD1. In addition, the base 2 has a third side SD3 and a fourth side SD4 opposite to the third side SD3. For example, in top view, the base 2 is a rectangular shape with the first side SD1, the second side SD2, the third side SD3, and the fourth side SD4. In addition, the rectangular shape does not need to be a strict rectangle; for example, it can also be a shape with chamfered corners.

[0075] As described above, the vibration device 1 of this embodiment includes: a base 2, which includes a semiconductor substrate 20 and a through electrode 40 penetrating between a first surface 21 and a second surface 22 of the semiconductor substrate 20; and a vibration element 5, which is disposed on the first surface 21 side of the semiconductor substrate 20. Furthermore, as... Figure 10 As shown, an oscillation circuit 11 is disposed on the second surface 22 of the semiconductor substrate 20. This oscillation circuit is electrically connected to the vibrating element 5 via through electrodes 40 and 41, causing the vibrating element 5 to oscillate and generate an oscillation signal OSC. An output circuit 12 outputs a clock signal CK based on the oscillation signal OSC. For example, the oscillation circuit 11 causes the vibrating element 5 to oscillate, thereby generating the oscillation signal OSC. The output circuit 12 buffers the oscillation signal OSC and outputs it as the clock signal CK. Furthermore, the clock signal CK from the output circuit 12 is output from the external connection terminal 91. That is, from... Figure 4 The clock signal CK of the output circuit 12 is output from the terminal TCK implemented by the contact pad 38.

[0076] In the vibration device 1 of this embodiment, the integrated circuit 10 includes a passive element, which is configured such that, when viewed from a direction orthogonal to the first surface 21, at least a portion of the passive element overlaps with the joint JA. Further details are available using… Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 16 As will be described later, however, the oscillation circuit 11, the reference voltage generation circuit 14A, the regulator circuit 14B, the temperature compensation circuit 15, and the temperature sensor 16 include resistors or capacitors as passive components. Figure 6 The stress in the area not overlapping with the joint JA is significantly affected. Specifically, when a passive element exists in the area not overlapping with the joint JA, it deforms due to stress, causing its characteristics to deviate from the designed characteristics. Therefore, arranging the oscillation circuit 11, reference voltage generation circuit 14A, regulator circuit 14B, temperature compensation circuit 15, and temperature sensor 16 in the area not overlapping with the joint JA results in a circuit containing passive elements, thus affecting the characteristics of the vibration device 1. In this respect, the vibration device 1 of this embodiment is configured such that the oscillation circuit 11, reference voltage generation circuit 14A, regulator circuit 14B, temperature compensation circuit 15, and temperature sensor 16 overlap with the joint JA. By arranging the passive element in the area overlapping with the joint JA, and in an area with less stress influence, the deformation of the passive element can be minimized. This allows for the stabilization of the passive element's characteristics. Consequently, the oscillation characteristics of the packaged vibration device 1 can be stabilized.

[0077] Furthermore, the passive component in this embodiment is at least one of a capacitor or a resistor. For example, as described later. Figure 12 The reference voltage generation circuit 14A includes resistive elements, namely resistors RD1 to RD3. Furthermore, for example, as described later... Figure 13 The regulator circuit 14B includes resistive elements, namely resistors RD1 to RD3, and a capacitive element, namely capacitor CA. Therefore, deformation of these resistors and capacitors can be suppressed. Therefore, changes in the capacitance of the capacitor or the resistance value of the resistor can be suppressed. Therefore, changes in the oscillation frequency of the vibrating device 1 can be suppressed.

[0078] Furthermore, the capacitor element in this embodiment is at least one of a MIM (Metal-Insulator-Metal) capacitor, a PIP (Polysilicon-Insulator-Polysilicon) capacitor, or a MOS (Metal-Oxide-Semiconductor) capacitor. In the vibration device 1, a MIM capacitor or a PIP capacitor is used to obtain a larger capacitance. Furthermore, to compensate for temperature variations in the oscillation frequency, a MOS capacitor is used as a variable capacitance element whose capacitance value changes according to the applied voltage. That is, these capacitors are generally widely used in the vibration device 1. By applying the method of this embodiment, these capacitors are positioned in locations with minimal stress influence, thereby suppressing deformation of these capacitors. This suppresses changes in the capacitance of these capacitors. Consequently, it suppresses changes in the oscillation frequency of the vibration device.

[0079] Furthermore, in this embodiment, when viewed from above, the control circuit 13 and the storage unit 17 are disposed inside the inner wall line 9L of the cover. That is, the integrated circuit 10 includes a predetermined circuit disposed in a region that does not overlap with the joint JA when viewed from above, and the predetermined circuit includes at least one of the control circuit 13 or the memory circuit, i.e., the storage unit 17. For example, for the portion of the signal in the control circuit 13 where the high and low levels are fixed, the effect of stress is very small, and therefore, the effect of stress on the oscillation frequency of the vibrating device is small. Therefore, disposing the control circuit 13, etc., at a position overlapping with the joint JA reduces the scope for disposing circuits with a large stress influence at the position overlapping with the joint JA. Therefore, by disposing the control circuit 13 and the storage unit 17, which have fewer obstacles due to stress, at a position where the stress influence is large, it is possible to increase the scope for disposing circuits with a large stress influence at a position where the stress influence is small.

[0080] Furthermore, in this embodiment, such as Figure 10As shown, in top view, the oscillation circuit 11 is positioned closer to the first side SD1 than the second side SD2. Specifically, in top view, the oscillation circuit 11 is positioned between the first side SD1 and the through electrodes 40 and 41. That is, the oscillation circuit 11 is positioned in the region between the first side SD1 and the line connecting the through electrodes 40 and 41. For example, the oscillation circuit 11 is positioned along the first side SD1, with its length direction along the first side SD1. Moreover, the oscillation circuit 11 is electrically connected to the vibration element 5 via wirings LA and LB, and terminals TXA and TXB implemented by contact pads 36 and 37, causing the vibration element 5 to oscillate. For example, the circuit elements constituting the oscillation circuit 11, such as transistors, capacitors, and resistors, have conductive layers such as metal layers and diffusion layers that have an area when viewed from top view. Therefore, because the conductive layer in the oscillation circuit 11 is capacitively coupled to the external connection terminal 91, the signal component of the clock signal CK output from the external connection terminal 91 is transmitted to the oscillation circuit 11 as noise, which may have an adverse effect on the oscillation characteristics. In this respect, in this embodiment, the oscillation circuit 11 is positioned close to the first side SD1 when viewed from above, thus increasing the distance between it and the external connection terminal 91, which is positioned close to the second side SD2 when viewed from above. Therefore, the capacitance of the capacitive coupling between the oscillation circuit 11 and the external connection terminal 91 can be reduced, thereby suppressing the degradation of the oscillation characteristics of the oscillation circuit 11.

[0081] Figure 11 An example of the structure of the oscillation circuit 11 is shown. The oscillation circuit 11 includes a drive circuit 132, capacitors C1 and C2 for DC cutoff, a reference voltage supply circuit 134, and a first variable capacitor circuit 136. Furthermore, the oscillation circuit 11 may include a capacitor C4 for DC cutoff and a second variable capacitor circuit 137. Additionally, capacitors C4 and the second variable capacitor circuit 137 are not essential structural elements, and variations can be implemented without them. Furthermore, capacitors C31 to C3n are provided between the first variable capacitor circuit 136 and the second variable capacitor circuit 137 and the GND node.

[0082] The driving circuit 132 is a circuit that drives the vibrating element 5 to oscillate. The driving circuit 132 includes a current source ISA, a bipolar transistor BP0, and a resistor RB. The current source ISA is located between the power node of the power supply voltage VREG and the bipolar transistor BP0, supplying a constant current to the bipolar transistor BP0.

[0083] Bipolar transistor BP0 is the transistor that drives the oscillating element 5. Its base node becomes the input node NI of the driving circuit 132, and its collector node becomes the output node NQ of the driving circuit 132. Resistor RB is placed between the collector node and the base node of bipolar transistor BP0.

[0084] The capacitor C1 for DC cutoff is placed between the input node NI of the drive circuit 132 and the wiring LA. By placing this capacitor C1, the DC component of the oscillation signal is cut off, and only the AC component is transmitted to the input node NI of the drive circuit 132, enabling the bipolar transistor BPO to operate properly. Alternatively, the capacitor C1 for DC cutoff can also be placed between the output node NQ of the drive circuit 132 and the wiring LA.

[0085] The reference voltage supply circuit 134 supplies reference voltages VR1 to VRn to the first variable capacitor circuit 136 and the second variable capacitor circuit 137. The reference voltage supply circuit 134 includes, for example, multiple resistors connected in series between the node of the regulating power supply voltage VREG and the GND node, and outputs a voltage after dividing the voltage of VREG as the reference voltages VR1 to VRn. Furthermore, the reference voltage supply circuit 134 supplies a reference voltage VRB for setting the bias voltage to the wiring LA. Thus, the center voltage of the amplitude of the oscillation signal in the wiring LA can be set to the reference voltage VRB. Additionally, the center voltage of the amplitude of the oscillation signal in the wiring LB is set, for example, based on the base / emitter voltage of the bipolar transistor BPO and the base current flowing through the resistor RB.

[0086] One end of capacitor C2, used for DC disconnection, is electrically connected to wiring LA, and the other end is electrically connected to node NS1, the supply node for temperature compensation voltage VCP. Temperature compensation voltage VCP is supplied to node NS1 via resistor RC1. One end of the first variable capacitor circuit 136 is electrically connected to node NS1 and is supplied with temperature compensation voltage VCP. Furthermore, reference voltage supply circuit 134 supplies reference voltages VR1 to VRn to nodes NR1 to NRn at the other end of the first variable capacitor circuit 136. Moreover, capacitors C31 to C3n are provided between nodes NR1 to NRn (the supply nodes for reference voltages VR1 to VRn) and the GND node. One end of capacitor C4, used for DC disconnection, is electrically connected to wiring LB, and the other end is electrically connected to node NS2, the supply node for temperature compensation voltage VCP. Temperature compensation voltage VCP is supplied to node NS2 via resistor RC2. Furthermore, switches and capacitors C7 and C8 are provided between wiring LA and the GND node to adjust the load capacitance of wiring LA. Furthermore, switches and capacitors C5 and C6 are provided between the wiring LB and the GND node to adjust the load capacitance of the wiring LB. One end of the second variable capacitor circuit 137 is electrically connected to the supply node NS2 and is supplied with a temperature compensation voltage VCP. Additionally, the reference voltage supply circuit 134 supplies reference voltages VR1 to VRn to the supply nodes NR1 to NRn at the other end of the second variable capacitor circuit 137. The first variable capacitor circuit 136 includes n variable capacitor elements. n is an integer greater than 2. The n variable capacitor elements are, for example, MOS-type variable capacitor elements, composed of n transistors. Reference voltages VR1 to VRn are supplied to the gates of the n transistors. Furthermore, the source and drain of each of the n transistors are short-circuited, and the temperature compensation voltage VCP is supplied to the supply node NS1 connected to the short-circuited source and drain. Moreover, the capacitance of the DC cutoff capacitor C2 is much larger than the capacitance of the first variable capacitor circuit 136. By using the first variable capacitor circuit 136 with this structure, the linearity of the capacitance change of the total capacitance of the first variable capacitor circuit 136 can be ensured over a wide temperature compensation voltage VCP range. Furthermore, the structure of the second variable capacitor circuit 137 is the same as that of the first variable capacitor circuit 136, therefore a detailed description is omitted.

[0087] As described above, in the vibration device 1 of this embodiment, the integrated circuit 10 includes an oscillation circuit 11 that oscillates the vibration element 5 and outputs an oscillation signal. The passive component is at least one of a capacitor or a resistor included in the oscillation circuit 11. As described above, the resistor (not shown) included in the reference voltage supply circuit 134 deforms due to stress, and when the resistance value is unstable, the reference voltages VR1 to VRn supplied from the reference voltage supply circuit 134 are also unstable. Consequently, the voltage applied to the first variable capacitor circuit 136 is also unstable. Furthermore, as Figure 8As described above, the capacitances of capacitors C1, C2, C31 to C3n, and C4 to C8 are also unstable due to stress. This instability in the load capacitance of the oscillation circuit 11 causes frequency variations in the oscillating device 1. To address this, by applying the method of this embodiment, the capacitors or resistors included in the oscillation circuit 11 are positioned where stress is less of a concern, thereby suppressing deformation of the capacitors or resistors included in the oscillation circuit 11. This suppresses changes in the capacitance of the capacitors or the resistance of the resistors included in the oscillation circuit 11. Consequently, changes in the oscillation frequency of the oscillating device 1 are suppressed.

[0088] Figure 12 An example of the structure of a reference voltage generation circuit 14A is shown. The reference voltage generation circuit 14A includes an N-type transistor TD1, resistors RD1, RD2, and RD3 disposed between the VDD node and the GND node, and bipolar transistors BP1 and BP2. Furthermore, the reference voltage generation circuit 14A includes P-type transistors TD1 and TD2 whose gates are biased by a voltage BS, and a bipolar transistor BP3 disposed between the drain node of transistor TD2 and the GND node. The reference voltage generation circuit 14A is a bandgap reference circuit that generates and outputs a reference voltage VREF based on the bandgap voltage. For example, the base / emitter voltages of the PNP-type bipolar transistors BP1 and BP2 are set to VBE1 and VBE2, respectively, and ΔVBE = VBE1 - VBE2. The reference voltage generation circuit 14A outputs, for example, a reference voltage VREF of VREF = K × ΔVBE + VBE2. K is set by the resistance values ​​of resistors RD1 and RD2. For example, VBE2 has a negative temperature characteristic, and ΔVBE has a positive temperature characteristic. Therefore, by adjusting the resistance values ​​of resistors RD1 and RD2, a constant reference voltage VREF that is not temperature-dependent can be generated. Furthermore, the generated reference voltage VREF becomes a constant voltage referenced to ground voltage. Additionally, the reference voltage generation circuit 14A is not limited to... Figure 12 The structure includes circuits with various structures, such as those that can generate a reference voltage VREF using the work function difference voltage of transistors.

[0089] As described above, in the vibration device 1 of this embodiment, the integrated circuit 10 includes a reference voltage generation circuit 14A that generates a reference voltage used in the integrated circuit 10, and the passive component is a resistive element included in the integrated circuit 10. As described above, the resistors RD1, RD2, and RD3 included in the reference voltage generation circuit 14A deform due to stress, and when the resistance value is unstable, the reference voltage VREF is also unstable. As a result, the regulating power supply voltage VREG output from the regulator circuit 14B (described later) is also unstable, and the load capacitance of the oscillation circuit 11 fluctuates. This causes the problem of frequency variation in the vibration device 1. In this regard, by applying the method of this embodiment, the resistive element included in the reference voltage generation circuit 14A is positioned where the influence of stress is minimal, thereby suppressing the deformation of the resistive element included in the reference voltage generation circuit 14A. As a result, the change in the resistance value of the resistive element included in the reference voltage generation circuit 14A can be suppressed, and therefore, the reference voltage VREF and the regulating power supply voltage VREG can be stabilized. As a result, the change in the oscillation frequency of the vibration device 1 can be suppressed.

[0090] Figure 13 An example of the structure of regulator circuit 14B is shown. Regulator circuit 14B includes an N-type transistor TA1 for driving, resistors RA1 and RA2 connected in series between the VDD node and the GND node, and an operational amplifier OPA. Furthermore, regulator circuit 14B may include a resistor RA3 and a capacitor CA located at the output terminal of operational amplifier OPA. A reference voltage VREF is input to the non-inverting input terminal of operational amplifier OPA, and a voltage VDA obtained by dividing the regulated power supply voltage VREG1 through resistors RA1 and RA2 is input to the inverting input terminal. Moreover, the output terminal of operational amplifier OPA is input to the gate of transistor TA1 via resistor RA3, and the regulated power supply voltage VREG is output from the drain node of transistor TA1. Alternatively, regulator circuit 14B can set resistors RA1 and RA2 to fixed values, thereby outputting a fixed regulated power supply voltage VREG. However, the resistance values ​​of resistors RA1 and RA2 can also be set to be variable. Thus, for example, during manufacturing and shipping, the resistance values ​​can be adjusted to compensate for variations in the regulated power supply voltage VREG corresponding to process variations.

[0091] As described above, in the vibration device 1 of this embodiment, the integrated circuit 10 includes a regulator circuit 14B that generates a regulating power supply voltage VREG, and the passive component is a resistive element included in the regulator circuit 14B. As described above, the resistors RA1 and RA2 included in the regulator circuit 14B deform due to stress. When the resistance value changes, the ratio of resistance RA1 to resistance RA2 changes, causing the regulating power supply voltage VREG to fluctuate. This causes fluctuations in the load capacitance of the oscillation circuit 11, resulting in frequency fluctuations in the vibration device 1. Regarding this, by applying the method of this embodiment, the resistive element included in the regulator circuit 14B is positioned where the stress effect is minimal, thereby suppressing deformation of the resistive element included in the regulator circuit 14B. This suppresses changes in the resistance value of the resistive element included in the regulator circuit 14B, and thus suppresses fluctuations in the regulating power supply voltage VREG. Consequently, fluctuations in the oscillation frequency of the vibration device 1 can be suppressed.

[0092] Furthermore, as described above, the vibration device 1 of this embodiment includes at least one of a reference voltage generation circuit 14A that generates a reference voltage used in the integrated circuit 10, or a regulator circuit 14B that generates a power supply voltage VREG used in the integrated circuit 10. At least a portion of the passive or active elements included in at least one of the reference voltage generation circuit 14A or the regulator circuit 14B are configured to overlap with the joint JA when viewed from a direction orthogonal to the first surface 21. For example, in addition to including passive elements as described above, the reference voltage generation circuit 14A also includes bipolar transistors BP1 to BP3 as active elements. Figure 9 As described above, when bipolar transistors BP1 to BP3 are present in a region that does not overlap with the junction JA, the base currents of bipolar transistors BP1 to BP3 change due to stress. As a result, the reference voltage VREF becomes unstable, and similarly, the frequency of the oscillating device 1 changes. Regarding this, by applying the method of this embodiment, for example, by arranging resistors RD1 to RD3 as passive elements or bipolar transistors BP1 to BP3 as active elements in the region overlapping with the junction JA, their characteristics can be stabilized. Therefore, the oscillation characteristics of the packaged oscillating device 1 can be stabilized.

[0093] Figure 14An example of the structure of temperature sensor 16 is shown. Temperature sensor 16 includes a bipolar transistor BP4, a resistor RE1, a variable resistor circuit REA, and a current source ISB. The current source ISB is disposed between the power supply node NVD and the first node N1, and outputs a constant current IA to the first node N1. For example, the current source ISB is composed of a resistor disposed between the power supply node NVD and the GND node, and a current mirror circuit that mirrors the current flowing through the resistor to output a constant current IA. The first node N1 is connected to the base node of bipolar transistor BP4. Resistor RE1 is disposed between the first node N1 and the collector node of bipolar transistor BP4. That is, one end of resistor RE1 is connected to the first node N1, and the other end of resistor RE1 is connected to the collector node of bipolar transistor BP4. The variable resistor circuit REA is disposed between the emitter node of bipolar transistor BP4 and the GND node. That is, one end of the variable resistor circuit REA is connected to the emitter node of bipolar transistor BP4, and the other end of the variable resistor circuit REA is connected to the GND node. Zero-correction data is input from storage unit 17 to variable resistor circuit REA, and the resistance value of variable resistor circuit REA is set by this zero-correction data. As a result, a temperature-dependent temperature detection voltage VT is output from the collector node of bipolar transistor BP4.

[0094] As described above, in the vibration device 1 of this embodiment, the integrated circuit 10 includes a temperature sensor 16 for detecting temperature, and the passive component is a resistive element included in the temperature sensor 16. As described above, the resistor RE1 and other components included in the temperature sensor 16 deform due to stress, and the temperature detection voltage VT fluctuates when the resistance value changes. As a result, the load capacitance of the oscillation circuit 11 fluctuates, causing frequency fluctuations in the vibration device 1. In this regard, by applying the method of this embodiment, the resistive element included in the temperature sensor 16 is positioned at a location where the influence of stress is minimal, thereby suppressing deformation of the resistive element included in the temperature sensor 16. As a result, changes in the resistance value of the resistive element included in the temperature sensor 16 can be suppressed, and therefore, the temperature detection voltage VT can be stabilized. As a result, changes in the oscillation frequency of the vibration device 1 can be suppressed.

[0095] Figure 15 An example of the structure of the temperature compensation circuit 15 is shown. The temperature compensation circuit 15 includes a 0th-order correction circuit 152, a 1st-order correction circuit 154, a higher-order correction circuit 156, and a current-to-voltage conversion circuit 158. Furthermore, in cases of 3rd, 4th, or 5th-order corrections, multiple correction circuits such as the 3rd, 4th, and 5th-order correction circuits are provided as the higher-order correction circuit 156. The higher-order correction circuit 156 is also called a function generation circuit, which generates a function current corresponding to a polynomial that approximates the characteristics of the temperature compensation voltage VCP. For example, the polynomial is a function of temperature.

[0096] Temperature compensation circuit 15 performs temperature compensation using an analog method based on polynomial approximation. Specifically, temperature compensation circuit 15 generates and outputs a temperature compensation voltage VCP by approximating the temperature as a function, i.e., a polynomial, with temperature as the variable. Therefore, storage unit 17 stores the 0th-order coefficients, 1st-order coefficients, and higher-order coefficients of the polynomial that approximates the characteristics of the temperature compensation voltage VCP as 0th-order correction data, 1st-order correction data, and higher-order correction data, respectively. Furthermore, 0th-order correction circuit 152, 1st-order correction circuit 154, and higher-order correction circuit 156 output 0th-order correction current signals, 1st-order correction current signals, and higher-order correction current signals based on the 0th-order correction data, 1st-order correction data, and higher-order correction data stored in storage unit 17. The 0th-order correction current signals, 1st-order correction current signals, and higher-order correction current signals can be referred to as the 0th-order component signal, 1st-order component signal, and higher-order component signal of the function current, respectively. Moreover, in 1st-order correction circuit 154 and higher-order correction circuit 156, 1st-order correction current signals and higher-order correction current signals are generated and output based on the temperature detection voltage VT, which changes linearly with respect to temperature. The current-to-voltage conversion circuit 158 ​​performs addition processing on the 0th-order correction current signal, the 1st-order correction current signal, and the higher-order correction current signal, and then performs current-to-voltage conversion to output the temperature compensation voltage VCP. This achieves temperature compensation based on a polynomial approximation analog method. Furthermore, in the case where the temperature compensation is performed using the temperature sensor 16 for 0th-order correction as described above, the structure of the 0th-order correction circuit 152 can be omitted. In this case, to correct for deviations in the temperature detection voltage characteristics caused by variations in the bias voltage of the temperature detection voltage VT, for example, a 2nd-order correction circuit and a 4th-order correction circuit can be provided in the temperature compensation circuit 15 performing 5th-order polynomial approximation temperature compensation.

[0097] Figure 16 An example of the structure of the high-order correction circuit 156 is shown. The high-order correction circuit 156 includes bipolar transistors BP51 to BP5(2N+1), bipolar transistors BP61 to BP6(2N+1), resistors RF1 to RF(2N+1), resistors RG1 to RG(2N+1), and current sources ISC1 to ISC(2N+1). N is a natural number. Furthermore, the reference voltages VS1 to VS(N+1) and reference voltage VG, described later, are output from the voltage generation circuit not shown.

[0098] A differential pair is formed by bipolar transistor BP51 and bipolar transistor BP61. The base terminal of bipolar transistor BP51 is input with a reference voltage VS1, the collector terminal is connected to a reference voltage supply line 159 that supplies the reference voltage VG, and the emitter terminal is electrically connected to a current source ISC1 via a resistor RF1. The base terminal of bipolar transistor BP61 is input with a temperature detection voltage VT, the collector terminal is connected to a current-voltage conversion circuit 158, and the emitter terminal is electrically connected to the current source ISC1 via a resistor RG1. The current source ISC1 flows a constant current IB1 through the differential pair formed by bipolar transistor BP51 and bipolar transistor BP61 via the resistor RF1 and the resistor RG1. The same applies to the differential pair formed by bipolar transistor BP5(2N + 1) and bipolar transistor BP6(2N + 1).

[0099] In addition, a differential pair is formed by bipolar transistor BP52 and bipolar transistor BP62. The base terminal of bipolar transistor BP52 is input with a reference voltage VS2, the collector terminal is connected to the current-voltage conversion circuit 158, and the emitter terminal is electrically connected to a current source ISC2 via a resistor RG1. The base terminal of bipolar transistor BP62 is input with the temperature detection voltage VT, the collector terminal is electrically connected to the reference voltage supply line 159, and the emitter terminal is electrically connected to the current source ISC2 via a resistor RG2. The current source ISC2 flows a constant current IB(2N) through the differential pair formed by bipolar transistor BP52 and bipolar transistor BP62 via the resistor RF2 and the resistor RG2. The same applies to the differential pair formed by bipolar transistor BP5(2N) and bipolar transistor BP6(2N).

[0100] The value of the temperature detection voltage VT decreases approximately linearly with respect to the temperature T and is consistent with the reference voltages VS1, VR2,..., VSN, VS(2N + 1) when the temperature T is T1, T2,..., T(2N), T(2N + 1), respectively. Also, let T1 < T2 <... < T(2N) < T(2N + 1). Regarding well-known methods, detailed descriptions are omitted. However, by including a differential pair with this structure, the current value from the current-voltage conversion circuit 158 monotonically decreases near the temperature T = T1, monotonically increases near the temperature T = T2, and thereafter, depending on the number of differential pairs, monotonic decrease and monotonic increase alternate. Thus, although not shown in the figure, the temperature dependence of the current value from the current-voltage conversion circuit 158 shows a pattern of repeated fluctuations.

[0101] As described above, in the vibration device 1 of this embodiment, the integrated circuit 10 includes a temperature compensation circuit 15 that performs temperature compensation for the oscillation frequency of the vibration element 5, and the passive component is the resistive element included in the temperature compensation circuit 15. As described above, the higher-order correction circuit 156 of the temperature compensation circuit 15 includes resistors RF1 to RF(2N+1) and resistors RG1 to RG(2N+1) constituting each differential pair. These resistors deform due to stress, and when the resistance value changes, the current value on the wiring connected to the current-to-voltage conversion circuit 158 ​​changes. As a result, the temperature compensation voltage VCP changes, and therefore, the load capacitance of the oscillation circuit 11 changes, causing the frequency of the vibration device 1 to fluctuate. In this regard, by applying the method of this embodiment, the resistive element included in the temperature compensation circuit 15 is positioned where the influence of stress is minimal, thereby suppressing the deformation of the resistive element included in the temperature compensation circuit 15. As a result, the change in the resistance value of the resistive element included in the temperature compensation circuit 15 can be suppressed, and therefore, the temperature compensation voltage VCP can be stabilized. As a result, the change in the oscillation frequency of the vibration device 1 can be suppressed.

[0102] Furthermore, the vibration device 1 of this embodiment includes at least one of a temperature sensor 16 for detecting temperature or a temperature compensation circuit 15 for temperature compensation of the oscillation frequency of the vibration element 5. At least a portion of the passive or active element included in at least one of the temperature sensor 16 or the temperature compensation circuit 15 is configured to overlap with the joint 73 when viewed from a direction orthogonal to the first surface 21. Figure 14 , Figure 16 As described above, the temperature sensor 16 or temperature compensation circuit 15, in addition to the passive components, also includes bipolar transistors BP4, BP51~BP5(2N+1), and BP61~BP6(2N+1) as active components. Figure 9 As described above, when BP4, BP51-BP5(2N+1), and BP61-BP6(2N+1) are present in the region that does not overlap with the junction JA, the base currents of the bipolar transistors BP4, BP51-BP5(2N+1), and BP61-BP6(2N+1) change due to stress. This causes fluctuations in the temperature compensation voltage VCP, resulting in variations in the load capacitance of the oscillation circuit 11 and causing frequency fluctuations in the oscillation device 1. In this embodiment, the oscillation device 1 is configured such that the temperature sensor 16 and the temperature compensation circuit 15 overlap with the junction JA. By arranging passive or active components in the region overlapping with the junction JA, the characteristics of the passive or active components can be stabilized. This stabilizes the oscillation characteristics of the packaged oscillation device 1.

[0103] This embodiment is not limited to the above-described situation and can be implemented in various variations. Figure 17This is a top view showing a modified example of this embodiment. The vibrating device 1 may also include a PLL circuit 18. For example, by providing a fractional-N type PLL circuit 18, a clock signal CK of arbitrary frequency can be output after multiplying the frequency of the oscillation signal of the oscillation circuit 11. Furthermore, the PLL circuit 18, like the control circuit 13, is positioned inside the inner wall line 9L of the cover when viewed from above. That is, when viewed from above, the PLL circuit 18 is positioned in a position that does not overlap with the joint JA. This is because the PLL circuit 18 performs correction within the feedback loop, therefore, the influence of stress can be considered small. By positioning the PLL circuit 18 in a position where the influence of stress is large, the leeway for placing circuits with a large influence of stress in positions where the influence of stress is small can be increased.

[0104] As described above, the vibration device of this embodiment includes a semiconductor substrate, a base, a vibration element, and a cover. The semiconductor substrate has a first surface and a second surface opposite to the first surface. The base includes an integrated circuit disposed on either the first or second surface. The vibration element is electrically connected to the integrated circuit and is disposed on the first surface side. The cover is engaged with the base at a joint portion to accommodate the vibration element. The integrated circuit includes a passive element, which is configured such that at least a portion of the passive element overlaps with the joint portion when viewed from a direction orthogonal to the first surface.

[0105] Thus, the vibration device of this embodiment includes an integrated circuit disposed on a first or second surface of a semiconductor substrate. Furthermore, the integrated circuit includes passive components, which are configured such that, when viewed from a direction orthogonal to the first surface, at least a portion of the passive component overlaps with a joint portion that engages with the cover. This configuration reduces the impact of stress on the passive components compared to a configuration where the passive components do not overlap with the joint portion when viewed from above. Consequently, deformation of the passive components caused by stress can be suppressed. This suppresses changes in the characteristics of the passive components, and therefore, effectively suppresses changes in the frequency characteristics of the vibration device.

[0106] In addition, passive components can be at least one of capacitors or resistors.

[0107] By placing the capacitor or resistor in a location where stress is minimal, deformation of the capacitor or resistor can be suppressed. This, in turn, suppresses changes in the capacitance of the capacitor or the resistance of the resistor. Consequently, it suppresses changes in the oscillation frequency of the vibrating device.

[0108] In addition, the capacitor element can be at least one of MIM (Metal-Insulator-Metal) capacitor, PIP (polysilicon-Insulator-polysilicon) capacitor or MOS (Metal-Oxide-Semiconductor) capacitor.

[0109] By placing the capacitors commonly used in vibrating devices in locations with minimal stress, deformation of these capacitors can be suppressed. This, in turn, suppresses changes in the capacitance of these capacitors. Consequently, changes in the oscillation frequency of the vibrating device can be suppressed.

[0110] In addition, an integrated circuit may include an oscillating circuit that causes a vibrating element to oscillate and outputs an oscillating signal, wherein the passive element is at least one of a capacitive element or a resistive element included in the oscillating circuit.

[0111] By placing the capacitors or resistors in the oscillation circuit at locations less affected by stress, deformation of these components can be suppressed. This, in turn, suppresses changes in the capacitance of the capacitors or the resistance of the resistors. Consequently, it suppresses changes in the oscillation frequency of the vibrating device.

[0112] In addition, the base may include a through electrode, the integrated circuit has a first side and a second side opposite to the first side, and an oscillation circuit is arranged between the first side and the through electrode when viewed from a direction orthogonal to the first surface.

[0113] By positioning the oscillating circuit closer to the first side, the distance between the external connection terminal positioned closer to the second side and the oscillating circuit can be increased, thereby reducing the capacitance of the capacitive coupling between the oscillating circuit and the external connection terminal.

[0114] In addition, an integrated circuit may also include a reference voltage generation circuit that generates a reference voltage used in the integrated circuit, and the passive component is the resistive element included in the reference voltage generation circuit.

[0115] By placing the resistive element in the reference voltage generation circuit at a location where stress has minimal impact, deformation of the resistive element can be suppressed. This, in turn, suppresses changes in the resistance value of the resistive element. Consequently, it suppresses changes in the oscillation frequency of the vibrating device.

[0116] In addition, integrated circuits may also include regulator circuits that generate the power supply voltage used in the integrated circuit, and passive components are the resistive elements contained in the regulator circuit.

[0117] By placing the resistive element in the regulator circuit at a location where stress is minimal, deformation of the resistive element can be suppressed. This, in turn, suppresses changes in the resistance value of the resistive element. Consequently, it suppresses changes in the oscillation frequency of the vibrating device.

[0118] In addition, integrated circuits can also include temperature sensors that detect temperature, and passive components are the resistive elements contained in the temperature sensor.

[0119] By placing the resistive element within the temperature sensor in a location with minimal stress, deformation of the resistive element can be suppressed. This, in turn, suppresses changes in the resistance value of the resistive element. Consequently, it suppresses changes in the oscillation frequency of the vibrating device.

[0120] In addition, integrated circuits may also include temperature compensation circuits that compensate for the oscillation frequency of the vibrating element, and passive components are resistive elements included in the temperature compensation circuit.

[0121] By placing the resistive element in the temperature compensation circuit at a location where stress is minimal, deformation of the resistive element can be suppressed. This, in turn, suppresses changes in the resistance value of the resistive element. Consequently, it suppresses changes in the oscillation frequency of the vibrating device.

[0122] In addition, the integrated circuit may also include a defined circuit disposed in a region that does not overlap with the junction when viewed from above, the defined circuit including at least one of a control circuit or a memory circuit.

[0123] In this way, control circuits and memory circuits that are less susceptible to stress are placed in locations where stress is greater, thereby increasing the flexibility to place circuits with greater stress influence in locations where stress is less significant.

[0124] Furthermore, the vibration device of this embodiment includes a semiconductor substrate, a base, a vibration element, and a cover. The semiconductor substrate has a first surface and a second surface opposite to the first surface. The base includes an integrated circuit disposed on the first surface or the second surface. The vibration element is electrically connected to the integrated circuit and is disposed on the first surface side. The cover is engaged with the base at a joint portion to accommodate the vibration element. The integrated circuit includes at least one of a reference voltage generating circuit for generating a reference voltage used in the integrated circuit or a regulator circuit for generating a power supply voltage for regulating the integrated circuit. At least a portion of the passive or active elements included in at least one of the reference voltage generating circuit or regulator circuit are configured to overlap with the joint portion when viewed from a direction orthogonal to the first surface.

[0125] By placing the passive or active components in the reference voltage generation circuit or regulator circuit in locations less affected by stress, deformation of these components can be suppressed. This, in turn, suppresses changes in the characteristics of the passive or active components. Consequently, it suppresses changes in the oscillation frequency of the vibrating device.

[0126] Furthermore, the vibration device of this embodiment includes a semiconductor substrate, a base, a vibration element, and a cover. The semiconductor substrate has a first surface and a second surface opposite to the first surface. The base includes an integrated circuit disposed on the first surface or the second surface. The vibration element is electrically connected to the integrated circuit and is disposed on the first surface side. The cover is joined to the base at a joint portion in a manner that accommodates the vibration element. The integrated circuit includes at least one of a temperature sensor for detecting temperature or a temperature compensation circuit for temperature compensation of the oscillation frequency of the vibration element. At least a portion of a passive element or an active element included in at least one of the temperature sensor or the temperature compensation circuit is configured to overlap with the joint portion when viewed from a direction orthogonal to the first surface.

[0127] By placing the passive or active components of the temperature sensor or temperature compensation circuit in locations with minimal stress influence, deformation of these components can be suppressed. This, in turn, suppresses changes in the characteristics of the passive or active components. Consequently, it suppresses changes in the oscillation frequency of the vibrating device.

[0128] Furthermore, while this embodiment has been described in detail above, those skilled in the art will readily understand that various modifications can be made without substantially departing from the new aspects and effects of the invention. Therefore, all such modifications are included within the scope of the invention. For example, in the specification or drawings, a term described at least once with a different term that is more general or synonymous can be replaced with that different term at any point in the specification or drawings. Moreover, all combinations of this embodiment and its modifications are also included within the scope of the invention. Furthermore, the structure, operation, etc., of the vibrating device are not limited to those described in this embodiment, and various modifications can be implemented.

Claims

1. A vibration device, characterized in that, The vibration device includes: A base comprising a semiconductor substrate and an integrated circuit, the semiconductor substrate having a first surface and a second surface opposite to the first surface, the integrated circuit being disposed on the first surface or the second surface; a vibrating element electrically connected to the integrated circuit and disposed on the first surface side; and a cover engaging with the base at a joint portion of the base to accommodate the vibrating element, the integrated circuit comprising a resistive element configured such that at least a portion of the resistive element overlaps with the joint portion when viewed from a direction orthogonal to the first surface.

2. The vibration device according to claim 1, characterized in that, The integrated circuit includes an oscillation circuit that causes the vibrating element to oscillate and outputs an oscillation signal, and the resistive element is a resistive element included in the oscillation circuit.

3. The vibration device according to claim 1 or 2, characterized in that, The integrated circuit includes a reference voltage generating circuit that generates a reference voltage used in the integrated circuit, and the resistive element is a resistive element included in the reference voltage generating circuit.

4. The vibration device according to claim 1 or 2, characterized in that, The integrated circuit includes a regulator circuit that generates a power supply voltage for use in the integrated circuit, and the resistive element is a resistive element included in the regulator circuit.

5. The vibration device according to claim 1 or 2, characterized in that, The integrated circuit includes a temperature sensor for detecting temperature, and the resistive element is a resistive element included in the temperature sensor.

6. The vibration device according to claim 1 or 2, characterized in that, The integrated circuit includes a temperature compensation circuit that performs temperature compensation for the oscillation frequency of the vibrating element, and the resistive element is a resistive element included in the temperature compensation circuit.

7. The vibration device according to claim 1 or 2, characterized in that, The integrated circuit includes defined circuitry disposed in a region that does not overlap with the junction when viewed from above, the defined circuitry including at least one of control circuitry or memory circuitry.

8. A vibrating device, characterized in that, The vibration device includes: A base comprising a semiconductor substrate and an integrated circuit, the semiconductor substrate having a first surface and a second surface opposite to the first surface, the integrated circuit being disposed on the first surface or the second surface; a vibrating element electrically connected to the integrated circuit and disposed on the first surface side; and a cover engaging with the base at a joint portion of the base to accommodate the vibrating element, the integrated circuit comprising at least one of a reference voltage generating circuit for generating a reference voltage used in the integrated circuit or a regulator circuit for generating a regulated power supply voltage used in the integrated circuit, at least a portion of a resistive element or an active element included in the reference voltage generating circuit or the regulator circuit being configured to overlap the joint portion when viewed from a direction orthogonal to the first surface.

9. A vibration device, characterized in that, The vibration device includes: A base comprising a semiconductor substrate and an integrated circuit, the semiconductor substrate having a first surface and a second surface opposite to the first surface, the integrated circuit being disposed on the first surface or the second surface; a vibrating element electrically connected to the integrated circuit and disposed on the first surface side; and a cover engaging with the base at a joint portion of the base to accommodate the vibrating element, the integrated circuit comprising at least one of a temperature sensor for detecting temperature or a temperature compensation circuit for temperature compensation of the oscillation frequency of the vibrating element, at least a portion of a resistive element or an active element included in the temperature sensor or the temperature compensation circuit being configured to overlap the joint portion when viewed from a direction orthogonal to the first surface.

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