An integrator circuit

Abstract

The application discloses an integrator circuit, comprising a sampling module, a feedback module, an integration module and an amplifier, wherein the amplifier comprises an amplification module and a bias module; the sampling module is connected with the amplification module and the bias module respectively, and is used for collecting an input signal; the feedback module is connected with the amplification module and the bias module respectively, and is used for providing a feedback signal for the amplification module; the integration module is connected with the amplification module, and is used for generating a rectangular wave signal; the amplification module is connected with the sampling module, the feedback module, the integration module and the bias module respectively, and is used for amplifying the input signal; and the bias module is connected with the sampling module, the feedback module and the amplification module respectively, and is used for providing a bias voltage for the amplification module. According to the integrator circuit, the amplifier is divided into the amplification module and the bias module, the bias module provides the bias voltage for the amplification module, and the switches in the feedback module and the sampling module are easy to be turned on.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of electronic circuit, more particularly, relates to an integrator circuit. BACKGROUND

[0002] Integrator circuit is one of the most commonly used circuits in electronic technology, and usually the integrator can be realized by using a switched-capacitor circuit.

[0003] Figure 1 is a double-sampled first-stage integrator structure. Cs is a sampling capacitor, Cint is an integration capacitor, and Cdac is a feedback capacitor. The switch on the left side of the Cs / Cdac capacitor is a CMOS pass gate, which can accept a wide range of input voltages. The switch on the right side of the Cs / Cdac capacitor is an NMOS switch, and the VCM voltage and the Amp_p / Amp_n voltage are basically the same and stable.

[0004] For an analog-to-digital converter, the process selected for design includes two kinds of voltage devices, such as a 1.8V / 5V process or a 1.8V / 3V process. That is, the process provides 1.8V and 5V devices, or 1.8V and 3V devices. In this way, the analog interface can achieve the widest possible voltage range, and the digital circuit can use low-voltage devices to reduce power consumption area. Taking 5V as an example, if the system is powered by a single power supply, and the power supply voltage varies in a large range, such as 2.2V-5V, this will bring difficulties to the integrator in Figure 1 Figure 1 The switches in are 5V, and when the power supply is low, the on-resistance of the switch becomes very large at the middle level, resulting in difficulty in turning on.

[0005] For the CMOS pass gate on the left side, back-gate driving can be used to reduce the on-resistance. However, the switch on the right side is a critical sampling switch, and the back-gate driving method is not suitable. Due to the back-gate effect, the threshold voltage (Vth) of the NMOS becomes large at the middle voltage, close to VDD / 2, and the switch is difficult to turn on.

[0006] Therefore, there is a particular need for an integrator circuit that is easy to turn on. SUMMARY

[0007] The purpose of the present application is to provide an integrator circuit that is easy to turn on.

[0008] ​In order to achieve the above object, the application provides an integrator circuit, comprising a sampling module, a feedback module, an integration module and an amplifier, wherein the amplifier comprises an amplification module and a biasing module; the sampling module is connected with the amplification module and the biasing module respectively, and is used for collecting an input signal; the feedback module is connected with the amplification module and the biasing module respectively, and is used for providing a feedback signal for the amplification module; the integration module is connected with the amplification module, and is used for generating a rectangular wave signal; the amplification module is connected with the sampling module, the feedback module, the integration module and the biasing module respectively, and is used for amplifying the input signal; and the biasing module is connected with the sampling module, the feedback module and the amplification module respectively, and is used for providing a bias voltage for the amplification module.

[0009] Preferably, the amplification module comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube; the gate of the first NMOS tube is connected with a first bias voltage, the source of the first NMOS tube is connected with a negative electrode of a power supply, and the drain of the first NMOS tube is connected with the source of the second NMOS tube and the source of the third NMOS tube; the gate of the second NMOS tube is connected with a sampling module, a feedback module and an integration module respectively, the source of the second NMOS tube is connected with the source of the third NMOS tube and the drain of the first NMOS tube respectively, and the drain of the second NMOS tube is connected with the source of the fourth NMOS tube; the gate of the third NMOS tube is connected with the sampling module, the feedback module and the integration module respectively, the source of the third NMOS tube is connected with the source of the second NMOS tube and the drain of the first NMOS tube respectively, and the drain of the third NMOS tube is connected with the source of the fifth NMOS tube; the gate of the fourth NMOS tube is connected with the gate of the fifth NMOS tube, the source of the fourth NMOS tube is connected with the drain of the second NMOS tube, and the drain of the fourth NMOS tube is connected with the drain of the first PMOS tube; the gate of the fifth NMOS tube is connected with the gate of the fourth NMOS tube, the source of the fifth NMOS tube is connected with the drain of the third NMOS tube, and the drain of the fifth NMOS tube is connected with the drain of the second PMOS tube; the gate of the first PMOS tube is connected with the gate of the second PMOS tube, the source of the first PMOS tube is connected with the drain of the third PMOS tube, and the drain of the first PMOS tube is connected with the drain of the fourth NMOS tube; the gate of the second PMOS tube is connected with the gate of the first PMOS tube, the source of the second PMOS tube is connected with the drain of the fourth PMOS tube, and the drain of the second PMOS tube is connected with the drain of the fifth NMOS tube; the gate of the third PMOS tube is connected with a second bias voltage, the drain of the third PMOS tube is connected with the source of the first PMOS tube, and the source of the third PMOS tube is connected with a positive electrode of the power supply; and the gate of the fourth PMOS tube is connected with the second bias voltage, the drain of the fourth PMOS tube is connected with the source of the second PMOS tube, and the source of the fourth PMOS tube is connected with the positive electrode of the power supply.

[0010] Preferably, the drain of the first PMOS tube is connected with the drain of the fourth NMOS tube at a negative electrode output of the amplification module, and the drain of the second PMOS tube is connected with the drain of the fifth NMOS tube at a positive electrode output of the amplification module.

[0011] Preferably, the biasing module comprises a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor and a fifth PMOS transistor; a gate of the sixth NMOS transistor is connected with a drain of the sixth NMOS transistor and a source of the eighth NMOS transistor, the drain of the sixth NMOS transistor is connected with the gate of the sixth NMOS transistor and the source of the eighth NMOS transistor respectively, and a source of the sixth NMOS transistor is connected with a negative electrode of a power supply; a gate of the seventh NMOS transistor is connected with a drain of the seventh NMOS transistor and a source of the ninth NMOS transistor, the drain of the seventh NMOS transistor is connected with the gate of the seventh NMOS transistor, the source of the ninth NMOS transistor, a sampling module and a feedback module respectively, and a source of the seventh NMOS transistor is connected with the negative electrode of the power supply; a gate of the eighth NMOS transistor is connected with a drain of the eighth NMOS transistor, a gate of the ninth NMOS transistor and a drain of the fifth PMOS transistor, the drain of the eighth NMOS transistor is connected with the gate of the eighth NMOS transistor, the gate of the ninth NMOS transistor and the drain of the fifth PMOS transistor, and a source of the eighth NMOS transistor is connected with the gate and the drain of the sixth NMOS transistor; the gate of the ninth NMOS transistor is connected with the drain and the gate of the eighth NMOS transistor and the drain of the fifth PMOS transistor, a drain of the ninth NMOS transistor is connected with a positive electrode of the power supply, and a source of the ninth NMOS transistor is connected with the gate, the drain of the seventh NMOS transistor, the sampling module and the feedback module respectively; a gate of the fifth PMOS transistor is connected with a second biasing voltage, a drain of the fifth PMOS transistor is connected with the gate of the ninth NMOS transistor, the drain of the eighth NMOS transistor and the gate, and a source of the fifth PMOS transistor is connected with the positive electrode of the power supply.

[0012] Preferably, the sampling module comprises a first capacitor, a second capacitor, a first transmission gate switch, a second transmission gate switch, a third transmission gate switch, a fourth transmission gate switch, a first sampling switch, a second sampling switch, a third sampling switch and a fourth sampling switch; one end of the first transmission gate switch is connected with the input positive pole and one end of the third transmission gate switch respectively, and the other end of the first transmission gate switch is connected with one end of the second transmission gate switch and one end of the first capacitor respectively; the other end of the second transmission gate switch is connected with the input negative pole and the other end of the fourth transmission gate switch respectively, and one end of the second transmission gate switch is connected with the other end of the first transmission gate switch and one end of the first capacitor respectively; one end of the first capacitor is connected with one end of the second transmission gate switch and the other end of the first transmission gate switch respectively, and the other end of the first capacitor is connected with one end of the first sampling switch and one end of the second sampling switch respectively; one end of the first sampling switch is connected with the other end of the first capacitor and one end of the second sampling switch respectively, and the other end of the first sampling switch is connected with the feedback module, the integral module and the gate of the second NMOS tube respectively; one end of the second sampling switch is connected with the other end of the first capacitor and one end of the first sampling switch respectively, and the other end of the second sampling switch is connected with the feedback module, the source of the ninth NMOS tube and the gate of the seventh NMOS tube respectively; one end of the third transmission gate switch is connected with the input positive pole and one end of the first transmission gate switch respectively, and the other end of the third transmission gate switch is connected with one end of the fourth transmission gate switch and one end of the second capacitor respectively; the other end of the fourth transmission gate switch is connected with the input negative pole and the other end of the second transmission gate switch respectively, and one end of the fourth transmission gate switch is connected with the other end of the third transmission gate switch and one end of the second capacitor respectively; one end of the second capacitor is connected with one end of the fourth transmission gate switch and the other end of the third transmission gate switch respectively, and the other end of the second capacitor is connected with one end of the third sampling switch and one end of the fourth sampling switch respectively; one end of the third sampling switch is connected with the other end of the second capacitor and one end of the fourth sampling switch respectively, and the other end of the third sampling switch is connected with the feedback module, the integral module and the gate of the third NMOS tube respectively; one end of the fourth sampling switch is connected with the other end of the second capacitor and one end of the third sampling switch respectively, and the other end of the fourth sampling switch is connected with the feedback module, the source of the ninth NMOS tube, the gate of the seventh NMOS tube and the other end of the second sampling switch respectively.

[0013] Preferably, the feedback module comprises a third capacitor, a fourth capacitor, a fifth transmission gate switch, a sixth transmission gate switch, a seventh transmission gate switch, an eighth transmission gate switch, a first feedback switch, a second feedback switch, a third feedback switch and a fourth feedback switch; one end of the fifth transmission gate switch is connected with the positive reference voltage, the other end of the fifth transmission gate switch is connected with one end of the sixth transmission gate switch and one end of the third capacitor respectively; one end of the sixth transmission gate switch is connected with the other end of the fifth transmission gate switch and one end of the third capacitor respectively, the other end of the sixth transmission gate switch is connected with the negative reference voltage; one end of the third capacitor is connected with one end of the sixth transmission gate switch and the other end of the fifth transmission gate respectively, the other end of the third capacitor is connected with one end of the first feedback switch and one end of the second feedback switch respectively; one end of the first feedback switch is connected with the other end of the third capacitor and one end of the second feedback switch respectively, the other end of the first feedback switch is connected with the integral module, the gate of the second NMOS and the other end of the first sampling switch respectively; one end of the second feedback switch is connected with the other end of the third capacitor and one end of the first feedback switch respectively, the other end of the second feedback switch is connected with the source of the ninth NMOS, the gate of the seventh NMOS, the other end of the second sampling switch and the other end of the fourth sampling switch respectively; one end of the seventh transmission gate switch is connected with the positive reference voltage, the other end of the seventh transmission gate switch is connected with one end of the eighth transmission gate switch and one end of the fourth capacitor respectively; one end of the eighth transmission gate switch is connected with the other end of the seventh transmission gate switch and one end of the fourth capacitor respectively, the other end of the eighth transmission gate switch is connected with the negative reference voltage; one end of the fourth capacitor is connected with one end of the eighth transmission gate switch and the other end of the seventh transmission gate respectively, the other end of the fourth capacitor is connected with one end of the third feedback switch and one end of the fourth feedback switch respectively; one end of the third feedback switch is connected with the other end of the fourth capacitor and one end of the fourth feedback switch respectively, the other end of the third feedback switch is connected with the integral module, the gate of the third NMOS and the other end of the third sampling switch respectively; one end of the fourth feedback switch is connected with the other end of the fourth capacitor and one end of the third feedback switch respectively, the other end of the fourth feedback switch is connected with the source of the ninth NMOS, the gate of the seventh NMOS, the other end of the second feedback switch, the other end of the second sampling switch and the other end of the fourth sampling switch respectively.

[0014] Preferably, the integral module comprises a fifth capacitor and a sixth capacitor; one end of the fifth capacitor is connected with the other end of the first feedback switch, the gate of the second NMOS tube and the other end of the first sampling switch respectively, and the other end of the fifth capacitor is connected with the drain of the first PMOS tube and the drain of the fourth NMOS tube respectively; one end of the sixth capacitor is connected with the other end of the third feedback switch, the gate of the third NMOS tube and the other end of the third sampling switch respectively, and the other end of the sixth capacitor is connected with the drain of the second PMOS tube and the drain of the fifth NMOS tube respectively.

[0015] Preferably, the first transmission gate switch, the fourth transmission gate switch, the second sampling switch, the fourth sampling switch, the second feedback switch and the fourth feedback switch are synchronously turned on or turned off, and the second transmission gate switch, the third transmission gate switch, the first sampling switch, the third sampling switch, the first feedback switch and the third feedback switch are synchronously turned on or turned off.

[0016] Preferably, the threshold voltages of the second NMOS tube, the third NMOS tube, the sixth NMOS tube and the seventh NMOS tube are a first threshold voltage, and the threshold voltages of the first NMOS tube, the fourth NMOS tube, the fifth NMOS tube, the eighth NMOS tube, the ninth NMOS tube, the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube and the fifth PMOS tube are a second threshold voltage, and the second threshold voltage is greater than the first threshold voltage.

[0017] The integral circuit of the present application has the advantages that the integral circuit of the present application divides the amplifier into an amplification module and a biasing module, and the biasing module provides a biasing voltage for the amplification module, so that the switches in the feedback module and the sampling module are easily turned on.

[0018] The device of the present application has other characteristics and advantages, which will be apparent from or set forth in the accompanying drawings and the detailed description that follows, which together serve to explain certain principles of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0019] The above and other objects, features and advantages of the present application will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which like reference characters refer to like parts throughout the several views, and wherein:

[0020] Figure 1 A structure diagram of a prior integral circuit is shown.

[0021] Figure 2 A schematic diagram of an integral circuit according to the present application is shown.

[0022] Reference Signs List:

[0023] 102, sampling module; 104, feedback module; 106, integration module; 108, amplification module; 110, bias module; M5, first PMOS transistor; M6, second PMOS transistor; M7, third PMOS transistor; M8, fourth PMOS transistor; M9, fifth PMOS transistor; M0, first NMOS transistor; LM1, second NMOS transistor; LM2, third NMOS transistor; M3, fourth NMOS transistor; M4, fifth NMOS transistor; LM3, sixth NMOS transistor; LM4, seventh NMOS transistor; M10, eighth NMOS transistor; M11, ninth NMOS transistor; CS1, first capacitor; CS2, second capacitor; Cdac1, third capacitor; Cdac2, fourth capacitor; Cint1, fifth capacitor; Cint2, sixth capacitor; S11, first transmission gate switch; S21, second transmission gate switch; S22, third transmission gate switch; S12, fourth transmission gate switch; S24, first sampling switch; S14, second sampling switch; S25, third sampling switch; S15, fourth sampling switch; S23, first feedback switch; S13, second feedback switch; S26, third feedback switch; S16, fourth feedback switch; S31, fifth transmission gate switch; S32, sixth transmission gate switch; S33, seventh transmission gate switch; S34, eighth transmission gate switch; VDD, positive power supply; GND, negative power supply. DETAILED DESCRIPTION

[0024] Preferred embodiments of the present application will be described in more detail below. Although the following describes preferred embodiments of the present application, it is to be understood that the present application can be carried out in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thorough and complete, and fully convey the scope of the application to those skilled in the art.

[0025] According to an integrator circuit of the present application, comprising: a sampling module, a feedback module, an integration module and an amplifier, the amplifier comprising an amplification module and a bias module; the sampling module is connected with the amplification module and the bias module respectively, and the sampling module is used for collecting an input signal; the feedback module is connected with the amplification module and the bias module respectively, and the feedback module is used for providing a feedback signal for the amplification module; the integration module is connected with the amplification module, and the integration module is used for generating a rectangular wave signal; the amplification module is connected with the sampling module, the feedback module, the integration module and the bias module respectively, and the amplification module is used for amplifying the input signal; the bias module is connected with the sampling module, the feedback module and the amplification module respectively, and the bias module is used for providing a bias voltage for the amplification module.

[0026] Specifically, the feedback module provides a bias voltage for the amplification module, when the power supply is as low as 2.2V, the bias voltage is 0.55V, the sampling switch and the feedback switch can still be normally opened, and the circuit works normally.

[0027] According to the exemplary embodiment, the integrator circuit divides the amplifier into an amplification module and a bias module, the bias module provides a bias voltage for the amplification module, and the switches in the feedback module and the sampling module are easily turned on.

[0028] As a preferred solution, the amplification module comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube; the gate of the first NMOS tube is connected with a first bias voltage, the source of the first NMOS tube is connected with the negative pole of the power supply, and the drain of the first NMOS tube is connected with the source of the second NMOS tube and the source of the third NMOS tube; the gate of the second NMOS tube is connected with the sampling module, the feedback module and the integration module respectively, the source of the second NMOS tube is connected with the source of the third NMOS tube and the drain of the first NMOS tube respectively, and the drain of the second NMOS tube is connected with the source of the fourth NMOS tube; the gate of the third NMOS tube is connected with the sampling module, the feedback module and the integration module respectively, the source of the third NMOS tube is connected with the source of the second NMOS tube and the drain of the first NMOS tube respectively, and the drain of the third NMOS tube is connected with the source of the fifth NMOS tube; the gate of the fourth NMOS tube is connected with the gate of the fifth NMOS tube, the source of the fourth NMOS tube is connected with the drain of the second NMOS tube, and the drain of the fourth NMOS tube is connected with the drain of the first PMOS tube; the gate of the fifth NMOS tube is connected with the gate of the fourth NMOS tube, the source of the fifth NMOS tube is connected with the drain of the third NMOS tube, and the drain of the fifth NMOS tube is connected with the drain of the second PMOS tube; the gate of the first PMOS tube is connected with the gate of the second PMOS tube, the source of the first PMOS tube is connected with the drain of the third PMOS tube, and the drain of the first PMOS tube is connected with the drain of the fourth NMOS tube; the gate of the second PMOS tube is connected with the gate of the first PMOS tube, the source of the second PMOS tube is connected with the drain of the fourth PMOS tube, and the drain of the second PMOS tube is connected with the drain of the fifth NMOS tube; the gate of the third PMOS tube is connected with a second bias voltage, the drain of the third PMOS tube is connected with the source of the first PMOS tube, and the source of the third PMOS tube is connected with the positive pole of the power supply; the gate of the fourth PMOS tube is connected with the second bias voltage, the drain of the fourth PMOS tube is connected with the source of the second PMOS tube, and the source of the fourth PMOS tube is connected with the positive pole of the power supply.

[0029] Specifically, the whole amplification module works in a 5V voltage domain (2.2V-5V). The voltage of the seventh NMOS mirror is the voltage of the sixth NMOS, and the VCM node has a push-pull capability, which can quickly establish a common-mode signal when driving the sampling capacitor. The device Vth (about 0.55V) of 1.8V is less than the device Vth (about 1.1V) of 5V after back gate modulation. Vgs_LM3 / 4 = Vgs_LM1 / 2 + Vds_M0. For the sampled 5V NMOS switch, when the power supply is as low as 2.2V, the VCM is 0.55V, and the sampling switch and the feedback switch can still be normally opened, and the circuit works normally.

[0030] As a preferred solution, the connection between the drain of the first PMOS and the drain of the fourth NMOS is the negative output of the amplification module, and the connection between the drain of the second PMOS and the drain of the fifth NMOS is the positive output of the amplification module.

[0031] As a preferred solution, the biasing module includes a sixth NMOS, a seventh NMOS, an eighth NMOS, a ninth NMOS and a fifth PMOS. The gate of the sixth NMOS is connected to the drain of the sixth NMOS and the source of the eighth NMOS, the drain of the sixth NMOS is connected to the gate of the sixth NMOS and the source of the eighth NMOS, and the source of the sixth NMOS is connected to the negative of the power supply. The gate of the seventh NMOS is connected to the drain of the seventh NMOS and the source of the ninth NMOS, the drain of the seventh NMOS is connected to the gate of the seventh NMOS, the source of the ninth NMOS, the sampling module and the feedback module, and the source of the seventh NMOS is connected to the negative of the power supply. The gate of the eighth NMOS is connected to the drain of the eighth NMOS, the gate of the ninth NMOS and the drain of the fifth PMOS, the drain of the eighth NMOS is connected to the gate of the eighth NMOS, the gate of the ninth NMOS and the drain of the fifth PMOS, and the source of the eighth NMOS is connected to the gate and drain of the sixth NMOS. The gate of the ninth NMOS is connected to the drain and gate of the eighth NMOS and the drain of the fifth PMOS, the drain of the ninth NMOS is connected to the positive of the power supply, and the source of the ninth NMOS is connected to the gate, drain of the seventh NMOS, sampling module and feedback module. The gate of the fifth PMOS is connected to the second bias voltage, the drain of the fifth PMOS is connected to the gate of the ninth NMOS, the drain of the eighth NMOS, and the source of the fifth PMOS is connected to the positive of the power supply.

[0032] Specifically, the biasing module provides a bias voltage for the amplification module.

[0033] As a preferred solution, the sampling module comprises a first capacitor, a second capacitor, a first transmission gate switch, a second transmission gate switch, a third transmission gate switch, a fourth transmission gate switch, a first sampling switch, a second sampling switch, a third sampling switch and a fourth sampling switch; one end of the first transmission gate switch is connected with the input positive pole and one end of the third transmission gate respectively, and the other end of the first transmission gate switch is connected with one end of the second transmission gate and one end of the first capacitor respectively; the other end of the second transmission gate switch is connected with the input negative pole and the other end of the fourth transmission gate respectively, and one end of the second transmission gate switch is connected with the other end of the first transmission gate and one end of the first capacitor respectively; one end of the first capacitor is connected with one end of the second transmission gate switch and the other end of the first transmission gate respectively, and the other end of the first capacitor is connected with one end of the first sampling switch and one end of the second sampling switch respectively; one end of the first sampling switch is connected with the other end of the first capacitor and one end of the second sampling switch respectively, and the other end of the first sampling switch is connected with the feedback module, the integral module and the gate of the second NMOS tube respectively; one end of the second sampling switch is connected with the other end of the first capacitor and one end of the first sampling switch respectively, and the other end of the second sampling switch is connected with the feedback module, the source of the ninth NMOS tube and the gate of the seventh NMOS tube respectively; one end of the third transmission gate switch is connected with the input positive pole and one end of the first transmission gate respectively, and the other end of the third transmission gate switch is connected with one end of the fourth transmission gate and one end of the second capacitor respectively; the other end of the fourth transmission gate switch is connected with the input negative pole and the other end of the second transmission gate respectively, and one end of the fourth transmission gate switch is connected with the other end of the third transmission gate and one end of the second capacitor respectively; one end of the second capacitor is connected with one end of the fourth transmission gate switch and the other end of the third transmission gate respectively, and the other end of the second capacitor is connected with one end of the third sampling switch and one end of the fourth sampling switch respectively; one end of the third sampling switch is connected with the other end of the second capacitor and one end of the fourth sampling switch respectively, and the other end of the third sampling switch is connected with the feedback module, the integral module and the gate of the third NMOS tube respectively; one end of the fourth sampling switch is connected with the other end of the second capacitor and one end of the third sampling switch respectively, and the other end of the fourth sampling switch is connected with the feedback module, the source of the ninth NMOS tube, the gate of the seventh NMOS tube and the other end of the second sampling switch respectively.

[0034] Specifically, the sampling module obtains a sampling signal input to the amplifier.

[0035] As a preferred solution, the feedback module comprises a third capacitor, a fourth capacitor, a fifth transmission gate switch, a sixth transmission gate switch, a seventh transmission gate switch, an eighth transmission gate switch, a first feedback switch, a second feedback switch, a third feedback switch and a fourth feedback switch; one end of the fifth transmission gate switch is connected with the positive reference voltage, and the other end of the fifth transmission gate switch is connected with one end of the sixth transmission gate switch and one end of the third capacitor respectively; one end of the sixth transmission gate switch is connected with the other end of the fifth transmission gate switch and one end of the third capacitor respectively, and the other end of the sixth transmission gate switch is connected with the negative reference voltage; one end of the third capacitor is connected with one end of the sixth transmission gate switch and the other end of the fifth transmission gate respectively, and the other end of the third capacitor is connected with one end of the first feedback switch and one end of the second feedback switch respectively; one end of the first feedback switch is connected with the other end of the third capacitor and one end of the second feedback switch respectively, and the other end of the first feedback switch is connected with the integral module, the gate of the second NMOS tube and the other end of the first sampling switch respectively; one end of the second feedback switch is connected with the other end of the third capacitor and one end of the first feedback switch respectively, and the other end of the second feedback switch is connected with the source of the ninth NMOS tube, the gate of the seventh NMOS tube, the other end of the second sampling switch and the other end of the fourth sampling switch respectively; one end of the seventh transmission gate switch is connected with the positive reference voltage, and the other end of the seventh transmission gate switch is connected with one end of the eighth transmission gate switch and one end of the fourth capacitor respectively; one end of the eighth transmission gate switch is connected with the other end of the seventh transmission gate switch and one end of the fourth capacitor respectively, and the other end of the eighth transmission gate switch is connected with the negative reference voltage; one end of the fourth capacitor is connected with one end of the eighth transmission gate switch and the other end of the seventh transmission respectively, and the other end of the fourth capacitor is connected with one end of the third feedback switch and one end of the fourth feedback switch respectively; one end of the third feedback switch is connected with the other end of the fourth capacitor and one end of the fourth feedback switch respectively, and the other end of the third feedback switch is connected with the integral module, the gate of the third NMOS tube and the other end of the third sampling switch respectively; one end of the fourth feedback switch is connected with the other end of the fourth capacitor and one end of the third feedback switch respectively, and the other end of the fourth feedback switch is connected with the source of the ninth NMOS tube, the gate of the seventh NMOS tube, the other end of the second feedback switch, the other end of the second sampling switch and the other end of the fourth sampling switch respectively.

[0036] Specifically, the feedback module inputs the analog-to-digital conversion feedback signal to the amplifier.

[0037] As a preferred solution, the integration module comprises a fifth capacitor and a sixth capacitor; one end of the fifth capacitor is connected with the other end of the first feedback switch, the gate of the second NMOS transistor and the other end of the first sampling switch respectively, and the other end of the fifth capacitor is connected with the drain of the first PMOS transistor and the drain of the fourth NMOS transistor respectively; one end of the sixth capacitor is connected with the other end of the third feedback switch, the gate of the third NMOS transistor and the other end of the third sampling switch respectively, and the other end of the sixth capacitor is connected with the drain of the second PMOS transistor and the drain of the fifth NMOS transistor respectively.

[0038] Specifically, the fifth capacitor and the sixth capacitor change the amplifier output signal into a rectangular wave signal.

[0039] As a preferred solution, the first transmission gate switch, the fourth transmission gate switch, the second sampling switch, the fourth sampling switch, the second feedback switch and the fourth feedback switch are synchronously turned on or turned off, and the second transmission gate switch, the third transmission gate switch, the first sampling switch, the third sampling switch, the first feedback switch and the third feedback switch are synchronously turned on or turned off.

[0040] Specifically, the first transmission gate switch, the fourth transmission gate switch, the second sampling switch, the fourth sampling switch, the second feedback switch and the fourth feedback switch are turned on or turned off at the same time, i.e. these switches are located at the same phase, and the second transmission gate switch, the third transmission gate switch, the first sampling switch, the third sampling switch, the first feedback switch and the third feedback switch are synchronously turned on or turned off, i.e. these switches are located at the same phase.

[0041] As a preferred solution, the threshold voltage of the second NMOS transistor, the third NMOS transistor, the sixth NMOS transistor and the seventh NMOS transistor is a first threshold voltage, the threshold voltage of the first NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor and the fifth PMOS transistor is a second threshold voltage, the second preset voltage is greater than the first preset voltage, and the second threshold voltage is greater than the first threshold voltage.

[0042] Specifically, the second NMOS transistor, the third NMOS transistor, the sixth NMOS transistor and the seventh NMOS transistor are low-voltage MOS transistors, so that the sampling switches and the feedback switches are easy to be turned on.

[0043] Embodiment

[0044] Figure 2 A schematic diagram of an integrator circuit according to the present application is shown.

[0045] As Figure 2As shown, the integrator circuit comprises a sampling module 102, a feedback module 104, an integration module 106, and an amplifier, wherein the amplifier comprises an amplification module 108 and a bias module 110; the sampling module 102 is connected with the amplification module 108 and the bias module 110 respectively, and is configured to collect an input signal; the feedback module 104 is connected with the amplification module 108 and the bias module 110 respectively, and is configured to provide a feedback signal for the amplification module 108; the integration module 106 is connected with the amplification module 108, and is configured to generate a rectangular wave signal; the amplification module 108 is connected with the sampling module 102, the feedback module 104, the integration module 106, and the bias module 110 respectively, and is configured to amplify the input signal; and the bias module 110 is connected with the sampling module 102, the feedback module 104, and the amplification module 108 respectively, and is configured to provide a bias voltage for the amplification module 108.

[0046] The amplification module 108 comprises a first NMOS tube M0, a second NMOS tube LM1, a third NMOS tube LM2, a fourth NMOS tube M3, a fifth NMOS tube M4, a first PMOS tube M5, a second PMOS tube M6, a third PMOS tube M7, and a fourth PMOS tube M8. The gate of the first NMOS tube M0 is connected with a first bias voltage, the source of the first NMOS tube M0 is connected with a negative electrode of a power supply, and the drain of the first NMOS tube M0 is connected with the source of the second NMOS tube LM1 and the source of the third NMOS tube LM2. The gate of the second NMOS tube LM1 is connected with the sampling module 102, the feedback module 104, and the integration module 106, respectively, the source of the second NMOS tube LM1 is connected with the source of the third NMOS tube LM2 and the drain of the first NMOS tube M0, respectively, and the drain of the second NMOS tube LM1 is connected with the source of the fourth NMOS tube M3. The gate of the third NMOS tube LM2 is connected with the sampling module 102, the feedback module 104, and the integration module 106, respectively, the source of the third NMOS tube LM2 is connected with the source of the second NMOS tube LM1 and the drain of the first NMOS tube M0, respectively, and the drain of the third NMOS tube LM2 is connected with the source of the fifth NMOS tube M4. The gate of the fourth NMOS tube M3 is connected with the gate of the fifth NMOS tube M4, the source of the fourth NMOS tube M3 is connected with the drain of the second NMOS tube LM1, and the drain of the fourth NMOS tube M3 is connected with the drain of the first PMOS tube M5. The gate of the fifth NMOS tube M4 is connected with the gate of the fourth NMOS tube M3, the source of the fifth NMOS tube M4 is connected with the drain of the third NMOS tube LM2, and the drain of the fifth NMOS tube M4 is connected with the drain of the second PMOS tube M6. The gate of the first PMOS tube M5 is connected with the gate of the second PMOS tube M6, the source of the first PMOS tube M5 is connected with the drain of the third PMOS tube M7, and the drain of the first PMOS tube M5 is connected with the drain of the fourth NMOS tube M3. The gate of the second PMOS tube M6 is connected with the gate of the first PMOS tube M5, the source of the second PMOS tube M6 is connected with the drain of the fourth PMOS tube M8, and the drain of the second PMOS tube M6 is connected with the drain of the fifth NMOS tube M4. The gate of the third PMOS tube M7 is connected with a second bias voltage, the drain of the third PMOS tube M7 is connected with the source of the first PMOS tube M5, and the source of the third PMOS tube M7 is connected with a positive electrode of the power supply. The gate of the fourth PMOS tube M8 is connected with the second bias voltage, the drain of the fourth PMOS tube M8 is connected with the source of the second PMOS tube M6, and the source of the fourth PMOS tube M8 is connected with the positive electrode of the power supply.

[0047] The drain of the first PMOS M5 and the drain of the fourth NMOS M3 are connected to the negative output of the amplification module 108, and the drain of the second PMOS M6 and the drain of the fifth NMOS M4 are connected to the positive output of the amplification module 108.

[0048] The bias module 110 includes a sixth NMOS LM3, a seventh NMOS LM4, an eighth NMOS M10, a ninth NMOS M11 and a fifth PMOS M9. The gate of the sixth NMOS LM3 is connected to the drain of the sixth NMOS LM3 and the source of the eighth NMOS M10, the drain of the sixth NMOS LM3 is connected to the gate of the sixth NMOS LM3 and the source of the eighth NMOS M10, and the source of the sixth NMOS LM3 is connected to the negative power supply. The gate of the seventh NMOS LM4 is connected to the drain of the seventh NMOS LM4 and the source of the ninth NMOS M11, the drain of the seventh NMOS LM4 is connected to the gate of the seventh NMOS LM4, the source of the ninth NMOS M11, the sampling module 102 and the feedback module 104, and the source of the seventh NMOS LM4 is connected to the negative power supply. The gate of the eighth NMOS M10 is connected to the drain of the eighth NMOS M10, the gate of the ninth NMOS M11 and the drain of the fifth PMOS M9, the drain of the eighth NMOS M10 is connected to the gate of the eighth NMOS M10, the gate of the ninth NMOS M11 and the drain of the fifth PMOS M9, and the source of the eighth NMOS M10 is connected to the gate and drain of the sixth NMOS LM3. The gate of the ninth NMOS M11 is connected to the drain, gate of the eighth NMOS M10 and the drain of the fifth PMOS M9, the drain of the ninth NMOS M11 is connected to the positive power supply, and the source of the ninth NMOS M11 is connected to the gate, drain of the seventh NMOS LM4, the sampling module 102 and the feedback module 104. The gate of the fifth PMOS M9 is connected to the second bias voltage, the drain of the fifth PMOS M9 is connected to the gate of the ninth NMOS M11, the drain of the eighth NMOS M10, and the source of the fifth PMOS M9 is connected to the positive power supply.

[0049] The sampling module 102 comprises a first capacitor CS1, a second capacitor CS2, a first transmission gate switch S11, a second transmission gate switch S21, a third transmission gate switch S22, a fourth transmission gate switch S12, a first sampling switch S24, a second sampling switch S14, a third sampling switch S25 and a fourth sampling switch S15. One end of the first transmission gate switch S11 is connected to the input positive pole and one end of the third transmission gate, respectively, and the other end of the first transmission gate switch S11 is connected to one end of the second transmission gate and one end of the first capacitor CS1, respectively. The other end of the second transmission gate switch S21 is connected to the input negative pole and the other end of the fourth transmission gate, respectively, and one end of the second transmission gate switch S21 is connected to the other end of the first transmission gate and one end of the first capacitor CS1, respectively. One end of the first capacitor CS1 is connected to one end of the second transmission gate switch S21 and the other end of the first transmission gate, respectively, and the other end of the first capacitor CS1 is connected to one end of the first sampling switch S24 and one end of the second sampling switch S14, respectively. One end of the first sampling switch S24 is connected to the other end of the first capacitor CS1 and one end of the second sampling switch S14, respectively, and the other end of the first sampling switch S24 is connected to the feedback module 104, the integral module 106 and the gate of the second NMOS tube LM1, respectively. One end of the second sampling switch S14 is connected to the other end of the first capacitor CS1 and one end of the first sampling switch S24, respectively, and the other end of the second sampling switch S14 is connected to the feedback module 104, the source of the ninth NMOS tube M11 and the gate of the seventh NMOS tube LM4, respectively. One end of the third transmission gate switch S22 is connected to the input positive pole and one end of the first transmission gate, respectively, and the other end of the third transmission gate switch S22 is connected to one end of the fourth transmission gate and one end of the second capacitor CS2, respectively. The other end of the fourth transmission gate switch S12 is connected to the input negative pole and the other end of the second transmission gate, respectively, and one end of the fourth transmission gate switch S12 is connected to the other end of the third transmission gate and one end of the second capacitor CS2, respectively. One end of the second capacitor CS2 is connected to one end of the fourth transmission gate switch S12 and the other end of the third transmission gate, respectively, and the other end of the second capacitor CS2 is connected to one end of the third sampling switch S25 and one end of the fourth sampling switch S15, respectively. One end of the third sampling switch S25 is connected to the other end of the second capacitor CS2 and one end of the fourth sampling switch S15, respectively, and the other end of the third sampling switch S25 is connected to the feedback module 104, the integral module 106 and the gate of the third NMOS tube LM2, respectively. One end of the fourth sampling switch S15 is connected to the other end of the second capacitor CS2 and one end of the third sampling switch S25, respectively, and the other end of the fourth sampling switch S15 is connected to the feedback module 104, the source of the ninth NMOS tube M11, the gate of the seventh NMOS tube LM4 and the other end of the second sampling switch S14, respectively.

[0050] The feedback module 104 comprises a third capacitor Cdac1, a fourth capacitor Cdac2, a fifth transmission gate switch S31, a sixth transmission gate switch S32, a seventh transmission gate switch S33, an eighth transmission gate switch S34, a first feedback switch S23, a second feedback switch S13, a third feedback switch S26 and a fourth feedback switch S16. One end of the fifth transmission gate switch S31 is connected with the positive reference voltage, and the other end of the fifth transmission gate switch S31 is connected with one end of the sixth transmission gate switch S32 and one end of the third capacitor Cdac1 respectively. One end of the sixth transmission gate switch S32 is connected with the other end of the fifth transmission gate switch S31 and one end of the third capacitor Cdac1 respectively, and the other end of the sixth transmission gate switch S32 is connected with the negative reference voltage. One end of the third capacitor Cdac1 is connected with one end of the sixth transmission gate switch S32 and the other end of the fifth transmission gate respectively, and the other end of the third capacitor Cdac1 is connected with one end of the first feedback switch S23 and one end of the second feedback switch S13 respectively. One end of the first feedback switch S23 is connected with the other end of the third capacitor Cdac1 and one end of the second feedback switch S13 respectively, and the other end of the first feedback switch S23 is connected with the integral module 106, the gate of the second NMOS tube LM1 and the other end of the first sampling switch S24 respectively. One end of the second feedback switch S13 is connected with the other end of the third capacitor Cdac1 and one end of the first feedback switch S23 respectively, and the other end of the second feedback switch S13 is connected with the source of the ninth NMOS tube M11, the gate of the seventh NMOS tube LM4, the other end of the second sampling switch S14 and the other end of the fourth sampling switch S15 respectively. One end of the seventh transmission gate switch S33 is connected with the positive reference voltage, and the other end of the seventh transmission gate switch S33 is connected with one end of the eighth transmission gate switch S34 and one end of the fourth capacitor Cdac2 respectively. One end of the eighth transmission gate switch S34 is connected with the other end of the seventh transmission gate switch S33 and one end of the fourth capacitor Cdac2 respectively, and the other end of the eighth transmission gate switch S34 is connected with the negative reference voltage. One end of the fourth capacitor Cdac2 is connected with one end of the eighth transmission gate switch S34 and the other end of the seventh transmission gate respectively, and the other end of the fourth capacitor Cdac2 is connected with one end of the third feedback switch S26 and one end of the fourth feedback switch S16 respectively. One end of the third feedback switch S26 is connected with the other end of the fourth capacitor Cdac2 and one end of the fourth feedback switch S16 respectively, and the other end of the third feedback switch S26 is connected with the integral module 106, the gate of the third NMOS tube LM2 and the other end of the third sampling switch S25 respectively.One end of the fourth feedback switch S16 is connected with the other end of the fourth capacitor Cdac2 and one end of the third feedback switch S26 respectively, and the other end of the fourth feedback switch S16 is connected with the source of the ninth NMOS M11, the gate of the seventh NMOS LM4, the other end of the second feedback switch S13, the other end of the second sampling switch S14 and the other end of the fourth sampling switch S15 respectively.

[0051] The integral module 106 includes the fifth capacitor Cint1 and the sixth capacitor Cint2, one end of the fifth capacitor Cint1 is connected with the other end of the first feedback switch S23, the gate of the second NMOS LM1 and the other end of the first sampling switch S24 respectively, and the other end of the fifth capacitor Cint1 is connected with the drain of the first PMOS M5 and the drain of the fourth NMOS M3 respectively, one end of the sixth capacitor Cint2 is connected with the other end of the third feedback switch S26, the gate of the third NMOS LM2 and the other end of the third sampling switch S25 respectively, and the other end of the sixth capacitor Cint2 is connected with the drain of the second PMOS M6 and the drain of the fifth NMOS M4 respectively.

[0052] The first transmission gate switch S11, the fourth transmission gate switch S12, the second sampling switch S14, the fourth sampling switch S15, the second feedback switch S13 and the fourth feedback switch S16 are synchronously turned on or turned off, and the second transmission gate switch S21, the third transmission gate switch S22, the first sampling switch S24, the third sampling switch S25, the first feedback switch S23 and the third feedback switch S26 are synchronously turned on or turned off.

[0053] The threshold voltage of the second NMOS LM1, the third NMOS LM2, the sixth NMOS LM3 and the seventh NMOS LM4 is the first threshold voltage, the threshold voltage of the first NMOS M0, the fourth NMOS M3, the fifth NMOS M4, the eighth NMOS M10, the ninth NMOS M11, the first PMOS M5, the second PMOS M6, the third PMOS M7, the fourth PMOS M8 and the fifth PMOS M9 is the second threshold voltage, the second preset voltage is greater than the first preset voltage, and the second threshold voltage is greater than the first threshold voltage.

[0054] The above has described the embodiments of the present application, the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. An integrator circuit, characterized in that, include: The system includes a sampling module, a feedback module, an integration module, and an amplifier, wherein the amplifier includes an amplification module and a bias module. The sampling module is connected to the amplification module and the bias module respectively, and the sampling module is used to acquire the input signal; The feedback module is connected to the amplification module and the bias module respectively, and the feedback module uses... This provides a feedback signal for the amplification module; The integration module is connected to the amplification module, and the integration module is used to generate a rectangular wave signal. The amplification module is connected to the sampling module, the feedback module, the integration module, and the bias module respectively, and the amplification module is used to amplify the input signal; The bias module is connected to the sampling module, the feedback module, and the amplification module respectively, and the bias module is used to provide a bias voltage to the amplification module; The bias module includes a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a fifth PMOS transistor; The gate of the sixth NMOS transistor is connected to its drain and the source of the eighth NMOS transistor. The drain of the sixth NMOS transistor is connected to its gate and the source of the eighth NMOS transistor. The source of the sixth NMOS transistor is connected to the negative power supply. The gate of the seventh NMOS transistor is connected to its drain and the source of the ninth NMOS transistor. The drain of the seventh NMOS transistor is connected to its gate, the source of the ninth NMOS transistor, the sampling module, and the feedback module, respectively. The source of the seventh NMOS transistor is connected to the negative power supply. The gate of the eighth NMOS transistor is connected to its drain, the gate of the ninth NMOS transistor, and the drain of the fifth PMOS transistor. The drain of the eighth NMOS transistor is connected to its gate, the gate of the ninth NMOS transistor, and the drain of the fifth PMOS transistor. The source of the eighth NMOS transistor is connected to the gate and drain of the sixth NMOS transistor. The gate of the ninth NMOS transistor is connected to the drain and gate of the eighth NMOS transistor and the drain of the fifth PMOS transistor. The drain of the ninth NMOS transistor is connected to the positive power supply. The source of the ninth NMOS transistor is connected to the gate and drain of the seventh NMOS transistor, the sampling module, and the feedback module, respectively. The gate of the fifth PMOS transistor is connected to the second bias voltage, the drain of the fifth PMOS transistor is connected to the gate of the ninth NMOS transistor, the drain and gate of the eighth NMOS transistor, and the source of the fifth PMOS transistor is connected to the positive power supply.

2. The integrator circuit according to claim 1, characterized in that, The amplification module includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor; The gate of the first NMOS transistor is connected to the first bias voltage, the source of the first NMOS transistor is connected to the negative power supply, and the drain of the first NMOS transistor is connected to the source of the second NMOS transistor and the source of the third NMOS transistor. The gate of the second NMOS transistor is connected to the sampling module, the feedback module and the integration module respectively; the source of the second NMOS transistor is connected to the source of the third NMOS transistor and the drain of the first NMOS transistor respectively; and the drain of the second NMOS transistor is connected to the source of the fourth NMOS transistor. The gate of the third NMOS transistor is connected to the sampling module, the feedback module and the integration module respectively. The source of the third NMOS transistor is connected to the source of the second NMOS transistor and the drain of the first NMOS transistor respectively. The drain of the third NMOS transistor is connected to the source of the fifth NMOS transistor. The gate of the fourth NMOS transistor is connected to the gate of the fifth NMOS transistor, the source of the fourth NMOS transistor is connected to the drain of the second NMOS transistor, and the drain of the fourth NMOS transistor is connected to the drain of the first PMOS transistor. The gate of the fifth NMOS transistor is connected to the gate of the fourth NMOS transistor, the source of the fifth NMOS transistor is connected to the drain of the third NMOS transistor, and the drain of the fifth NMOS transistor is connected to the drain of the second PMOS transistor. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor, the source of the first PMOS transistor is connected to the drain of the third PMOS transistor, and the drain of the first PMOS transistor is connected to the drain of the fourth NMOS transistor. The gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, the source of the second PMOS transistor is connected to the drain of the fourth PMOS transistor, and the drain of the second PMOS transistor is connected to the drain of the fifth NMOS transistor. The gate of the third PMOS transistor is connected to the second bias voltage, the drain of the third PMOS transistor is connected to the source of the first PMOS transistor, and the source of the third PMOS transistor is connected to the positive terminal of the power supply. The gate of the fourth PMOS transistor is connected to the second bias voltage, the drain of the fourth PMOS transistor is connected to the source of the second PMOS transistor, and the source of the fourth PMOS transistor is connected to the positive terminal of the power supply.

3. The integrator circuit according to claim 2, characterized in that, The connection between the drain of the first PMOS transistor and the drain of the fourth NMOS transistor is the negative output of the amplification module, and the connection between the drain of the second PMOS transistor and the drain of the fifth NMOS transistor is the positive output of the amplification module.

4. The integrator circuit according to claim 2, characterized in that, The sampling module includes a first capacitor, a second capacitor, a first transmission gate switch, a second transmission gate switch, a third transmission gate switch, a fourth transmission gate switch, a first sampling switch, a second sampling switch, a third sampling switch, and a fourth sampling switch; One end of the first transmission gate switch is connected to the positive input terminal and one end of the third transmission gate, respectively; the other end of the first transmission gate switch is connected to one end of the second transmission gate and one end of the first capacitor, respectively. The other end of the second transmission gate switch is connected to the negative input terminal and the other end of the fourth transmission gate, respectively; one end of the second transmission gate switch is connected to the other end of the first transmission gate and one end of the first capacitor, respectively. One end of the first capacitor is connected to one end of the second transmission gate switch and the other end of the first transmission gate, and the other end of the first capacitor is connected to one end of the first sampling switch and one end of the second sampling switch. One end of the first sampling switch is connected to the other end of the first capacitor and one end of the second sampling switch, and the other end of the first sampling switch is connected to the feedback module, the integration module, and the gate of the second NMOS transistor. One end of the second sampling switch is connected to the other end of the first capacitor and one end of the first sampling switch, respectively. The other end of the second sampling switch is connected to the feedback module, the source of the ninth NMOS transistor, and the gate of the seventh NMOS transistor, respectively. One end of the third transmission gate switch is connected to the positive input terminal and one end of the first transmission gate, respectively; the other end of the third transmission gate switch is connected to one end of the fourth transmission gate and one end of the second capacitor, respectively. The other end of the fourth transmission gate switch is connected to the negative input terminal and the other end of the second transmission gate, and one end of the fourth transmission gate switch is connected to the other end of the third transmission gate and one end of the second capacitor. One end of the second capacitor is connected to one end of the fourth transmission gate switch and the other end of the third transmission gate, and the other end of the second capacitor is connected to one end of the third sampling switch and one end of the fourth sampling switch. One end of the third sampling switch is connected to the other end of the second capacitor and one end of the fourth sampling switch, respectively; the other end of the third sampling switch is connected to the feedback module, the integration module and the gate of the third NMOS transistor, respectively. One end of the fourth sampling switch is connected to the other end of the second capacitor and one end of the third sampling switch, respectively. The other end of the fourth sampling switch is connected to the feedback module, the source of the ninth NMOS transistor, the gate of the seventh NMOS transistor, and the other end of the second sampling switch, respectively.

5. The integrator circuit according to claim 4, characterized in that, The feedback module includes a third capacitor, a fourth capacitor, a fifth transmission gate switch, a sixth transmission gate switch, a seventh transmission gate switch, an eighth transmission gate switch, a first feedback switch, a second feedback switch, a third feedback switch, and a fourth feedback switch; One end of the fifth transmission gate switch is connected to the positive reference voltage, and the other end of the fifth transmission gate switch is connected to one end of the sixth transmission gate switch and one end of the third capacitor, respectively. One end of the sixth transmission gate switch is connected to the other end of the fifth transmission gate switch and one end of the third capacitor, and the other end of the sixth transmission gate switch is connected to the negative reference voltage. One end of the third capacitor is connected to one end of the sixth transmission gate switch and the other end of the fifth transmission gate, respectively; the other end of the third capacitor is connected to one end of the first feedback switch and one end of the second feedback switch, respectively. One end of the first feedback switch is connected to the other end of the third capacitor and one end of the second feedback switch, respectively. The other end of the first feedback switch is connected to the integration module, the gate of the second NMOS transistor and the other end of the first sampling switch, respectively. One end of the second feedback switch is connected to the other end of the third capacitor and one end of the first feedback switch, respectively. The other end of the second feedback switch is connected to the source of the ninth NMOS transistor, the gate of the seventh NMOS transistor, the other end of the second sampling switch, and the other end of the fourth sampling switch, respectively. One end of the seventh transmission gate switch is connected to the positive reference voltage, and the other end of the seventh transmission gate switch is connected to one end of the eighth transmission gate switch and one end of the fourth capacitor, respectively. One end of the eighth transmission gate switch is connected to the other end of the seventh transmission gate switch and one end of the fourth capacitor, respectively; the other end of the eighth transmission gate switch is connected to the negative reference voltage. One end of the fourth capacitor is connected to one end of the eighth transmission gate switch and the other end of the seventh transmission gate, respectively; the other end of the fourth capacitor is connected to one end of the third feedback switch and one end of the fourth feedback switch, respectively. One end of the third feedback switch is connected to the other end of the fourth capacitor and one end of the fourth feedback switch, respectively; the other end of the third feedback switch is connected to the integration module, the gate of the third NMOS transistor and the other end of the third sampling switch, respectively. One end of the fourth feedback switch is connected to the other end of the fourth capacitor and one end of the third feedback switch, respectively. The other end of the fourth feedback switch is connected to the source of the ninth NMOS transistor, the gate of the seventh NMOS transistor, the other end of the second feedback switch, the other end of the second sampling switch, and the other end of the fourth sampling switch, respectively.

6. The integrator circuit according to claim 5, characterized in that, The integration module includes a fifth capacitor and a sixth capacitor; One end of the fifth capacitor is connected to the other end of the first feedback switch, the gate of the second NMOS transistor, and the other end of the first sampling switch, respectively. The other end of the fifth capacitor is connected to the drain of the first PMOS transistor and the drain of the fourth NMOS transistor, respectively. One end of the sixth capacitor is connected to the other end of the third feedback switch, the gate of the third NMOS transistor, and the other end of the third sampling switch, respectively. The other end of the sixth capacitor is connected to the drain of the second PMOS transistor and the drain of the fifth NMOS transistor, respectively.

7. The integrator circuit according to claim 6, characterized in that, The first transmission gate switch, the fourth transmission gate switch, the second sampling switch, the fourth sampling switch, the second feedback switch, and the fourth feedback switch are simultaneously turned on or off, and the second transmission gate switch, the third transmission gate switch, the first sampling switch, the third sampling switch, the first feedback switch, and the third feedback switch are simultaneously turned on or off.

8. The integrator circuit according to claim 7, characterized in that, The threshold voltages of the second, third, sixth, and seventh NMOS transistors are the first threshold voltages, and the threshold voltages of the first, fourth, fifth, eighth, and ninth NMOS transistors, as well as the first, second, third, fourth, and fifth PMOS transistors, are the second threshold voltages, which are greater than the first threshold voltages.

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