Method and circuit for eliminating metastability effects in non-binary differential analog-to-digital converters
By using a synchronous clock, an N-ary code decoder, and a subtractor in a non-binary differential analog-to-digital converter, the performance degradation caused by metastability was resolved, the signal-to-noise distortion ratio was restored, and the performance of the ADC was improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TONGJI UNIV
- Filing Date
- 2022-04-15
- Publication Date
- 2026-05-29
AI Technical Summary
In high-speed, high-precision ADCs, comparators are susceptible to noise, leading to increased metastability and affecting the accuracy of the ADC output codewords. This is especially true in ADCs using synchronous clocks, which results in a decrease in the signal-to-noise ratio (SNDR).
A non-binary differential analog-to-digital converter with a synchronous clock, combined with an N-ary code decoder and an N-ary subtractor, converts non-binary digital codes into N-ary digital codes and performs subtraction operations to eliminate metastability effects.
By combining binary code decoding and a subtractor, the signal-to-noise ratio (SNDR) was restored to the level without metastability, thus eliminating the negative impact of metastability on ADC performance.
Smart Images
Figure CN114826260B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit technology and relates to a method and circuit for eliminating the metastability effects of a non-binary differential analog-to-digital converter. Background Technology
[0002] With the advancement and development of wireless communication and electronic science and technology, people's lives are becoming increasingly reliant on electronic devices. Various portable electronic devices, such as mobile phones and smart bracelets, have become indispensable for daily work and life. In today's digital world, where computing power is constantly increasing, the realization of concepts such as autonomous driving and the Internet of Things requires us to obtain more comprehensive real-time analog information from the analog domain of the real world more quickly. This places higher demands on the performance of analog-to-digital converter (ADC) chips, making the design of high-speed, high-precision, and low-power ADCs a key research focus for experts and scholars both domestically and internationally.
[0003] However, with advancements in manufacturing processes, the feature size of CMOS devices is shrinking, and the operating power supply voltage is decreasing. This leads to lower LSB voltages in high-speed, high-precision ADCs, making comparators highly susceptible to noise and increasing the likelihood of metastability. This, in turn, affects the accuracy of the ADC output codewords, a situation that is particularly unavoidable in ADCs using synchronous clocks. The presence of metastability reduces the ADC's signal-to-noise ratio (SNDR), severely impacting its performance. Summary of the Invention
[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method and circuit for eliminating the metastability of non-binary differential analog-to-digital converters, so as to solve the problem of performance degradation of non-binary differential analog-to-digital converters caused by the occurrence of comparator metastability.
[0005] According to one aspect of the present invention, a circuit is provided to eliminate the metastability effects of a non-binary differential analog-to-digital converter, comprising:
[0006] A non-binary differential analog-to-digital converter with a synchronous clock is used to process the input differential analog signal to obtain two strings of non-binary digital codes;
[0007] An N-ary code decoder, wherein the input of the N-ary code decoder is coupled to the output of the non-binary differential analog-to-digital converter, is used to convert two strings of non-binary digital codes output by the analog-to-digital converter into two strings of N-ary digital codes;
[0008] An N-ary subtractor, wherein the input of the N-ary subtractor is coupled to the output of the N-ary code decoder, is used to subtract two strings of N-ary digital codes decoded by the N-ary code decoder to obtain a string of N-ary digital codes.
[0009] In a preferred embodiment of the present invention, the non-binary analog-to-digital converter is a non-binary differential analog-to-digital converter with redundant bits.
[0010] In a preferred embodiment of the present invention, the non-binary differential analog-to-digital converter is a 16-bit SARADC.
[0011] In a preferred embodiment of the present invention, the N-ary code decoder is an N-bit signed code decoder. Preferably, the N-ary code decoder includes a binary code decoder, the input of which is coupled to the output of a non-binary differential 16-bit SAR ADC using a synchronous clock, for converting two strings of non-binary digital codes output by the ADC into two strings of signed binary digital codes.
[0012] In a preferred embodiment of the present invention, the N-ary subtractor is an N-bit signed subtractor. Preferably, the N-ary subtractor includes a binary subtractor, the input of which is coupled to the output of a binary code decoder, for subtracting two strings of signed binary codes output by the decoder to obtain a string of signed binary codes, which is then output.
[0013] According to another aspect of the present invention, a method for eliminating metastability effects in a non-binary differential analog-to-digital converter is also provided, comprising:
[0014] S1. The input differential analog signal is converted into two strings of non-binary digital codes by using a non-binary differential analog-to-digital converter with a synchronous clock;
[0015] S2. Convert the two strings of non-binary digital codes into two strings of N-ary digital codes using an N-ary code decoder;
[0016] S3. Subtract two strings of N-ary digit codes using an N-ary subtractor to obtain a single string of N-ary digit codes, and then output the result.
[0017] In a preferred embodiment of the present invention, the non-binary analog-to-digital converter is a non-binary differential analog-to-digital converter with redundant bits.
[0018] In a preferred embodiment of the present invention, the non-binary differential analog-to-digital converter is a 16-bit SARADC.
[0019] In a preferred embodiment of the present invention, the N-ary code decoder is an N-bit signed code decoder. Preferably, the N-ary code decoder includes a binary code decoder, the input of which is coupled to the output of a non-binary differential 16-bit SAR ADC using a synchronous clock, for converting two strings of non-binary digital codes output by the ADC into two strings of signed binary digital codes.
[0020] In a preferred embodiment of the present invention, the N-ary subtractor is an N-bit signed subtractor. Preferably, the N-ary subtractor includes a binary subtractor, the input of which is coupled to the output of a binary code decoder, for subtracting two strings of signed binary codes output by the decoder to obtain a string of signed binary codes, which is then output.
[0021] The circuit provided by this invention for eliminating the metastability effects of a non-binary differential analog-to-digital converter (ADC) uses a binary code decoder to convert two strings of non-binary digital codes output by the ADC into two strings of signed binary digital codes. Then, the two strings of signed binary digital codes output by the decoder are subtracted by the binary subtractor to obtain a string of signed binary digital codes. The signal-to-noise distortion ratio (SNDR) of this string of digital codes is restored to the level when there is no metastability, thereby eliminating the impact of metastability on ADC performance. Attached Figure Description
[0022] To further illustrate the various embodiments, the present invention provides accompanying drawings. These drawings are part of the disclosure of the present invention, primarily used to illustrate the embodiments and to explain the operating principles of the embodiments in conjunction with the relevant descriptions in the specification. With reference to these drawings, those skilled in the art should be able to understand other possible implementations and the advantages of the present invention. Components in the drawings are not drawn to scale, and similar component symbols are generally used to represent similar components.
[0023] Figure 1 This is a block diagram of a circuit for eliminating the metastability effects of a non-binary differential analog-to-digital converter according to an embodiment of the present invention.
[0024] Figure 2 yes Figure 1 The circuit shown is a schematic diagram of a 16-bit SARADC (non-binary differential analog-to-digital converter) using a synchronous clock.
[0025] Figure 3 yes Figure 2 The figure shows the FFT simulation results of a 16-bit SARADC with a non-binary differential analog-to-digital converter in the absence of metastability.
[0026] Figure 4This is a simulation result diagram showing the metastability occurring during the 13th comparison of the comparator.
[0027] Figure 5 The image shows the FFT simulation results of a 16-bit SARADC (non-binary differential analog-to-digital converter) under metastability conditions during the 13th comparison of the comparator.
[0028] Figure 6 The image shows the FFT simulation results of a 16-bit SARADC (non-binary differential analog-to-digital converter) that experiences metastability during the 13th comparison of the comparator, and the effects of metastability are eliminated by the circuit proposed in this invention.
[0029] Figure 7 This is a simulation result diagram showing the metastability occurring during the second-to-last comparison of the comparator;
[0030] Figure 8 The image shows the FFT simulation results of a 16-bit SARADC (non-binary differential analog-to-digital converter) under metastability conditions during the penultimate comparison of the comparator.
[0031] Figure 9 The image shows the FFT simulation results of a 16-bit SARADC (non-binary differential analog-to-digital converter) that experiences metastability during the second-to-last comparison of the comparator, and the results after eliminating the metastability effect using the circuit proposed in this invention.
[0032] Figure 10 The image shows a comparison of FFT simulations of a 16-bit SARADC (non-binary differential analog-to-digital converter) before and after metastability is eliminated using the circuit proposed in this invention. Detailed Implementation
[0033] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, so as to better understand the purpose, features and advantages of the present invention. It should be understood that the embodiments shown in the drawings are not intended to limit the scope of the present invention, but are only for illustrating the essential spirit of the technical solution of the present invention.
[0034] In the following description, certain specific details are set forth for the purpose of illustrating various disclosed embodiments in order to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the art will recognize that embodiments may be practiced without one or more of these specific details. In other instances, well-known apparatuses, structures, and techniques associated with this application may not have been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.
[0035] Throughout this specification, references to "an embodiment" or "an embodiment" indicate that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Therefore, the appearance of "in an embodiment" or "an embodiment" in various places throughout the specification does not necessarily refer to the same embodiment. Furthermore, a particular feature, structure, or characteristic may be combined in any manner in one or more embodiments.
[0036] In the following description, in order to clearly demonstrate the structure and working method of the present invention, a number of directional terms will be used. However, terms such as "front", "back", "left", "right", "outside", "inside", "outward", "inward", "up", and "down" should be understood as convenient terms and not as limiting terms.
[0037] This invention provides a method and circuit for eliminating the effects of metastability in non-binary differential analog-to-digital converters (ADCs), addressing the performance degradation of ADCs caused by comparator metastability. Specific embodiments will be described below.
[0038] Please see Figure 1 , Figure 1 A block diagram illustrating the principle of the circuit for eliminating the metastability effects of a non-binary differential analog-to-digital converter provided by this invention is shown. Figure 1 As shown, the circuit includes: a non-binary differential analog-to-digital converter 1 using a synchronous clock; a binary code decoder 2, the input of which is coupled to the output of the non-binary differential analog-to-digital converter 1; and a binary subtractor 3, the input of which is coupled to the output of the binary code decoder 2. The non-binary differential analog-to-digital converter 1 receives an analog input signal at its input, converts the differential input analog signal into differential non-binary digital code, resulting in two strings of non-binary digital codes. The binary code decoder 2 converts these two strings of non-binary digital codes into two strings of binary digital codes. The binary subtractor 3 then subtracts the two strings of binary digital codes to obtain a single binary digital code, which is then output. This digital code restores the signal-to-noise ratio (SNDR) to the level before metastability occurs, thus eliminating the impact of metastability on ADC performance. It should be understood that this embodiment is described in binary, but the circuit is also adaptable to other number systems, i.e., it can sample an N-ary code decoder and an N-ary subtractor. Preferably, the N-ary code decoder is an N-bit signed code decoder. The N-ary subtractor is an N-bit signed subtractor.
[0039] Please see Figure 2 , Figure 2 A schematic diagram of a non-binary differential analog-to-digital converter 1 using a synchronous clock is shown. Figure 2 As shown, the non-binary differential analog-to-digital converter 1 using a synchronous clock has the functions of dual-ended input and dual-ended output. The differential input signals Vin and Vip are sampled by the DAC capacitor array through the clock-controlled bootstrap switch. Then, the control signal generated by the clock signal is converted and compared by the control logic circuit. Finally, the output register outputs the result of the comparator in dual-ended mode.
[0040] Preferably, the non-binary differential analog-to-digital converter 1 is a non-binary differential analog-to-digital converter with redundant bits. In one specific embodiment, the non-binary differential analog-to-digital converter 1 can be a commercially available 16-bit SARADC.
[0041] To further demonstrate the effectiveness of the circuit described in this invention for eliminating the metastability effects of a non-binary differential analog-to-digital converter, the following simulation experiments were conducted. The simulation experiments employed dynamic circuit simulation technology in Cadence simulation software, using TSMC 28nm CMOS technology, with a power supply voltage of 1V and a high-level reset output for the comparator. The simulation results are as follows: Figures 3 to 10 As shown.
[0042] Figure 3 The figure shows the 64-point FFT simulation results of a 16-bit SARADC with a synchronous clock and a non-binary differential analog-to-digital converter under metastability-free conditions. In this embodiment, a signal-to-distortion noise ratio (SNDR) of 95.62 dB, an effective bit length (ENOB) of 15.59, and a spurious-free dynamic range (SFDR) of 99.99 dB are achieved.
[0043] Figure 4 The simulation results are shown when the metastability occurs during the 13th comparison of the comparator. At this time, the comparator has no result during the 13th comparison, and both outputs of the comparator, Comn and Comp, are high.
[0044] Figure 5 The figure shows the 64-point FFT simulation results of a 16-bit SARADC with a synchronous clock and a non-binary differential analog-to-digital converter (SARADC) in a metastable state during the 13th comparator comparison. In this embodiment, the SNDR is 70.10 dB, ENOB is 11.35, and SFDR is 83.82 dB.
[0045] Figure 6The figure shows the FFT simulation results at 64 points for a 16-bit SARADC using a synchronous clock non-binary differential analog-to-digital converter, after metastability occurs during the 13th comparator comparison and the metastability effect is eliminated by the circuit proposed in this invention. In this embodiment, the SNDR is 95.51dB, ENOB is 15.57, and SFDR is 101.68dB.
[0046] Figure 7 The simulation results are shown when metastability occurs during the penultimate comparison of the comparator. At this point, the comparator produces no result during the penultimate comparison, and both the outputs Comn and Comp at the comparator's terminals are high.
[0047] Figure 8 The figure shows the 64-point FFT simulation results of a 16-bit SARADC with a synchronous clock and a non-binary differential analog-to-digital converter, under metastability conditions occurring during the penultimate comparator comparison. In this embodiment, an SNDR of 93.47 dB, an ENOB of 15.23 dB, and an SFDR of 99.75 dB are achieved.
[0048] Figure 9 The figure shows the FFT simulation results at 64 points for the 16-bit SARADC (non-binary differential analog-to-digital converter) using synchronous clock in this invention, after metastability occurs during the penultimate comparison of the comparator and the metastability effect is eliminated by the circuit proposed in this invention. In this embodiment, the SNDR is 95.60dB, ENOB is 15.59, and SFDR is 101.71dB.
[0049] Figure 10 The diagram shows a 64-point FFT simulation comparison of a 16-bit SARADC (non-binary differential analog-to-digital converter) using a synchronous clock, before and after metastability was eliminated using the circuit proposed in this invention. It can be seen that the circuit proposed in this invention can eliminate the effects of metastability, restoring the SNDR (Single-bit Differential Response Rate) to the level before metastability occurred. Furthermore, metastability occurring in earlier comparison cycles leads to greater SNDR decay, which is actually proportional to the capacitor weight of the DAC array corresponding to that comparison cycle; that is, the larger the capacitor weight of the bit where metastability occurred, the greater the SNDR decay.
[0050] Furthermore, the present invention also provides a method for eliminating the metastability effects of non-binary differential analog-to-digital converters, comprising the following steps:
[0051] S1. The input differential analog signal is converted into two strings of non-binary digital codes by using a non-binary differential analog-to-digital converter with a synchronous clock;
[0052] S2. The two strings of non-binary digital codes output from the non-binary differential analog-to-digital converter are converted into two strings of signed N-ary digital codes using an N-ary code decoder.
[0053] S3. Then, the two strings of signed N-ary digit codes output by the decoder are subtracted by the N-ary subtractor to obtain a string of signed N-ary digit codes.
[0054] Through the above steps, the signal-to-noise ratio (SNDR) of this digital code is restored to the level before metastability occurs, thus eliminating the impact of metastability on ADC performance. Furthermore, in actual chip operation, it is subject to various noises, and metastability occurs more frequently than in simulations, making this invention more practically significant.
[0055] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A circuit for eliminating the metastability effects of a non-binary differential analog-to-digital converter, characterized in that, include: A 16-bit SAR ADC with a synchronous clock is used to process the input differential analog signal to obtain two strings of non-binary digital codes. An N-ary code decoder, wherein the input of the N-ary code decoder is coupled to the output of the non-binary differential analog-to-digital converter, is used to convert two strings of non-binary digital codes output by the analog-to-digital converter into two strings of N-ary digital codes with signed bits. An N-ary subtractor, wherein the input of the N-ary subtractor is coupled to the output of the N-ary code decoder, is used to subtract two strings of signed N-ary numbers decoded by the N-ary code decoder to obtain a string of N-ary numbers.
2. The circuit according to claim 1, characterized in that, The non-binary differential analog-to-digital converter is a non-binary differential analog-to-digital converter with redundant bits.
3. The circuit according to claim 1, characterized in that, The N-ary code decoder is an N-bit signed code decoder.
4. The circuit according to claim 1, characterized in that, The N-ary subtractor is an N-bit signed subtractor.
5. A method for eliminating metastability effects in non-binary differential analog-to-digital converters, characterized in that, Includes the following steps: S1. The input differential analog signal is converted into two strings of non-binary digital codes by using a 16-bit SAR ADC with a synchronous clock. S2. Convert the two strings of non-binary digital codes into two strings of signed N-ary digital codes using an N-ary code decoder; S3. Subtract two strings of signed N-ary digit codes using an N-ary subtractor to obtain a single string of N-ary digit codes, and then output the result.
6. The method according to claim 5, characterized in that, The non-binary differential analog-to-digital converter is a non-binary differential analog-to-digital converter with redundant bits.
7. The method according to claim 5, characterized in that, The N-ary code decoder is an N-bit signed code decoder.
8. The method according to claim 5, characterized in that, The N-ary subtractor is an N-bit signed subtractor.