Analog-to-digital conversion system and method

Abstract

An analog-to-digital conversion system and an analog-to-digital conversion method, the analog-to-digital conversion system comprises an analog-to-digital converter and a power supply. The analog-to-digital converter is used to convert an analog input signal to generate a digital output signal, and to generate a control signal according to the state of the converted analog input signal. The power supply is used to provide a supply voltage to the analog-to-digital converter, and to change the ability of the power supply to provide a supply current according to the control signal to stabilize the supply voltage.

Description

Technical Field

[0001] The invention relates to a conversion system, and in particular to an analog-to-digital conversion system and an analog-to-digital conversion method. Background Art

[0002] The analog-to-digital converter consumes a large amount of power during operation. When the power supply device fails to provide sufficient power, the voltage output by the power supply device will drop. At this time, the performance of the analog-to-digital converter operation will be reduced. However, the analog-to-digital converter does not consume a large amount of power in every period of operation. Therefore, how the power supply device can be used with the analog-to-digital converter to perform operations that consume a large amount of power to maintain the performance of the analog-to-digital converter operation has become one of the problems that the art is eager to solve. Summary of the invention

[0003] The present invention discloses an analog-to-digital conversion system, which includes an analog-to-digital converter and a power supply. The analog-to-digital converter is used to convert an analog input signal to generate a digital output signal, and is used to generate a control signal according to the state of the converted analog input signal. The power supply is used to provide a supply voltage to the analog-to-digital converter, and change the ability of the power supply to provide a supply current according to the control signal to stabilize the supply voltage.

[0004] The present invention discloses an analog-to-digital conversion method, which includes the following operations: converting an analog input signal to generate a digital output signal; generating a control signal according to the state of the converted analog input signal; and providing a supply voltage and a supply current. Providing the supply voltage and the supply current includes changing the ability to provide the supply current according to the control signal to stabilize the supply voltage.

[0005] Compared to the prior art, the analog-to-digital conversion system and method of the present application utilizes the state of the digital output signal generated by the analog-to-digital converter to adjust the ability of the power supply to provide supply current, so as to maintain the working efficiency of the analog-to-digital converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various embodiments of the present application can be best understood when reading the following embodiments and the accompanying drawings. It should be noted that the various features in the drawings are not drawn to scale in accordance with standard operating practices in the art. In fact, the size of certain features may be deliberately enlarged or reduced in order to be clearly described.

[0007] Figure 1 FIG. 4 is a schematic diagram of an analog-to-digital conversion system in some embodiments of the present invention.

[0008] Figure 2 FIG. 4 is a schematic diagram of a power supply in some embodiments of the present invention.

[0009] Figure 3 FIG. 4 is a schematic diagram of an analog-to-digital converter in some embodiments of the present invention.

[0010] Figure 4 Schematic diagram of a power supply in some other embodiments of the present invention.

[0011] Figure 5 Schematic diagram of the waveform of the control signal in other embodiments of the present invention.

[0012] Explanation of symbols

[0013] 10: Analog-to-digital conversion system

[0014] 100: Power supply

[0015] 200: Analog-to-digital converter

[0016] 400: Analog-to-digital converter

[0017] SA: Analog input signal

[0018] SD: Digital output signal

[0019] SC: Control signal

[0020] Vo: supply voltage

[0021] Io: Supply current

[0022] 110: Voltage control circuit

[0023] 120: Power transistor

[0024] 130: Current mirror circuit

[0025] C1: Capacitor

[0026] C2: Capacitor

[0027] C3: Capacitor

[0028] R1: Resistor

[0029] R2: Resistor

[0030] R3: Resistor

[0031] M1: Transistor

[0032] M2: Transistor

[0033] M3: Transistor

[0034] M4: Transistor

[0035] M5: Transistor

[0036] NC: Control Node

[0037] VC: Control voltage

[0038] OP: Amplifier

[0039] IB1: Current source

[0040] IB2: Current source

[0041] Vref: reference voltage

[0042] V1: system voltage

[0043] V2: system voltage

[0044] V3: System voltage

[0045] 210: Analog-to-digital conversion circuit

[0046] 220: Control signal generating circuit

[0047] SK: At least one switching control signal

[0048] clk1: clock signal

[0049] clk2: clock signal

[0050] T1: Time period

[0051] T2: Time period

[0052] T3: Time

[0053] T4: Time

[0054] T5: Time

[0055] T6: Time

[0056] T7: Time DETAILED DESCRIPTION

[0057] Figure 1 The analog-to-digital conversion system 10 is a schematic diagram of some embodiments of the present invention. The analog-to-digital conversion system 10 includes a power supply 100 and an analog-to-digital converter (ADC) 200 for converting an analog input signal SA into a digital output signal SD.

[0058] The power supply 100 provides a supply voltage Vo and a supply current Io to the ADC 200 , and the ADC 200 converts the analog input signal SA into a digital output signal SD using the supply voltage Vo and the supply current Io.

[0059] The operation of ADC 200 can be divided into a high power consumption state, a low power consumption state and an idle state. When ADC 200 is used for sampling operation, ADC 200 is in a low power consumption state, and when ADC 200 is used for conversion operation, ADC 200 is in a high power consumption state. When ADC 200 finishes the conversion operation and before the next sampling operation, it is in an idle state. Under the sampling operation, ADC 200 mainly performs sampling on the analog input signal SA. Under the conversion operation, ADC 200 mainly converts the sampled analog input signal SA to generate a digital output signal SD. Under the sampling operation, the sampling circuit in ADC 200 performs the operation, and the power consumed is very low. Under the conversion operation, the power consumed by the operation of ADC 200 is much greater than the power consumed under the sampling operation.

[0060] In the prior art, the peak power required by the ADC during the conversion operation is greater than the power provided by the power supply. In this case, when the ADC needs to consume the peak power, the power provided by the power supply is insufficient to supply the ADC, causing the supply voltage to drop, thereby reducing the performance of the ADC.

[0061] Compared to the prior art, the analog-to-digital conversion system 10 provided by the present invention can generate a control signal SC from the ADC 200 to the power supply 100 according to the high power consumption state of the ADC 200 during the conversion operation when the ADC 200 generates a digital output signal SD, so that the power supply 100 can change its ability to provide the supply current Io according to the control signal SC, thereby stabilizing the provided supply voltage Vo. For details, please refer to Figures 2 to 4 Description.

[0062] Figure 2 Schematic diagram of a power supply 100 according to some embodiments of the present invention. The power supply 100 includes a voltage control circuit 110, a power transistor 120, a capacitor C1, a capacitor C2, a capacitor C3 and a resistor R1. The voltage control circuit 110 is coupled to the control end of the power transistor 120 through a control node NC. The first end of the capacitor C1 is used to receive a control signal SC, and the second end of the capacitor C1 is coupled to the control end of the power transistor 120 through the control node NC. The first end of the power transistor 120 is used to receive a reference voltage Vref, and the second end of the power transistor 120 is coupled to the first end of the capacitor C2 and the first end of the resistor R1. The second end of the power transistor 120 is used to generate a supply voltage Vo and provide a supply current Io to the ADC 200 through the second end of the power transistor 120. The second end of the capacitor C2 and the second end of the resistor R1 are grounded. The first end of the capacitor C3 is coupled to the control end of the power transistor 120 through the control node NC, and the second end of the capacitor C3 is grounded. In some embodiments, the power supply 100 may not include the capacitor C3.

[0063] The voltage control circuit 110 is used to generate a control voltage VC on a control node NC, and the power transistor 120 generates a supply voltage Vo and a supply current Io according to a reference voltage Vref and a voltage level on the control node NC. When the control signal SC is not the ground potential of the analog-to-digital conversion system 10, it changes the voltage level on the control node NC through the capacitor C1. Therefore, when the reference voltage Vref and the control voltage VC do not change, the supply voltage Vo and the supply current Io generated by the power transistor 120 change with the change of the voltage level of the control signal SC.

[0064] In some embodiments, the power transistor 120 is an N-type transistor. When the voltage level on the control node NC is increased, the voltage level on the control terminal of the power transistor 120 is increased, and the ability of the power transistor 120 to provide the supply current Io is increased. In some embodiments, the control signal SC is a digital signal, which has a first level or a second level, wherein the second level is lower than the first level. When the control signal SC has the first level, the current value of the supply current Io provided by the power transistor 120 is greater than the current value of the supply current Io provided by the power transistor 120 when the control signal SC has the second level.

[0065] Please also refer to Figure 1 and Figure 2 . When ADC 200 is in sampling operation, ADC 200 is in a low power consumption state and consumes very low power. Supply current Io generally does not flow to ADC 200, so that the supply voltage Vo at the second end of power transistor 120 remains stable. Under sampling operation, ADC 200 has a low dependence on supply current Io. Therefore, the voltage level of control signal SC is controlled at a lower second level, and the ability of power transistor 120 to provide supply current Io is not improved. In some embodiments, under sampling operation, because supply current Io does not flow to ADC 200, charge is accumulated at the first end of capacitor C2, thereby increasing the voltage level of supply voltage Vo.

[0066] When the ADC 200 is in the conversion operation, the ADC 200 consumes more power than the power supply 100 originally provided in certain periods. Compared with the sampling operation, the ADC 200 is in a high power consumption state under the conversion operation. In order to keep the supply voltage Vo stable, the voltage level of the control signal SC is controlled at a higher first level, and the ability of the power transistor 120 to provide the supply current Io is improved to match the power required by the ADC 200. When the power supplied by the power supply 100 is sufficient to provide the ADC 200, the supply voltage Vo will not decrease, thereby stabilizing the supply voltage Vo.

[0067] In some embodiments, the voltage control circuit 110 is used to provide a control voltage VC with less noise. The voltage control circuit 110 includes a current source IB1, an amplifier OP, a transistor M1, a resistor R2, and a resistor R3. The current source IB1 is coupled to the positive input terminal of the amplifier OP and the first end of the resistor R2. The output terminal of the amplifier OP is coupled to the control node NC and the control terminal of the transistor M1. The first end of the transistor M1 is coupled to the system voltage V1. The negative input terminal of the amplifier OP is coupled to the first end of the resistor R3 and the second end of the transistor M1. The second ends of the resistors R2 and R3 are grounded.

[0068] Please refer to Figure 3 . Figure 3 2 is a schematic diagram of an ADC 200 according to some embodiments of the present invention. The ADC 200 includes an analog-to-digital conversion circuit 210 and a control signal generating circuit 220. The control signal generating circuit 220 is used to generate at least one conversion control signal SK to the analog-to-digital conversion circuit 210, so that the analog-to-digital conversion circuit 210 samples an analog input signal SA and converts the sampled analog input signal SA to generate a digital output signal SD according to the at least one conversion control signal SK. The control signal generating circuit 220 is also used to generate a control signal SC to the power supply 100 according to the at least one conversion control signal SK.

[0069] In some embodiments, the ADC 200 is a successive-approximation register ADC (SAR ADC) for converting an analog input signal SA into an n-bit digital output signal SD. In the conversion mode, the analog-to-digital conversion circuit 210 sequentially generates the analog input signal SA into an n-bit digital output signal SD according to at least one conversion control signal SK, where n is a positive integer. In some embodiments, when the analog-to-digital conversion circuit 210 converts and generates the digital output signal SD, the analog-to-digital conversion circuit 210 is in the high power consumption state described above during the time between the first bit (i.e., the most significant bit MSB) and the nth bit (i.e., the least significant bit LSB).

[0070] The control signal generating circuit 220 generates the control signal SC according to the operation state of the analog-to-digital conversion circuit 210. Specifically, in the sampling operation, the control signal generating circuit 220 generates the control signal SC having the second level according to at least one conversion control signal SK. In some embodiments, in the conversion operation, the control signal generating circuit 220 generates the control signal SC having the first level according to at least one conversion control signal SK. Figure 2 In the conversion operation, the control signal SC with the first level makes Figure 2 The capability of the medium power transistor 120 to provide the supply current Io is increased.

[0071] In some other embodiments, in the conversion operation, according to at least one conversion control signal SK, the control signal generating circuit 220 generates a control signal SC having a first level between the x-th bit and the y-th bit of the digital output signal SD, and generates a control signal SC having a second level between the 1st bit and the x-th bit and between the y-th bit and the n-th bit of the digital output signal SD. Both x and y are positive integers, y is greater than x, and n is greater than or equal to y. That is, only in a part of the time period of the conversion operation (as mentioned above, the time from the 1st bit to the nth bit of the digital output signal SD belongs to the conversion operation, but only the control signal SC between the x-th bit and the y-th bit of the digital output signal SD corresponds to a higher level), the ability of the power transistor 120 to provide the supply current Io is improved. In other words, the control signal generating circuit 220 is used to select the part of the time period of the high power consumption state in the conversion operation to generate the control signal SC that can improve the ability of the power transistor 120 to provide the supply current Io according to the operation state (high power consumption state or low power consumption state) of the analog-to-digital conversion circuit 210.

[0072] The operation of the SAR ADC 200 generating the control signal SC according to the operation state of the analog-to-digital conversion circuit 210 (i.e., corresponding the control signal SC between the x-th bit and the y-th bit of the output signal SD to a higher level, and corresponding the control signal SC between the 1st bit and the x-1th bit and the y+1th bit and the n-th bit to a lower level) can be implemented through the content of the invention patent application No. 102101306 (publication No. TW 201429166A). The invention patent application No. 102101306 is incorporated herein by reference.

[0073] The above configurations of the power supply 100 and the ADC 200 are only for illustrative purposes. Various configurations of the power supply 100 and the ADC 200 are within the consideration and scope of the present invention. For example, in other embodiments, the power supply 100 may be Figure 4 The power supply 400 shown is substituted.

[0074] refer to Figure 4 . Figure 4 FIG. 4 is a schematic diagram of a power supply 400 according to another embodiment of the present invention. The power supply 400 includes a voltage control circuit 110, a power transistor 120, a capacitor C2, a resistor R1, a current mirror circuit 130, a transistor M2 and a transistor M3. Figure 2The configuration of the voltage control circuit 110, the power transistor 120, the capacitor C2, and the resistor R1 of the power supply 400 is substantially the same as the configuration of the voltage control circuit 110, the power transistor 120, the capacitor C2, and the resistor R1 of the power supply 100, and the details thereof are not repeated here.

[0075] like Figure 4 As shown, the current mirror circuit 130 is coupled to the first end of the transistor M2. The second end of the transistor M2 is coupled to the control end of the power transistor 120 through the control node NC. The first end of the transistor M3 is coupled to the control end of the power transistor 120 through the control node NC, and the second end of the transistor M3 is grounded. The control end of the transistor M2 and the control end of the transistor M3 are used to receive the control signal SC. In some embodiments, the current mirror circuit 130 includes a transistor M4, a transistor M5 and a current source IB2. The first end of the transistor M4 is used to receive the system voltage V2, the second end of the transistor M4 is coupled to the first end of the transistor M2, the control end of the transistor M4 is coupled to the control end of the transistor M5, the second end of the transistor M5 and the first end of the current source IB2, the first end of the transistor M5 is used to receive the system voltage V3, and the second end of the current source IB2 is grounded. In some embodiments, the system voltage V2 is equal to the system voltage V3.

[0076] In some embodiments, transistor M2 is a P-type transistor and transistor M3 is an N-type transistor. When the control signal SC has a first level, transistor M2 is turned off and transistor M3 is turned on. The voltage level of the control node NC is reduced due to the conduction of transistor M3, so that the ability of the power transistor 120 to provide the supply current Io is reduced. When the control signal SC has a second level, transistor M3 is turned off and transistor M2 is turned on. The voltage level of the control node NC is increased due to the conduction of transistor M2, so that the ability of the power transistor 120 to provide the supply current Io is increased.

[0077] Please also refer to Figure 3 , Figure 4 and Figure 5 In other embodiments, Figure 3 The ADC 200 in the embodiment is a pipeline analog-to-digital converter (pipeline ADC). The pipeline ADC 200 is controlled to be in a sampling operation or a conversion operation by a clock signal clk1 and a clock signal clk2 in at least one conversion control signal SK. Figure 5In the example, when one of the clock signal clk1 and the clock signal clk2 has a first level (such as time periods T1, T2, T3, and T4), the pipeline ADC 200 is controlled in a sampling operation. When both the clock signal clk1 and the clock signal clk2 have a second level (such as time periods T5, T6, and T7), the pipeline ADC 200 is controlled in a conversion operation. In the sampling operation, the ADC 200 generates a control signal SC having a first level to the power supply 400. In the conversion operation, the ADC 200 generates a control signal SC having a second level to the power supply 400. Based on such an operation, the ability of the power supply 400 to provide the supply current Io in the conversion operation can be improved, so that the supply voltage Vo tends to be stable. In some embodiments, the control signal generating circuit 220 performs a NAND gate logic operation on the clock signal clk1 and the clock signal clk2 to generate the control signal SC. According to the logic operation of the NAND gate, when one of the clock signal clk1 and the clock signal clk2 has the first level, the control signal SC has the second level. When both the clock signal clk1 and the clock signal clk2 have the second level, the control signal SC has the first level.

[0078] The above description briefly presents the features of certain embodiments of the present application, so that those skilled in the art to which the present application belongs can more fully understand the various implementation methods of the present application. Those skilled in the art to which the present application belongs should understand that they can easily use the present application as a basis to design or change other processes and structures to achieve the same purpose and / or achieve the same advantages as the implementation methods described herein. Those skilled in the art to which the present application belongs should understand that these equivalent implementation methods still belong to the concept and scope of the present application, and they can be subjected to various changes, substitutions and changes without deviating from the concept and scope of the present application.

Claims

1. An analog-to-digital conversion system, comprising: An analog-to-digital converter is used to convert an analog input signal to generate a digital output signal, and to generate a control signal according to a state of the converted analog input signal, wherein: In a sampling operation, converting the state of the analog input signal to a low power consumption state, and in a conversion operation, converting the state of the analog input signal to a high power consumption state; and A power supply is used to provide a supply voltage to the analog-to-digital converter and change a capability of the power supply to provide a supply current according to the control signal to stabilize the supply voltage.

2. The analog-to-digital conversion system as claimed in claim 1, wherein the power supply comprises: a voltage control circuit for generating a control voltage at a control node; and A power transistor, wherein a first end of the power transistor is used to receive a reference voltage, a control end of the power transistor is used to couple the control node, and the power transistor is used to output the supply voltage at a second end of the power transistor according to the reference voltage, the control voltage and the control signal.

3. The analog-to-digital conversion system as claimed in claim 2, wherein the power supply further comprises: a first capacitor, wherein a first terminal of the first capacitor is used to receive the control signal, and a second terminal of the first capacitor is used to couple to the control node; a second capacitor, wherein a first terminal of the second capacitor is coupled to the second terminal of the power transistor, and a second terminal of the second capacitor is coupled to a ground terminal; and A first resistor, wherein a first end of the first resistor is coupled to the second end of the power transistor, and a second end of the first resistor is coupled to the ground end.

4. The analog-to-digital conversion system as claimed in claim 3, wherein the power supply further comprises: A third capacitor is coupled between the control node and the ground terminal.

5. The analog-to-digital conversion system as claimed in claim 2, wherein the power supply further comprises: a current mirror circuit; a first transistor, wherein a first terminal of the first transistor is coupled to the current mirror circuit, a second terminal of the first transistor is coupled to the control node, and a control terminal of the first transistor is used to receive the control signal; and a second transistor, wherein a first terminal of the second transistor is coupled to the control node, a second terminal of the second transistor is coupled to a ground terminal, and a control terminal of the second transistor is used to receive the control signal, When the control signal has a first level, the first transistor is turned off and the second transistor is turned on, so that a voltage level on the control node is reduced, and when the control signal has a second level lower than the first level, the second transistor is turned off and the first transistor is turned on, so that the voltage level on the control node is increased.

6. An analog-to-digital conversion method, comprising: Converting an analog input signal to generate a digital output signal; A control signal is generated according to a state of the analog input signal, wherein: In a sampling operation, converting the state of the analog input signal to a low power consumption state, and in a conversion operation, converting the state of the analog input signal to a high power consumption state; and Providing a supply voltage and a supply current, including: A capability of providing the supply current is changed according to the control signal to stabilize the supply voltage.

7. The analog-to-digital conversion method as claimed in claim 6, wherein providing the supply voltage and the supply current further comprises: Receiving a reference voltage through a first terminal of a power transistor; generating a control voltage; and The supply voltage is outputted through a second terminal of the power transistor according to the reference voltage, the control voltage and the control signal.

8. The analog-to-digital conversion method as claimed in claim 7, wherein outputting the supply voltage according to the reference voltage, the control voltage and the control signal comprises: Receiving the control signal through a first terminal of a first capacitor; and The control voltage is received through a control terminal of the power transistor and coupled to a second terminal of the first capacitor.

9. The analog-to-digital conversion method as claimed in claim 8, wherein providing the supply voltage and the supply current further comprises: The control terminal of the power transistor is grounded through a second capacitor.

10. The analog-to-digital conversion method of claim 8, wherein the control signal has a first level or a second level, wherein the second level is lower than the first level, wherein in the sampling operation, the control signal has the second level, and in the conversion operation, the control signal has the first level or the second level, In the conversion operation, a voltage level of the control terminal of the power transistor is increased by the control signal through the first capacitor to improve the ability of the power transistor to provide the supply current.

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