Power efficient near-memory analog multiply and accumulate (MAC)

Abstract

A near memory system is provided for computation of a layer in a machine learning application. The near memory system includes an array of memory cells for storing an array of filter weights. Multiplication and accumulation circuits are coupled to columns in the array to form computation of the layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to non-provisional application No. 16 / 721,819, filed on December 19, 2019, entitled “POWER EFFICIENT NEAR MEMORYANALOG MULTIPLY-AND-ACCUMULATE (MAC)”, which application is assigned to the assignee of the present application and is expressly incorporated herein by reference. Technical Field

[0003] The present application relates to a multiply-and-accumulate (MAC) circuit, and more particularly to a power-efficient near-memory analog MAC. Background Art

[0004] Computer processing of data typically uses a von Neumann architecture, where data is retrieved from memory for processing in arithmetic and logic units. In computationally intensive applications such as machine learning, the flow of data to and from memory becomes a bottleneck for processing speed. To address this data movement bottleneck, near-memory architectures have been developed, where the data processing hardware is located adjacent to the memory units. Summary of the Invention

[0005] According to a first aspect of the present invention, there is provided a near memory system comprising: an array of memory cells arranged into a plurality of rows and a plurality of columns, wherein each row is configured to store a plurality of filter weights for a layer in a machine learning application; and a multiply and accumulate (MAC) circuit coupled to each column, the MAC circuit being configured to multiply the plurality of filter weights of an accessed row in a row by a corresponding plurality of inputs to provide a plurality of products, the MAC circuit being further configured to sum the plurality of products to provide an output of the layer.

[0006] According to a second aspect of the present invention, there is provided a near memory system comprising: a plurality of memory cell arrays, wherein each array is arranged into a plurality of rows and columns, and wherein each row is further configured to store a plurality of filter weights for a layer in a machine learning application, and wherein each memory cell array is subdivided into a plurality of subarrays; and a plurality of multiply and accumulate (MAC) circuits, the plurality of MAC circuits corresponding to the plurality of subarrays, each MAC circuit being coupled to each column in the corresponding subarray, each MAC circuit being configured to multiply a plurality of filter weights from an accessed row in the corresponding subarray by a corresponding plurality of inputs to provide a plurality of products, the MAC circuits being further configured to sum the plurality of products to provide a sum, and wherein each array further comprises an adder to sum the sums from the MAC circuits of the array to form an output of the array.

[0007] According to a third aspect of the present invention, there is provided a method for a near memory system, comprising: asserting a word line for a row of memory cells to retrieve a plurality of filter weights for output neurons in a layer for a machine learning application; multiplying the plurality of filter weights with a plurality of input neurons in a multiplication and accumulation circuit coupled to a column of memory cells to form a plurality of products; and summing the plurality of products to calculate a value of the output neuron.

[0008] These and other advantageous features will be better understood from the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Illustration of a conventional fully connected layer used in a neural network.

[0010] Figure 2A A near memory system with digital multiply and accumulate (MAC) circuitry according to one aspect of the present disclosure is illustrated.

[0011] Figure 2B Illustrated is a bit cell and decoder for a near memory system according to an aspect of the present disclosure.

[0012] Figure 3 A segmented near memory system according to an aspect of the present disclosure is illustrated.

[0013] Figure 4 A near memory system with analog MAC circuits according to one aspect of the present disclosure is illustrated, wherein filter weights and input neuron weights are both single-bit signals.

[0014] Figure 5 A near memory system with analog MAC circuitry is illustrated, wherein filter weights are unit weights and input neuron weights are multi-bit weights, according to an aspect of the present disclosure.

[0015] Figure 6 A near memory system with analog MAC circuitry is illustrated, wherein filter weights and input neuron weights are multi-bit weights, according to an aspect of the present disclosure.

[0016] Figure 7 is a flow chart of an exemplary method of operation for a near memory system according to an aspect of the present disclosure.

[0017] Figure 8 Several exemplary electronic systems, each incorporating a near memory system according to an aspect of the present disclosure, are illustrated.

[0018] Embodiments of the present disclosure and their advantages may be best understood by referring to the following detailed description.It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the accompanying drawings. DETAILED DESCRIPTION

[0019] A near memory architecture is provided with a multiply and accumulate (MAC) circuit for multiplying a plurality of input neurons from a previous layer in a machine learning application with a plurality of filter weights to form a plurality of products. The MAC circuit sums the products to calculate an output neuron for a layer (e.g., a fully connected layer) in the machine learning application. While the following discussion is directed to a machine learning embodiment, it should be understood that other types of multiplications of input vectors and filter weights can be calculated using a near memory with a MAC circuit as disclosed herein. Figure 1 An example fully connected layer 100 is shown having M output neurons. The M output neurons range from the 0th output neuron to the (M-1)th output neuron. The previous layer 105 includes N input neurons from the 0th input neuron to the (N-1)th input neuron. Typically, the integer N is substantially greater than the integer M. For clarity of illustration, only the first two and last neurons are shown for each layer.

[0020] Each output neuron in the fully connected layer 100 receives a weighted version of each input neuron in the previous layer 105. For example, output neuron 0 in the fully connected layer 100 receives a weighted version of the 0th input neuron, a weighted version of the first input neuron, and so on to a weighted version of the (N-1)th input neuron. Therefore, each output neuron in the fully connected layer 100 is associated with N weights used to weight the input neurons from the previous layer 105. As used herein, the weights for the output neurons in the fully connected layer 100 are collectively represented as filters. Therefore, each weight is also represented as a filter weight. Disclosed herein is a memory having a bit cell array for storing corresponding filters. The bit cell array is arranged in rows and columns. If each filter weight is a one-bit filter weight, each row can correspond to a filter for an output neuron. For example, assuming there are 128 output neurons with one-bit filter weights, the bit cell array will have 128 rows. In such an embodiment, the number of columns of the bit cell array corresponds to the number of input neurons. In an alternative embodiment, the filter weights can be multi-bit filter weights. Thus, in this multi-bit filter weight embodiment, each filter will correspond to a set of rows. The number of rows in each set of rows corresponds to the width (number of bits) for the multi-bit filter weight embodiment. In each set of rows, each row will correspond to a bit in the multi-bit weight, as will be further explained herein.

[0021] To calculate the value for the output neuron, a read operation occurs on the corresponding row in a one-bit filter weight embodiment (or sequentially across the rows of the corresponding group in a multi-bit weight embodiment) to access the stored filter weights. The accessed stored filter weights are then multiplied by the corresponding input neurons. The products from all multiplications of the stored filter weights with their corresponding input neurons are summed to form the output neuron. Although the multiplication of the stored filter weights with the corresponding input neurons can be performed using in-memory compute bit cells, it should be noted that in machine learning applications, fully connected layers have the majority of weights. The in-memory compute bit cells are significantly larger than conventional six-transistor (6T) static random access memory (SRAM) bit cells. Therefore, storing filter weights in a memory-based compute architecture for implementing a fully connected layer will require a relatively large amount of die space (e.g., approximately four times that required for a conventional 6T bit cell array). In addition, the read and write energy for the in-memory compute implementation is relatively high.

[0022] Thus, a near memory architecture is disclosed that includes, in some embodiments, a 6T array of bit cells arranged in rows and columns for storing filter weights. The rows correspond to filters such that there is a row (or a group of rows in multi-bit filter weight embodiments) of bit cells for each output neuron. In a read operation, a row of bit cells is accessed at a time to retrieve the stored filter weights in order to calculate the corresponding output neuron. Specifically, each bit cell row has its own word line, while each bit cell column has its bit line pair formed by a bit line and a complementary bit line. To calculate the output neuron, the voltage for the word line is asserted. The bit line pair of each column is then charged according to the weight stored in the accessed bit cell. To perform the multiplication of the stored weights as represented by the column's charged line pair, each column is associated with a MAC circuit that performs the multiplication of the stored weights with the corresponding input neuron. The MAC circuit sums the resulting products to complete the calculation for the output neuron.

[0023] Figure 2A An example near memory system 200 for a one-bit filter weight embodiment is shown in FIG. An array of bit cells (e.g., six-transistor (6T) bit cells) is arranged in rows and columns. Each row corresponds to a filter for an output neuron. In other words, the bit cells across the rows store the filter weights for the output neurons. Each row corresponds to an output neuron on a one-to-one basis. For simplicity, each output neuron is also referred to herein as an output. Similarly, for simplicity, each input neuron is also referred to herein as an input. Since there is a filter weight for each input, each column of bit cells corresponds to one input on a one-to-one basis. For clarity, in FIG. Figure 2AOnly the first bit cell row (Filter 1) and the second bit cell row (Filter 2) are labeled in FIG. Each bit cell column has a bit line pair formed by a bit line (BL) and a complement bit line (BLB). MAC circuit 205 calculates the multiplication of the filter weight for the output and the corresponding input. In this multiplication, the first input is multiplied by the first filter weight to form a first product, the second input is multiplied by the second filter weight to form a second product, and so on. The MAC circuit sums the resulting products from the accessed row to calculate the corresponding output of the fully connected layer. This calculation is performed on a filter-by-filter basis (equivalent to an output-by-output basis). To access the stored filter weights for a row, the word line for that row is asserted (not shown). The bit line for each column is then charged at the intersection of the column and the accessed row using the stored filter weight for that bit cell. To make bit decisions from the charged line pair based on the stored filter weights, MAC circuit 205 includes a sense amplifier (SA) for each column. However, it should be noted that the sense amplifier can be omitted in alternative embodiments. For example, in an alternative embodiment, the sense amplifiers can be replaced by latches. MAC circuit 205 also includes logic gates, such as exclusive-or-not (XNOR) logic gates for each column. The XNOR gate for each column receives the stored filter weights from the sense amplifier for that column. In an alternative embodiment, an exclusive-or (XOR) gate or other suitable logic gate can be used to perform binary multiplication. In some embodiments without sense amplifiers, each XNOR gate receives the true bit line (or complement bit line) directly.

[0024] For illustration purposes, the near memory system 200 includes only eight bit cell columns. Figure 2A Only the first column 210 is noted in FIG. Thus, these eight columns correspond to eight input neurons ranging from input neuron IN1 to input neuron IN8. The XNOR gate of each column performs an XNOR on the stored filter weights for that column and the input neurons for that column to calculate the product for binary multiplication. The MAC circuit 205 includes a digital adder to add the products (XNOR gate output signals) to complete the calculation of the output neurons for the accessed row. Thus, the MAC circuit 205 will calculate the various output neurons sequentially. This introduces some latency, but since the number of output neurons for a fully connected layer is typically relatively small, this is manageable.

[0025] Figure 2BAn example bit cell 220 for near memory system 200 is shown in greater detail. In some embodiments, the stored filter weights are latched by a cross-coupled pair of inverters 215. Each inverter can be formed by a series combination of a p-type metal oxide semiconductor (PMOS) transistor and an n-type metal oxide semiconductor (NMOS) transistor. A one-bit filter weight is provided to the Q output node of one of the inverters. Conversely, a complement of the one-bit filter weight is provided to the QB output node of the remaining inverter in the inverters. During a read operation for accessing a row including bit cell 220, a word line voltage for a word line (WL) is asserted. Word line WL drives the gates of NMOS access transistor M1 and NMOS access transistor M2. Access transistor M1 is coupled between the Q output node and a bit line BL for the column including bit cell 220. Similarly, access transistor M2 is coupled between the QB output node and a complement bit line BLB for the column. When word line WL is asserted, access transistors M1 and M2 turn on, causing one of the bit lines to be discharged while the other remains in its precharged state. Since the cross-coupled inverter 215 requires four transistors, the total number of transistors used in the bit cell 220 is six transistors, which is conventional for an SRAM bit cell. A controller, such as decoder 225, controls the assertion of word line WL. This assertion by the controller is part of the sequential assertion of the word lines for the near memory system 200. For example, the controller may assert the word line for the first row to calculate the first output of the fully connected layer, then assert the word line for the second row to calculate the second output of the fully connected layer, and so on.

[0026] Even though the number of output neurons is relatively small, the processing energy used for the near memory system 200 may still be significant. For example, assume there are 128 bit cell rows. The bit lines that extend across so many rows can have a large amount of capacitance. With this increased bit line capacitance, since the bit lines in a bit line pair are discharged during a read operation, the charge of the bit line pair after a read operation for the stored filter weights requires a corresponding amount of charge to be discharged to ground. To reduce latency and power consumption, one can Figure 3 The bit cell array for the near memory system 300 is segmented as shown. For example, assume that the near memory system 200 of FIG. 2 has 128 bit cell rows. Referring again to FIG. Figure 1, the filter stores weights for the output neurons. For example, output neuron 0 requires N filter weights to multiply by the N corresponding input neurons. Therefore, there is a zeroth filter weight for the zeroth input neuron, a first filter weight for the first input neuron, and so on. Each input neuron is multiplied by its corresponding filter weight to form a product. The corresponding output neuron is the sum of all the resulting products. Without segmentation, an array for 128 filters and 1024 input neurons would be an array of 128 rows and 1024 columns.

[0027] Such arrays are segmented in the near memory system 300 into a first array 305, a second array 310, a third array 315, and a fourth array 320. Due to the segmentation, the columns of 128 bit cells that would form the filter in the unsegmented embodiment are subdivided into columns of 32 bit cells in the first array 305, a corresponding column of 32 bit cells in the second array 310, a corresponding column of 32 bit cells in the third array 315, and a corresponding column of 32 bit cells in the fourth array 320. It should be understood that the segmentation can vary in alternative embodiments. Each array includes 32 bit cell rows arranged in 1024 columns. In some embodiments, semiconductor manufacturing processes cannot support word lines that extend across such a relatively large number of columns. Therefore, each bit cell array can be subdivided into 32 rows × 128 columns (32 × 128) subarrays. Since there are 1024 columns, there are eight subarrays per bit cell array in the near memory 300 for each array, but it should be understood that in alternative embodiments, the number of columns and the number of rows can vary. Each subarray has its own MAC circuit. Since the array is divided into subarrays, the accumulated output from each MAC circuit of the array is summed by an adder (ADDER) to generate the output of the fully connected layer.

[0028] It should be understood that any suitable memory technology may be used to construct Figure 3 For example, arrays 305, 310, 315, and 320 may be arrays of SRAM bit cells, ferroelectric RAM (FRAM) bit cells, magnetic RAM (MRAM) bit cells, resistive RAM (RRAM) bit cells, or phase change memory (PCM) bit cells.

[0029] The resulting segmentation of arrays (such as arrays 305, 310, 315, and 320) is highly advantageous in terms of reducing latency. Within each array, processing of rows occurs sequentially, as controlled by a controller such as that discussed with respect to near memory system 200. However, the segmentation in near memory system 300 results in processing four rows simultaneously, making it four times faster than near memory system 200. More generally, if the number of arrays from the segmentation is N, then computation of a fully connected layer will be N times faster than a comparable computation without segmentation. Additionally, since the bit lines for each array extend across a reduced number of rows compared to a non-segmented architecture such as near memory system 200, the read energy used to access the rows is reduced due to segmentation. It should be understood that in alternative embodiments, the output of each adder can be quantized by a quantizer (not shown). Because the MAC circuitry is external to the bit cell arrays, the MAC circuitry can be easily modified to support multi-bit filter weights and multi-bit input neurons.

[0030] The digital processing in the MAC circuit in the aforementioned embodiment consumes power. To reduce this power consumption, this paper discloses a near memory system that utilizes analog MAC circuits. Figure 4 FIGURE 4 illustrates a single-bit input neuron near memory system 400 with an analog MAC circuit 405. As discussed with respect to near memory systems 200 or 300, an array of bit cells (such as 6T bit cells) is arranged in rows and columns. As discussed with respect to the digital MAC circuit, the analog MAC circuit 405 includes a logic gate (such as an XNOR gate) and a sense amplifier (SA) for each column. Instead of using a digital adder, the analog MAC circuit 405 includes a capacitor C for each column. Each column's XNOR gate drives the first plate of the corresponding capacitor C. The second plate of each capacitor C is coupled to the input of an analog-to-digital converter (ADC). Before a MAC operation, each second plate is charged to the supply voltage by coupling the second plate to a power node while the first plate is grounded. After a row is accessed, the output of each XNOR gate is either grounded or charged to the supply voltage, depending on the result of its binary multiplication. While the XNOR gate drives the first plate, the second plate remains coupled to the power node. Thus, each capacitor C is discharged or remains charged based on the corresponding XNOR operation. An analog-to-digital converter (ADC) then converts the accumulated charge retained by capacitor C to provide the output neuron value.

[0031] Referring back to the near memory systems 200 and 300, it should be understood that each MAC circuit can be implemented as an analog MAC circuit 405. The resulting analog MAC operation is very advantageous because MAC power consumption dominates in digital MAC circuit embodiments. However, the use of analog MAC circuit 405 significantly reduces power consumption relative to comparable digital MAC implementations.

[0032] Figure 5 5 shows an analog MAC circuit 500 for a unit filter weight and multi-bit input neuron layer. For clarity of illustration, Figure 5 The memory array is not shown in FIG4 because it is arranged in rows and columns as discussed for near memory systems 200, 300, and 400. Analog MAC circuit 500 is similar to analog MAC circuit 405, with each column associated with a sense amplifier (SA), an XNOR gate, and a capacitor C. Each XNOR gate sequentially processes its multi-bit input neuron bit by bit, such as with increasing magnitude from the least significant bit to the most significant bit. A sequential accumulator 505 then adds the results of the sequential processing of the multi-bit input neuron to the corresponding filter weight. In the sequential accumulation performed by sequential accumulator 505, the voltage of each bit from the multi-bit input neuron is accumulated according to its significance. For example, assume that the multi-bit input neuron is three bits wide. Each bit results in a voltage on the second plate of capacitor C, which is scaled by sequential accumulator 505 according to the significance of the bit. Sequential accumulator 505 then adds the resulting voltages to provide an accumulated voltage that is converted by the ADC into a digital value for the output neuron.

[0033] The filter weights themselves may be multi-bit filter weights. Figure 6 FIG. 6 shows an analog MAC circuit 600 for a multi-bit filter weight and multi-bit input neuron layer. For clarity of illustration, Figure 6 The bit cell array is not shown in FIG, but as discussed with respect to near memory systems 200, 300, and 400, the bit cell array is arranged in rows and columns. Because the filter weights are multi-bit, a single filter weight requires a set of bit cell rows for its bits. The rows are asserted sequentially according to their importance (such as from the least significant bit to the most significant bit) in the set of rows for the multi-bit filter weights. For each bit in the multi-bit weight, analog MAC circuit 600 operates as discussed with respect to analog MAC circuit 500. Thus, there is a sense amplifier SA, an XNOR gate, and a capacitor C for each column, as well as a sequential accumulator 505 in analog MAC circuit 600. While a row is asserted, a bit from a multi-bit input neuron is processed sequentially by each XNOR gate using a bit from the multi-bit filter weight, and the results are accumulated by sequential accumulator 505, as similarly discussed with respect to analog MAC circuit 500. A second sequential accumulator 605 (which may also be designated as a weight summer 605) accumulates the results after each row in a set of rows for the multi-bit weights is accessed. The accumulation is scaled by the weight summer 605 according to the importance of each bit in the multi-bit weights to provide an output neuron value.

[0034] Figure 7A flowchart of a near memory system method is shown in FIG. The method includes act 700 of asserting a wordline for a row of memory cells to retrieve a plurality of filter weights for output neurons in a fully connected layer for a machine learning application. Asserting the wordline for any of near memory systems 200 and 300 is an example of act 700. Similarly, asserting the wordline for a near memory system including any of analog MAC circuits 400, 500, and 600 is an example of act 700. The method also includes act 705 of multiplying, in a multiplication and accumulation circuit coupled to the column of memory cells, the plurality of filter weights with a plurality of input neurons from a previous layer in the machine learning application to form a plurality of products. The multiplication in the MAC logic disclosed herein is an example of act 705. Finally, the method includes act 710 of summing the plurality of products to calculate a value for an output neuron. The summing of the plurality of products by the MAC circuit disclosed herein is an example of act 710.

[0035] The near memory system disclosed herein may be advantageously incorporated into any suitable mobile device or electronic system. Figure 8 As shown, a cellular phone 800, a laptop computer 805, and a tablet PC 810 can all include a near memory system according to the present disclosure. Other exemplary electronic systems (such as music players, video players, communication devices, and personal computers) can also be configured with a near memory system constructed according to the present disclosure.

[0036] It should be understood that many modifications, substitutions, and variations may be made to the materials, devices, configurations, and methods of use of the apparatus of the present disclosure without departing from the scope of the present invention. In view of this, the scope of the present disclosure should not be limited to that of the specific embodiments shown and described herein, as they are by way of some examples thereof, but should be fully commensurate with the scope of the claims hereinafter appended and their functional equivalents.

Claims

1. A near memory system, comprising: an array of memory cells arranged into a plurality of rows and a plurality of columns, wherein each row is configured to store a plurality of filter weights for a layer in a machine learning application; as well as a multiply and accumulate MAC circuit coupled to each column, the MAC circuit configured to multiply the plurality of filter weights from an accessed row of the rows with a plurality of inputs of the layer to provide a plurality of products, the MAC circuit further configured to sum the plurality of products to provide an output of the layer, Wherein each input is a multi-bit input, the MAC circuit further comprises a sequential accumulator configured to provide an accumulation result based on serial processing of the multi-bit inputs.

2. The near memory system of claim 1 , further comprising: a plurality of word lines, the plurality of word lines corresponding to the plurality of rows, each word line extending across its corresponding row; as well as The controller is configured to sequentially assert the word lines to form the access row among the rows.

3. The near memory system of claim 1 , wherein each memory cell is selected from the group consisting of: a static random access memory (SRAM) bit cell, a magnetic RAM (MRAM) bit cell, a resistive RAM (RRAM) bit cell, a ferroelectric RAM (FRAM) bit cell, and a phase change memory (PCM) bit cell.

4. The near memory system of claim 3, wherein each SRAM bit cell is a six-transistor SRAM bit cell. 5 . The near memory system of claim 1 , wherein the MAC circuit comprises a plurality of logic gates corresponding to the plurality of columns, and wherein each logic gate is configured to multiply a filter weight with an input to form a binary product.

6. The near memory system of claim 5, wherein each logic gate comprises an XNOR gate.

7. The near memory system of claim 6, wherein the MAC circuit further comprises a digital adder to add the output from each XNOR gate.

8. The near memory system of claim 6, wherein the MAC circuit further comprises: A plurality of capacitors corresponding to the plurality of XNOR gates and wherein each XNOR gate is configured to drive a first plate for the corresponding capacitor.

9. The near memory system of claim 8, wherein the MAC circuit further comprises an analog-to-digital converter coupled to the second plate for each capacitor.

10. The near memory system of claim 8, wherein the sequential accumulator is coupled to the second plate of each capacitor to accumulate the charge from each second plate to provide the accumulated result.

11. The near memory system of claim 10, wherein the layer is a fully connected layer, and wherein the MAC circuit further comprises an analog-to-digital converter configured to convert the accumulated result into an output of the fully connected layer.

12. A near memory system: a plurality of memory cell arrays, wherein each array is arranged into a plurality of rows and columns, and wherein each row is configured to store a plurality of filter weights for a layer in a machine learning application, and wherein each memory cell array is subdivided into a plurality of sub-arrays; and a plurality of multiply and accumulate MAC circuits, the plurality of MAC circuits corresponding to the plurality of subarrays, each MAC circuit being coupled to each column in the corresponding subarray, each MAC circuit being configured to multiply the plurality of filter weights from an accessed row in the rows in the corresponding subarray with a corresponding plurality of inputs to provide a plurality of products, the MAC circuits being further configured to sum the plurality of products to provide a sum, and wherein each array further comprises an adder to add the sums from the MAC circuits of the array to form an output of the array, Wherein each input is a multi-bit input, each MAC circuit further comprises a sequential accumulator configured to provide an accumulation result based on serial processing of the multi-bit input.

13. The near memory system of claim 12, wherein each memory cell is a static random access memory (SRAM) bit cell.

14. The near memory system of claim 13, wherein each SRAM bit cell is a six-transistor SRAM bit cell.

15. The near memory system of claim 12, wherein each MAC circuit comprises a plurality of logic gates corresponding to a plurality of columns in the corresponding subarray, and wherein each logic gate is configured to multiply a filter weight with a corresponding one of the inputs to form a binary product.

16. The near memory system of claim 15, wherein each logic gate comprises an XNOR gate.

17. The near memory system of claim 16, wherein each MAC circuit further comprises a digital adder to add outputs from each of the XNOR gates of the MAC circuit.

18. The near memory system of claim 16, wherein each MAC circuit further comprises: A plurality of capacitors corresponding to the plurality of XNOR gates in the MAC circuit and wherein each XNOR gate is configured to drive a first plate for a corresponding capacitor.

19. The near memory system of claim 18, wherein each MAC circuit further comprises an analog-to-digital converter coupled to the second plate for each capacitor in the MAC circuit.

20. The near memory system of claim 18, wherein the sequential accumulator is coupled to a second plate of each of the capacitors of the MAC circuit to sequentially accumulate charge from each second plate for each capacitor in the MAC circuit to provide an accumulated result.

21. The near memory system of claim 20, wherein the layer is a fully connected layer, and wherein each MAC circuit further comprises an analog-to-digital converter configured to convert the accumulated result into a digital value, and wherein each adder is further configured to: add the digital values ​​from the MAC circuits of the array to provide an output of the fully connected layer.

22. The near memory system of claim 12, wherein the near memory system is integrated into a mobile device.

23. The near memory system of claim 22, wherein the mobile device is a cellular telephone.

24. A method for a near memory system, comprising: asserting a word line for a row of memory cells to retrieve a plurality of filter weights for output neurons in a layer for a machine learning application; multiplying the plurality of filter weights and a plurality of input neurons in a multiply and accumulate circuit coupled to the column of memory cells to form a plurality of products; summing the plurality of products to calculate a value of the output neuron; as well as Additional word lines are sequentially asserted to sequentially compute values ​​for additional output neurons in the layer.

25. The method of claim 24, wherein summing the plurality of products comprises: Digitize the voltages from multiple capacitors.

26. The method of claim 24, wherein summing the plurality of products comprises digital summing.

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