Selectively non-volatile memory device and associated reading method

Abstract

The invention relates to a selective non-volatile memory device (1) comprising a first electrode (3), a second electrode (4) and at least one layer (2) made of an active material. The device (1) has at least two programmable memory states associated with two voltage thresholds and also provides a selective action when it is in a high resistive state.

Description

Technical Field

[0001] The technical field of this invention is non-volatile memory. This invention relates to a device that integrates both non-volatile memory functionality and selective functionality. This invention also relates to a method for reading this device. Background Technology

[0002] For applications that require information storage even when the voltage is cut off, non-volatile memories of the EEPROM or FLASH type, which perform charge storage on the floating gate of a field-effect transistor, are conventionally used. However, these memories have the following disadvantages:

[0003] -Long write time (a few microseconds),

[0004] -Limited density, because the reduction in transistor size leads to a reduction in read signals, i.e., a decrease in the difference between the two states of a memory point, and a reduction in the duration of information retention.

[0005] - A limited number of write cycles because the retention of information decreases with each write cycle due to defects generated in the gate oxide of the transistor, allowing electrons to escape from the floating gate.

[0006] Therefore, this type of memory does not have the characteristics required to support the development of new technologies such as SCM memory (“storage-class memory”), which have seen significant growth, particularly due to their ability to increase computer performance while reducing its power consumption.

[0007] Recently, other types of rewritable nonvolatile memories have emerged based on active materials, such as phase change materials (PCRAM memory or "phase change RAM", also known as PCM "phase change memory"), ionicly conductive (CBRAM memory or "conductive bridge RAM"), metal oxide (OxRAM memory or "oxide resistive RAM"), ferroelectric (FERAM memory or "ferroelectric RAM"), magnetic (MRAM memory or "magnetic RAM"), or spin-transferrient magnetic (STTRAM memory or "spin torque transfer RAM"). These memories are resistive (i.e., they can have at least two states, "off" or "conductive," corresponding to switching from a resistive state ("off") to a smaller resistive state ("conductive")).

[0008] Resistive memories require two electrodes to operate. In the case of PCRAM memories, chalcogenide materials are used, and a significant contrast in resistance exists between their amorphous (resistive) phase and their crystalline (conductive) phase. This phenomenon is based on PCRAM phase-change memory, where a phase transition is induced by the Joule effect due to an electrical pulse, the shape of which allows for a specific temperature distribution within the memory. Therefore, PCRAM memories include active regions based on chalcogenide materials. The operation of PCRAM memories is based on the phase transition of the chalcogenide material, which is induced by heating of the material under the action of specific electrical pulses generated by its two electrodes. This transition is accomplished between a low-resistivity and thermodynamically stable ordered crystalline phase and a high-resistivity and thermodynamically unstable disordered amorphous phase.

[0009] In this context, PCRAM resistive memory, based on the most mature non-volatile resistive memory technology, represents a very good candidate for supporting the development of SCM memory.

[0010] Recently, the possibility of systems with 3D-type integration has garnered significant attention, enabling increased memory density on the same chip surface through the integration of several layers of memory stacked on top of each other. This 3D integration is based on the use of "cross" type integration (also referred to by the term "cross point"). PCRAM resistive memory is particularly important for its ability to be integrated at high density via "cross" type integration.

[0011] This architecture 200 in Figure 1 The diagram illustrates and includes multiple access lines 201, 202, 203, and 204, and multiple memory cells (here, four cells C11, C21, C22, and C12) of a non-volatile, rewritable PCRAM type. The access lines are formed by top parallel bit lines 201 and 202 and bottom word lines 203 and 204 perpendicular to the bit lines. The basic cells C11, C21, C22, and C12 are sandwiched at the intersections of bit lines 201 and 202 and word lines 203 and 204. Therefore, architecture 200 forms a network in which each memory cell can be individually addressed by selecting the correct bit lines and the correct word lines.

[0012] However, this type of architecture does have some drawbacks. Therefore, the state reading phase of a cell is performed by polarizing the desired rows and columns; then, parasitic leakage currents through adjacent cells can be observed. Here we assume:

[0013] - Unit C11 is in the off state (high resistance state);

[0014] - Unit C21 is in a conductive state (low resistance state);

[0015] - Unit C22 is in a conductive state (low resistance state);

[0016] - Unit C12 is in a conductive state (low resistance state).

[0017] Reading the resistance state of unit C11 involves polarizing bit line 201 and word line 204 respectively (applying a potential difference Vbias between these two lines). Theoretically, the measurement current should flow only according to arrow 205 as shown by the dashed line. In practice, due to the fact that three other units are in a conductive state, a parasitic leakage current (“leakage”) indicated by arrow 206 passes through non-resistive units C21, C22, and C12. This leakage current, especially in the unfavorable case where adjacent elements of the unit under test are in a conductive state, can interfere with the measurement until it prevents the distinction between the conductive and open states of the unit under test.

[0018] Known solutions to this problem involve adding a p / n junction diode (e.g., with a Si base) 207 in series with each in the cell to act as a selector. The behavior of this "diode" type is defined as the behavior of a device based on two access terminals having a voltage above V. th The voltage has a very low conductivity, and when the voltage exceeds V... th It has high electrical conductivity. Each memory cell is called 1R, and each selector is called 1S. This is therefore referred to as memory point 1R / 1S. Figure 2 The diagram illustrates such an architecture 300. Figure 1 and 2 In the figures, common elements share the same reference numerals; it should be understood that... Figure 2 Units C11, C21, C22, and C12 are in relation to Figure 1 Units C11, C21, C22, and C12 have the same resistance state. In this case, since diodes 207 are unipolar, they block the passage of parasitic current, thus only authorizing the current indicated by arrow 210 caused by the polarization of bit line 201 and word line 204 (a potential difference Vbias is applied between these two lines).

[0019] However, as Figure 2 The architecture shown also raises certain difficulties, particularly related to the fact that standard diodes with Si bases are not the most relevant solution because they are difficult to manufacture, have excessively high series resistance and low current density in the "active" state, which is incompatible with the programming of resistive memories. Consequently, the diode maintains a limited current intensity in conduction mode. Therefore, currently, for a given silicon surface, it is impossible to create a device with the same surface as the memory cell and sufficient current I to pass through it. ON (The diode's current density is too low) and it also has a relatively low leakage current I. OFFThe diode. This situation presents particularly serious difficulties when using diodes connected in series with phase-change type cells of PCRAM that require large switching currents.

[0020] This is why several alternative solutions have been investigated over the past few years. Different types of selectors can be found in the literature, such as FAST (“Field-Assisted Superlinear Threshold”), MIEC (“Mixed Ion Electron Conductivity”), and OTS (“Bidirectional Threshold Switching”).

[0021] The selection device consists of two electrodes and an active material, wherein the electrodes are arranged on either side of the active material, allowing a voltage to be applied to it. In the case of an OTS-type selector, the active material can be a chalcogenide alloy. Figure 3 The diagram illustrates the basic principle of the device's operation. The device is highly resistive in the off state. Once a voltage greater than a threshold voltage is applied, the current rapidly increases to bring the device into a conductive state (low resistance state). Once the current or voltage decreases below a specific value known as a "hold" or "retain" value, the device becomes off again. Therefore, once the threshold voltage V is reached... th The primary function of the selected device is to block the passage of low-voltage current (subthreshold) and allow the passage of high current density.

[0022] The main challenge with the crossover structure is finding a good trade-off in the electrical performance between the memory 1R and the selector 1S. To be integrated with the resistive memory 1R, the selector 1S must exhibit several specific constraints. In fact, when the selector is in its "off" state, it must have a size close to that of the memory and a low leakage current I. OFF At the same time, it remains compatible with the storage characteristics of memory 1R.

[0023] To further improve the integration density of resistive memory, a conventional solution is to reduce the size of the surface between the active material of the resistive memory and its bottom electrode, so as to allow for a reduction in the programming current of the resistive memory.

[0024] According to another storage method, the article "An Access-Transistor-Free (OT / 1R) Non-Volatile Resistance Random Access Memory (RRAM) Using a Novel Threshold Switching, Self-Rectifying Chalcogenide Device" (Yi-Chou Chen et al., IEDM 2003) describes the integration of an active layer made of chalcogenides (Ge2Sb2Te5 is widely used to create PCRAM memories) into the device, allowing for the possibility of different amorphous volumes, different resistances (i.e., if the amorphous volume decreases, the resistance of the programmed state decreases), but, depending on the programming pulse parameters used, particularly different threshold voltages V. th This paper proposes using this electrical property to program information stored in a threshold voltage V by controlling the amorphous volume obtained through electrical pulses of varying intensities. th The parameters formed. This characteristic is also described in patent application US2004 / 0257848A1, which describes the possibility of modulating the threshold voltage by controlling the intensity and duration of the electrical pulse, and using phase-change memory only in its amorphous phase.

[0025] However, the device described in the article "An Access-Transistor-Free (OT / IR) Non-Volatile Resistance Random Access Memory (RRAM) Using a Novel ThresholdSwitching, Self-Rectifying Chalcogenide Device" also has approximately 10 -6 The subthreshold current of A is too high to be used without a selector in the cross array. Furthermore, it has been observed that the programming of these memories is not well controlled, and the duration of the programming pulse must be very short to prevent any crystallization of the material. Summary of the Invention

[0026] This invention provides a solution to the problems mentioned above by proposing a non-volatile memory device adapted for integration into a device with a "cross" architecture, and makes it possible to overcome the limitations of using resistive memory in series with a selector.

[0027] A first aspect of the present invention relates to a selectively non-volatile memory device, the selectively non-volatile memory device comprising:

[0028] -First electrode;

[0029] -Second electrode;

[0030] - At least one layer made of active material, called an active memory layer, is disposed between the first electrode and the second electrode;

[0031] The device has at least two programmable memory states:

[0032] -With the first threshold voltage V of the active layer th1 The associated first programmable non-volatile memory state, in which the device has a characteristic voltage and current, such that once a voltage greater than or equal to V is applied between the first and second electrodes... th1 When the applied voltage is less than V, the device switches from a high-resistance state to a lower-resistance state. th1 When the device returns to its high-resistance state, the current through the memory in the high-resistance state is strictly less than 10 ohms. -7 A;

[0033] - With a voltage strictly greater than the first threshold voltage V th1 The second threshold voltage V th2 The associated second non-volatile memory state, in which the device has a characteristic voltage and current, such that once a voltage greater than or equal to V is applied between the first electrode and the second electrode... th2 When the applied voltage is less than V, the device switches from a high-resistance state to a lower-resistance state. th2 When the device returns to its high-resistance state, the current through the memory in the high-resistance state is strictly less than 10 ohms. -7 A.

[0034] According to the present invention, the active layer is made of a mixture of As2Te3 alloy and Ge3Se7 alloy.

[0035] This invention provides a device that integrates both non-volatile rewritable memory functionality and selective functionality. By using this device, at least two values ​​V can be obtained.th1 and V th2 A programmable threshold voltage is used to provide non-volatile memory functionality: the memory state is given by the value of this programmable threshold voltage in the device. In other respects, unlike PCRAM memory, the non-volatile memory device according to the invention is not a resistive memory because the memory state does not depend on the resistance state of the device. The "selectivity" function is provided by a voltage strictly less than 10. -7 The subthreshold current of A (i.e., when the device depends on whether it is in memory state V) th1 or V th2 separately subjected to strictly less than V th1 or V th2 When the voltage is at a certain level, the current through the device provides a subthreshold current value comparable to those provided by a known selector. Note that the selectivity is volatile in such a way that the voltage at the device terminals depends on whether it is in a memory state V. thl Or V th2 By passing the device under Vth1 or Vth2 respectively, the device becomes strictly less than 10 -7 A is a high-resistivity current with high strength.

[0036] Therefore, the device according to the first aspect of the invention can be considered as a selective device with non-volatile threshold switching (or "NVTS"). The selected material is a chalcogenide material (i.e., a compound containing at least one chalcogenide element, such as oxygen, sulfur, selenium, tellurium, or polonium) obtained by combining As2Te3 and Ge3Se7 alloys, wherein As2Te3 causes "switching" type behavior and Ge3Se7 causes an increase in the system's gap, which allows for a reduction in leakage current.

[0037] Chalcogenide materials will be selected that have very high resistivity in their amorphous static (off state) state and strong conductivity once subjected to a voltage greater than their threshold voltage, such as so-called "OTS" materials, but with the special property of possible threshold voltage modulation.

[0038] Therefore, the material is advantageously chosen to not exhibit any crystallization during its operation. Due to the selection of this particular material, it is possible to:

[0039] - Ensure a very large subthreshold resistance to reduce leakage current in cross-type arrays;

[0040] - It has a programmable threshold voltage that depends on the shape of the applied pulse (in particular, according to the falling flank of the pulse).

[0041] Note that according to this first aspect of the invention, the threshold voltage state V corresponds to... th1The first non-volatile memory state can be achieved by applying a value greater than V. th2 The voltage pulse is programmed to have a predetermined falloff flank with a predetermined non-zero duration, and the falloff flank duration is greater than that of the programming voltage pulse for the second memory state. Therefore, the behavior of the voltage threshold change of the material will be advantageously affected by the duration of the falloff flank of the programming pulse. Interestingly, when reading patent application US2004 / 0257848 A1, one would not naturally gravitate towards a solution where it is clearly stated that using a pulse with a significant falloff flank can trigger crystallization of the material, and thus trigger losses during operation. There is no difference in the use of different falloff flank durations for the two programming states. Furthermore, the falloff flanks described in this patent application are all less than 50 ns, specifically to prevent crystallization. Such a phase transition would involve the possible partial or complete loss of information due to various factors, such as temperature or parasitic effects of the control circuitry.

[0042] Finally, it is interesting to observe that the programming of the highest threshold voltage in this patent application is obtained by applying a given programming current and a voltage pulse greater than the highest voltage threshold (this deviates from the device according to the first aspect of the invention, wherein the highest threshold voltage V th2 Programming is achieved by applying the included V th1 With V th2 Between, and therefore less than V th2 (obtained from voltage pulses).

[0043] In addition to the features already mentioned in the preceding paragraphs, a device according to one aspect of the invention may have one or more of the following additional features, which are considered individually or according to any technically permissible combination:

[0044] - The mixture contains more than 15% and strictly less than 60% of As2Te3 alloy by weight.

[0045] - The mixture contains substantially 20% As2Te3 alloy by weight.

[0046] -Based on the first threshold voltage V th1 With the second threshold voltage Vth2 The desired difference between the two values ​​determines the thickness of the active layer.

[0047] - The active layer consists of a single active layer made of a mixture of As2Te3 alloy and Ge3Se7 alloy.

[0048] - The active layer consists of a stack of layers, each with a thickness of less than or equal to 5 nm. These layers together form a stack of a mixture of As2Te3 alloy and Ge3Se7 alloy to form the active layer.

[0049] A second aspect of the invention relates to a method for writing a second memory state in a device according to the invention, by applying a given programming current and including V th1 With V th2 The second non-volatile memory state is programmed by a current pulse with a predetermined duration falling flank.

[0050] A third aspect of the invention relates to a method for writing a first memory state into a device according to the invention, by applying an application greater than V th2 A voltage pulse is used to program a first non-volatile memory state, the voltage pulse having a predetermined fall flank with a predetermined non-zero duration, and a duration greater than the fall flank duration of the programming voltage pulse for a second memory state written by the method according to the second aspect of the invention.

[0051] Advantageously, greater than V th2 The voltage pulse with a predetermined non-zero duration falling flank preferably includes 10 6 V / s and 10 8 The slope between V / s.

[0052] A fourth aspect of the invention relates to a method for reading the memory state of a device according to the invention, the method comprising the steps of: applying a force strictly greater than V th1 And strictly less than V th2 The voltage pulse has a predetermined falling wing with a predetermined non-zero duration, and is longer than the duration of the falling wing of the programming voltage pulse of the second memory state written by the method for writing according to the second aspect of the invention.

[0053] The invention and its various applications will be better understood when reading the following description and when examining the accompanying drawings. Attached Figure Description

[0054] These figures are shown for informational purposes and are in no way intended to limit the invention.

[0055] Figure 1 A first addressing architecture for multiple memory cells according to the prior art is shown;

[0056] Figure 2 A second addressing architecture for multiple memory cells according to the prior art is shown;

[0057] Figure 3A diagram illustrating the operating principle of the selective device is shown;

[0058] Figure 4 A diagram of a device according to a first aspect of the present invention is shown;

[0059] Figure 5 This illustrates how, based on the voltage applied between the bottom and top electrodes of the device, [the following is observed]... Figure 4 The change in current on the logarithmic scale of the device;

[0060] Figure 6 The illustration shows how it can be used. Figure 4 The device serves as an example of memory programming and read pulses;

[0061] Figure 7 Showing according to Figure 4 The slope of the falling flank of the programming pulse and the behavior of the threshold voltage of the active layer of the device are determined by the three materials.

[0062] Figure 8 It shows that according to Figure 4 The slope of the falling flank of the programming pulse for the active layer of the device of three materials, and the behavior of the subthreshold current.

[0063] Figure 9 It shows Figure 4 The slope of the descending side "ramp" of the programming pulse of the device;

[0064] Figure 10 The diagram shows the voltage thresholds for four different thicknesses of the active layer. Figure 4 The voltage threshold variation of the active layer material of the device in an embodiment.

[0065] Figure 11 Another embodiment of the programming pulse is shown. Detailed Implementation

[0066] Unless otherwise noted, the same element appearing in different figures has a unique reference numeral.

[0067] As should be seen below, device 1 is a device used as a non-volatile memory and a selector, wherein these two functions are integrated into the same device 1, which includes:

[0068] - First electrode or bottom electrode 3;

[0069] -Second electrode or top electrode 4;

[0070] - Layer 2, made of active material, is called the active storage layer and is disposed between the first electrode and the second electrode.

[0071] The top electrode of the device is defined as the electrode located above the device, and the bottom electrode of the device is defined as the electrode located below the device, with these electrodes located on each side of the device. Of course, the adjectives "top" and "bottom" are used here to such an extent, relative to the assembly including the top electrode, the device, and the bottom electrode, that when the assembly is flipped, the electrode previously identified as top becomes the bottom electrode, and the electrode previously identified as bottom becomes the top electrode. Similarly, the vertical arrangement of the electrodes may also include an active layer 2 arranged between the two electrodes 3 and 4.

[0072] The bottom electrode 3 and the top electrode 4 are each made of a conductive material, which can be different or the same for the two electrodes 3 and 4. Such conductive materials are, for example, TiN, TaN, W, TiWN, TiSiN, or WN.

[0073] For example, the active layer 2 is a layer of chalcogenide-type active material implemented by mixing (e.g., by co-sputtering) an As2Te3 and Ge3Se7 alloy. Advantageously, the mixture forming the active material contains more than 15% and strictly less than 60% As2Te3 by weight. As a preferred embodiment, the mixture forming the active material here contains 20% As2Te3 by weight. The principle of co-sputtering is to use the energy of plasma on the surface of one or more sputtering targets (here, As2Te3 and Ge3Se7 targets) to pull out the atoms of the material of this or these targets one by one and deposit them onto, for example, the bottom electrode 3.

[0074] The material of active layer 2 is chosen to allow device 1 to have very high resistivity in its amorphous resting state (the so-called "off" state) and strong conductivity once subjected to a voltage greater than a threshold voltage. The specificity of the chosen material allows modulation of this threshold voltage, which can have several values ​​(at least two threshold voltages V). th1 and V th2 This is due to the control of the descent flank of the electrically programmed pulse, which will be further covered below. Figure 5 The two threshold voltages V are shown in the figure. th1 and V th2 The existence of (it should be understood that more than two threshold voltages with specific programming can be considered) is illustrated in the figure for two threshold voltages V obtained by programming device 1. th1 and V th2 The change in current through device 1 (on a logarithmic scale) is based on the voltage applied between the bottom 3 and top 4 electrodes. Note that in the embodiment described here, the second threshold voltage V... th2 Strictly greater than the first threshold voltage V th1 .

[0075] Therefore, when device 1 has a threshold voltage V th1 At that time, as long as the voltage at the terminal of device 1 is strictly less than V th1 The intensity of the current passing through the device (by I) Leak The subthreshold current (or subthreshold current specification) is very low (therefore, the device's resistance is very strong). Once the threshold voltage V is reached... th1 The current increases rapidly, and device 1 becomes highly conductive. Once the voltage drops back to V... thl Next, device 1 again becomes a low conductor. Note that the material of the active layer is chosen here to make the subthreshold current particularly low; otherwise, the intensity of the subthreshold current is strictly less than 10. -7 A.

[0076] When device 1 has a voltage V that is strictly greater than the first threshold voltage V th1 The second threshold voltage V th2 The behavior of the devices is similar in this case. In this situation, the voltage at the terminals of device 1 must be strictly less than V. th2 The current passing through it (I) Leak The intensity of the current (or subthreshold current) is very low. Once the threshold voltage V is reached... th2 The current increases rapidly, and device 1 becomes highly conductive. Once the voltage drops back to V... th2 Next, device 1 becomes a low conductor again. Here again, the subthreshold current intensity is strictly less than 10. -7 A.

[0077] The specific properties of the material selected for active layer 2 will enable it to provide a threshold voltage V based on the type of electrical programming pulse in device 1. th Modulation. In other respects, device 1 has at least two different voltage thresholds (first threshold voltage V) due to the material of the active layer. th1 Second threshold voltage V th2 This voltage threshold will react differently depending on the shape of the electrical programming pulse, and particularly on the falling flank of the electrical programming pulse. This operation will be explained in more detail below.

[0078] It should be understood that, unlike resistive memories of the PCRAM or CBRAM type, the memory state does not depend on the resistivity of device 1, but rather on the value of the threshold voltage V. th1 or V th2 It can be programmed and written to device 1 in a non-volatile manner. Therefore, device 1 according to the invention can be specified by the term "NVTS" or "non-volatile threshold switching" (device with a non-volatile switching threshold). The memory information is given here by the value of the threshold voltage.

[0079] Furthermore, it has a strict value of less than 10. -7 The intensity of the subthreshold current of A and the volatile behavior of the resistivity of device 1 (i.e., the device switches to a conducting state or a resistive state according to whether the voltage is higher or lower than the threshold voltage) make it possible for device 1 to also act as a selector; in the cross-type configuration, the current through the device is very low when there is no polarization voltage greater than the threshold voltage at the terminals of the device, and parasitic leakage current of the "leaking" type can be prevented.

[0080] Therefore, device 1 is both a non-volatile memory device (with a threshold voltage for storing information) and a selector (with very low leakage current).

[0081] The following will explain the reference. Figure 6 Programming and reading of the device 1 according to the present invention. Figure 6 An embodiment of time-based programming voltage pulses (three pulses 100, 101, and 102) and readout is shown, enabling the use of the device 1 according to the invention as a memory. Note that the programming and readout voltages can be reversed in polarity, as the device according to the invention responds equally to pulses with reversed signs. Therefore, when the reference voltage has a voltage less than the second threshold voltage V... th2 The intensity of the first voltage V th1 When comparing two negative voltages, it is important to understand that the absolute values ​​of the two voltages should be compared.

[0082] Pulse 100 (called RESET) causes device 1 to reach the second threshold voltage V. th2 A programming pulse indicating the programming state. This pulse includes a first threshold voltage V. th1 With the second threshold voltage V th2 The voltage intensity between them.

[0083] According to the first configuration, device 1 is already under the condition of the second threshold voltage V. th2 The device is in the programmed state indicated. In this case, device 1 will remain in this state. In fact, sufficient programming current must flow in device 1 for a change in the threshold voltage to occur. Here, according to... Figure 5 When the voltage value remains at the second threshold voltage V th2 In the following situations, no switching will occur. Furthermore, this characteristic allows for the maintenance of device 1's durability. However, according to the second configuration, if the device is under the threshold voltage V... th1 In the programming state indicated, when the programming voltage exceeds the threshold voltage V th1At this time, device 1 switches to a conductive state, allowing a significant level of programming current to pass through. The duration of the falling flank of pulse 100 is very short (close to zero). For the specific material of active layer 2, the combination of the presence of a significant programming current (i.e., the conductive state of device 1) and the appropriate selection of the substantially zero duration of the falling flank of the pulse makes it possible to modify the threshold voltage of device 1, and to have a voltage range from V... th1 To V th2 The subsequent changes (therefore, the write memory state V) th2 Although memory state V th1 (Written into memory device 1).

[0084] The correlation between the fall duration of the programming pulse and the threshold voltage is in Figure 7 As shown in the figure, Figure 7 The threshold voltage V is shown for three materials, Mat1, Mat2, and Mat3, in the active layer. th (in volts) Behavior based on the slope of the descending flank (in V / s).

[0085] The active material Mat1 is a mixture of As2Te3 and Ge3Se7 alloys, containing 20% ​​As2Te3 by weight.

[0086] The active material Mat2 is a mixture of As2Te3 and Ge3Se7 alloys, containing 40% As2Te3 by weight.

[0087] The active material Mat3 is a mixture of As2Te3 and Ge3Se7 alloys, containing 60% As2Te3 by weight.

[0088] Figure 9 The slope (“ramp”) of the descent flank is defined in the code. This is the ratio between the maximum amplitude of the programming voltage pulse and the duration of the descent flank. In other respects, for a given amplitude, the shorter the duration of the descent flank, the greater the slope.

[0089] exist Figure 7 It was observed that, for material Mat1, the threshold voltage increases significantly with the slope of the descending flank. Therefore, for composition Mat1, there exists a threshold voltage V. th The window, the threshold voltage V th The window is from a voltage threshold of approximately 2.25V (for approximately 0.510V). 7 The slope of V / s, i.e., the duration of the significant drop flank, is approximately 3.5V to the threshold voltage (for approximately 0.8.10). 9 The slope of V / s (i.e., the duration of a very short descent flank) is very significant within the range.

[0090] Therefore, if the device is under the threshold voltage V th1 In the programmed state indicated, and with the very short duration of the falling wing of pulse 100 used for device 1 in a conductive state, the value of the threshold voltage will be modified due to the duration of the wing, and the threshold voltage will be changed to the value V by selecting an appropriate duration for the falling wing. th2 .

[0091] Pulse 101 (referred to as setting) is used to bring device 1 to the level of the first threshold voltage V. th1 The programming pulse indicates the programming state. This pulse has a voltage greater than the second threshold voltage V. th2 The voltage intensity and the duration of the descent flank with a duration greater than 100 pulses.

[0092] Here, unlike reset programming, the effect of pulse 101 is independent of the initial memory state. This is because programming pulse 101 has a voltage exceeding the second threshold voltage V. th2 The voltage intensity (and, therefore, not to mention the threshold voltage V) th1 Therefore, once its threshold voltage is exceeded (regardless of its value in V), th1 Or V th2 Device 1 will then become conductive. Therefore, the current will reach a substantially sufficient level. The invention then lies in the selection of the material of the active layer 2, thereby reducing the duration of the sidewalls so that the first threshold voltage V can be transmitted. th1 Here, the slope (“ramp rate”) of the descending flank is advantageously included in 10. 7 V / s and 10 6 Between V / s, this can, for example, cause a 3.5V pulse for a duration including a drop flank between 350ns and 3.5μs. By applying this reduced duration, the first threshold voltage V th1 The "write" is in device 1.

[0093] exist Figure 7 It was observed that material Mat1 has the largest memory window relative to materials Mat2 and Mat3 (and therefore, the first threshold voltage V). th1 With the second threshold voltage V th2 (the maximum difference between them). Therefore, it is preferable to choose an As2Te3 alloy of about 20% by weight. However, material Mat2, with an As2Te3 alloy of about 40% by weight, also offers this possibility of a more reduced window. On the other hand, material Mat3, with an As2Te3 alloy of about 60% by weight, has a window that is too small to allow writing two different voltage thresholds in the same device according to the invention. Note that the threshold voltage V at both ends of the curve can be selected.th1 and V th2 (Vthmin and Vthmax), but nothing prevents them from being placed at another location on the curve: in this case, therefore, the duration of the slope of the descending flank will be adapted (and, if the second threshold voltage V is considered to be...). th2 Below V th2 If the maximum value is reached, then the duration of pulse 101 is reduced.

[0094] Advantageously, the alloy used for the active layer 2 does not exhibit any crystallization during the operation of the device 1 as an NVTS.

[0095] This type of behavior relates to the reorganization of the material structure that occurs during the application of a pulse with a sufficiently long drop flank, causing a decrease in the device's threshold voltage. It should be emphasized that even though a crystalline phase is present for As2Te3 and for Ge3Se7, no corresponding crystalline phase is present in the case of the considered mixture of As2Te3 and Ge3Se7 alloys. Phase segregation alone can cause the formation of one or more crystalline phases (i.e., e.g., after excessive temperature rise, after cycling through the device's over-resistive / over-conducting states, etc.). However, NVTS-type behavior can be obtained by retaining an amorphous phase parallel to the partially or fully crystalline phase in the device. This configuration is also compatible with the memory and selective functionality of the device 1 for the purposes of this invention.

[0096] Typically, methods for programming the device according to the present invention include:

[0097] - The reset step includes applying a method based on the material of the active layer of device 1, including V th1 and V th2 A voltage pulse with a predetermined duration falling flank is applied between the two voltage pulses to cause device 1 to reach a voltage level equal to the first threshold voltage V. th2 The programming state indicated;

[0098] - The setup steps include applying a predetermined descent wing with a predetermined non-zero duration greater than V, based on the material of the active layer of device 1. th2 And a voltage pulse longer than the duration of the falling flank of the reset programming voltage pulse, so that device 1 reaches the second threshold voltage V. th1 The programming state is represented.

[0099] Figure 8 The behavior of the subthreshold current (“leakage current”) for the three materials Mat1, Mat2, and Mat3 in the active layer 2 of device 1, based on the slope of the falling flank of the programming pulse, is illustrated. It was observed that for all three materials Mat1, Mat2, and Mat3, the subthreshold current remains well below 10 Ω·cm. -7A is a very low value, regardless of the slope of the falling flank of the programming pulse. This behavior allows for selective functionality of device 1.

[0100] Figure 6 The pulse 102 shown is a pulse that enables the reading of the memory state of device 1. The read pulse 102 is generated by a pulse having a first threshold voltage V. th1 Second threshold voltage V th2 The pulse is formed between the intermediate voltages. This is achieved by reading the voltage from the first threshold voltage V. th1 In the case of the programming state indicated, due to the threshold voltage V being exceeded... th1 Device 1 will become conductive, but a falling flank with a pulse duration substantially the same as the duration of the set-write will make it possible to reconstruct the voltage from the first initial threshold voltage V. th1 The programming state is represented, but the second programming state V is not written. th2 The risk of [something]. Detecting the current through device 1 indicates that device 1 is in a memory state V. th1 Conversely, the reading is performed by the second threshold voltage V. th2 In the indicated programming state, device 1 will remain resistive (no switching) because the second threshold voltage V is not exceeded. th2 In device 1, there is no current detection indicator that the device is in memory state V. th2 If no switch occurs, read state V. th2 And at the same time maintain this state V th2 There is no risk of interference (such as untimely writes).

[0101] Typically, the method for reading the memory state of a device according to the present invention includes applying a force strictly greater than V. th1 And strictly less than V th2 The step of the voltage pulse, wherein the voltage pulse has a predetermined falling flank of a predetermined non-zero duration and is greater than the second memory state V. th2 The duration of the falling flank of the programming voltage pulse (advantageously, with respect to the first memory state V) th1 The duration of the falling flank of the programming voltage pulse is substantially the same, that is, it has an advantage of including 10 7 V / s and 10 6 (the slope of the descending flank between V / s).

[0102] Given the influence of the slope of the programming pulse on the material of active layer 2, V can be considered. th1 and V th2 Intermediate programming states between these states are used to obtain multi-level programming of the MLC ("Multi-level Unit") type.

[0103] It should also be noted that the thickness of the active layer is advantageously determined according to the first threshold voltage V. th1 With the second threshold voltage V th2 The selection is based on the expected difference between them. Specifically in... Figure 10 The option is shown in the image. Figure 10 The diagram illustrates the variation of the voltage threshold of material Mat2 based on four different thicknesses of the active layer 2: 10 nm, 15 nm, 25 nm, and 50 nm. Therefore, increasing the thickness of the active layer advantageously increases the memory window, i.e., the possible difference between the minimum and maximum threshold voltages. This increase deviates from the current trend in PCRAM, which aims to reduce the thickness of PCRAM.

[0104] Although the invention has been described more specifically in the case of a mixture of d'As2Te3 and Ge3Se7, other alloys can be used, for example, in combination with matrices of Si, Ge, As, Sb, Bi, S, Se, and Te, and also in conjunction with the introduction of elements (i.e., dopants) such as C, N, or O. In particular, AsSe, AsTe, GeSe, and GeS alloys with different stoichiometry are among those alloys that can be combined to obtain the desired mechanism. Advantageously, combinations between type IV-VI alloys (e.g., having Ge and Se matrices) and type VI-V alloys (e.g., having As and Te matrices) can be used, with the interstitial energy of the type IV-VI alloys being significantly higher than that of the type VI-V alloys. Furthermore, it should be noted that although the active layer 2 is described as a material layer (a mixture of As2Te3 and Ge3Se7 alloys), configurations of active layers in the form of multilayer materials providing memory behavior and NVTS selectors are also applicable to devices according to the invention.

[0105] Deposition techniques for different layers (electrodes, active layers) are well known to those skilled in the art. These can be, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) techniques.

[0106] Of course, the programming described above is given for illustrative purposes only; intelligent programming can be considered, where the pulses can depend on the initial programming state of the device. For example, this is the case when the device according to the invention has just been read, and the state to be programmed corresponds to the state just read: in this case, programming pulses can be overcome.

[0107] Similarly, this allows us to obtain the memory state V. th1 Any form of pulse that restructures the material's structure certainly constitutes a possible alternative. In particular, this can be achieved by considering the threshold voltage V. th The changes have an effective effect on the same flank portion to further reduce the pulse's descent flank. Figure 11 This type of pulse 200 is shown in the image. (Compared to...) Figure 6 Conversely, pulse 200, also known as the setting pulse 101, is used to bring device 1 to the level of the first threshold voltage V. th1 The programming pulse indicates the programming state. This pulse 200 has a voltage greater than the second threshold voltage V. th2 The voltage intensity and reduced descent flank 201, but its duration remains greater than Figure 6 The duration of the descent flank of pulse 100. This commentary is also valid for reading pulses.

[0108] Figure 6 and Figure 11 The total duration of each pulse is selected to ensure that the device switches (if necessary) and the programming current reaches state V through a sufficient duration. th2 For a mixture of As2Te3 and Ge3Se7 alloys, the total duration can, for example, be between 10 ns and 300 ns. The programming current, depending on the size (i.e., surface area) of the device according to the invention, is between 1 mA and 2 mA in our example case.

[0109] In an alternative, the device according to the invention can be co-integrated in series with a resistive memory to produce a device that allows access (reading and programming) of the resistive memory using the selectability features of the device according to the invention, while also having inherent memory characteristics.

Claims

1. A selective non-volatile memory device (1), comprising: - First electrode (3); - Second electrode (4); - At least one layer (2) made of active material, called an active memory layer, is disposed between the first electrode and the second electrode; The selective non-volatile memory device (1) has at least two programmable memory states: - with the first threshold voltage V for the active layer (2) th1 The associated first programmable nonvolatile memory state, in which the selective nonvolatile memory device has a characteristic voltage and current, such that once a voltage greater than or equal to V is applied between the first and second electrodes... th1 When the applied voltage is less than V, the selective non-volatile memory device switches from a high-resistance state to a lower-resistance state, and this happens when the applied voltage is strictly less than V. th1 When the selective non-volatile memory device returns to its high-resistance state, the current through the selective non-volatile memory device in the high-resistance state is strictly less than 10. -7 A; - With a voltage strictly greater than the first threshold voltage V th1 The second threshold voltage V th2 The associated second non-volatile memory state, in which the selective non-volatile memory device has a characteristic voltage and current, such that once a voltage greater than or equal to V is applied between the first and second electrodes... th2 When the applied voltage is less than V, the selective non-volatile memory device switches from a high-resistance state to a lower-resistance state, and this happens when the applied voltage is strictly less than V. th2 When the selective non-volatile memory device returns to its high-resistance state, the current through the selective non-volatile memory device in the high-resistance state is strictly less than 10. -7 A; The active memory layer is made of a mixture of As2Te3 alloy and Ge3Se7 alloy.

2. The selective non-volatile memory device according to claim 1, characterized in that, The mixture contains more than 15% and strictly less than 60% by weight of As2Te3 alloy.

3. The selective non-volatile memory device according to claim 2, characterized in that, The mixture contains substantially 20% by weight of As2Te3 alloy.

4. The selective non-volatile memory device according to claim 1, characterized in that, According to the first threshold voltage V th1 With the second threshold voltage V th2 The thickness of the active memory layer is selected based on the expected difference between the two values.

5. The selective non-volatile memory device according to claim 1, characterized in that, The active memory layer consists of a single active layer made of a mixture of As2Te3 alloy and Ge3Se7 alloy.

6. The selective non-volatile memory device according to claim 1, characterized in that, The active memory layer is composed of stacked layers, each layer having a thickness of less than or equal to 5 nm.

7. A method for writing a second non-volatile memory state into a selective non-volatile memory device according to any one of claims 1 to 6, characterized in that, By applying a given programmed current and a descent flank with a predetermined duration, including V th1 With V th2 The current pulses between the two signals program the state of the second non-volatile memory.

8. A method for writing a first programmable non-volatile memory state into a selective non-volatile memory device according to any one of claims 1 to 6, characterized in that, By applying a predetermined descent flank with a predetermined non-zero duration greater than V th2 The first programmable nonvolatile memory state is programmed by a voltage pulse and a falling wing of a programming voltage pulse greater than the duration of the second nonvolatile memory state written by the method according to claim 7.

9. The method according to claim 8, characterized in that, Greater than V th2 The voltage pulse with a predetermined non-zero duration falling flank has included 10 6 V / s and 10 8 The slope between V / s.

10. A method for reading the memory state of a selective non-volatile memory device according to any one of claims 1 to 6, characterized in that, The method includes the following steps: applying an element with a value strictly greater than V. th1 And strictly less than V th2 A voltage pulse having a predetermined falling wing of a predetermined non-zero duration, and longer than the duration of the falling wing of the programming voltage pulse for the second non-volatile memory state written by the method according to claim 7.

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