Array substrate, display device

Abstract

The present disclosure relates to the field of display technology, and proposes an array substrate and a display device. The array substrate includes a base substrate, a first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer is located on one side of the base substrate, and includes a first conductive portion for forming a gate of a driving transistor, and a second conductive portion for forming a first electrode of a capacitor; the second conductive layer is arranged on the side of the first conductive layer away from the base substrate, and includes a third conductive portion for forming a second electrode of the capacitor, and the orthographic projection of the third conductive portion on the base substrate at least partially overlaps with the orthographic projection of the second conductive layer on the base substrate; the third conductive layer is arranged on the side of the second conductive layer away from the base substrate, and includes a fourth conductive portion, and the orthographic projection of the fourth conductive portion on the base substrate at least partially overlaps with the orthographic projection of the third conductive portion on the base substrate, and the fourth conductive portion is electrically connected to the second conductive portion, and is used to form the first electrode of the capacitor. The capacitor in this array substrate has a large capacitance value.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] In related technologies, OLED display panels typically include a pixel driver circuit, which includes a driver transistor and a capacitor. During the display panel's light-emitting phase, the driver transistor uses the charge stored in the capacitor to provide a driving current to the light-emitting unit. However, in high-pixel-density display panels, the layout space available for capacitor placement is limited, resulting in the capacitor failing to meet the required capacitance parameters.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field.

[0004] Disclosed content

[0005] According to one aspect of the present disclosure, an array substrate is provided, wherein the array substrate includes a pixel driving circuit, the pixel driving circuit includes a driving transistor and a capacitor connected to the gate of the driving transistor, and the array substrate also includes: a base substrate, a first conductive layer, a second conductive layer, and a third conductive layer. A first conductive layer is located on one side of the base substrate, the first conductive layer includes: a first conductive portion and a second conductive portion, the first conductive portion is used to form the gate of the driving transistor; the orthographic projection of the second conductive portion on the base substrate does not intersect with the orthographic projection of the first conductive portion on the base substrate, and the second conductive portion is used to form part of the first electrode of the capacitor; a second conductive layer is arranged on the side of the first conductive layer away from the base substrate, the second conductive layer includes a third conductive portion, the orthographic projection of the third conductive portion on the base substrate at least partially overlaps with the orthographic projection of the second conductive portion on the base substrate, and the third conductive portion is electrically connected to the first conductive portion, and the third conductive portion is used to form the second electrode of the capacitor; a third conductive layer is arranged on the side of the second conductive layer away from the base substrate, the third conductive layer includes a fourth conductive portion, the orthographic projection of the fourth conductive portion on the base substrate at least partially overlaps with the orthographic projection of the third conductive portion on the base substrate, and the fourth conductive portion is electrically connected to the second conductive portion, and the fourth conductive portion is used to form part of the first electrode of the capacitor.

[0006] In an exemplary embodiment of the present disclosure, the orthographic projection of the first conductive portion and the orthographic projection of the third conductive portion on the base substrate are spaced apart in a first direction, and the third conductive layer further comprises:

[0007] The first connection part extends along the first direction in the orthographic projection of the substrate substrate. The first connection part is electrically connected to the first conductive part through a via hole, and the first connection part is electrically connected to the third conductive part through a via hole.

[0008] In an exemplary embodiment of the present disclosure, the fourth conductive part includes a first sub-conductive part; the orthographic projection of the first sub-conductive part on the substrate substrate does not intersect with the orthographic projection of the third conductive part on the substrate substrate, and the orthographic projection of the first sub-conductive part on the substrate substrate at least partially coincides with the orthographic projection of the second conductive part on the substrate substrate; the first sub-conductive part is electrically connected to the second conductive part through a via hole.

[0009] In an exemplary embodiment of the present disclosure, the third conductive layer further includes a power line that extends along the first direction. The orthographic projection of the third conductive part on the substrate substrate is located on one side of the orthographic projection of the power line on the substrate substrate in the second direction, and the first direction intersects with the second direction; wherein, the fourth conductive part is electrically connected to the power line, and the orthographic projection of the fourth conductive part on the substrate substrate is located on one side of the orthographic projection of the power line on the substrate substrate in the second direction.

[0010] In an exemplary embodiment of the present disclosure, the array substrate includes a plurality of the pixel driving circuits; the first conductive layer includes a plurality of the second conductive parts, and the orthographic projections of the plurality of second conductive parts on the substrate substrate are spaced apart along the second direction.

[0011] In an exemplary embodiment of the present disclosure, the third conductive layer includes a plurality of the power lines that are spaced apart along the second direction. The plurality of power lines include adjacent first power line and second power line. The orthographic projection of the second power line on the substrate substrate is located on one side of the orthographic projection of the first power line on the substrate substrate in the second direction; the second conductive part is electrically connected to the first power line through the first sub-conductive part, and the second conductive part is connected to the second power line through a via hole.

[0012] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a second transistor. The first pole of the second transistor is connected to the first pole of the driving crystal, and the second pole is connected to the gate of the driving transistor. The first conductive layer further includes a first gate line that extends along the second direction in the orthographic projection of the substrate substrate, and the orthographic projection of the first gate line on the substrate substrate is located between the orthographic projection of the first conductive part on the substrate substrate and the orthographic projection of the second conductive part on the substrate substrate. Part of the first gate line is used to form the gate of the second transistor.

[0013] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a first transistor, a first electrode of the first transistor is connected to a second electrode of the second transistor, the first conductive layer further includes a second gate line, the second gate line extends along the second direction on the orthographic projection of the substrate, and the orthographic projection of the second gate line on the substrate is located on a side of the orthographic projection of the second conductive portion on the substrate away from the orthographic projection of the first gate line on the substrate, and a portion of the second gate line is used to form a gate of the first transistor.

[0014] In an exemplary embodiment of the present disclosure, the array substrate also includes an active layer, which is arranged between the base substrate and the first conductive layer. The active layer includes a first active portion, and the first active portion extends along the first direction in the orthographic projection of the base substrate. The first active portion is used to electrically connect the second electrode of the second transistor and the first electrode of the first transistor; wherein the orthographic projection of the first active portion on the base substrate passes through the gap between adjacent second conductive portions arranged on the orthographic projection of the base substrate.

[0015] In an exemplary embodiment of the present disclosure, the third conductive layer also includes a fifth conductive portion, which is electrically connected between the fourth conductive portion and the power line, the power line includes a first edge, and the fifth conductive portion includes a second edge connected to the first edge, and the angle formed by the orthographic projection of the first edge on the substrate and the orthographic projection of the second edge on the substrate is less than 180°; the orthographic projection of the fifth conductive portion on the substrate at least partially overlaps with the orthographic projection of the first active portion on the substrate.

[0016] In an exemplary embodiment of the present disclosure, the first conductive layer further includes: a sixth conductive portion, the sixth conductive portion extending along the first direction on the orthographic projection of the substrate and connected to the first gate line; the active layer further includes a second active portion, a third active portion, and a fourth active portion, the orthographic projection of the second active portion on the substrate is located on the orthographic projection of the first gate line on the substrate, and the second active portion is used to form a first channel region of the second transistor; the orthographic projection of the third active portion on the substrate is located on the orthographic projection of the sixth conductive portion on the substrate, and the third active portion is used to form a second channel region of the second transistor; the fourth active portion is connected between the second active portion and the third active portion, and the orthographic projection of the fourth active portion on the substrate does not intersect with the orthographic projection of the first conductive layer on the substrate; the third conductive layer further includes a seventh conductive portion, the seventh conductive portion is connected to the fourth conductive portion, and the orthographic projection of the seventh conductive portion on the substrate at least partially overlaps with the orthographic projection of the fourth active portion on the substrate.

[0017] In an exemplary embodiment of the present disclosure, the active layer further includes: a fifth active portion, the fifth active portion is connected between the third active portion and the first active portion, and the orthographic projection of the fifth active portion on the substrate does not intersect with the orthographic projection of the first conductive layer on the substrate; and the orthographic projection of the fifth active portion on the substrate at least partially coincides with the orthographic projection of the first connection portion on the substrate, and the fifth active portion is electrically connected to the first connection portion through a via hole.

[0018] In an exemplary embodiment of the present disclosure, the active layer further includes: a sixth active portion, the orthographic projection of the sixth active portion on the substrate is strip-shaped and extends along the second direction, and the sixth active portion is used to form the channel region of the driving transistor.

[0019] In an exemplary embodiment of the present disclosure, the size of the orthographic projection of the sixth active portion on the substrate in the first direction is 1.1-1.5 times the size of the orthographic projection of the first gate line on the substrate in the first direction.

[0020] In an exemplary embodiment of the present disclosure, the orthographic projection of the first conductive portion on the substrate is strip-shaped and extends along the second direction, and the size of the orthographic projection of the first conductive portion on the substrate in the second direction is 2.5-5 times its size in the first direction.

[0021] In an exemplary embodiment of the present disclosure, the active layer further includes: a seventh active portion, an eighth active portion, and a ninth active portion. The orthographic projection of the seventh active portion on the substrate is located on the orthographic projection of the second gate line on the substrate and is used to form the first channel region of the first transistor; the orthographic projection of the eighth active portion on the substrate is located on the orthographic projection of the second gate line on the substrate and is used to form the second channel region of the first transistor; the ninth active portion is connected between the seventh active portion and the eighth active portion, and the orthographic projection of the ninth active portion on the substrate does not intersect with the orthographic projection of the first conductive layer on the substrate. The third conductive layer further includes an eighth conductive portion, the eighth conductive portion is electrically connected to the power supply line, the power supply line includes a third edge, the eighth conductive portion includes a fourth edge connected to the third edge, and the included angle formed by the orthographic projection of the third edge on the substrate and the orthographic projection of the fourth edge on the substrate is less than 180°; the orthographic projection of the eighth conductive portion on the substrate at least partially coincides with the orthographic projection of the ninth active portion on the substrate.

[0022] In an exemplary embodiment of the present disclosure, the third conductive layer further includes a plurality of data lines. The positive projections of the plurality of data lines on the substrate are spaced apart along the second direction and extend along the first direction. The plurality of data lines include a first data line. The positive projection of the first data line on the substrate is located between the positive projection of the second power supply line on the substrate and the positive projection of the fourth conductive portion on the substrate. And the positive projection of the first data line on the substrate at least partially coincides with the positive projection of the second conductive portion on the substrate.

[0023] According to one aspect of the present disclosure, a display device is provided, and the display device includes the above-mentioned array substrate.

[0024] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0026] Figure 1 is a schematic circuit diagram of a pixel driving circuit of the present disclosure;

[0027] Figure 2 is Figure 1 a timing diagram of each node in a driving method of the pixel driving circuit;

[0028] Figure 3 is a structural layout of an array substrate in the related art;

[0029] Figure 4 is Figure 3 a partial cross-sectional view along the dashed line A in ;

[0030] Figure 5 is a partial structural layout of an exemplary embodiment of an array substrate of the present disclosure;

[0031] Figure 6 is Figure 5 a cross-sectional view along the dashed line A in ;

[0032] Figure 7 is Figure 6 a structural layout of the first conductive layer in ;

[0033] Figure 8 is Figure 6 a structural layout of the second conductive layer in ;

[0034] Figure 9 For Figure 6 the structural layout of the third conductive layer in;

[0035] Figure 10 For Figure 6 the layout structure of the active layer in;

[0036] Figure 11 the structural layout of another exemplary embodiment of the disclosed array substrate;

[0037] Figure 12 For Figure 11 the structural layout of the active layer in;

[0038] Figure 13 For Figure 11 the structural layout of the first conductive layer in;

[0039] Figure 14 For Figure 11 the structural layout of the second conductive layer in;

[0040] Figure 15 For Figure 11 the structural layout of the third conductive layer in;

[0041] Figure 16 the structural layout of another exemplary embodiment of the disclosed array substrate;

[0042] Figure 17 For Figure 16 the structural layout of the anode layer in. Detailed implementation manners

[0043] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more complete and comprehensive, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote the same or similar structures, and thus their detailed description will be omitted.

[0044] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the directions of the examples described in the accompanying drawings. It can be understood that if the device of the icon is flipped so that it is upside down, the component described as "upper" will become the component described as "lower". Other relative terms such as "higher", "lower", "top", "bottom", "left", "right", etc. also have similar meanings. When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is "directly" disposed on another structure, or that a structure is "indirectly" disposed on another structure through another structure.

[0045] The terms "a", "an", and "the" are used to denote the presence of one or more elements / components / distinctions / etc.; the terms "comprising" and "having" are used to denote an open-ended inclusion meaning and mean that there may be additional elements / components / distinctions / etc. in addition to the listed elements / components / distinctions / etc.

[0046] As Figure 1 shown, it is a schematic circuit diagram of a pixel driving circuit according to the present disclosure. The pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. Among them, the first pole of the first transistor T1 is connected to the node N, the second pole is connected to the initialization signal terminal Vinit, and the gate is connected to the reset signal terminal Re; the first pole of the second transistor T2 is connected to the first pole of the driving transistor T3, the second pole is connected to the node N; the gate is connected to the gate driving signal terminal Gate; the gate of the driving transistor T3 is connected to the node N; the first pole of the fourth transistor T4 is connected to the data signal terminal Da, the second pole is connected to the second pole of the driving transistor T3, and the gate is connected to the gate driving signal terminal Gate; the first pole of the fifth transistor T5 is connected to the first power supply signal terminal VDD, the second pole is connected to the second pole of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the first pole of the sixth transistor T6 is connected to the first pole of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the first pole of the seventh transistor T7 is connected to the initialization signal terminal Vinit, and the second pole is connected to the second pole of the sixth transistor T6. The pixel driving circuit may be connected to a light-emitting unit OLED for driving the light-emitting unit OLED to emit light, and the light-emitting unit OLED may be connected between the second pole of the sixth transistor T6 and the second power supply terminal VSS. Among them, the transistors T1-T7 may all be P-type transistors.

[0047] As Figure 2 shown, it is Figure 1Timing diagrams of each node in a driving method of a pixel driving circuit. Among them, Gate represents the timing of the gate driving signal terminal Gate, Re represents the timing of the reset signal terminal Re, EM represents the timing of the enable signal terminal EM, and Da represents the timing of the data signal terminal Da. The driving method of this pixel driving circuit may include a reset stage t1, a compensation stage t2, and a light-emitting stage t3. In the reset stage t1: the reset signal terminal Re outputs a low-level signal, the first transistor T1 and the seventh transistor T7 are turned on, and the initialization signal terminal Vinit inputs an initialization signal to the second pole of the node N and the sixth transistor T6. In the compensation stage t2: the gate driving signal terminal Gate outputs a low-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and at the same time the data signal terminal Da outputs a driving signal to write a voltage Vdata + Vth to the node N, where Vdata is the voltage of the driving signal and Vth is the threshold voltage of the driving transistor T3. In the light-emitting stage t3: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata + Vth stored in the capacitor C. According to the driving transistor output current formula I = (μWCox / 2L)(Vgs - Vth) 2 , where μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. In the pixel driving circuit of the present disclosure, the output current I of the driving transistor = (μWCox / 2L)(Vdata + Vth - Vdd - Vth) 2 . This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0048] As Figure 3 , 4 shown, Figure 3 is the structural layout of an array substrate in the related art, Figure 4 and Figure 3 is a partial cross-sectional view along the dotted line A in Figure 3 . The array substrate shown in Figure 1 can form Figure 3 , 4 shown, in the related art, the array substrate includes a substrate substrate 01, an active layer (including an active portion 02) on one side of the substrate substrate 01, a first gate insulating layer 03 on the side of the active layer facing away from the substrate substrate, a first gate layer (including a gate portion 04) on the side of the first gate insulating layer facing away from the substrate substrate, a second gate insulating layer 05 on the side of the first gate layer facing away from the substrate substrate, and a second gate layer (including a gate portion 06) on the side of the second gate insulating layer facing away from the substrate substrate. Among them, the active portion 02 can form Figure 1In the channel region of the driving transistor T3, the gate portion 04 can be formed Figure 1 In the gate of the driving transistor T3, the gate portion 06 and the gate portion 04 can be formed Figure 1 The capacitor C therein. However, due to the limited layout area of the gate portion 06 and the gate portion 04, the capacitance value of the capacitor C often cannot reach the preset capacitance parameter.

[0049] Based on this, the present exemplary embodiment provides an array substrate, as Figure 5 、 6 Shown in Figures 7, 8, and 9, Figure 5 Is a partial structure layout diagram of an exemplary embodiment of the array substrate of the present disclosure, Figure 6 Is Figure 5 A cross-sectional view along the dotted line A in Figure 7 Is Figure 6 The structure layout diagram of the first conductive layer in Figure 8 Is Figure 6 The structure layout diagram of the second conductive layer in Figure 9 Is Figure 6 The structure layout diagram of the third conductive layer in. Wherein, the array substrate may include a pixel driving circuit, and the pixel driving circuit may be as Figure 1 Shown. The array substrate may further include: a substrate substrate 0, a first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer may be located on one side of the substrate substrate 0, and the first conductive layer may include: a first conductive portion 11 and a second conductive portion 12. The first conductive portion 11 may be used to form the gate of the driving transistor T3; the orthographic projection of the second conductive portion 12 on the substrate substrate 0 may not intersect with the orthographic projection of the first conductive portion 11 on the substrate substrate 0, and the second conductive portion 12 may be used to form a part of the first electrode of the capacitor C; the second conductive layer may be disposed on the side of the first conductive layer away from the substrate substrate 0, and the second conductive layer may include a third conductive portion 23. The orthographic projection of the third conductive portion 23 on the substrate substrate 0 may at least partially coincide with the orthographic projection of the second conductive portion on the substrate substrate 0, and the third conductive portion 23 is electrically connected to the first conductive portion 11. The third conductive portion 23 may be used to form the second electrode of the capacitor C; the third conductive layer may be disposed on the side of the second conductive layer away from the substrate substrate 0, and the third conductive layer may include a fourth conductive portion 34. The orthographic projection of the fourth conductive portion 34 on the substrate substrate 0 may at least partially coincide with the orthographic projection of the third conductive portion 23 on the substrate substrate 0, and the fourth conductive portion 34 may be electrically connected to the second conductive portion 12. The fourth conductive portion 34 may be used to form a part of the first electrode of the capacitor C.

[0050] In this exemplary embodiment, the third conductive portion 23 can serve as the second electrode of the capacitor C, and the second conductive portion 12 and the fourth conductive portion 34 can jointly serve as the first electrode of the capacitor C. The third conductive portion 23 can form a parallel plate capacitor structure with the second conductive portion 12 and the fourth conductive portion 34, respectively. That is, the capacitor C can be composed of the two parallel plate capacitor structures described above in parallel, so that the capacitor C has a larger capacitance value.

[0051] It should be understood that in other exemplary embodiments, the pixel driving circuit in the array substrate of the present disclosure may also have other structures. As long as the pixel driving circuit includes a driving transistor and a capacitor connected to the gate of the driving transistor, the array substrate can achieve a capacitor with a larger capacitance value through the above structure.

[0052] In this exemplary embodiment, Figure 6 As shown, the array substrate may further include a first gate insulating layer 4 located between the first conductive layer and the second conductive layer, and a dielectric layer 5 located between the second conductive layer and the third conductive layer. The first gate insulating layer 4 may be a silicon oxide layer, and the dielectric layer 5 may be a silicon nitride layer. The first conductive layer, the second conductive layer, and the third conductive layer may all be formed by at least one metal layer. For example, the first conductive layer, the second conductive layer, and the third conductive layer may all be formed by stacking a first titanium layer, an aluminum layer, and a second titanium layer in sequence. The base substrate may be formed by an insulating material. For example, the base substrate may include a first polyimide (PI) layer, a first silicon oxide (SiO) layer, an amorphous silicon layer, a second polyimide (PI) layer, and a second silicon oxide layer in sequence.

[0053] In this exemplary embodiment, Figure 5 , 6 As shown, the orthographic projection of the first conductive part 11 on the substrate and the orthographic projection of the third conductive part 23 on the substrate can be spaced apart in the first direction X. The third conductive part 23 may include a second sub-conductive part 232, and the orthographic projection of the second sub-conductive part 232 on the substrate does not intersect with the orthographic projection of the fourth conductive part 34 on the substrate. The third conductive layer may further include a first connecting part 31. The orthographic projection of the first connecting part 31 on the substrate may extend along the first direction X, and the first connecting part 31 may be electrically connected to the first conductive part 11 through a via 92, and the first connecting part 31 may be electrically connected to the second sub-conductive part 232 through a via 91. Combined Figure 1 The first conductive portion 11 is actually used to connect the gate of the driving transistor T3 and the second electrode of the capacitor C.

[0054] In this exemplary embodiment, Figure 5 , 6As shown in Figures 8 and 9, the fourth conductive portion 34 may include a first sub-conductive portion 341; the orthographic projection of the first sub-conductive portion 341 on the base substrate may not intersect with the orthographic projection of the third conductive portion 23 on the base substrate, and the orthographic projection of the first sub-conductive portion 341 on the base substrate at least partially overlaps with the orthographic projection of the second conductive portion 12 on the base substrate. The first sub-conductive portion 341 may be electrically connected to the second conductive portion 12 through a via 93, thereby achieving electrical connection between the fourth conductive portion 34 and the second conductive portion 12. It should be understood that in other exemplary embodiments, the fourth conductive portion 34 and the second conductive portion 12 may also be connected through other structures. For example, the fourth conductive portion 34 may be electrically connected to the second conductive portion 12 through a via that passes through the third conductive portion 23 and is insulated from the third conductive portion 23.

[0055] In this exemplary embodiment, Figure 5 , 6 , as shown in 10, Figure 10 for Figure 5 In this exemplary embodiment, the array substrate may further include an active layer, and the active layer may be located between the base substrate and the first conductive layer. Figure 5 , 6 As shown in Figure 10, the active layer may include: a sixth active portion 66, the orthographic projection of the sixth active portion 66 on the base substrate may be a strip and extend along the second direction Y, and the sixth active portion 66 may be used to form the channel region of the driving transistor T3. The first conductive portion 11 may also be a strip-shaped structure extending along the second direction Y, and the orthographic projection of the first conductive portion 11 on the base substrate may cover the orthographic projection of the sixth active portion 66 on the base substrate. The second direction Y may intersect with the first direction X, for example, the second direction Y may be perpendicular to the first direction. In this exemplary embodiment, the channel region of the driving transistor T3 is set to a strip-shaped structure extending along the second direction, thereby reducing the size of the driving transistor T3 in the first direction, so as to reserve space for setting the capacitor C in the first direction X. Specifically, the sixth active portion 66 and the first conductive portion 11 may be rectangular, rounded rectangular, or other structures. The size of the orthographic projection of the first conductive portion 11 on the substrate in the second direction may be 2.5-5 times, for example, 2.2 times, 3.5 times, 4 times, or 5 times, of its size in the first direction. Figure 6 As shown, the array substrate may further include a second gate insulating layer 7 located between the active layer and the first conductive layer. The second gate insulating layer 7 may also be a silicon oxide layer.

[0056] In this exemplary embodiment, Figure 11 , 12 , 13, 14, 15, Figure 11This is a structural diagram of another exemplary embodiment of the array substrate disclosed herein. Figure 12 for Figure 11 The structural layout of the active layer, Figure 13 for Figure 11 The structural layout of the first conductive layer, Figure 14 for Figure 11 The structural layout of the second conductive layer, Figure 15 for Figure 11 The structural layout of the third conductive layer.

[0057] Figure 11 The array substrate shown may include Figure 5 - 10 The arbitrary structure of the array substrate shown. Figure 5 - 10 The array substrate shown in FIG. Figure 11 , 15 As shown, the third conductive layer may further include a power line 321, the power line 321 may extend along the first direction X, and the third conductive portion 23 may be located on the side of the power line 321 on the orthographic projection of the substrate in the second direction Y. The fourth conductive portion 34 may be electrically connected to the power line 321, and the orthographic projection of the fourth conductive portion 34 on the substrate may be located on the side of the power line 321 on the orthographic projection of the substrate in the second direction Y. The power line 321 may be used to provide Figure 1 The first power supply terminal signal VDD in the capacitor C is used to provide a power supply signal to the first electrode of the capacitor C.

[0058] In this exemplary embodiment, Figure 11 , 13 As shown, the array substrate may include a plurality of pixel driving circuits; the first conductive layer may include a plurality of second conductive portions 12, and the plurality of second conductive portions 12 are spaced apart along the second direction Y in the orthographic projection of the base substrate. In this exemplary embodiment, Figure 11 , 15 As shown, the third conductive layer may include multiple power lines, which may be spaced apart along the second direction Y. The multiple power lines may include adjacent power lines 321 and 322. The orthographic projection of the power line 322 on the substrate may be located on one side of the orthographic projection of the power line 321 on the substrate in the second direction Y. The second conductive portion 12 may be electrically connected to the power line 321 via the first sub-conductive portion 341 described above. Simultaneously, the second conductive portion 12 may be electrically connected to the power line 322 via the via 94. The second conductive portion 12 is simultaneously connected to two adjacent power lines, thereby improving the uniformity of the power supply voltage on the second conductive portion 12.

[0059] In this exemplary embodiment, the pixel driving circuit in the array substrate may further include a first transistor and a second transistor. The first pole of the second transistor is connected to the first pole of the driving crystal, and the second pole is connected to the gate of the driving transistor. The first pole of the first transistor is connected to the second pole of the second transistor. For example, the first transistor may be the first transistor T1 as shown in Figure 1 , and the second transistor may be the second transistor T2 as shown in Figure 1 . As shown in Figure 11 and 13 , the first conductive layer may further include a first gate line 13, and the first gate line 13 may be used to provide the gate driving signal terminal in Figure 1 . The orthographic projection of the first gate line 13 on the substrate may extend along the second direction Y, and the orthographic projection of the first gate line 13 on the substrate may be located between the orthographic projection of the first conductive portion 11 on the substrate and the orthographic projection of the second conductive portion 12 on the substrate. A partial conductive portion 131 of the first gate line 13 may be used to form the first gate of the second transistor T2. The first conductive layer may further include a second gate line 14, and the second gate line 14 may be used to provide the reset signal terminal in Figure 1 . The orthographic projection of the second gate line 14 on the substrate extends along the second direction Y, and the orthographic projection of the second gate line 14 on the substrate may be located on the side of the orthographic projection of the second conductive portion 12 on the substrate away from the orthographic projection of the first gate line 13 on the substrate. A partial conductive portion 141 of the second gate line 14 may be used to form the first gate of the first transistor T1, and a partial conductive portion 142 of the second gate line 14 may be used to form the second gate of the first transistor T1.

[0060] In this exemplary embodiment, as shown in Figure 11 and 12 , the active layer may further include a first active portion 61. The orthographic projection of the first active portion 61 on the substrate extends along the first direction X, and the first active portion 61 may be used to electrically connect the second pole of the second transistor T2 and the first pole of the first transistor T1; wherein, the orthographic projection of the first active portion 61 on the substrate may penetrate through the gap between adjacent orthographic projections of the second conductive portions 12 on the substrate. Among them, the original material for forming the active layer may be a semiconductor. During the manufacturing process of the array substrate, the active layer may be conductorized by using the first conductive layer as a mask, so as to convert the semiconductor structure outside the transistor channel region into a conductive structure. By arranging the second conductive portions 12 at intervals along the second direction Y, a gap for routing the first active portion 61 may be reserved between adjacent second conductive portions 12.

[0061] In this exemplary embodiment, as Figure 11 , 15 shown, the third conductive layer may further include a fifth conductive portion 35. The fifth conductive portion 35 may be connected between the fourth conductive portion 34 and the power supply line 321. The power supply line 321 may include a first edge 3211. The fifth conductive portion 35 may include a second edge 352 connected to the first edge 3211. The included angle formed by the orthographic projection of the first edge 3211 on the substrate and the orthographic projection of the second edge 352 on the substrate may be less than 180°. That is, the fifth conductive portion 35 may protrude from the power supply line 321 along the second direction Y. Wherein, the orthographic projection of the fifth conductive portion 35 on the substrate at least partially coincides with the orthographic projection of the first active portion 61 on the substrate. The fifth conductive portion 35 and the first active portion 61 may form a parallel plate capacitor structure, and this parallel plate capacitor structure may form a parallel structure with the parallel plate capacitor structure formed by the fourth conductive portion 34 and the third conductive portion 23. Thus, this setting may further increase the capacitance value of the capacitor C.

[0062] In this exemplary embodiment, as Figure 11 , 13 shown, the first conductive layer may further include: a sixth conductive portion 16. The orthographic projection of the sixth conductive portion 16 on the substrate may extend along the first direction X and be connected to the first gate line 13. Specifically, as Figure 13 shown, the sixth conductive portion 16 may extend from the first gate line 13 in the first direction X. As Figure 12 shown, the active layer may further include a second active portion 62, a third active portion 63, and a fourth active portion 64. The orthographic projection of the second active portion 62 on the substrate is located on the orthographic projection of the first gate line 13 on the substrate. The second active portion 62 may be used to form the first channel region of the second transistor T2. The orthographic projection of the third active portion 63 on the substrate may be located on the orthographic projection of the sixth conductive portion 16 on the substrate. The third active portion 63 may be used to form the second channel region of the second transistor T2. The fourth active portion 64 may be connected between the second active portion and the third active portion, and the orthographic projection of the fourth active portion 64 on the substrate does not intersect with the orthographic projection of the first conductive layer on the substrate. As Figure 11As shown, the second transistor T2 has a dual-gate structure. The dual-gate second transistor T2 has a small leakage current, thereby reducing the leakage current of the capacitor C through the second transistor during the light-emitting phase of the pixel driving circuit. However, because the fourth active portion 64 is a conductor, a parasitic capacitance is formed between the fourth active portion 64 and a portion of the first gate line 13 and the sixth conductive portion 16. When the voltage on the first gate line 13 changes, the voltage of the fourth active portion 64 will also change accordingly due to the bootstrap effect of the capacitor, thereby causing the fourth active portion 64 to leak to the source and drain of the second transistor T2, ultimately leading to abnormal driving of the pixel driving circuit.

[0063] In this exemplary embodiment, Figure 11 , 15 As shown, the third conductive layer may further include a seventh conductive portion 37. The seventh conductive portion 37 may be connected to the fourth conductive portion 34, and the orthographic projection of the seventh conductive portion 37 on the substrate at least partially overlaps with the orthographic projection of the fourth active portion 64 on the substrate. This arrangement allows the seventh conductive portion 37 and the fourth active portion 64 to form a parallel plate capacitor structure. Because the seventh conductive portion 37 is connected to the power line, the seventh conductive portion 37 has a stable voltage, thereby suppressing potential changes in the fourth active portion 64, thereby reducing leakage current from the fourth active portion 64 to the source and drain of the second transistor T2.

[0064] In this exemplary embodiment, Figure 11 , 12 As shown, the active layer may further include a fifth active portion 65, which may be connected between the third active portion 63 and the first active portion 61. The orthographic projection of the fifth active portion 65 on the substrate may extend along the second direction, and the orthographic projection of the fifth active portion 65 on the substrate does not intersect with the orthographic projection of the first conductive layer on the substrate. The orthographic projection of the fifth active portion 65 on the substrate at least partially overlaps with the orthographic projection of the first connecting portion 31 on the substrate, and the fifth active portion 65 may be electrically connected to the first connecting portion 31 through a via 95. This configuration allows the second electrode of the second transistor T2 to be electrically connected to the gate of the driving transistor.

[0065] In this exemplary embodiment, Figure 11 , 12, as shown in FIG. 15, the active layer may further include: a seventh active portion 67, an eighth active portion 68, and a ninth active portion 69. The orthographic projection of the seventh active portion 67 on the substrate may be located on the orthographic projection of the second gate line 14 on the substrate, and is used to form the first channel region of the first transistor T1; the orthographic projection of the eighth active portion 68 on the substrate may be located on the orthographic projection of the second gate line 14 on the substrate, and is used to form the second channel region of the first transistor T1; the ninth active portion 69 may be connected between the seventh active portion 67 and the eighth active portion 68. The orthographic projection of the ninth active portion 69 on the substrate does not intersect with the orthographic projection of the first conductive layer on the substrate, and the orthographic projection of the ninth active portion 69 on the substrate may be located on the side of the orthographic projection of the second gate line 14 on the substrate away from the orthographic projection of the first gate line 13 on the substrate. Similarly, the first transistor T1 has a double-gate structure, and the first transistor T1 with the double-gate structure has a smaller leakage current, so that the leakage current of the capacitor C through the first transistor during the light-emitting stage of the pixel driving circuit can be reduced. However, since the ninth active portion 69 is a conductor, there is a parasitic capacitance between the ninth active portion 69 and a part of the second gate line 14. When the voltage on the second gate line 14 changes, based on the bootstrap effect of the capacitor, the voltage of the ninth active portion 69 will also change accordingly, resulting in the leakage of the ninth active portion 69 to the source-drain of the first transistor T1, and ultimately causing abnormal driving of the pixel driving circuit.

[0066] In this exemplary embodiment, as Figure 15 shown, the third conductive layer may further include an eighth conductive portion 38. The eighth conductive portion 38 may be electrically connected to the power supply line 321. The power supply line 321 includes a third edge 3213. The eighth conductive portion 38 includes a fourth edge 384 connected to the third edge 3213. The included angle formed by the orthographic projection of the third edge 3213 on the substrate and the orthographic projection of the fourth edge 384 on the substrate is less than 180°. That is, the eighth conductive portion 38 protrudes from the power supply line 321 in the second direction. The orthographic projection of the eighth conductive portion 38 on the substrate may at least partially coincide with the orthographic projection of the ninth active portion 69 on the substrate. This setting can enable the eighth conductive portion 38 and the ninth active portion 69 to form a parallel-plate capacitor structure. Since the eighth conductive portion 38 is connected to the power supply line, the eighth conductive portion 38 has a stable voltage, so that the eighth conductive portion 38 can suppress the potential change of the ninth active portion 69, thereby reducing the leakage current of the ninth active portion 69 to the source-drain of the first transistor T1.

[0067] In this exemplary embodiment, as Figure 10 , 12As shown, the size of the sixth active portion 66 in the positive projection of the substrate on the first direction X may be 1.1-1.5 times the size of the first gate line 13 in the positive projection of the substrate on the first direction, for example, 1.1 times, 1.3 times, 1.5 times. The size of the first conductive portion 11 in the positive projection of the substrate on the first direction may be 1.5-2.5 times the size of the first gate line 13 in the positive projection of the substrate on the first direction, for example, 1.5 times, 2 times, 2.5 times.

[0068] As Figure 11 shown, the array substrate provided by this exemplary embodiment may form a pixel driving circuit as Figure 1 shown. The array substrate may further include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

[0069] As Figure 12 shown, the active layer may further include a tenth active portion 610, an eleventh active portion 611, a twelfth active portion 612, and a thirteenth active portion 613. Among them, the tenth active portion 610 may be used to form the channel region of the fourth transistor T4; the eleventh active portion 611 may be used to form the channel region of the fifth transistor T5; the twelfth active portion 612 may be used to form the channel region of the sixth transistor T6; the thirteenth active portion 613 may be used to form the channel region of the seventh transistor.

[0070] As Figure 13 shown, the first conductive layer may further include a third gate line 17, and the third gate line 17 may be used to provide Figure 1 the enable signal terminal in. The positive projection of the third gate line 17 on the substrate may be located on the side of the positive projection of the first conductive portion 11 on the substrate away from the positive projection of the first gate line 13 on the substrate. The first gate line 13 may further include a conductive portion 134, and the conductive portion 134 may be used to form the gate of the fourth transistor T4. The third gate line 17 may include a conductive portion 175 and a conductive portion 176. The conductive portion 175 may be used to form the gate of the fifth transistor, and the conductive portion 176 may be used to form the gate of the sixth transistor. Among them, the gate of the seventh transistor T7 may share the conductive portion 147 in the second gate line 14 corresponding to the next row of pixel units.

[0071] As Figure 15As shown, the third conductive layer may further include a second connecting portion 39, a third connecting portion 310, and a data line 311. The second connecting portion 39 may be connected to the active layer on one side of the eighth active portion 68 through a via 96 to connect the second electrode of the first transistor T1. The third connecting portion 310 may be connected to the active layer between the twelfth active portion 612 and the thirteenth active portion 613 through a via 97 to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The first electrode of the seventh transistor T7 may be connected to the second connecting portion 39 in the next row of pixel units. The data line 311 may be connected to the first electrode of the fourth transistor T4 through a via 98. As shown Figure 15 As shown, in this exemplary embodiment, the third conductive layer may include a plurality of data lines, for example, the third conductive layer may further include a data line 312, and the plurality of data lines are spaced apart along the second direction Y in the orthographic projection of the base substrate and extend along the first direction X. Figure 15 The orthographic projection of the data line 312 on the substrate can be located between the orthographic projection of the power line 322 on the substrate and the orthographic projection of the fourth conductive portion 34 on the substrate. Figure 11 As shown, the orthographic projection of the data line 312 on the base substrate at least partially overlaps with the orthographic projection of the second conductive portion 12 on the base substrate.

[0072] like Figure 16 FIG. 1 is a structural diagram of another exemplary embodiment of the array substrate disclosed herein. The array substrate may further include an anode layer, such as Figure 17 As shown, Figure 16 Structural layout of the anode layer. The array substrate can adopt a GGRB pixel arrangement, and the anode layer can include a first anode portion 81, a second anode portion 82, a third anode portion 83, a fourth anode portion 84, and an anode wiring 85. The first anode portion 81 can form the anode of the R sub-pixel, the second anode portion 82 and the third anode portion 83 can form the anode of the G sub-pixel, and the fourth anode portion 8 can form the anode of the B sub-pixel. The first anode portion 81, the third anode portion 83, and the fourth anode portion 84 can be connected to the third connection portion 310 in the same row of pixel units through a via hole to connect the second electrode of the seventh transistor T7 in the pixel driving circuit of the row. The second anode portion 82 can be connected to the third connection portion 310 in the adjacent upper row of pixel units to connect the second electrode of the seventh transistor T7 in the adjacent upper row of pixel driving circuit. The anode wiring 85 can be connected to the second connection portion 39 in the same row of pixel units to provide Figure 1 The initialization signal terminal Vinit shown in .

[0073] This exemplary embodiment further provides a display device, which includes the above-mentioned array substrate. The display device can be a mobile phone, a tablet computer, a television, or other display device.

[0074] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that fall within the generality of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0075] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. An array substrate, wherein, The array substrate includes a pixel driving circuit, the pixel driving circuit includes a driving transistor and a capacitor connected to the gate of the driving transistor, and the array substrate further includes: substrate; A first conductive layer is located on one side of the base substrate, and the first conductive layer includes: a first conductive portion, wherein the first conductive portion is used to form a gate of the driving transistor; a second conductive portion, wherein an orthographic projection of the second conductive portion on the base substrate does not intersect with an orthographic projection of the first conductive portion on the base substrate, and the second conductive portion is used to form a portion of the first electrode of the capacitor; The second conductive layer is provided on a side of the first conductive layer facing away from the base substrate, and includes: a third conductive portion, wherein an orthographic projection of the third conductive portion on the base substrate at least partially overlaps with an orthographic projection of the second conductive portion on the base substrate, the third conductive portion is electrically connected to the first conductive portion, and the third conductive portion is configured to form a second electrode of the capacitor; A third conductive layer is provided on a side of the second conductive layer facing away from the base substrate, and the third conductive layer includes: a fourth conductive portion, wherein an orthographic projection of the fourth conductive portion on the base substrate at least partially overlaps with an orthographic projection of the third conductive portion on the base substrate, the fourth conductive portion is electrically connected to the second conductive portion, and the fourth conductive portion is configured to form a portion of the first electrode of the capacitor; The third conductive layer further includes: A power line extends along a first direction, the third conductive portion is located on one side of the orthographic projection of the power line on the base substrate in a second direction, and the first direction intersects the second direction; The fourth conductive portion is electrically connected to the power line, and an orthographic projection of the fourth conductive portion on the base substrate is located on one side of the orthographic projection of the power line on the base substrate in the second direction.

2. The array substrate according to claim 1, wherein The orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the third conductive portion on the base substrate are spaced apart in a first direction, and the third conductive layer further comprises: The first connecting portion extends along the first direction when projected onto the base substrate. The first connecting portion is electrically connected to the first conductive portion through a via hole, and the first connecting portion is electrically connected to the third conductive portion through a via hole.

3. The array substrate according to claim 2, wherein, The fourth conductive portion includes a first sub-conductive portion; The orthographic projection of the first sub-conductive portion on the base substrate does not intersect with the orthographic projection of the third conductive portion on the base substrate, and the orthographic projection of the first sub-conductive portion on the base substrate at least partially overlaps with the orthographic projection of the second conductive portion on the base substrate; The first sub-conductive portion is electrically connected to the second conductive portion through a via.

4. The array substrate according to claim 1, wherein The array substrate includes a plurality of pixel driving circuits; The first conductive layer includes a plurality of second conductive portions, and the plurality of second conductive portions are spaced apart and distributed along the second direction on an orthographic projection of the base substrate.

5. The array substrate according to claim 3, wherein: The third conductive layer includes a plurality of the power supply lines, the plurality of the power supply lines are spaced apart along the second direction, the plurality of the power supply lines include adjacent first and second power supply lines, and a positive projection of the second power supply line on the substrate is located on one side of a positive projection of the first power supply line on the substrate in the second direction; The second conductive portion is electrically connected to the first power supply line through the first sub-conductive portion, and the second conductive portion is connected to the second power supply line through a via.

6. The array substrate according to claim 4, wherein, The pixel driving circuit further includes a second transistor, a first pole of the second transistor is connected to a first pole of the driving transistor, a second pole is connected to a gate of the driving transistor, and the first conductive layer further includes: A first gate line, which extends along the second direction in a positive projection on the substrate, and the positive projection of the first gate line on the substrate is located between a positive projection of the first conductive portion on the substrate and a positive projection of the second conductive portion on the substrate, and a part of the first gate line is used to form a gate of the second transistor.

7. The array substrate according to claim 6, wherein, The pixel driving circuit further includes a first transistor, a first pole of the first transistor is connected to a second pole of the second transistor, and the first conductive layer further includes: A second gate line, which extends along the second direction in a positive projection on the substrate, and the positive projection of the second gate line on the substrate is located on a side of the positive projection of the second conductive portion on the substrate away from the positive projection of the first gate line on the substrate, and a part of the second gate line is used to form a gate of the first transistor.

8. The array substrate according to claim 7, wherein, The array substrate further includes an active layer, the active layer is disposed between the substrate and the first conductive layer, and the active layer includes: A first active portion, which extends along the first direction in a positive projection on the substrate, and the first active portion is used to electrically connect a second pole of the second transistor and a first pole of the first transistor; Wherein, the positive projection of the first active portion on the substrate penetrates through a gap between positive projections of adjacent second conductive portions on the substrate.

9. The array substrate according to claim 8, wherein The third conductive layer further includes: A fifth conductive portion, which is connected between the fourth conductive portion and the power supply line, the power supply line includes a first edge, the fifth conductive portion includes a second edge connected to the first edge, and an included angle formed by the positive projection of the first edge on the substrate and the positive projection of the second edge on the substrate is less than 180°; The positive projection of the fifth conductive portion on the substrate at least partially coincides with the positive projection of the first active portion on the substrate.

10. The array substrate according to claim 8, wherein, The first conductive layer further includes: A sixth conductive portion, which extends along the first direction in a positive projection on the substrate and is connected to the first gate line; The active layer further includes: A second active portion, which is located on the positive projection of the first gate line on the substrate in the positive projection on the substrate, and the second active portion is used to form a first channel region of the second transistor. The third active part is located in the orthographic projection of the substrate on the orthographic projection of the sixth conductive part on the substrate. The third active part is used to form the second channel region of the second transistor; The fourth active part is connected between the second active part and the third active part, and the orthographic projection of the fourth active part on the substrate does not intersect with the orthographic projection of the first conductive layer on the substrate; The third conductive layer further includes: The seventh conductive part is connected to the fourth conductive part, and the orthographic projection of the seventh conductive part on the substrate at least partially coincides with the orthographic projection of the fourth active part on the substrate.

11. The array substrate according to claim 10, wherein, The orthographic projection of the first conductive part on the substrate and the orthographic projection of the third conductive part on the substrate are spaced apart in a first direction. The third conductive layer further includes: The first connecting part extends in the first direction in the orthographic projection on the substrate. The first connecting part is electrically connected to the first conductive part through a via, and the first connecting part is electrically connected to the third conductive part through a via; The active layer further includes: The fifth active part is connected between the third active part and the first active part. The orthographic projection of the fifth active part on the substrate does not intersect with the orthographic projection of the first conductive layer on the substrate; And the orthographic projection of the fifth active part on the substrate at least partially coincides with the orthographic projection of the first connecting part on the substrate, and the fifth active part is electrically connected to the first connecting part through a via.

12. The array substrate according to claim 8, wherein, The active layer further includes: The sixth active part is used to form the channel region of the driving transistor. The orthographic projection of the sixth active part on the substrate is strip-shaped and extends along the second direction.

13. The array substrate according to claim 12, wherein, The size of the orthographic projection of the sixth active part on the substrate in the first direction is 1.1 - 1.5 times the size of the orthographic projection of the first gate line on the substrate in the first direction.

14. The array substrate according to claim 12, wherein, The orthographic projection of the first conductive part on the substrate is strip-shaped and extends along the second direction. The size of the orthographic projection of the first conductive part on the substrate in the second direction is 2.5 - 5 times its size in the first direction.

15. The array substrate according to claim 8, wherein, The active layer further includes: The seventh active part is located in the orthographic projection of the substrate on the orthographic projection of the second gate line on the substrate, and is used to form the first channel region of the first transistor; The eighth active part is located in the orthographic projection of the substrate on the orthographic projection of the second gate line on the substrate, and is used to form the second channel region of the first transistor; The ninth active part is connected between the seventh active part and the eighth active part, and the orthographic projection of the ninth active part on the substrate does not intersect with the orthographic projection of the first conductive layer on the substrate; The third conductive layer further includes: The eighth conductive part is electrically connected to the power supply line; The power supply line includes a third edge, and the eighth conductive part includes a fourth edge connected to the third edge. The included angle between the orthographic projection of the third edge on the substrate and the orthographic projection of the fourth edge on the substrate is less than 180°; The positive projection of the eighth conductive portion on the substrate substrate coincides at least partially with the positive projection of the ninth active portion on the substrate substrate.

16. The array substrate according to claim 5, wherein The third conductive layer further includes a plurality of data lines, and the positive projections of the plurality of data lines on the substrate substrate are spaced apart along the second direction and extend along the first direction; The plurality of data lines include a first data line, and the positive projection of the first data line on the substrate substrate is located between the positive projection of the second power supply line on the substrate substrate and the positive projection of the fourth conductive portion on the substrate substrate; And the positive projection of the first data line on the substrate substrate coincides at least partially with the positive projection of the second conductive portion on the substrate substrate.

17. A display device, wherein, An array substrate according to any one of claims 1-16 is included.

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