Circuit and method for transferring two differential encoded client clock domains between integrated circuits over a third carrier clock domain

Abstract

A method for transmitting encoded first client clock signals and second client clock signals between integrated circuits via a carrier clock domain, the method comprising: in a first integrated circuit, encoding a phase change of the first client clock signal from a last recorded phase onto a carrier clock signal at a first position; encoding a phase change of the second client clock signal from a last recorded phase onto a carrier clock signal at a second position different from the first position; and transmitting the carrier clock signal, carrying the encoded phases of the first client clock signal and the second client clock signal, from the first integrated circuit to the second integrated circuit via a single wire.

Description

Technical Field

[0001] This invention relates to integrated circuit systems operating in multiple clock domains. More specifically, this invention relates to circuits and methods for transmitting two differentially coded client clock domains between integrated circuits via a third carrier clock domain. Background Technology

[0002] In existing device implementations, the backplane or middleware board uses a single physical pin to carry timing information between two separate boards. For existing PLL implementations, a single physical line can only carry frequency / phase / time information for one clock domain. Sometimes it's necessary to carry frequency / phase / time information for two independent clock domains on a single physical line; for example, the frequency / phase / time information for the SyncE clock domain and the PTP clock domain. A simple solution is to increase the number of wires from one to two, but this is not always feasible due to existing deployments and backward compatibility in device designs.

[0003] Existing solutions include the 8A34003 system synchronizer IC, available from Integrated Device Technology, Inc., San Jose, California. This implementation uses an input-output signal format that combines frequency / phase / time information from two clock domains, using a clock signal from one domain as the carrier and a clock signal from the other as the client. The 8A34003 signal format does not support a third clock domain. A drawback of this existing solution is that by requiring one of the two clock signals to be the carrier and the other as the client, it introduces adverse effects, including: the carrier may disappear (if the input to the device is disconnected); the carrier may dynamically change its source; the carrier may be transient or unstable; and the carrier may have a large frequency offset from the client. All of these adverse effects can lead to degraded client performance and may result in system noise and noise transmission performance that does not meet system requirements. Summary of the Invention

[0004] According to one aspect of the present invention, a method for transmitting a first client clock signal in a first client clock domain and a second client clock signal in a second client clock domain between a first integrated circuit and a second integrated circuit via a carrier clock signal in a carrier clock domain includes: providing a stable reference clock source to the first integrated circuit; generating a carrier clock signal from the stable reference clock source in the first integrated circuit and phase-locking the generated carrier clock signal to the stable reference clock source; providing the first client clock signal in the first client clock domain to the first integrated circuit; phase-locking the first client clock signal to the first client clock signal using a DPLL converter; providing the second client clock signal in the second client clock domain to the first integrated circuit; and phase-locking the second client clock signal to the first client clock signal using a DPLL converter. Phase-locked to a second client clock signal; latching the current phase of a first client clock signal and encoding the phase change of the first client clock signal since the last latched phase as a first phase word information in a first position; latching the current phase of a second client clock signal and encoding the phase change of the second client clock signal since the last latched phase as a second phase word information in a second position different from the first position; and modulating a carrier signal to generate the first phase word information, the second phase word information, and non-phase word information, and transmitting the first phase word information, the second phase word information, and the non-phase word information from a first integrated circuit to a second integrated circuit via a single line in a specified subframe time slot.

[0005] According to one aspect of the present invention, generating a carrier clock signal in a first integrated circuit and performing phase-locked loop (PLL) on the carrier clock signal includes generating the carrier clock signal in a carrier clock signal PLL in the first integrated circuit; providing a first client clock signal to the first integrated circuit includes providing the first client clock signal to the first client clock signal PLL in the first integrated circuit; and providing a second client clock signal to the first integrated circuit includes providing the second client clock signal to the second client clock signal PLL in the first integrated circuit.

[0006] According to one aspect of the invention, encoding the phase change of the first client clock signal and the second client clock signal onto the carrier clock signal includes encoding a plurality of bits representing the phase change of the first client clock signal and the second client clock signal by modulating the timing of the edges of the carrier clock signal, thereby changing the duty cycle of the carrier clock signal to represent the value of each bit.

[0007] According to one aspect of the invention, modulating the timing of the edges of the carrier clock signal to change the duty cycle of the carrier clock signal includes modulating the timing of the falling edge of the carrier clock signal.

[0008] According to one aspect of the invention, the timing of the falling edge of the modulated carrier clock signal includes setting the timing of the falling edge of the carrier clock signal to create a duty cycle of less than 50% to represent a first digital bit value, and setting the timing of the falling edge of the carrier clock signal to create a duty cycle of 50% to represent a second digital bit value.

[0009] According to one aspect of the invention, the method further includes setting the timing of the falling edge of the carrier clock signal to create a duty cycle greater than 50% to represent the marker bit.

[0010] According to one aspect of the invention, encoding the phase change of the first client clock signal in the first bit position includes encoding the phase change of the first client clock signal in the first phase word; and encoding the phase change of the second client clock signal in the second bit position, which is different from the first bit position, includes encoding the phase change of the second client clock signal in the second phase word.

[0011] According to one aspect of the invention, the method further includes encoding the Time of Day (ToD) information from the ToD counter onto a carrier clock signal in a third position, which is different from the first and second positions.

[0012] According to one aspect of the invention, encoding the time of day (ToD) information onto a carrier clock signal in a third position includes encoding the time of day (ToD) information as a first non-phase word information.

[0013] According to one aspect of the invention, the method further includes encoding data from the message passing channel onto a carrier clock signal in a fourth position, which is different from the first and second positions, and onto first non-phase word information in a third position.

[0014] According to one aspect of the invention, encoding data from the messaging channel onto a carrier clock signal in a fourth bit position includes encoding the data from the messaging channel as a second non-phase word information.

[0015] According to one aspect of the invention, the method further includes: receiving a modulated carrier clock signal from a first integrated circuit via a single line in a second integrated circuit; decoding a phase change of a first client clock signal relative to the carrier clock signal from the modulated carrier clock signal; providing the decoded phase change of the first client clock signal to a first client clock signal phase-locked loop; decoding a phase change of a second client clock signal relative to the carrier clock signal from the modulated carrier clock signal; providing the decoded phase change of the second client clock signal to a second client clock signal phase-locked loop; and providing the carrier clock signal received in the second integrated circuit to a carrier clock signal phase-locked loop.

[0016] According to one aspect of the present invention, a system for transmitting a first client clock signal and a second client clock signal between a first integrated circuit and a second integrated circuit via a carrier clock signal comprises: a first integrated circuit coupled to a second integrated circuit; a carrier clock signal phase-locked loop (PLL) located in the first integrated circuit, the PLL having an input terminal coupled to a reference frequency source in the carrier clock domain; a first client clock signal PLL located in the first integrated circuit, the first client clock signal PLL having an input terminal coupled to a first client clock signal; and a second client clock signal PLL. The second client clock signal phase-locked loop is located in the first integrated circuit and has an input terminal coupled to the second client clock signal. An encoder circuit, also located in the first integrated circuit, is configured to: encode information about the phase change of the first client clock signal relative to a carrier clock signal into a carrier clock signal at a first position; encode information about the phase change of the second client clock signal relative to the carrier clock signal into a carrier clock signal at a second position different from the first position; and transmit the carrier clock signal carrying the encoded information about the phase change of the first and second client clock signals from the first integrated circuit to the second integrated circuit via a single communication line.

[0017] According to one aspect of the invention, the encoder circuit is further configured to: encode ToD information onto a carrier clock signal; and encode data from the message passing channel onto the carrier clock signal.

[0018] According to one aspect of the invention, the system further includes: a decoder circuit located in a second integrated circuit, the decoder circuit being configured to: receive, in the second integrated circuit via a single communication line, a carrier clock signal carrying encoded information about phase changes of a first client clock signal and a second client clock signal from a first integrated circuit; decode the phase change information of the first client clock signal from the carrier clock signal; and decode the phase change information of the second client clock signal from the carrier clock signal; and the system further includes a carrier clock signal phase-locked loop located in the second integrated circuit, the carrier clock signal phase-locked loop having an input terminal coupled to the decoder circuit to receive the carrier clock signal; a first client clock signal phase-locked loop having an input terminal coupled to the decoder to receive the decoded phase change information of the first client clock signal; and a second client clock signal phase-locked loop having an input terminal coupled to the decoder to receive the decoded phase change information of the second client clock signal.

[0019] According to one aspect of the invention, the decoder is further configured to: decode the ToD information from the carrier clock signal; and decode data from the message passing channel from the carrier clock signal. Attached Figure Description

[0020] The invention will now be explained in more detail with reference to the embodiments and accompanying drawings, in which:

[0021] Figure 1 This is a simplified block diagram of an integrated circuit system comprising two integrated circuits according to one aspect of the present invention, illustrating an exemplary method for transmitting clock signals between two differentially coded client clock domains via a carrier clock domain between the integrated circuits;

[0022] Figure 2 This is a waveform diagram illustrating an exemplary coding method for transmitting data in the carrier clock domain;

[0023] Figure 3 It is a diagram illustrating a possible arrangement of an exemplary information frame order for transmitting the phase of a first clock domain, the phase of a second clock domain, and non-phase information including ToD and message passing channels between integrated circuits, according to one aspect of the present invention.

[0024] Figure 4 It shows Figure 3 A diagram illustrating an exemplary arrangement of 200-bit non-phase word data in a subframe;

[0025] Figure 5 It shows Figure 4A diagram showing possible arrangements of 200 bits of non-phase word data in a messaging channel illustrates a non-limiting example of how 30 bits of user data can be arranged in a messaging channel according to one aspect of the invention.

[0026] Figure 6 This is a flowchart illustrating an exemplary method according to an aspect of the present invention for encoding and transmitting data from a first encoded client clock domain and a second encoded client clock domain between a first integrated circuit and a second integrated circuit via a carrier clock domain; and

[0027] Figure 7 This is a flowchart illustrating an exemplary method for decoding data in a second integrated circuit according to one aspect of the present invention. Detailed Implementation

[0028] Those skilled in the art will recognize that the following description is merely illustrative and not intended to be limiting in any way. Other embodiments will readily occur to those skilled in the art.

[0029] According to an exemplary embodiment of the invention, an interface is provided that can transmit information over a single wire, such as, but not limited to, OCXO frequency, Synchronous Ethernet (SyncE) frequency and PTP frequency, phase, and Time of Day (ToD). The invention can also be used to transmit other information. This interface is designed to minimize PCB traces while meeting all the requirements of chip-to-chip and board-to-board timing connections in next-generation WAN networking devices.

[0030] This invention applies to systems employing three clock domains. The carrier clock signal originates from a stable source (e.g., a local temperature-controlled crystal oscillator). The carrier clock signal serves as a baseline reference for the first and second client clock signals corresponding to the first and second client clock domains. The carrier clock signal also serves as the master clock for both the encoder and decoder. By modulating the properties of the carrier clock signal (such as amplitude) or the timing (position) of its falling or rising edges, relevant information about the first and second client clock signals is encoded via the carrier clock signal to transmit the encoded information about the first and second client clock signals.

[0031] In one exemplary embodiment of the invention, the modulation allows each carrier clock signal cycle to encode logic 0 (e.g., creating a 25 / 75 duty cycle if the falling or rising edge is earlier than expected), logic 1 (e.g., creating a 50 / 50 duty cycle if the falling or rising edge is in the normal position), or a tag (e.g., creating a 75 / 25 duty cycle if the falling or rising edge is later than expected). Those skilled in the art will readily observe that the relative timing or other attributes assigned to encode logic 0, logic 1, and tag names according to the invention are arbitrary, and the choice of which to assign is primarily a design choice.

[0032] The encoded information consists of multiple bits representing the phase change of the first client clock signal since it was last recorded. The phase change information for the second client clock signal is encoded in the same manner as that for the first client clock signal.

[0033] This invention provides the ability to transmit information such as frequency / phase / time information from multiple client clock domains via a single physical line. This reduces the number of wires / traces required in applications such as between integrated circuits on the backplane of a modular chassis system or between integrated circuits on a circuit board. The term clock domain refers to a set of clock signals that are frequency-locked and optionally phase-locked together by a PLL. Therefore, clock signals in a clock domain do not necessarily have the same nominal frequency; however, because the clock signals are frequency-locked and optionally phase-locked together by a PLL, all signals have the same frequency offset, as defined below.

[0034] First refer to Figure 1 The simplified block diagram illustrates a system 10 comprising two integrated circuits according to one aspect of the invention, to illustrate an exemplary method for transmitting frequency / phase / time information about clock signals from two client clock domains between respective integrated circuits via a carrier clock domain.

[0035] The system 10 of the present invention comprises two parts: an encoder part indicated in bracket 12 and a decoder part indicated in bracket 14.

[0036] The first integrated circuit 16 located in the encoder section 12 includes a carrier digital phase-locked loop (DPLL) 18, which is locked to a stable reference clock source such as the output clock signal of a temperature-controlled crystal oscillator (OCXO) 20 to generate a carrier clock signal 22 at its output.

[0037] SyncE DPLL 24 is locked to a first client clock signal, such as SyncE clock signal 26, and PTPDPLL 28 is locked to a second client clock signal, such as that from a PTP slave, represented by PTP clock signal 30. In the exemplary embodiment, a 1-pulse-per-second (PPS) signal received from the GPS receiver is input via line 32. GPS is illustrated as a non-limiting embodiment of a Global Navigation Satellite System (GNSS), and timing inputs from any GNSS are particularly considered, although other sources are possible. Host software 34 transmits the Time of Day (ToD) setting signal and user messages via a bus such as SPI / I2C 36. The ToD setting signal is sent to ToD counter 38.

[0038] The phase word and non-phase word encoder 40 periodically latches or records non-phase word information, including information such as ToD information obtained from ToD counter 38, frequency offset between carrier clock signal 22 and SyncE signal from DPLL 24, frequency offset between carrier clock signal 22 and PTP signal from PTP DPLL 28, and user message content sent from host software 34. The frequency offset information is expressed in parts per trillion and can be obtained, for example, by counting the actual number of cycles of SyncE clock signal 26 (or actual number of cycles of PTP clock signal 30) for every certain number of cycles of carrier clock signal 22, and comparing this actual number of cycles with the nominal number of SyncE clock cycles (or nominal number of PTP clock cycles) for each of those carrier clock cycles. If there is no variance, the offset is zero; if there is variance, the offset can be expressed in parts per trillion. As an example, the number of 25MHz SyncE clock cycles occurring during 2,000 2kHz carrier clock cycles should be 25 million. If the actual quantity is 25,000,006, the difference is +6 / 25,000,000. If the actual quantity is 24,999,994, the difference is -6 / 25,000,000. Both can be expressed in parts per trillion (ppt) or parts per million (ppm). According to an exemplary embodiment of the invention, such as... Figure 4 and Figure 5 As shown, the maximum value this field can hold is 1953ppm, or 1,953,000,000ppt.

[0039] The phase word and non-phase word encoder 40 also latches or records and determines phase word information at periodic intervals. This phase word information includes the difference between the current phase (ω) of the SyncE clock signal output from DPLL 24 and the phase of the SyncE clock signal last latched by the phase word and non-phase word encoder 40 from DPLL 24, and the difference between the current phase (ω) of the output clock signal from PTP DPLL 28 and the phase of the output PTP clock signal last latched by the phase word and non-phase word encoder 40 from PTP DPLL 28. The phase word and non-phase word encoder 40 then encodes all this information into multiple individual bits in a format created by modulating the carrier clock signal (in one embodiment, by modulating the pulse width of the falling (or rising) edge of the carrier clock), as will be seen herein. According to one aspect of the invention, the encoded information is transmitted via a single line 42.

[0040] The second integrated circuit 44 in the decoder section 14 includes a phase word and a phase word decoder 46, which decodes the a phase word and phase word information encoded in the phase word and a phase word encoder 40 in the integrated circuit 16.

[0041] The carrier DPLL 48 generates a reference clock signal on line 50, which, due to being phase-locked to the carrier clock signal 22, is frequency-locked to the output clock signal of the oven-controlled crystal oscillator (OCXO) 20 in the encoder section. Figure 1 In the exemplary embodiment, the output frequency of DPLL 48 is shown to be the same as the output frequency of OCXO 20; however, those skilled in the art will understand that the output frequency of DPLL 48 need not be the same as the nominal frequency of the output of OCXO 20 and can be any nominal frequency that is most useful at the decoder end. The carrier DPLL 48 in decoder section 14 is synchronized / locked to the carrier clock signal 22 received from encoder section 12, thereby ensuring that decoder section 14 shares the same phase / time reference with encoder section 12. This is valuable because the information carried about the client clock signal on the carrier is relative to carrier clock signal 22.

[0042] SyncE DPLL 52 drives SyncE clock signal 54, and PTP DPLL 56 drives PTP clock signal 58. PTP1 PPS signals are driven out via line 60. Host software 62 running in decoder section 14 can read received ToD information from ToD counter 64, which receives the ToD information from phase word and non-phase word decoder 46. ToD counter 64 communicates with host software 62 via a bus such as SPI / I2C 66. User messages are also provided to host software 62 from phase word and non-phase word decoder 46 via bus 66.

[0043] As can be seen from the above description, Figure 1 The integrated circuit system 10 utilizes three clock signals, each associated with a corresponding clock domain. A carrier clock signal 22, derived from a stable source (oven-controlled local oscillator (OCXO) 20), is used in the first integrated circuit 16 as a baseline reference for the phase word and non-phase word encoders 40 to encode the two client clock signals.

[0044] The carrier clock signal 22 also serves as the master clock stabilization source for the SyncE DPLL 52, which generates the SyncE clock output signal on line 54. The SyncE DPLL 52 synchronizes / locks to the SyncE clock signal 26 encoded by the carrier clock signal 22 using a combination of phase word information encoded in the channel (i.e., by the aforementioned modulation scheme) and the phase of the carrier DPLL 48. The PTP DPLL 56 synchronizes / locks to the PTP clock signal 30 using a combination of phase word information encoded by the aforementioned modulation scheme and the phase of the carrier DPLL 48. The PTP DPLL 56 outputs the PTP clock signal on line 58 and the PTP 1 PPS signal on line 60. The host software 62 running in the decoder section 14 receives ToD information and user messages via bus 66.

[0045] Now for reference Figure 2The waveform diagram indicated at reference numeral 70 illustrates a method of encoding information via the carrier clock signal 22 by modulating the falling edge position of the carrier clock signal 22. According to an exemplary embodiment of the invention, if the falling edge is earlier than expected, the modulation allows each carrier clock signal cycle (falling edge) to encode logic 0, thereby creating a 25 / 75 duty cycle, as shown in reference numeral 72; if the falling edge is in the normal position, logic 1 is encoded, thereby creating a 50 / 50 duty cycle, as shown in reference numeral 74; or if the falling edge is later than expected, a flag is encoded, thereby creating a 75 / 25 duty cycle, as shown in reference numeral 76. Those skilled in the art will understand that the duty cycles defining the characteristics of logic 0, logic 1, and the flag are arbitrary, and 25 / 75, 50 / 50, and 75 / 25 duty cycles can be used to represent other combinations of logic 0, logic 1, and the flag.

[0046] The encoded information represents both phase word information and non-phase word information as described above, and is therefore transmitted between the first integrated circuit 16 and the second integrated circuit 44 in the form of duty cycle modulation of the carrier clock signal 22.

[0047] In one exemplary embodiment of the invention, the carrier clock signal 22 is a 2kHz clock signal locked to the OCXO 20. The frequency of the OCXO 20 is typically thousands of times higher than the frequency of the carrier clock signal 22.

[0048] The carrier DPLL 18 in encoder section 12 can be locked to OCXO 20, thus having the same long-term frequency accuracy as OCXO 20. A 2kHz carrier clock signal 22 is generated by the carrier DPLL 18 locked to its local OCXO 20. In one exemplary embodiment of the invention, the phase word and non-phase word encoder 40 generates a superframe every 2,000 carrier cycles, the superframe beginning with two 75% duty cycle pulses indicating the start of the superframe. It should be understood that using a 2kHz carrier clock signal and using a superframe every 2,000 carrier cycles is not intended to limit in any way; other values ​​for both the carrier clock signal frequency 22 and the median of the superframe can be utilized without exceeding the limits.

[0049] The phase word and non-phase word encoder 40 stores the accurate PTP field ToD of the rising edge of the first marker pulse of each superframe. Then, the phase word and non-phase word encoder inserts this ToD into the non-phase word bit in the superframe, such as... Figure 4 and Figure 5 The ones listed in the text.

[0050] Periodically, in one exemplary embodiment 75 times per second, the phase word and non-phase word encoder 40 latches the current phase information of PTPDPLL 28 and SyncE DPLL 24, respectively, and determines the phase changes since the last phase information was latched. The phase word and non-phase word encoder inserts these phase changes into predefined time slots in the superframe data, specifically into the time slots of the PTP phase word and SyncE phase word fields for each subframe.

[0051] In an exemplary embodiment, the rising edges of the carrier clock signal 22 are spaced at equal intervals and have low jitter, while the falling edges of the carrier clock signal 22 are modulated to convey data as described herein. In one embodiment of the invention, the data is a continuous stream of 2,000-bit superframes with a superframe rate of 1 Hz. In one exemplary embodiment, each superframe contains 200 bits of non-phase word data, 900 bits of PTP phase word data, and 900 bits of SyncE phase word data.

[0052] In one embodiment of the invention, a 2,000-bit superframe consists of 25 frames (80 bits per frame). Figure 3 As depicted in this embodiment, each frame can consist of three subframes of 26, 27, and 27 bits respectively, with a total of 75 subframes per superframe. The beginning of the first subframe in a superframe is identified using two flag bits.

[0053] Those skilled in the art will note that for every 75 subframes per superframe (i.e., 75 subframes per second), decoder section 14 receives both SyncE phase updates and PTP phase updates at a rate of 75 Hz. SyncEDPLL 52 and PTP DPLL 56 in decoder section 14 can be locked to these phase update streams in substantially the same manner as they are locked to the 75 Hz clock signal.

[0054] In one exemplary embodiment of the present invention, the 200-bit non-phase word data can be as follows: Figure 4 The arrangement is as depicted in the text. Figure 3 The bit field shown is repeated 25 times in a superframe. Additionally, Figure 5 It shows Figure 4 A diagram showing possible arrangements of 200 bits of non-phase word data illustrates a non-limiting example of how 30 bits of user data can be arranged in a messaging channel according to one aspect of the invention.

[0055] The phase word and non-phase word decoder 46 receives a 2kHz carrier clock signal and achieves superframe alignment by observing two consecutive marker pulses.

[0056] Phase word and non-phase word decoder 46 uses Figure 4The ToD time bit introduced in the non-phase word information shown in the table adjusts the current day time in the ToD counter 64 once per second. The decoder section 14 also phase-locks its output PTP clock signal 58 and output PTP 1PPS signal 60 in response to the introduced PTP phase word stream, and phase-locks its output SyncE clock signal 54 in response to the introduced SyncE phase word stream.

[0057] If the carrier clock signal 22 being tracked by decoder section 14 is not subject to activity monitoring or frequency monitoring, decoder section 14 may switch to a secondary signal (e.g., another instance of wire 42, not shown), or switch to holdover if no secondary signal is available.

[0058] Now for reference Figure 6 The flowchart illustrates an exemplary method 80 for encoding data in encoder section 12 according to one aspect of the invention. The method begins at reference numeral 82 in the appendix.

[0059] At reference numeral 84, a stable reference clock source, such as an OCXO, is provided to the first integrated circuit. At reference numeral 86, a carrier clock signal is generated from this stable reference clock source in the first integrated circuit and phase-locked to the stable reference clock source. At reference numeral 88, a first client clock signal, such as the SyncE client clock signal, in the first client clock domain is provided to the first integrated circuit. At reference numeral 90, the first client clock signal DPLL is phase-locked to the first client clock signal, for example, the SyncE DPLL 24 in encoder section 12 is phase-locked to the SyncE signal 26. At reference numeral 92, a second client clock signal, such as the PTP client clock signal, in the second client clock domain is provided to the first integrated circuit. At reference numeral 94, the second client clock signal DPLL is phase-locked, for example, the PTPDPLL 28 is phase-locked to the PTP clock 30 and PTP 1PPS 32.

[0060] At reference numeral 96, the first client clock phase is latched, and the phase change (e.g., SyncE clock signal phase) since the first client clock phase was last latched / recorded is determined, and this phase change is encoded as phase word information in the first position in the phase word and non-phase word encoder 40. At reference numeral 98, the second client clock signal phase is latched, and the phase change (e.g., PTP clock signal phase) since the second client clock signal phase was last latched / recorded is determined, and this phase change is encoded as phase word information in the second position in the phase word and non-phase word encoder 40. At reference numeral 100, ToD information received from ToD counter 38 is latched and encoded as non-phase word information. At reference numeral 102, any received user message data is latched and encoded as non-phase word information in the phase word and non-phase word encoder 40.

[0061] At reference numeral 104, the carrier clock signal is preferably modulated to transmit a marker pulse. At reference numeral 106, the carrier clock signal is modulated to transmit the encoded first client clock signal frequency and phase difference, the second client clock signal frequency and phase difference, ToD, and user message data in a specified subframe time slot. The method then returns to reference numeral 96, where the sequence of actions performed via reference numerals 96 to 106 is repeated.

[0062] Now for reference Figure 7 The flowchart illustrates an exemplary method 110 for decoding data in a decoder section 14 of a second integrated circuit according to one aspect of the invention. The method begins at reference numeral 112.

[0063] At reference numeral 114, in the decoder section 14, a modulated carrier clock signal 22 is received from the encoder section 12 via a single line (such as wire 42), the modulated carrier clock signal 22 having encoded phase changes of a first client clock signal (e.g., SyncE clock signal 26) and a second client clock signal (e.g., PTP clock signal 30).

[0064] At reference numeral 116, the phase change of the first client clock signal (e.g., SyncE clock signal 26) is decoded from the carrier clock signal 22. At reference numeral 118, the decoded phase change of the first client clock signal is provided to the first client (e.g., SyncE) DPLL 52 in the second integrated circuit 44 of the decoder section 14.

[0065] At reference numeral 120, the phase change of the second client clock signal (e.g., PTP clock signal 30) is decoded from the carrier clock signal 22. At reference numeral 122, the decoded phase change of the second client clock signal is provided to the second client (e.g., PTP) DPLL 56 in the second integrated circuit 44 of the decoder section 14. At reference numeral 124, the carrier clock signal 22 received in the decoder section 14 is provided to the carrier DPLL 48 in the second integrated circuit 44 of the decoder section 14. The method then returns to reference numeral 114, where the sequence of actions performed via reference numerals 114 to 124 is repeated.

[0066] This invention offers several advantages. First, it supports carrying multiple clock signal information through a single physical pin / wire / trace.

[0067] Second, preferably, the clock signal is encoded relative to a known, stable local reference (e.g., a temperature-controlled crystal oscillator (OCXO 20)). This avoids attenuation of the first and second clock signals due to instability of the carrier clock signal. In prior art solutions, the carrier clock signal comes from external (unknown) sources that are affected by frequency offsets, phase transients, and may switch between different sources.

[0068] Third, the OCXO signal is a stable local reference, which serves as the master oscillator for both encoder section 12 and decoder section 14. This avoids the need to instantiate the master oscillator in either encoder 12 or decoder 14.

[0069] Fourth, regarding the carrier clock signal, differential encoding is performed on the client clock signal in order to compress information and keep the interface speed at an extremely slow rate, such as 2kbps.

[0070] This invention allows for full compliance with major telecommunications standards, such as ITU-T G.8262, G.8262.1, G.8273.2 and G.8273.4.

[0071] While embodiments and applications of the invention have been shown and described, it will be apparent to those skilled in the art that further modifications can be made without departing from the inventive concept herein. Therefore, the invention is not limited except in the spirit of the appended claims.

Claims

1. A method for transmitting a first client clock signal in a first client clock domain and a second client clock signal in a second client clock domain between a first integrated circuit and a second integrated circuit via a carrier clock signal in a carrier clock domain, the method comprising: Provide a stable reference clock source to the first integrated circuit; In the first integrated circuit, the carrier clock signal is generated from the stable reference clock source, and the generated carrier clock signal is phase-locked to the stable reference clock source; Provide the first client clock signal in the first client clock domain to the first integrated circuit; Phase-locked to the first client clock signal by DPLL; Provide the first integrated circuit with the second client clock signal from the second client clock domain; Phase-locked to the second client clock signal by DPLL; The current phase of the first client clock signal is latched, and the phase change of the first client clock signal since the last latched phase of the first client clock signal is encoded as the first phase word information in the first position. The current phase of the second client clock signal is latched, and the phase change of the second client clock signal since the last latched phase of the second client clock signal is encoded as a second phase word information in a second bit position that is different from the first bit position; as well as The carrier clock signal is modulated to generate first phase word information, second phase word information, and non-phase word information, and the first phase word information, second phase word information, and non-phase word information are transmitted from the first integrated circuit to the second integrated circuit via a single line in a specified subframe time slot.

2. The method according to claim 1, wherein: Generating the carrier clock signal in the first integrated circuit and performing phase-locked loop (PLL) on the carrier clock signal includes generating the carrier clock signal in a carrier clock signal PLL in the first integrated circuit. Providing the first client clock signal to the first integrated circuit includes providing the first client clock signal to a first client clock signal phase-locked loop in the first integrated circuit; and Providing the second client clock signal to the first integrated circuit includes providing the second client clock signal to the second client clock signal phase-locked loop in the first integrated circuit.

3. The method of claim 1, wherein encoding the phase change of the first client clock signal and the second client clock signal onto the carrier clock signal comprises encoding a plurality of bits representing the phase change of the first client clock signal and the second client clock signal by modulating the timing of the edges of the carrier clock signal, thereby changing the duty cycle of the carrier clock signal to represent the value of each bit.

4. The method of claim 3, wherein modulating the timing of the edges of the carrier clock signal to change the duty cycle of the carrier clock signal includes modulating the timing of the falling edge of the carrier clock signal.

5. The method of claim 4, wherein the timing of modulating the falling edge of the carrier clock signal comprises setting the timing of the falling edge of the carrier clock signal to create a duty cycle of less than 50% to represent a first digital bit value, and setting the timing of the falling edge of the carrier clock signal to create a duty cycle of 50% to represent a second digital bit value.

6. The method of claim 5, further comprising setting the timing of the falling edge of the carrier clock signal to create a duty cycle greater than 50% to represent a flag bit.

7. The method according to claim 1, wherein: Encoding the phase change of the first client clock signal in the first position includes encoding the phase change of the first client clock signal in the first phase word; and Encoding the phase change of the second client clock signal in a second bit position, which is different from the first bit position, includes encoding the phase change of the second client clock signal in a second phase word.

8. The method of claim 1, further comprising encoding the time of day information from the time of day (ToD) counter onto the carrier clock signal in a third position different from the first and second bit positions.

9. The method of claim 8, wherein encoding the Time of Day (ToD) information onto the carrier clock signal in the third position comprises encoding the Time of Day (ToD) information as a first non-phase word information.

10. The method of claim 8, further comprising encoding data from the messaging channel onto a carrier clock signal in a fourth bit position different from the first bit position and the second bit position, and onto first non-phase word information in the third bit position.

11. The method of claim 10, wherein encoding data from the messaging channel onto the carrier clock signal in the fourth bit position comprises encoding the data from the messaging channel as a second non-phase word information.

12. The method according to claim 1, further comprising: In the second integrated circuit, the modulated carrier clock signal from the first integrated circuit is received via the single line; The phase change of the first client clock signal relative to the carrier clock signal is decoded from the modulated carrier clock signal; The decoded phase change of the first client clock signal is provided to the first client clock signal phase-locked loop; The phase change of the second client clock signal relative to the carrier clock signal is decoded from the modulated carrier clock signal; The decoded phase change of the second client clock signal is provided to the second client clock signal phase-locked loop; as well as The carrier clock signal received in the second integrated circuit is provided to the carrier clock signal phase-locked loop.

13. A system for transmitting a first client clock signal and a second client clock signal between a first integrated circuit and a second integrated circuit via a carrier clock signal, the system comprising: The first integrated circuit is coupled to the second integrated circuit; A carrier clock signal phase-locked loop, wherein the carrier clock signal phase-locked loop is located in the first integrated circuit, and the carrier clock signal phase-locked loop has an input terminal, the input terminal being coupled to a reference frequency source in the carrier clock domain; A first client clock signal phase-locked loop is located in the first integrated circuit. The first client clock signal phase-locked loop has an input terminal, which is coupled to the first client clock signal. A second client clock signal phase-locked loop is located in the first integrated circuit. The second client clock signal phase-locked loop has an input terminal, which is coupled to the second client clock signal. An encoder circuit, located within the first integrated circuit, is configured to: Information about the phase change of the first client clock signal relative to the carrier clock signal is encoded into the carrier clock signal in the first position; Information about the phase change of the second client clock signal relative to the carrier clock signal is encoded into the carrier clock signal at a second bit position that is different from the first bit position; as well as The carrier clock signal, which carries encoded information about the phase changes of the first client clock signal and the second client clock signal, is transmitted from the first integrated circuit to the second integrated circuit via a single communication line.

14. The system of claim 13, wherein the encoder circuit is further configured to: Encode the day's time information into the carrier clock signal; and Data from the message passing channel is encoded onto the carrier clock signal.

15. The system of claim 13, further comprising: Decoder circuit, located in the second integrated circuit, is configured to: In the second integrated circuit, a carrier clock signal carrying encoded information about the phase changes of the first client clock signal and the second client clock signal is received from the first integrated circuit via the single communication line; The phase change information of the first client clock signal is decoded from the carrier clock signal; as well as The phase change information of the second client clock signal is decoded from the carrier clock signal; A carrier clock signal phase-locked loop is located in the second integrated circuit. The carrier clock signal phase-locked loop has an input terminal, which is coupled to the decoder circuit to receive the carrier clock signal. A first client clock signal phase-locked loop has an input terminal, which is coupled to a decoder to receive the decoded phase change information of the first client clock signal. and The second client clock signal phase-locked loop has an input terminal that is coupled to the decoder to receive the decoded phase change information of the second client clock signal.

16. The system of claim 15, wherein the decoder is further configured to: Decode the current day's time information from the carrier clock signal; and Data from the message passing channel is decoded from the carrier clock signal.

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