Page table switching implementation method and system for RISC-V architecture

Abstract

The present invention discloses a page table switching implementation method and system for RISC-V architecture, the system includes a CPU and an MMU, the method includes: the CPU creates a temporary page table, stores the physical address corresponding to the temporary page table in a paging mechanism register; the CPU enables the MMU; after the MMU is enabled, the CPU access address is switched from the physical address space to the virtual address space; the CPU creates a formal page table, and replaces the physical address corresponding to the temporary page table stored in the paging mechanism register with the physical address corresponding to the formal page table. It can be seen that the present invention realizes that at the initial stage of system startup, there is no need to create a formal page table that occupies a large storage space at the beginning through the transition from the temporary page table to the formal page table. Instead, a temporary page table that occupies a small storage space is first created and used. There is no need to create two temporary page tables that occupy a large storage space in the prior art, and the steps of switching page tables multiple times are not required, which helps to simplify the page table switching process, improve the page table switching speed, and improve the efficiency of memory resource utilization.

Description

Technical Field

[0001] The present invention relates to the field of memory optimization technology, and in particular to a page table switching implementation method and system for a RISC-V architecture. Background Art

[0002] A physical address is an address number corresponding to a memory space. The range of physical addresses is related to the actual memory size. When the size of physical memory remains unchanged, virtual addresses are often used to maximize memory utilization and improve memory efficiency. In practical applications, the memory management unit (MMU) is often used to help the processor access memory space through virtual addresses. The MMU works by querying the page table to convert the virtual address issued by the processor into the corresponding physical address, thereby helping the processor access the corresponding memory space.

[0003] In practice, it has been found that the kernel of a RISC-V architecture-based processor has three pre-created page tables, and the processor needs to go through all three page tables to complete the switch from the temporary page table to the official page table (from trampoline_pg_dir to early_pg_dir and then to swapper_pg_dir). This switching process is cumbersome and wastes memory space (the storage space occupied by the temporary page table trampoline_pg_dir is not released after switching to another page table). Especially for IoT devices with limited memory space, the memory space wasted during the page table switching process can significantly affect the performance of IoT devices. Therefore, it is very important to simplify the page table switching process and reduce memory space waste in the RISC-V architecture. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a page table switching implementation method and system for the RISC-V architecture. By transitioning from a temporary page table to a formal page table, it is achieved that at the initial stage of system startup, there is no need to create a formal page table that occupies a large storage space from the beginning. Instead, a temporary page table that occupies a small storage space is first created and used. At the same time, there is no need to create two temporary page tables that occupy a large storage space in the prior art, and there is no need to switch from the first temporary page table to the second temporary page table and then to the formal page table. This helps to simplify the page table switching process, increase the page table switching speed, and improve the efficiency of memory resource utilization.

[0005] In order to solve the above technical problems, the first aspect of the present invention discloses a page table switching implementation method for the RISC-V architecture. The method is applied to a page table switching implementation system, the system including a CPU and an MMU, and the method includes:

[0006] The CPU creates a temporary page table and stores a physical address corresponding to the temporary page table in a paging mechanism register, so that after the MMU is enabled, the MMU obtains the temporary page table according to the physical address corresponding to the temporary page table stored in the paging mechanism register and converts the intercepted access address into a corresponding physical address according to the temporary page table; wherein the temporary page table includes the physical address of a portion of the storage space and a virtual address that has a mapping relationship with the physical address of each storage space in the portion of the storage space;

[0007] The CPU enables the MMU;

[0008] After the MMU is enabled, the access address of the CPU is switched from the physical address space to the virtual address space;

[0009] The CPU creates a formal page table and replaces the physical address corresponding to the temporary page table stored in the paging mechanism register with the physical address corresponding to the formal page table, so that the MMU converts the intercepted access address into the corresponding physical address according to the formal page table; wherein the formal page table includes the physical addresses of all storage spaces and the virtual addresses that have a mapping relationship with the physical addresses of each storage space.

[0010] As an optional implementation manner, in the first aspect of the present invention, after the MMU is enabled, switching the access address of the CPU from the physical address space to the virtual address space includes:

[0011] After the MMU is enabled, when the access address intercepted by the MMU is a physical address, obtaining a first virtual address stored in the exception entry register read by the CPU; the first virtual address is a virtual address corresponding to the physical address of the first storage space, and the first storage space is used to store the exception handling code;

[0012] Furthermore, after the MMU enables switching the access address of the CPU from the physical address space to the virtual address space and before the CPU creates a formal page table, the method further includes:

[0013] The MMU searches, based on the temporary page table, for a first physical address that has a mapping relationship with the first virtual address, and sends the first physical address to an address bus to trigger the CPU to call the exception handling code from the first storage space; wherein the CPU calls the exception handling code for the CPU to jump to read a second virtual address stored in a link register; the second virtual address stored in the link register is a virtual address corresponding to a physical address of a second storage space for storing a next program instruction to be called;

[0014] The MMU obtains the second virtual address read by the CPU, searches for a second physical address that has a mapping relationship with the second virtual address according to the temporary page table, and sends the second physical address to the address bus to trigger the CPU to call the program instructions stored in the second storage space corresponding to the second physical address.

[0015] As an optional implementation manner, in the first aspect of the present invention, before the CPU enables the MMU, the method further includes:

[0016] The CPU obtains a physical address of a first storage space for storing exception handling code, determines a virtual address corresponding to the physical address of the first storage space, and stores the virtual address corresponding to the first storage space in an exception entry register;

[0017] The CPU obtains the physical address of the second storage space for storing the next program instruction to be called, determines the virtual address corresponding to the physical address of the second storage space, and stores the virtual address corresponding to the second storage space in the link register.

[0018] As an optional implementation manner, in the first aspect of the present invention, the CPU determines the virtual address corresponding to the physical address of the first storage space, including:

[0019] The CPU searches for a virtual address that has a mapping relationship with the physical address of the first storage space according to a pre-created temporary page table, and determines the virtual address as the virtual address corresponding to the physical address of the first storage space; or

[0020] The CPU converts the physical address of the first storage space into its corresponding virtual address according to a predetermined conversion method.

[0021] As an optional implementation manner, in the first aspect of the present invention, the CPU converts the physical address of the first storage space into its corresponding virtual address according to a predetermined conversion method, including:

[0022] Get the first address of the CPU's kernel virtual address space and the first address of the kernel physical address space;

[0023] Subtracting the first address of the kernel physical address space from the first address of the kernel virtual address space to obtain an address space interval;

[0024] The physical address of the first storage space is added to the address space interval to obtain a virtual address corresponding to the physical address of the first storage space.

[0025] As an optional implementation, in the first aspect of the present invention, when the access address intercepted by the MMU is a physical address, and before the MMU obtains the first virtual address stored in the exception entry register read by the CPU, the method further includes:

[0026] The MMU generates an exception signal and sends the exception signal to the CPU, so that the CPU reads the first virtual address stored in the exception entry register according to the exception signal; wherein the exception signal is used to indicate that the access address intercepted by the MMU is a physical address.

[0027] As an optional implementation manner, in the first aspect of the present invention, the CPU enabling the MMU includes:

[0028] The paging mechanism enabling information is stored in the paging mechanism register to enable the paging mechanism.

[0029] A second aspect of the present invention discloses a page table switching implementation system for a RISC-V architecture, the system comprising a CPU and an MMU, the CPU comprising a creation processing module and an enabling module, and the MMU comprising a switching module, wherein:

[0030] The creation processing module is configured to create a temporary page table and store a physical address corresponding to the temporary page table in a paging mechanism register, so that after the MMU is enabled, the MMU obtains the temporary page table according to the physical address corresponding to the temporary page table stored in the paging mechanism register and converts the intercepted access address into a corresponding physical address according to the temporary page table; wherein the temporary page table includes the physical address of a portion of the storage space and a virtual address that has a mapping relationship with the physical address of each storage space in the portion of the storage space;

[0031] The enabling module is used to enable the MMU;

[0032] The switching module is configured to switch the access address of the CPU from the physical address space to the virtual address space after the MMU is enabled;

[0033] The creation processing module is also used to create a formal page table, replace the physical address corresponding to the temporary page table stored in the paging mechanism register with the physical address corresponding to the formal page table, so that the MMU converts the intercepted access address into the corresponding physical address according to the formal page table; wherein the formal page table includes the physical addresses of all storage spaces and the virtual addresses that have a mapping relationship with the physical address of each storage space.

[0034] As an optional implementation, in the second aspect of the present invention, the MMU further includes an acquisition module and a search and send module, wherein:

[0035] The acquisition module is configured to, after the MMU is enabled, acquire a first virtual address stored in the exception entry register read by the CPU when the access address intercepted by the MMU is a physical address; the first virtual address is a virtual address corresponding to a physical address of a first storage space, and the first storage space is used to store exception handling code;

[0036] The search and sending module is configured to, after the switching module switches the CPU's access address from the physical address space to the virtual address space and before the creation and processing module creates a formal page table, search, according to the temporary page table, for a first physical address that has a mapping relationship with the first virtual address, and send the first physical address to the address bus, so as to trigger the CPU to call the exception handling code from the first storage space; wherein the CPU calls the exception handling code for the CPU to jump to read the second virtual address stored in the link register; the second virtual address stored in the link register is a virtual address corresponding to the physical address of the second storage space for storing the next program instruction to be called;

[0037] The search and sending module is also used to obtain the second virtual address read by the CPU, search for the second physical address that has a mapping relationship with the second virtual address according to the temporary page table, and send the second physical address to the address bus to trigger the CPU to call the program instructions stored in the second storage space corresponding to the second physical address.

[0038] As an optional implementation, in the second aspect of the present invention, the CPU further includes an acquisition processing module, wherein:

[0039] The acquisition processing module is configured to acquire a physical address of a first storage space for storing exception handling code, determine a virtual address corresponding to the physical address of the first storage space, and store the virtual address corresponding to the first storage space in an exception entry register;

[0040] The acquisition processing module is further used to obtain the physical address of the second storage space for storing the next program instruction to be called, determine the virtual address corresponding to the physical address of the second storage space, and store the virtual address corresponding to the second storage space in the link register.

[0041] As an optional implementation, in the second aspect of the present invention, the manner in which the acquisition processing module determines the virtual address corresponding to the physical address of the first storage space specifically includes:

[0042] searching, according to a pre-created temporary page table, for a virtual address that has a mapping relationship with the physical address of the first storage space, and determining the virtual address as the virtual address corresponding to the physical address of the first storage space; or

[0043] The physical address of the first storage space is converted into its corresponding virtual address according to a predetermined conversion method.

[0044] As an optional implementation, in the second aspect of the present invention, the acquisition processing module converts the physical address of the first storage space into its corresponding virtual address according to a predetermined conversion method, specifically including:

[0045] Get the first address of the CPU's kernel virtual address space and the first address of the kernel physical address space;

[0046] Subtracting the first address of the kernel physical address space from the first address of the kernel virtual address space to obtain an address space interval;

[0047] The physical address of the first storage space is added to the address space interval to obtain a virtual address corresponding to the physical address of the first storage space.

[0048] As an optional implementation, in the second aspect of the present invention, the MMU further includes a generation and sending module, wherein:

[0049] The generation and sending module is used to generate an exception signal when the access address intercepted by the MMU is a physical address, and before the acquisition processing module obtains the first virtual address stored in the exception entry register read by the CPU, and send the exception signal to the CPU, so that the CPU reads the first virtual address stored in the exception entry register according to the exception signal; wherein the exception signal is used to indicate that the access address intercepted by the MMU is a physical address.

[0050] As an optional implementation manner, in the second aspect of the present invention, the manner in which the enabling module enables the MMU specifically includes:

[0051] The paging mechanism enabling information is stored in the paging mechanism register to enable the paging mechanism.

[0052] A third aspect of the present invention discloses a CPU, which is applied to a page table switching implementation system, and includes:

[0053] a memory storing executable program code;

[0054] a processor coupled to the memory;

[0055] The processor calls the executable program code stored in the memory to execute the steps performed by the CPU in the page table switching implementation method for the RISC-V architecture disclosed in the first aspect of the present invention.

[0056] A fourth aspect of the present invention discloses an MMU, which is applied to a page table switching implementation system, and includes:

[0057] a memory storing executable program code;

[0058] a processor coupled to the memory;

[0059] The processor calls the executable program code stored in the memory to execute the steps performed by the MMU in the page table switching implementation method for the RISC-V architecture disclosed in the first aspect of the present invention.

[0060] The fifth aspect of the present invention discloses a computer-storable medium, which stores computer instructions. When the computer instructions are called, they are used to execute the steps performed by the CPU or MMU in the page table switching implementation method for the RISC-V architecture disclosed in the first aspect of the present invention.

[0061] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0062] In an embodiment of the present invention, the CPU creates a temporary page table and stores the physical address corresponding to the temporary page table in a paging mechanism register, so that after the MMU is enabled, the MMU obtains the temporary page table according to the physical address corresponding to the temporary page table stored in the paging mechanism register and converts the intercepted access address into the corresponding physical address according to the temporary page table; wherein, the temporary page table includes the physical address of part of the storage space and the virtual address that has a mapping relationship with the physical address of each of the storage spaces in the part of the storage space; the CPU enables the MMU; after the MMU is enabled, the access address of the CPU is switched from the physical address space to the virtual address space; the CPU creates a formal page table and replaces the physical address corresponding to the temporary page table stored in the paging mechanism register with the physical address corresponding to the formal page table, so that the MMU converts the intercepted access address into the corresponding physical address according to the formal page table; wherein, the formal page table includes the physical addresses of all storage spaces and the virtual address that has a mapping relationship with the physical address of each of the storage spaces. It can be seen that the implementation of the present invention can achieve the transition from the temporary page table to the formal page table, so that there is no need to create a formal page table that occupies a large storage space at the beginning of the system startup, but first create and use a temporary page table that occupies a smaller storage space. At the same time, there is no need to create two temporary page tables that occupy a large storage space in the prior art, and the steps of switching from the first temporary page table to the second temporary page table and then to the formal page table, which helps to simplify the page table switching process, increase the page table switching speed, and improve the efficiency of memory resource utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0064] Figure 1 This is a flow chart of a method for implementing page table switching for a RISC-V architecture disclosed in an embodiment of the present invention;

[0065] Figure 2 This is a flow chart of another method for implementing page table switching for a RISC-V architecture disclosed in an embodiment of the present invention;

[0066] Figure 3 This is a schematic diagram of the structure of a page table switching implementation system for a RISC-V architecture disclosed in an embodiment of the present invention;

[0067] Figure 4This is a schematic diagram of the structure of another RISC-V architecture-oriented page table switching implementation system disclosed in an embodiment of the present invention;

[0068] Figure 5 It is a structural diagram of a CPU disclosed in an embodiment of the present invention.

[0069] Figure 6 This is a schematic diagram of the structure of an MMU disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0070] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0071] The terms "first," "second," and so on, in the description and claims of the present invention and the accompanying drawings are used to distinguish between different items, not to describe a specific order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, apparatus, product, or end comprising a series of steps or elements is not limited to the listed steps or elements but may optionally include steps or elements not listed therein, or may optionally include other steps or elements inherent to such process, method, product, or end.

[0072] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute a separate or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0073] The present invention discloses a page table switching implementation method and system for a RISC-V architecture. The method can realize that, at the initial stage of system startup, a formal page table that occupies a large storage space does not need to be created from the beginning through the transition from a temporary page table to a formal page table. Instead, a temporary page table that occupies a small storage space is first created and used. At the same time, there is no need to create two temporary page tables that occupy a large storage space, and the steps of switching from a first temporary page table to a second temporary page table and then to the formal page table in the prior art are eliminated. This helps to simplify the page table switching process, increase the page table switching speed, and improve the efficiency of memory resource utilization.

[0074] The following are detailed descriptions of each.

[0075] Example 1

[0076] See also Figure 1 , Figure 1 This is a flow chart of a method for implementing page table switching for a RISC-V architecture disclosed in an embodiment of the present invention. Figure 1 The page table switching implementation method described for the RISC-V architecture can be applied to a page table switching implementation system, which includes a CPU and an MMU. Figure 1 As shown, the page table switching implementation method for the RISC-V architecture may include the following operations:

[0077] 101. The CPU creates a temporary page table and stores the physical address corresponding to the temporary page table in the paging mechanism register, so that after the MMU is enabled, the MMU obtains the temporary page table according to the physical address corresponding to the temporary page table stored in the paging mechanism register and converts the intercepted access address into the corresponding physical address according to the temporary page table.

[0078] In an embodiment of the present invention, a temporary page table includes the physical address of a portion of the storage space and a virtual address that is mapped to the physical address of each storage space in the portion of the storage space. In an embodiment of the present invention, the temporary page table is the early_pg_dir page table commonly used in the RISC-V architecture. The space occupied by the early_pg_dir page table is released after kernel initialization is completed. Optionally, the temporary page table early_pg_dir can be created based on the setup_vm interface in the RISC-V architecture.

[0079] In an embodiment of the present invention, the paging mechanism register may be a satp register (S-mode control status register) based on the RISC-V architecture, and the satp register stores the first-level page table address.

[0080] 102. The CPU enables the MMU.

[0081] 103. After the MMU is enabled, the CPU's access address is switched from the physical address space to the virtual address space.

[0082] 104. The CPU creates a formal page table and replaces the physical address corresponding to the temporary page table stored in the paging mechanism register with the physical address corresponding to the formal page table, so that the MMU converts the intercepted access address into the corresponding physical address according to the formal page table.

[0083] In the embodiment of the present invention, the formal page table is the swapper_pg_dir page table commonly used in the RISC-V architecture. Optionally, the initialization and establishment of the page table swapper_pg_dir can be implemented based on the setup_vm_final function of the RISC-V architecture.

[0084] In the embodiment of the present invention, the formal page table includes the physical addresses of all storage spaces and the virtual addresses that have a mapping relationship with the physical address of each storage space.

[0085] It can be seen that the embodiment of the present invention realizes that there is no need to create a formal page table that occupies a large storage space at the beginning of the system startup through the transition from the temporary page table to the formal page table. Instead, a temporary page table that occupies a smaller storage space is first created and used. At the same time, there is no need to create two temporary page tables that occupy a large storage space in the prior art, and there is no need to switch from the first temporary page table to the second temporary page table and then to the formal page table. This helps to simplify the page table switching process, increase the page table switching speed, and improve the efficiency of memory resource utilization.

[0086] In an optional embodiment, the CPU enables the MMU, including:

[0087] The paging mechanism enabling information is stored in the paging mechanism register to enable the paging mechanism.

[0088] In this optional embodiment, the MODE portion of the satp register can be assigned a value in the S mode of the RISC-V architecture to enable the paging mechanism. When the paging mechanism is enabled, the MMU starts working and obtains the current page table through the page table address stored in the satp register to convert the intercepted access address according to the page table.

[0089] It can be seen that this optional embodiment can enable the MMU by enabling the paging mechanism, which helps to implement the subsequent operation of the MMU switching the CPU access address from the physical address space to the virtual address space.

[0090] Example 2

[0091] See also Figure 2 , Figure 2 This is a flow chart of another method for implementing page table switching for RISC-V architecture disclosed in an embodiment of the present invention. Figure 2 The page table switching implementation method described for the RISC-V architecture can be applied to a page table switching implementation system, which includes a CPU and an MMU. Figure 2 As shown, the page table switching implementation method for the RISC-V architecture may include the following operations:

[0092] 201. The CPU creates a temporary page table and stores the physical address corresponding to the temporary page table in the paging mechanism register, so that after the MMU is enabled, the MMU obtains the temporary page table according to the physical address corresponding to the temporary page table stored in the paging mechanism register and converts the intercepted access address into the corresponding physical address according to the temporary page table.

[0093] 202. The CPU enables the MMU.

[0094] 203. After the MMU is enabled, when the access address intercepted by the MMU is a physical address, the first virtual address stored in the exception entry register read by the CPU is obtained.

[0095] In an embodiment of the present invention, the first virtual address is a virtual address corresponding to a physical address of the first storage space, and the first storage space is used to store exception handling code. In an embodiment of the present invention, the exception entry register may be an stvec register based on the RISC-V architecture. Optionally, the exception entry register may be saved in the S mode of the RISC-V architecture.

[0096] 204. The CPU creates a formal page table and replaces the physical address corresponding to the temporary page table stored in the paging mechanism register with the physical address corresponding to the formal page table, so that the MMU converts the intercepted access address into the corresponding physical address according to the formal page table.

[0097] In the embodiment of the present invention, for other descriptions of step 201, step 202 and step 204, please refer to the detailed description of step 101, step 102 and step 104 in embodiment 1, which will not be repeated in the embodiment of the present invention.

[0098] It can be seen that the embodiment of the present invention realizes that at the beginning of the system startup, there is no need to create a formal page table that occupies a large storage space at the beginning through the transition from the temporary page table to the formal page table. Instead, a temporary page table that occupies a smaller storage space is created and used first. At the same time, there is no need to create two temporary page tables that occupy a large storage space in the prior art, and the steps of switching from the first temporary page table to the second temporary page table and then to the formal page table are not required. This helps to simplify the page table switching process, improve the page table switching speed, and improve the efficiency of memory resource utilization. When the access address of the CPU is intercepted as a physical address after the MMU is enabled, the first virtual address stored in the exception entry register read by the CPU is obtained. In this process, the CPU uses the virtual address as the access address of the storage space because it reads the virtual address (the access address of the CPU is a physical address after the MMU is enabled), thereby realizing the process of switching the CPU access address from the physical address space to the virtual address space. Since the virtual address space is much larger than the physical address space, it helps to improve the efficiency of using the storage space.

[0099] In an optional embodiment, after the MMU enables switching the CPU's access address from the physical address space to the virtual address space, and before the CPU creates the formal page table, the method further includes:

[0100] The MMU searches the temporary page table for a first physical address that has a mapping relationship with the first virtual address, and sends the first physical address to the address bus to trigger the CPU to call the exception handling code from the first storage space.

[0101] The MMU obtains the second virtual address read by the CPU, searches for the second physical address that has a mapping relationship with the second virtual address according to the temporary page table, and sends the second physical address to the address bus to trigger the CPU to call the program instructions stored in the second storage space corresponding to the second physical address.

[0102] In this optional embodiment, the CPU calls the exception handling code for the CPU to jump and read the second virtual address stored in the link register. The second virtual address stored in the link register is the virtual address corresponding to the physical address of the second storage space used to store the next program instruction to be called.

[0103] Optionally, the link register may be a ra register based on the RISC-V architecture, which is a link register returned by a function call. Optionally, the exception handling code includes a ret instruction, i.e., a function call return instruction in the RISC-V architecture. When the CPU reads the ret instruction, it jumps to read the address stored in the link register returned by the function call.

[0104] It can be seen that in this optional embodiment, the MMU converts the CPU's access address from a virtual address to a physical address according to the temporary page table, and triggers the CPU to read the storage space corresponding to the access address by sending the physical address to the address bus, thereby realizing the process of the CPU accessing the storage space according to the virtual address.

[0105] In another optional embodiment, before the CPU enables the MMU, the method further includes:

[0106] The CPU obtains the physical address of a first storage space for storing exception handling code, determines a virtual address corresponding to the physical address of the first storage space, and stores the virtual address corresponding to the first storage space in an exception entry register;

[0107] The CPU obtains the physical address of the second storage space for storing the next program instruction to be called, determines the virtual address corresponding to the physical address of the second storage space, and stores the virtual address corresponding to the second storage space in the link register.

[0108] Optionally, the relocate function of the RISC-V architecture can be used to store the corresponding virtual address in the exception entry register and the link register.

[0109] It can be seen that this optional embodiment determines the virtual addresses corresponding to the storage space for storing the exception handling code and the storage space for storing the next program instruction to be called before enabling the MMU, and stores the virtual addresses in designated registers respectively. This helps when the CPU subsequently reads the address stored in the register to read the address as a virtual address, and prompts the CPU's access address to switch from the physical address space to the virtual address space.

[0110] In yet another optional embodiment, the CPU determines the virtual address corresponding to the physical address of the first storage space, including:

[0111] The CPU searches for a virtual address that has a mapping relationship with the physical address of the first storage space according to a pre-created temporary page table, and determines the virtual address as the virtual address corresponding to the physical address of the first storage space; or

[0112] The CPU converts the physical address of the first storage space into its corresponding virtual address according to a predetermined conversion method.

[0113] It can be seen that this optional embodiment can convert the physical address into a virtual address according to the temporary page table or the conversion method, which helps the CPU to subsequently store the virtual address corresponding to the first storage space in the exception entry register.

[0114] In yet another optional embodiment, the CPU converts the physical address of the first storage space into its corresponding virtual address according to a predetermined conversion method, including:

[0115] Get the first address of the CPU's kernel virtual address space and the first address of the kernel physical address space;

[0116] Subtract the first address of the kernel virtual address space from the first address of the kernel physical address space to obtain the address space interval;

[0117] The physical address of the first storage space is added to the address space interval to obtain a virtual address corresponding to the physical address of the first storage space.

[0118] In this optional embodiment, the first address of the kernel physical address space is related to the division of the storage space, and the first address of the kernel virtual address space is related to the number of bits of the system. For example, assuming that the storage space of a device is 4G in total, which is distributed as IO space 0-1G and Memory space 1G-4G, the first address of its kernel physical address space is the physical address 0x40000000 corresponding to 1G. When the device system is a 39-bit system, the first address of the kernel virtual address space is 0xffffffc000000000 corresponding to the physical address 0x40000000.

[0119] In this optional embodiment, the physical address of the first storage space is based on the first address of the kernel physical address space, and its virtual address is based on the first address of the kernel virtual address space. When the offset address of the physical address is equal to the offset address of the virtual address, the physical address of the first storage space plus the difference between the first address of the kernel virtual address space and the first address of the kernel physical address space is the virtual address of the first storage space.

[0120] It can be seen that this optional embodiment can obtain the virtual address of the physical address by adding the difference between the base address of the virtual address and the base address of the physical address to the physical address when the offset addresses are equal, thereby realizing the conversion of the physical address to the virtual address, which helps the subsequent CPU to store the converted virtual address in the register.

[0121] In yet another optional embodiment, when the access address intercepted by the MMU is a physical address, and before the MMU obtains the first virtual address stored in the exception entry register read by the CPU, the method further includes:

[0122] The MMU generates an exception signal and sends the exception signal to the CPU, so that the CPU reads the first virtual address stored in the exception entry register according to the exception signal; wherein the exception signal is used to indicate that the access address intercepted by the MMU is a physical address.

[0123] It can be seen that this optional embodiment can generate an exception signal when the MMU intercepts the CPU's access address as a physical address, thereby triggering the CPU to read the first virtual address stored in the exception entry register according to the exception signal, thereby realizing the switching of the CPU's access address from the physical address space to the virtual address space. Since the virtual memory space is much larger than the physical address space, the efficiency of memory space utilization can be improved.

[0124] Example 3

[0125] See also Figure 3 , Figure 3 This is a schematic diagram of a page table switching implementation system for a RISC-V architecture disclosed in an embodiment of the present invention, the system includes a CPU and an MMU. Figure 3 The page table switching implementation system for the RISC-V architecture described above can be applied to a page table switching device. The CPU includes a creation processing module 301, an enabling module 302, and the MMU includes a switching module 303, wherein:

[0126] A creation processing module 301 is configured to create a temporary page table and store a physical address corresponding to the temporary page table in a paging mechanism register, so that after the MMU is enabled, the MMU obtains the temporary page table based on the physical address corresponding to the temporary page table stored in the paging mechanism register and converts the intercepted access address into a corresponding physical address based on the temporary page table; wherein the temporary page table includes the physical address of a portion of the storage space and a virtual address that has a mapping relationship with the physical address of each storage space in the portion of the storage space;

[0127] An enabling module 302, configured to enable the MMU;

[0128] A switching module 303 is used to switch the CPU's access address from the physical address space to the virtual address space after the MMU is enabled;

[0129] The creation processing module 301 is also used to create a formal page table, replace the physical address corresponding to the temporary page table stored in the paging mechanism register with the physical address corresponding to the formal page table, so that the MMU converts the intercepted access address into the corresponding physical address according to the formal page table; wherein the formal page table includes the physical addresses of all storage spaces and the virtual addresses that have a mapping relationship with the physical addresses of each storage space.

[0130] In an embodiment of the present invention, the temporary page table is the early_pg_dir page table commonly used in the RISC-V architecture. The space occupied by the early_pg_dir page table will be released after the kernel initialization is completed. Optionally, the temporary page table early_pg_dir can be created based on the setup_vm interface in the RISC-V architecture.

[0131] In an embodiment of the present invention, the paging mechanism register may be a satp register (S-mode control status register) based on the RISC-V architecture, and the satp register stores the first-level page table address.

[0132] In the embodiment of the present invention, the formal page table is the swapper_pg_dir page table commonly used in the RISC-V architecture. Optionally, the initialization and establishment of the page table swapper_pg_dir can be implemented based on the setup_vm_final function of the RISC-V architecture.

[0133] It can be seen that the embodiment of the present invention realizes that there is no need to create a formal page table that occupies a large storage space at the beginning of the system startup through the transition from the temporary page table to the formal page table. Instead, a temporary page table that occupies a smaller storage space is first created and used. At the same time, there is no need to create two temporary page tables that occupy a large storage space in the prior art, and there is no need to switch from the first temporary page table to the second temporary page table and then to the formal page table. This helps to simplify the page table switching process, increase the page table switching speed, and improve the efficiency of memory resource utilization.

[0134] In an optional embodiment, if Figure 4 As shown, the MMU further includes an acquisition module 304 and a search and send module 305, wherein:

[0135] An acquisition module 304 is configured to, after the MMU is enabled, acquire a first virtual address stored in the exception entry register read by the CPU when the access address intercepted by the MMU is a physical address; the first virtual address is a virtual address corresponding to the physical address of the first storage space, which is used to store exception handling code;

[0136] The search and sending module 305 is configured to search, according to the temporary page table, for a first physical address that has a mapping relationship with the first virtual address after the switching module 303 switches the CPU's access address from the physical address space to the virtual address space and before the creation processing module 301 creates the formal page table, and to send the first physical address to the address bus to trigger the CPU to call the exception handling code from the first storage space; wherein the CPU calls the exception handling code for the CPU to jump to read the second virtual address stored in the link register; the second virtual address stored in the link register is the virtual address corresponding to the physical address of the second storage space for storing the next program instruction to be called;

[0137] The search and sending module 305 is also used to obtain the second virtual address read by the CPU, search for the second physical address that has a mapping relationship with the second virtual address according to the temporary page table, and send the second physical address to the address bus to trigger the CPU to call the program instructions stored in the second storage space corresponding to the second physical address.

[0138] Optionally, the link register may be a ra register based on the RISC-V architecture, which is a link register returned by a function call. Optionally, the exception handling code includes a ret instruction, i.e., a function call return instruction in the RISC-V architecture. When the CPU reads the ret instruction, it jumps to read the address stored in the link register returned by the function call.

[0139] It can be seen that in this optional embodiment, when the MMU is enabled and the access address of the CPU is intercepted as a physical address, the first virtual address stored in the exception entry register read by the CPU is obtained. In this process, the CPU uses the virtual address as the access address of the storage space because it reads the virtual address (the access address of the CPU is a physical address after the MMU is enabled), thereby realizing the process of switching the CPU's access address from the physical address space to the virtual address space. Since the virtual address space is much larger than the physical address space, it helps to improve the efficiency of using the storage space; and, the MMU converts the CPU's access address from the virtual address to the physical address according to the temporary page table, and triggers the CPU to read the storage space corresponding to the access address by sending the physical address to the address bus, thereby realizing the process of the CPU accessing the storage space according to the virtual address.

[0140] In another optional embodiment, Figure 4 As shown, the CPU further includes an acquisition processing module 306, wherein:

[0141] an acquisition processing module 306 for acquiring a physical address of a first storage space for storing exception handling code, determining a virtual address corresponding to the physical address of the first storage space, and storing the virtual address corresponding to the first storage space in an exception entry register;

[0142] The acquisition processing module 306 is further configured to acquire the physical address of the second storage space for storing the next program instruction to be called, determine the virtual address corresponding to the physical address of the second storage space, and store the virtual address corresponding to the second storage space in the link register.

[0143] Optionally, the relocate function of the RISC-V architecture can be used to store the corresponding virtual address in the exception entry register and the link register.

[0144] It can be seen that this optional embodiment determines the virtual addresses corresponding to the storage space for storing the exception handling code and the storage space for storing the next program instruction to be called before enabling the MMU, and stores the virtual addresses in designated registers respectively. This helps when the CPU subsequently reads the address stored in the register to read the address as a virtual address, and prompts the CPU's access address to switch from the physical address space to the virtual address space.

[0145] In another optional embodiment, Figure 4 As shown, the acquisition processing module 306 determines the virtual address corresponding to the physical address of the first storage space in the following manner:

[0146] According to a pre-created temporary page table, searching for a virtual address that has a mapping relationship with the physical address of the first storage space, and determining the virtual address as the virtual address corresponding to the physical address of the first storage space; or

[0147] The physical address of the first storage space is converted into its corresponding virtual address according to a predetermined conversion method.

[0148] It can be seen that this optional embodiment can convert the physical address into a virtual address according to the temporary page table or the conversion method, which helps the CPU to subsequently store the virtual address corresponding to the first storage space in the exception entry register.

[0149] In another optional embodiment, Figure 4 As shown, the acquisition processing module 306 converts the physical address of the first storage space into its corresponding virtual address according to a predetermined conversion method, specifically including:

[0150] Get the first address of the CPU's kernel virtual address space and the first address of the kernel physical address space;

[0151] Subtract the first address of the kernel virtual address space from the first address of the kernel physical address space to obtain the address space interval;

[0152] The physical address of the first storage space is added to the address space interval to obtain a virtual address corresponding to the physical address of the first storage space.

[0153] In this optional embodiment, the first address of the kernel physical address space is related to the division of the storage space, and the first address of the kernel virtual address space is related to the number of bits of the system. For example, assuming that the storage space of a device is 4G in total, which is distributed as IO space 0-1G and Memory space 1G-4G, the first address of its kernel physical address space is the physical address 0x40000000 corresponding to 1G. When the device system is a 39-bit system, the first address of the kernel virtual address space is 0xffffffc000000000 corresponding to the physical address 0x40000000.

[0154] In this optional embodiment, the physical address of the first storage space is based on the first address of the kernel physical address space, and its virtual address is based on the first address of the kernel virtual address space. When the offset address of the physical address is equal to the offset address of the virtual address, the physical address of the first storage space plus the difference between the first address of the kernel virtual address space and the first address of the kernel physical address space is the virtual address of the first storage space.

[0155] It can be seen that this optional embodiment can obtain the virtual address of the physical address by adding the difference between the base address of the virtual address and the base address of the physical address to the physical address when the offset addresses are equal, thereby realizing the conversion of the physical address to the virtual address, which helps the subsequent CPU to store the converted virtual address in the register.

[0156] In another optional embodiment, Figure 4 As shown, the MMU further includes a generating and sending module 307, wherein:

[0157] A sending module 307 is generated to generate an exception signal when the access address intercepted by the MMU is a physical address, and before the acquisition processing module 306 obtains the first virtual address stored in the exception entry register read by the CPU, and sends the exception signal to the CPU so that the CPU reads the first virtual address stored in the exception entry register according to the exception signal; wherein the exception signal is used to indicate that the access address intercepted by the MMU is a physical address.

[0158] It can be seen that this optional embodiment can generate an exception signal when the MMU intercepts the CPU's access address as a physical address, thereby triggering the CPU to read the first virtual address stored in the exception entry register according to the exception signal, thereby realizing the switching of the CPU's access address from the physical address space to the virtual address space. Since the virtual memory space is much larger than the physical address space, the efficiency of memory space utilization can be improved.

[0159] In another optional embodiment, Figure 4 As shown, the enabling module 302 enables the MMU in the following ways:

[0160] The paging mechanism enabling information is stored in the paging mechanism register to enable the paging mechanism.

[0161] In this optional embodiment, the MODE portion of the satp register can be assigned a value in the S mode of the RISC-V architecture to enable the paging mechanism. When the paging mechanism is enabled, the MMU starts working and obtains the current page table through the page table address stored in the satp register to convert the intercepted access address according to the page table.

[0162] It can be seen that this optional embodiment can enable the MMU by enabling the paging mechanism, which helps to implement the subsequent operation of the MMU switching the CPU access address from the physical address space to the virtual address space.

[0163] Example 4

[0164] See also Figure 5 , Figure 5 This is a schematic diagram of the structure of a CPU disclosed in an embodiment of the present invention. Figure 5As shown, the CPU is applied to a page table switching implementation system, and the CPU may include:

[0165] A memory 401 storing executable program code;

[0166] a processor 402 coupled to the memory 401;

[0167] The processor 402 calls the executable program code stored in the memory 401 to execute the steps executed by the CPU in the page table switching implementation method for the RISC-V architecture described in the first embodiment of the present invention or the second embodiment of the present invention.

[0168] Example 5

[0169] See also Figure 6 , Figure 6 This is a schematic diagram of the structure of an MMU disclosed in an embodiment of the present invention. Figure 6 As shown, the MMU is applied to a page table switching implementation system, and the MMU may include:

[0170] A memory 501 storing executable program code;

[0171] a processor 502 coupled to the memory 501;

[0172] The processor 502 calls the executable program code stored in the memory 501 to execute the steps performed by the MMU in the page table switching implementation method for the RISC-V architecture described in the first embodiment of the present invention or the second embodiment of the present invention.

[0173] Example 6

[0174] An embodiment of the present invention discloses a computer-storable medium, which stores computer instructions. When the computer instructions are called, they are used to execute the steps performed by the CPU or MMU in the page table switching implementation method for the RISC-V architecture described in Embodiment 1 or Embodiment 2 of the present invention.

[0175] Example 7

[0176] An embodiment of the present invention discloses a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute the steps performed by a CPU or MMU in the page table switching implementation method for the RISC-V architecture described in Example 1 or Example 2.

[0177] The device embodiments described above are merely illustrative, wherein the modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, i.e., they may be located in one place or distributed across multiple network modules. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Those skilled in the art can understand and implement the present invention without inventive effort.

[0178] Through the detailed description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus the necessary general hardware platform, or of course, by means of hardware. Based on this understanding, the above technical solution, in essence, or the portion that contributes to the prior art, can be embodied in the form of a software product, which can be stored in a computer-readable storage medium, including a read-only memory (ROM), a random access memory (RAM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), a one-time programmable read-only memory (OTPROM), an electronically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, magnetic disk storage, magnetic tape storage, or any other computer-readable medium capable of carrying or storing data.

[0179] Finally, it should be noted that the page table switching implementation method and system for the RISC-V architecture disclosed in the embodiments of the present invention are only preferred embodiments of the present invention, and are only used to illustrate the technical solutions of the present invention, rather than to limit them. Although the present invention has been described in detail with reference to the aforementioned embodiments, it should be understood by those skilled in the art that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features therein can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A page table switching implementation method for RISC-V architecture, characterized in that: The method is applied to a page table switching implementation system, the system including a CPU and an MMU, and the method includes: The CPU creates a temporary page table and stores a physical address corresponding to the temporary page table in a paging mechanism register, so that after the MMU is enabled, the MMU obtains the temporary page table according to the physical address corresponding to the temporary page table stored in the paging mechanism register and converts the intercepted access address into a corresponding physical address according to the temporary page table; wherein the temporary page table includes the physical address of a portion of the storage space and a virtual address that has a mapping relationship with the physical address of each storage space in the portion of the storage space; The CPU enables the MMU; After the MMU is enabled, the access address of the CPU is switched from the physical address space to the virtual address space; The CPU creates a formal page table and replaces the physical address corresponding to the temporary page table stored in the paging mechanism register with the physical address corresponding to the formal page table, so that the MMU converts the intercepted access address into the corresponding physical address according to the formal page table; wherein the formal page table includes the physical addresses of all storage spaces and the virtual address that has a mapping relationship with the physical address of each storage space; After the MMU is enabled, the access address of the CPU is switched from the physical address space to the virtual address space, including: After the MMU is enabled, when the access address intercepted by the MMU is a physical address, obtaining a first virtual address stored in the exception entry register read by the CPU; the first virtual address is a virtual address corresponding to the physical address of the first storage space, and the first storage space is used to store the exception handling code; Furthermore, after the MMU enables switching the access address of the CPU from the physical address space to the virtual address space and before the CPU creates a formal page table, the method further includes: The MMU searches, based on the temporary page table, for a first physical address that has a mapping relationship with the first virtual address, and sends the first physical address to an address bus to trigger the CPU to call the exception handling code from the first storage space; wherein the CPU calls the exception handling code for the CPU to jump to read a second virtual address stored in a link register; the second virtual address stored in the link register is a virtual address corresponding to a physical address of a second storage space for storing a next program instruction to be called; The MMU obtains the second virtual address read by the CPU, searches for a second physical address that has a mapping relationship with the second virtual address according to the temporary page table, and sends the second physical address to the address bus to trigger the CPU to call the program instructions stored in the second storage space corresponding to the second physical address.

2. The method for implementing page table switching for RISC-V architecture according to claim 1, characterized in that: Before the CPU enables the MMU, the method further includes: The CPU obtains a physical address of a first storage space for storing exception handling code, determines a virtual address corresponding to the physical address of the first storage space, and stores the virtual address corresponding to the first storage space in an exception entry register; The CPU obtains the physical address of the second storage space for storing the next program instruction to be called, determines the virtual address corresponding to the physical address of the second storage space, and stores the virtual address corresponding to the second storage space in the link register.

3. The method for implementing page table switching for RISC-V architecture according to claim 2, characterized in that: The CPU determines the virtual address corresponding to the physical address of the first storage space, including: The CPU searches for a virtual address that has a mapping relationship with the physical address of the first storage space according to a pre-created temporary page table, and determines the virtual address as the virtual address corresponding to the physical address of the first storage space; or The CPU converts the physical address of the first storage space into its corresponding virtual address according to a predetermined conversion method.

4. The method for implementing page table switching for RISC-V architecture according to claim 3, characterized in that: The CPU converts the physical address of the first storage space into a corresponding virtual address according to a predetermined conversion method, including: Get the first address of the CPU's kernel virtual address space and the first address of the kernel physical address space; Subtracting the first address of the kernel physical address space from the first address of the kernel virtual address space to obtain an address space interval; The physical address of the first storage space is added to the address space interval to obtain a virtual address corresponding to the physical address of the first storage space.

5. The method for implementing page table switching for RISC-V architecture according to claim 1, 3 or 4, characterized in that: When the access address intercepted by the MMU is a physical address, and before the MMU obtains the first virtual address stored in the exception entry register read by the CPU, the method further includes: The MMU generates an exception signal and sends the exception signal to the CPU, so that the CPU reads the first virtual address stored in the exception entry register according to the exception signal; wherein the exception signal is used to indicate that the access address intercepted by the MMU is a physical address.

6. The method for implementing page table switching for RISC-V architecture according to claim 5, characterized in that: The CPU enabling the MMU includes: The paging mechanism enabling information is stored in the paging mechanism register to enable the paging mechanism.

7. A page table switching implementation system for RISC-V architecture, characterized in that: The system is used to execute the page table switching implementation method for the RISC-V architecture according to any one of claims 1 to 6, and the system includes a CPU and an MMU, the CPU includes a creation processing module and an enable module, and the MMU includes a switching module, wherein: The creation processing module is configured to create a temporary page table and store a physical address corresponding to the temporary page table in a paging mechanism register, so that after the MMU is enabled, the MMU obtains the temporary page table according to the physical address corresponding to the temporary page table stored in the paging mechanism register and converts the intercepted access address into a corresponding physical address according to the temporary page table; wherein the temporary page table includes the physical address of a portion of the storage space and a virtual address that has a mapping relationship with the physical address of each storage space in the portion of the storage space; The enabling module is used to enable the MMU; The switching module is configured to switch the access address of the CPU from the physical address space to the virtual address space after the MMU is enabled; The creation processing module is also used to create a formal page table, replace the physical address corresponding to the temporary page table stored in the paging mechanism register with the physical address corresponding to the formal page table, so that the MMU converts the intercepted access address into the corresponding physical address according to the formal page table; wherein the formal page table includes the physical addresses of all storage spaces and the virtual addresses that have a mapping relationship with the physical address of each storage space.

8. A CPU, characterized in that: The CPU is applied to a page table switching implementation system, and the CPU includes: a memory storing executable program code; a processor coupled to the memory; The processor calls the executable program code stored in the memory to execute the steps performed by the CPU in the page table switching implementation method for the RISC-V architecture as described in any one of claims 1 to 6.

9. A computer storage medium, characterized in that The computer storage medium stores computer instructions, which, when called, are used to execute the steps performed by the CPU or MMU in the page table switching implementation method for the RISC-V architecture as described in any one of claims 1 to 6.

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