Timing optimization circuit and method, chip and electronic device

Abstract

The embodiment of the present application discloses a timing optimization circuit and method, a chip and an electronic device, wherein the electronic device includes a chip provided with a timing optimization circuit, the timing optimization circuit includes a first register, a second register, and a third register, wherein the third register is a replica register of the first register; the path distance between the first register and the second register is greater than the path distance between the third register and the second register; when the timing report obtained by executing the timing analysis command indicates that there is a timing violation in the first timing path, the second timing path is used for timing optimization processing; the path starting point of the first timing path is the first register, and the path end point is the second register; the path starting point of the second timing path is the third register, and the path end point is the second register. The timing optimization method includes executing the timing analysis command and obtaining the timing report; when the timing report indicates that there is a timing violation in the first timing path, timing optimization processing is performed through the second timing path.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a timing optimization circuit and method, a chip and an electronic device. Background Art

[0002] As the scale of chip design becomes larger and the competition becomes more intense, the timing closure becomes more complex, and the requirements for chip back-end design become higher and higher. With the support of powerful Electronics Design Automation (EDA) tools, most timing problems can be solved automatically. However, when chip design enters the Engineering Change Order (Engineer Changing Order, ECO) stage, it is inevitable that some timing problems will be left behind that have not been optimized by the tools.

[0003] Currently, for the remaining timing violations in the ECO stage, common optimization methods such as optimizing data paths, lengthening or shortening clock trees, etc., the timing optimization effect is not ideal, which seriously affects the progress of the project and chip performance. Summary of the invention

[0004] The embodiments of the present application provide a timing optimization circuit and method, a chip and an electronic device, which can greatly improve the timing optimization effect, thereby shortening the time of chip back-end design and effectively improving the design efficiency and performance of the chip.

[0005] The technical solution of the embodiment of the present application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides a timing optimization circuit, the timing optimization circuit comprising: a first register, a second register, and a third register, wherein the third register is a replica register of the first register; a path distance between the first register and the second register is greater than a path distance between the third register and the second register;

[0007] When the timing report obtained by executing the timing analysis command indicates that there is a timing violation in the first timing path, the second timing path is used for timing optimization processing; wherein the path starting point of the first timing path is the first register, and the path end point is the second register; the path starting point of the second timing path is the third register, and the path end point is the second register.

[0008] In a second aspect, an embodiment of the present application provides a timing optimization method, which is applied to a timing optimization circuit, wherein the timing optimization circuit includes: a first register, a second register, and a third register, wherein the third register is a replica register of the first register; the path distance between the first register and the second register is greater than the path distance between the third register and the second register; the method includes:

[0009] When the timing report indicates that there is a timing violation in the first timing path, timing optimization processing is performed through the second timing path; wherein the path starting point of the first timing path is the first register, and the path end point is the second register; the path starting point of the second timing path is the third register, and the path end point is the second register.

[0010] In a third aspect, an embodiment of the present application provides a chip, wherein the chip includes the timing optimization circuit as described in the first aspect,

[0011] In a fourth aspect, an embodiment of the present application provides an electronic device, wherein the electronic device is the chip described in the third aspect.

[0012] The embodiment of the present application provides a timing optimization circuit and method, a chip and an electronic device, wherein the electronic device includes a chip provided with a timing optimization circuit, and the timing optimization circuit includes: a first register, a second register, a third register, and the third register is a replica register of the first register; the path distance between the first register and the second register is greater than the path distance between the third register and the second register; when the timing report obtained by executing the timing analysis command indicates that there is a timing violation in the first timing path, the second timing path is used for timing optimization processing; the path starting point of the first timing path is the first register, and the path end point is the second register; the path starting point of the second timing path is the third register, and the path end point is the second register. The timing optimization method includes executing the timing analysis command to obtain the timing report; when the timing report indicates that there is a timing violation in the first timing path, the timing optimization processing is performed through the second timing path. That is, in the present application, when a timing path with the first register as the path starting point is optimized, the corresponding new timing path can be constructed by cloning the third register of the first register, and the timing convergence effect is achieved by utilizing the characteristic that the third register is closer to the second register at the end point of the path. Such a timing optimization method can not only solve the timing problem efficiently and accurately, but also will not interfere with the timing of other registers connected to the back end of the first register, thus reducing the scope of influence. This can greatly improve the timing optimization effect, thereby shortening the chip back-end design time and effectively improving the chip design efficiency and performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 Indicates timing violation Figure 1 ;

[0014] Figure 2 An indication of the physical distance of the registers Figure 1 ;

[0015] Figure 3 An indication of the physical distance of the registers Figure 2 ;

[0016] Figure 4 Indicates timing violation Figure 2 ;

[0017] Figure 5 Schematic diagram of a circuit optimized for timing Figure 1 ;

[0018] Figure 6 Schematic diagram of the structure of the timing optimization circuit Figure 1 ;

[0019] Figure 7 Schematic diagram of the structure of the timing optimization circuit Figure 2 ;

[0020] Figure 8 Schematic diagram of the structure of the timing optimization circuit Figure 3 ;

[0021] Fig. 9 Indicates timing violation Figure 3 ;

[0022] Fig.10 Schematic diagram of a circuit optimized for timing Figure 2 ;

[0023] Fig.11 Schematic diagram of the implementation process of the timing optimization method Figure 1 ;

[0024] Fig.12 Schematic diagram of the implementation process of the timing optimization method Figure 2 ;

[0025] Fig.13 Schematic diagram of the implementation process of the timing optimization method Figure 3 ;

[0026] Fig.14 Schematic diagram of the chip structure Figure 1 ;

[0027] Fig.15 Schematic diagram of the chip structure Figure 2 ;

[0028] Fig.16 Schematic diagram of the structure of electronic equipment Figure 1 ;

[0029] Fig.17 Schematic diagram of the structure of electronic equipment Figure 2 . DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. It is understood that the specific embodiments described herein are only used to explain the related applications, rather than to limit the applications. It should also be noted that, for ease of description, only the parts related to the related applications are shown in the drawings.

[0031] Before further describing the embodiments of the present invention in detail, the nouns and terms involved in the embodiments of the present invention are described. The nouns and terms involved in the embodiments of the present invention are subject to the following interpretations.

[0032] Placement and Route (PnR). Place refers to layout and Route refers to routing.

[0033] Electronic Design Automation (EDA) refers to the use of Computer Aided Design (CAD) software to complete the functional design, synthesis, verification, physical design (including layout, routing, layout, design rule checking, etc.) of very large scale integrated circuit (VLSI) chips.

[0034] An Engineering Change Order (ECO) is usually used for engineering changes after the development of a new product is completed. After the engineering department confirms the necessary changes, it issues a document for joint signature by relevant units to ensure that inventory and work-in-progress are properly handled. Whether it is an immediate change or a change after use, the sales unit, manufacturing unit, and material unit must agree and take necessary actions. Usually, ECO involves a large scope and a long introduction process, requiring rigorous system management.

[0035] Clock tree synthesis (CTS) is to synthesize the clock tree of the design. The main purpose is to allow each clock to be transmitted to all D-type flip-flops (such as DFF) they drive in the shortest possible time.

[0036] Static timing analysis (STA) applies a specific timing model to analyze whether a specific circuit violates the timing constraint given by the designer. In other words, STA uses a complete analysis method to determine whether the integrated circuit (IC) can work properly in the user's timing environment, providing a good solution to the issue of ensuring IC quality. Based on the analysis method, STA can be divided into two types: Path-Based and Block-Based.

[0037] Design for Testability (DFT) is a technique used in chip design to test the chip internally. The purpose of DFT is to consider future testing during design. A common DFT method is to insert scan chains into the design to convert non-scan units (such as registers) into scan units.

[0038] Chip design is undoubtedly an important step in the chip manufacturing process, and chip design can be divided into front-end design and back-end design. The front-end is mainly responsible for logic implementation, usually using languages ​​such as Verilog and VHDL for behavioral description. The back-end is mainly responsible for turning the front-end design into a real schematic and layout, tape-out, and mass production. To put it in a metaphor, the front-end is like making a blueprint, which can be functional and structural. The back-end turns the blueprint into a real high-rise building.

[0039] Among them, the chip back-end design mainly includes the following parts:

[0040] 1. Design for Testability (such as Design For Test, DFT)

[0041] Chips often have built-in test circuits. The purpose of DFT is to consider future tests during the design process. A common DFT method is to insert scan chains into the design to turn non-scan units (such as registers) into scan units.

[0042] 2. Floor Plan

[0043] 3. Clock tree synthesis (CTS)

[0044] Simply put, it is the wiring of the clock. Due to the global command role of the clock signal in the digital chip, its distribution should be symmetrically connected to each register unit, so that when the clock reaches each register from the same clock source, the clock delay difference is minimized. This is why the clock signal needs to be wired separately.

[0045] 4. Wiring (PnR)

[0046] The wiring here is ordinary signal wiring, including the routing between various standard units (basic logic gate circuits). For example, the 0.13um process or 90nm process that we often hear about is actually the minimum width that the metal wiring can achieve here, which is the channel length of the MOS tube from a microscopic perspective.

[0047] 5. Parasitic parameter extraction

[0048] Due to the resistance of the wire itself, the mutual inductance between adjacent wires, and the coupling capacitance, signal noise, crosstalk, and reflection will be generated inside the chip. These effects will cause signal integrity problems, resulting in signal voltage fluctuations and changes, and if serious, will cause signal distortion errors. It is very important to extract parasitic parameters for re-analysis and verification to analyze signal integrity issues.

[0049] 6. Layout physical verification

[0050] The function and timing of the completed physical layout are verified. There are many verification items, such as layout vs schematic (LVS) verification, which is simply the comparison and verification between the layout and the gate-level circuit diagram after logic synthesis; design rule checking (such as Design Rule Checking, DRC), checking whether the connection spacing, connection width, etc. meet the process requirements, electrical rule checking (Electrical Rule Checking, ERC), checking for electrical rule violations such as short circuits and open circuits, etc.

[0051] In the back-end design process of the chip, ECO is a critical path that cannot be ignored. A good ECO process and strategy can speed up the tape-out time. Among them, the conventional ECO process can mainly include the following steps: determine whether there is a timing violation, if so, perform ECO correction, and then continue with the next static timing analysis.

[0052] As the scale of chip design grows, timing closure becomes more and more complex. With the support of powerful EDA tools, most timing problems can be solved automatically. However, when chip design enters the ECO stage, it is inevitable that some timing will not be optimized by the tool. For example, Figure 1 Indicates timing violation Figure 1 ,like Figure 1 As shown, there is a setup time violation on the timing path from FF1 to FF2.

[0053] Currently, for the remaining timing violations in the ECO stage, one optimization method is to continue optimizing the data path (such as Data path). However, for high-performance designs, EDA tools have already optimized the logic cells into the lowest threshold voltage and relatively large standard cells (such as Figure 1 As shown in the figure, if the data path is already a standard unit with the lowest threshold voltage and a relatively large drive, there will be little room for optimization. At this time, it is difficult to obtain a relatively large benefit on the data path, and due to the influence of the winding, the result is counterproductive.

[0054] Another commonly used optimization method is to lengthen or shorten the clock tree (skew clock), but in the ECO stage, not all registers have margin to do skew. Figure 1 There is no margin in the next stage of FF2, so the setup timing problem from FF1 to FF2 cannot be solved by postponing the clock tree of FF2. Although there is a margin in the previous stage of FF1, due to the large fanout after FF1, shortening the clock tree of FF1 may cause changes in the timing of registers in the FF group. Generally speaking, due to the complexity of high-performance design, the connections between registers are intricate and the fanout of registers is large. Modifying the clock tree in the ECO stage may expand the scope of influence and make the timing more unpredictable and uncontrollable. In other words, for the skew clock method, since the fanout of the registers is large and not all the previous and next stages of the registers have margins, there is a problem of too large an impact range and difficulty in control. It may even require re-layout and re-routing or frequency reduction, which seriously affects the progress of the project and chip performance.

[0055] It can be seen that the current common optimization methods for timing violations in the ECO stage do not have ideal timing convergence effects, which reduces chip performance, prolongs the time of chip back-end design, and even leads to serious consequences such as the project cannot be delivered on time.

[0056] In order to solve the above problems, the embodiment of the present application provides a timing optimization circuit and method, a chip and an electronic device, wherein the electronic device includes a chip provided with a timing optimization circuit, and the timing optimization circuit includes: a first register, a second register, a third register, and the third register is a replica register of the first register; the path distance between the first register and the second register is greater than the path distance between the third register and the second register; when the timing report obtained by executing the timing analysis command indicates that there is a timing violation in the first timing path, the second timing path is used for timing optimization processing; the path starting point of the first timing path is the first register, and the path end point is the second register; the path starting point of the second timing path is the third register, and the path end point is the second register. The timing optimization method includes executing the timing analysis command to obtain the timing report; when the timing report indicates that there is a timing violation in the first timing path, the timing optimization processing is performed through the second timing path. That is, in the present application, when a timing path with the first register as the path starting point is optimized, the corresponding new timing path can be constructed by cloning the third register of the first register, and the timing convergence effect can be achieved by utilizing the characteristic that the third register is closer to the second register at the end point of the path. Such a timing optimization method can not only solve the timing problem efficiently and accurately, but also will not interfere with the timing of other registers connected to the back end of the first register, thus reducing the scope of influence. This can greatly improve the timing optimization effect, thereby shortening the chip back-end design time and effectively improving the chip design efficiency and performance.

[0057] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0058] An embodiment of the present application provides a timing optimization circuit, which may include a first register, a second register, and a third register.

[0059] It should be noted that, in the embodiment of the present application, the third register may be a replica register of the first register, that is, the third register may be a register cloned based on the first register.

[0060] In the process of code-to-layout implementation, timing optimization is often one of the key steps. Among them, the timing violation in integrated circuit design is nothing more than insufficient setup time and hold time. Generally, when designing the clock path, it is required that different branches have the same delay.

[0061] It can be understood that the setup time constrains the time from the data at the input to the clock edge, so that the clock edge can sample it. The setup time constrains the maximum delay of the data path relative to the clock edge. The hold time is the time that the data must be kept after being sampled by the clock edge. The hold time constrains the minimum delay in the data path.

[0062] Accordingly, when performing timing optimization processing, it is often necessary to ensure that the setup time and / or hold time are sufficient. Therefore, in an embodiment of the present application, it is possible to choose to increase the delay by shortening the timing path, wherein the path distance between the first register and the second register in the timing optimization circuit can be set to be greater than the path distance between the third register and the second register.

[0063] That is to say, in an embodiment of the present application, the physical distance (path distance) between the third register and the second register may be smaller than the physical distance (path distance) between the first register and the second register, so that when there is a timing violation in the timing path from the first register to the second register, the timing convergence can be performed through the timing path from the third register to the second register.

[0064] For example, in the embodiments of the present application, Figure 2 An indication of the physical distance of the registers Figure 1 , Figure 3 An indication of the physical distance of the registers Figure 2 ,like Figure 2 and Figure 3 As shown, the physical distance (path distance) between the first register and the second register is d12, and the physical distance (path distance) between the third register and the second register is d32, wherein d32 is smaller than d12.

[0065] It can be understood that in an embodiment of the present application, compared with the first register, the cloned register (third register) corresponding to the first register in the timing optimization circuit can be arranged at a physical position closer to the second register, thereby ensuring that the path distance between the third register and the second register is smaller than the path distance between the first register and the second register.

[0066] Further, in an embodiment of the present application, when the timing report obtained by executing the timing analysis command indicates that there is a timing violation in the first timing path, the second timing path is used to perform timing optimization processing; wherein, the starting point of the first timing path is the first register, and the end point of the path is the second register; the starting point of the second timing path is the third register, and the end point of the path is the second register.

[0067] It should be noted that, in an embodiment of the present application, the timing path with the first register as the starting point and the second register as the end point is the first timing path, and the timing path with the third register as the starting point and the second register as the end point is the second timing path. After executing the timing analysis command to obtain the timing report, if the timing report indicates that there is a timing violation in the first timing path, then you can choose to use the second timing path for timing optimization processing to resolve the timing violation of the first timing path.

[0068] Furthermore, in an embodiment of the present application, since the third register is a replica register of the first register, in order to ensure consistency during the timing optimization circuit, it is necessary to ensure that the output port of the third register is connected to the input port of the second register, and at the same time, it is also necessary to ensure that all input ports of the third register are connected to all input ports of the first register.

[0069] It can be understood that in the embodiments of the present application, Figure 4 Indicates timing violation Figure 2 , Figure 5 Schematic diagram of a circuit optimized for timing Figure 1 ,like Figure 4 and 5 As shown, compared with the original timing path with timing violations, the timing optimization circuit disconnects the input port (such as the D port) of the second register and the output port (such as the Q port) of the first register. Compared with the first register, the cloned third register is placed in a physical position closer to the second register. At the same time, all input ports (such as the D port, the CP port, the E port, and the TE port) of the third register can be connected to the ports with the same name corresponding to the first register. Furthermore, it is necessary to connect the input port (such as the D port) of the second register and the output port (such as the Q port) of the third register, thereby completing the establishment of the second timing path for timing optimization processing.

[0070] Furthermore, in an embodiment of the present application, the timing optimization circuit may further include a clock buffer corresponding to the first register, wherein the clock buffer may be a clock buffer equivalent to the first register and in the same clock domain.

[0071] Correspondingly, in an embodiment of the present application, the clock port of the third register in the timing optimization circuit can also be connected to the back end of the clock buffer corresponding to the first register, that is, the clock port (CP port) of the third register can be connected to the back end of an equivalent clock buffer in the same clock domain.

[0072] Furthermore, in an embodiment of the present application, the timing optimization circuit may further include a register cluster, wherein input ports of the register cluster are all connected to output ports of the first register.

[0073] It should be noted that, in an embodiment of the present application, the back end of the first register in the timing optimization circuit may also be connected to multiple registers, that is, the back end of the first register is connected to a register cluster, and the fanout is large. At this time, even if there is a timing violation in the timing path between the first register and the second register, the timing optimization circuit proposed in the present application uses the cloned third register to construct a second timing path for converging the timing violation (that is, the timing path between the third register and the second register), which can accurately complete the timing convergence without affecting other registers in the register cluster at the back end of the first register, reducing the scope of influence, and not causing other timing problems.

[0074] It can be understood that, in the embodiments of the present application, a prerequisite for achieving timing closure by the timing optimization circuit may include the existence of a timing margin in the previous stage of the first register.

[0075] Accordingly, in an embodiment of the present application, the prerequisite for achieving timing closure by the timing optimization circuit may also include that there is no timing margin in the next stage of the second register. However, the present application does not impose strict restrictions on whether there is a timing margin in the next stage of the second register, that is, even if there is a timing margin in the next stage of the second register, the timing optimization circuit may be used to achieve timing closure.

[0076] Figure 6 Schematic diagram of the structure of the timing optimization circuit Figure 1 ,like Figure 6 As shown, the timing optimization circuit 10 may include: a first register 11, a second register 12, and a third register 13, wherein the third register 13 is a replica register of the first register 11; and the path distance between the first register 11 and the second register 12 is greater than the path distance between the third register 13 and the second register 12.

[0077] It should be noted that, in the embodiment of the present application, the third register 13 may be a replica register of the first register 11 , that is, the third register 13 may be a register cloned based on the first register 11 .

[0078] It can be understood that in an embodiment of the present application, the delay can be increased by shortening the timing path, wherein the path distance between the first register 11 and the second register 12 in the timing optimization circuit 10 can be set to be greater than the path distance between the third register 13 and the second register 12.

[0079] That is to say, in an embodiment of the present application, the physical distance (path distance) between the third register 13 and the second register 12 may be smaller than the physical distance (path distance) between the first register 11 and the second register 12, so that when there is a timing violation in the timing path from the first register 11 to the second register 12, the timing convergence can be performed through the timing path from the third register 13 to the second register 12.

[0080] It can be understood that in the embodiments of the present application, compared with the first register 11, the cloned register (third register 13) corresponding to the first register 11 in the timing optimization circuit can be arranged at a physical position closer to the second register 12, thereby ensuring that the path distance between the third register 13 and the second register 12 is smaller than the path distance between the first register 11 and the second register 12.

[0081] Further, in an embodiment of the present application, when the timing report obtained by executing the timing analysis command indicates that there is a timing violation in the first timing path, the second timing path is used to perform timing optimization processing; wherein, the starting point of the first timing path is the first register 11, and the end point of the path is the second register 12; the starting point of the second timing path is the third register 13, and the end point of the path is the second register 12.

[0082] It should be noted that, in an embodiment of the present application, the timing path with the first register 11 as the starting point and the second register 12 as the end point is the first timing path, and the timing path with the third register 13 as the starting point and the second register 12 as the end point is the second timing path. After executing the timing analysis command to obtain the timing report, if the timing report indicates that there is a timing violation in the first timing path, then you can choose to use the second timing path for timing optimization processing to resolve the timing violation of the first timing path.

[0083] Furthermore, in an embodiment of the present application, since the third register 13 is a replica register of the first register 11, in order to ensure consistency during the timing optimization circuit, it is necessary to ensure that the output port of the third register 13 is connected to the input port of the second register 12, and at the same time, it is also necessary to ensure that all input ports of the third register 13 are correspondingly connected to all input ports of the first register 11.

[0084] It can be understood that in the embodiments of the present application, compared with the original circuit with the timing path having a timing violation, the timing optimization circuit disconnects the input port (such as the D port) of the second register and the output port (such as the Q port) of the first register. Compared with the first register, the cloned third register is placed at a physical position closer to the second register. At the same time, all the input ports (such as the D port, the CP port, the E port, and the TE port) of the third register can be connected to the ports with the same name corresponding to the first register. Furthermore, it is necessary to connect the input port (such as the D port) of the second register and the output port (such as the Q port) of the third register, thereby completing the establishment of the second timing path for timing optimization processing.

[0085] Furthermore, in the embodiments of the present application, Figure 7 Schematic diagram of the structure of the timing optimization circuit Figure 2 ,like Figure 7 As shown, the timing optimization circuit 10 may further include a clock buffer 14 corresponding to the first register 11. The clock buffer 14 may be a clock buffer equivalent to the first register 11 and in the same clock domain.

[0086] Correspondingly, in an embodiment of the present application, the clock port of the third register 13 in the timing optimization circuit 10 can also be connected to the back end of the clock buffer 14 corresponding to the first register 11, that is, the clock port (CP port) of the third register can be connected to the back end of an equivalent clock buffer in the same clock domain.

[0087] Furthermore, in the embodiments of the present application, Figure 8 Schematic diagram of the structure of the timing optimization circuit Figure 3 ,like Figure 8 As shown, the timing optimization circuit 10 may further include a register cluster 15 , wherein input ports of the register cluster 15 are all connected to output ports of the first register 11 .

[0088] It should be noted that, in an embodiment of the present application, the back end of the first register in the timing optimization circuit may also be connected to multiple registers, that is, the back end of the first register is connected to a register cluster, and the fanout is large. At this time, even if there is a timing violation in the timing path between the first register and the second register, the timing optimization circuit proposed in the present application uses the cloned third register to construct a second timing path for converging the timing violation (that is, the timing path between the third register and the second register), which can accurately complete the timing convergence without affecting other registers in the register cluster at the back end of the first register, reducing the scope of influence, and not causing other timing problems.

[0089] It can be understood that, in the embodiments of the present application, a prerequisite for achieving timing closure by the timing optimization circuit may include the existence of a timing margin in the previous stage of the first register.

[0090] Accordingly, in an embodiment of the present application, the prerequisite for achieving timing closure by the timing optimization circuit may also include that there is no timing margin in the next stage of the second register. However, the present application does not impose strict restrictions on whether there is a timing margin in the next stage of the second register, that is, even if there is a timing margin in the next stage of the second register, the timing optimization circuit may be used to achieve timing closure.

[0091] In summary, the timing optimization circuit proposed in the embodiment of the present application can make full use of the timing margin of the previous level of the first register, and converge the timing violation problem from the first register to the second register by cloning the third register of the first register. During this timing optimization process, the timing of the register cluster behind the first register will not be affected. It can be seen that the timing optimization circuit proposed in the embodiment of the present application can be used to perform timing optimization processing, so that the timing paths with violations can be separated from the intricate timing network, and each one can be defeated, thereby minimizing the impact on the timing of the entire chip.

[0092] Fig. 9 Indicates timing violation Figure 3 , Fig.10 Schematic diagram of a circuit optimized for timing Figure 2 ,like Fig. 9 and 10As shown, there is a timing margin in the previous stage of FF1 (the first register), but there is no timing margin in the next stage of FF2 (the second register). If there is a violation in the timing path formed by FF1 to FF2, you can choose to disconnect the input port (such as D port) of FF2 to be connected, clone FF1' (the third register), put FF1' in a physical position close to FF2, and connect all the input ports of FF1' (such as D port, CP port, E port, TE port) to the corresponding ports of the same name of FF1. At this time, the clock port (CP port) of FF1' can also be connected to the back end of the equivalent clock buffer in the same clock domain. Finally, connect the output port (such as Q port) of FF1' to the input port (such as D port) of FF2, and then use the margin of the previous stage of FF1 to optimize the timing violation of the timing path formed by FF1 to FF2, and solve the timing problem of this group of registers. At this time, the timing from FF1 to FF group (register cluster) has not been changed, and the impact range has been minimized. It can be seen that without affecting the FF group timing, the margin of the previous level of FF1 is fully utilized, and the timing violation problem from FF1 to FF2 is converged by cloning the FF1 register (FF1'). The timing optimization processing implemented based on the timing optimization circuit is not only simple to operate and easy to implement, but also has a small impact range and will not cause other timing problems. It can effectively solve individual difficult timing problems and can effectively reduce the risk of wafer delay, thereby providing a solution for the timing convergence in the ECO stage.

[0093] The embodiment of the present application provides a timing optimization circuit, which includes: a first register, a second register, and a third register, and the third register is a replica register of the first register; the path distance between the first register and the second register is greater than the path distance between the third register and the second register; when the timing report obtained by executing the timing analysis command indicates that there is a timing violation in the first timing path, the second timing path is used for timing optimization processing; the path starting point of the first timing path is the first register, and the path end point is the second register; the path starting point of the second timing path is the third register, and the path end point is the second register. That is to say, in the present application, when a timing path with the first register as the path starting point is optimized, a corresponding new timing path can be constructed by cloning the third register of the first register, and the timing convergence effect can be achieved by using the characteristic that the third register is closer to the second register at the end of the path. Such a timing optimization method can not only solve the timing problem efficiently and accurately, but also will not interfere with the timing of other registers connected to the back end of the first register, reducing the scope of influence, thereby greatly improving the timing optimization effect, thereby shortening the time of chip back-end design, and effectively improving the design efficiency and performance of the chip.

[0094] An embodiment of the present application provides a timing optimization method, which is applied to a timing optimization circuit, wherein the timing optimization circuit may include a first register, a second register, and a third register.

[0095] It should be noted that, in the embodiment of the present application, the third register may be a replica register of the first register, that is, the third register may be a register cloned based on the first register.

[0096] Furthermore, in an embodiment of the present application, the delay can be increased by shortening the timing path, wherein the path distance between the first register and the second register in the timing optimization circuit can be set to be greater than the path distance between the third register and the second register.

[0097] That is to say, in an embodiment of the present application, the physical distance (path distance) between the third register and the second register may be smaller than the physical distance (path distance) between the first register and the second register, so that when there is a timing violation in the timing path from the first register to the second register, the timing convergence can be performed through the timing path from the third register to the second register.

[0098] It can be understood that in an embodiment of the present application, compared with the first register, the cloned register (third register) corresponding to the first register in the timing optimization circuit can be arranged at a physical position closer to the second register, thereby ensuring that the path distance between the third register and the second register is smaller than the path distance between the first register and the second register.

[0099] Fig.11 Schematic diagram of the implementation process of the timing optimization method Figure 1 ,like Fig.11 As shown, in an embodiment of the present application, the timing optimization method may include the following steps:

[0100] Step 101: Execute a timing analysis command to obtain a timing report.

[0101] In an embodiment of the present application, a timing analysis command may be executed first, and then a timing report may be obtained.

[0102] It is understandable that after the front-end design has been completed, when performing the back-end design of the chip, the library files and design data can be imported first. Among them, importing the library files and design data can also be understood as the beginning of the back-end design process of the chip. Among them, the required data can be imported first when performing the back-end design. Specifically, these data may include library files and design data, wherein the library files may be library files of standard cells, macro cells and I / O Pads provided by the chip foundry (Foundry), which include physical libraries, timing libraries and netlist libraries, which are given in the form of .lef, .tlf and .v respectively. The design data may be a gate-level netlist generated after the chip front-end design is synthesized, a script file with timing constraints and clock definitions, and a .gcf constraint file generated thereby.

[0103] It should be noted that, in an embodiment of the present application, based on the library file and the design data, the specific process of the STA tool executing the timing analysis command may include: first, executing the insertion command based on the library file and the design data to insert the gap; then, the extraction command may be executed to extract the parasitic parameters; finally, the STA tool executes the timing analysis command, performs static analysis on the parasitic parameters, and then a timing report may be generated.

[0104] It is understandable that in the embodiment of the present application, the timing report can be used to determine the timing violation of the chip. Among them, the timing report can obtain the specific conditions such as the path starting point, path end point and the clock path branch to which the timing violation corresponds.

[0105] Furthermore, in an embodiment of the present application, the timing report may also be used to indicate whether there is a timing violation in a first timing path from a first register to a second register.

[0106] Step 102: When the timing report indicates that there is a timing violation in the first timing path, timing optimization processing is performed through the second timing path; wherein the path starting point of the first timing path is the first register, and the path end point is the second register; the path starting point of the second timing path is the third register, and the path end point is the second register.

[0107] In an embodiment of the present application, after executing a timing analysis command and obtaining a timing report, if the timing report indicates that a first timing path has a timing violation, timing optimization processing needs to be performed through a second timing path.

[0108] It should be noted that, in an embodiment of the present application, the timing path with the first register as the starting point and the second register as the end point is the first timing path, and the timing path with the third register as the starting point and the second register as the end point is the second timing path. After executing the timing analysis command to obtain the timing report, if the timing report indicates that there is a timing violation in the first timing path, then you can choose to use the second timing path for timing optimization processing to resolve the timing violation of the first timing path.

[0109] Furthermore, in an embodiment of the present application, since the third register is a replica register of the first register, in order to ensure consistency during the timing optimization circuit, it is necessary to ensure that the output port of the third register is connected to the input port of the second register, and at the same time, it is also necessary to ensure that all input ports of the third register are connected to all input ports of the first register.

[0110] It can be understood that in the embodiments of the present application, compared with the original circuit with the timing path having timing violations, the timing optimization circuit disconnects the input port (such as the D port) of the second register and the output port (such as the Q port) of the first register. Compared with the first register, the cloned third register is placed at a physical position closer to the second register. At the same time, all the input ports (such as the D port, the CP port, the E port, and the TE port) of the third register can be connected to the ports with the same name corresponding to the first register. Furthermore, it is necessary to connect the input port (such as the D port) of the second register to the output port (such as the Q port) of the third register, thereby completing the establishment of the second timing path for timing optimization processing.

[0111] Furthermore, in an embodiment of the present application, the timing optimization circuit may further include a clock buffer corresponding to the first register, wherein the clock buffer may be a clock buffer equivalent to the first register and in the same clock domain.

[0112] Correspondingly, in an embodiment of the present application, the clock port of the third register in the timing optimization circuit can also be connected to the back end of the clock buffer corresponding to the first register, that is, the clock port (CP port) of the third register can be connected to the back end of an equivalent clock buffer in the same clock domain.

[0113] Furthermore, in an embodiment of the present application, the timing optimization circuit may further include a register cluster, wherein input ports of the register cluster are all connected to output ports of the first register.

[0114] It should be noted that, in an embodiment of the present application, the back end of the first register in the timing optimization circuit may also be connected to multiple registers, that is, the back end of the first register is connected to a register cluster, and the fanout is large. At this time, even if there is a timing violation in the timing path between the first register and the second register, the timing optimization circuit proposed in the present application uses the cloned third register to construct a second timing path for converging the timing violation (that is, the timing path between the third register and the second register), which can accurately complete the timing convergence without affecting other registers in the register cluster at the back end of the first register, reducing the scope of influence, and not causing other timing problems.

[0115] Fig.12 Schematic diagram of the implementation process of the timing optimization method Figure 2 ,like Fig.12 As shown, in an embodiment of the present application, after executing the timing analysis command and obtaining the timing report, that is, after step 101, the timing optimization method may specifically include the following steps:

[0116] Step 102a, when the timing report indicates that there is a timing violation in the first timing path and there is a timing margin in the previous stage of the first register, timing optimization processing is performed through the second timing path; wherein the starting point of the first timing path is the first register and the end point of the path is the second register; the starting point of the second timing path is the third register and the end point of the path is the second register.

[0117] In an embodiment of the present application, after executing the timing analysis command and obtaining the timing report, if the timing report indicates that there is a timing violation in the first timing path and there is a timing margin in the previous level of the first register, then timing optimization processing needs to be performed through the second timing path.

[0118] It can be understood that, in the embodiments of the present application, a prerequisite for achieving timing closure by the timing optimization circuit may include the existence of a timing margin in the previous stage of the first register.

[0119] Fig.13 Schematic diagram of the implementation process of the timing optimization method Figure 3 ,like Fig.13 As shown, in an embodiment of the present application, after executing the timing analysis command and obtaining the timing report, that is, after step 101, the timing optimization method may specifically include the following steps:

[0120] Step 102b, when the timing report indicates that there is a timing violation in the first timing path, there is a timing margin in the previous level of the first register, and there is no timing margin in the subsequent level of the second register, timing optimization processing is performed through the second timing path; wherein the starting point of the first timing path is the first register, and the end point of the path is the second register; the starting point of the second timing path is the third register, and the end point of the path is the second register.

[0121] In an embodiment of the present application, after executing the timing analysis command and obtaining the timing report, if the timing report indicates that there is a timing violation in the first timing path, and there is a timing margin in the previous level of the first register, and there is no timing margin in the next level of the second register, then timing optimization processing is required through the second timing path.

[0122] That is, in the embodiment of the present application, in addition to requiring the existence of a timing margin in the previous stage of the first register, the prerequisite for achieving timing convergence by the timing optimization circuit may also include the absence of a timing margin in the subsequent stage of the second register. However, the present application does not impose strict restrictions on whether there is a timing margin in the subsequent stage of the second register, that is, even if there is a timing margin in the subsequent stage of the second register, the timing optimization circuit can be used to achieve timing convergence.

[0123] In summary, through the timing optimization method proposed in the above steps 101 to 102, the timing margin of the previous level of the first register can be fully utilized, and the timing violation problem from the first register to the second register can be converged by cloning the third register of the first register. During this timing optimization process, the timing of the register cluster behind the first register will not be affected. It can be seen that the timing optimization circuit proposed in the embodiment of the present application is used for timing optimization processing, which can separate the timing paths with violations from the complex timing network, and achieve one by one, thereby minimizing the impact on the timing of the entire chip.

[0124] The embodiment of the present application provides a timing optimization method, which is applied to a timing optimization circuit, and the timing optimization circuit includes: a first register, a second register, and a third register, and the third register is a replica register of the first register; the path distance between the first register and the second register is greater than the path distance between the third register and the second register; when the timing report obtained by executing the timing analysis command indicates that there is a timing violation in the first timing path, the second timing path is used for timing optimization processing; the path starting point of the first timing path is the first register, and the path end point is the second register; the path starting point of the second timing path is the third register, and the path end point is the second register. The timing optimization method includes executing the timing analysis command to obtain the timing report; when the timing report indicates that there is a timing violation in the first timing path, the timing optimization processing is performed through the second timing path. That is to say, in the present application, when a timing path with the first register as the path starting point is optimized, the corresponding new timing path can be constructed by cloning the third register of the first register, and the timing convergence effect is achieved by utilizing the characteristic that the third register is closer to the second register at the end point of the path. Such a timing optimization method can not only solve the timing problem efficiently and accurately, but also will not interfere with the timing of other registers connected to the back end of the first register, thus reducing the scope of influence. This can greatly improve the timing optimization effect, thereby shortening the chip back-end design time and effectively improving the chip design efficiency and performance.

[0125] Based on the above embodiments, another embodiment of the present application provides a chip, Fig.14 Schematic diagram of the chip structure Figure 1 ,like Fig.14 As shown, the chip 20 may include a timing optimization circuit 10, wherein the timing optimization circuit 10 may include: a first register 11, a second register 12, and a third register 13, wherein the third register 13 is a replica register of the first register 11; and the path distance between the first register 11 and the second register 12 is greater than the path distance between the third register 13 and the second register 12.

[0126] It should be noted that, in the embodiment of the present application, the third register 13 may be a replica register of the first register 11 , that is, the third register 13 may be a register cloned based on the first register 11 .

[0127] It can be understood that in an embodiment of the present application, the delay can be increased by shortening the timing path, wherein the path distance between the first register 11 and the second register 12 in the timing optimization circuit 10 can be set to be greater than the path distance between the third register 13 and the second register 12.

[0128] That is to say, in an embodiment of the present application, the physical distance (path distance) between the third register 13 and the second register 12 may be smaller than the physical distance (path distance) between the first register 11 and the second register 12, so that when there is a timing violation in the timing path from the first register 11 to the second register 12, the timing convergence can be performed through the timing path from the third register 13 to the second register 12.

[0129] It can be understood that in the embodiments of the present application, compared with the first register 11, the cloned register (third register 13) corresponding to the first register 11 in the timing optimization circuit can be arranged at a physical position closer to the second register 12, thereby ensuring that the path distance between the third register 13 and the second register 12 is smaller than the path distance between the first register 11 and the second register 12.

[0130] Further, in an embodiment of the present application, when the timing report obtained by executing the timing analysis command indicates that there is a timing violation in the first timing path, the second timing path is used to perform timing optimization processing; wherein, the starting point of the first timing path is the first register 11, and the end point of the path is the second register 12; the starting point of the second timing path is the third register 13, and the end point of the path is the second register 12.

[0131] It should be noted that, in an embodiment of the present application, the timing path with the first register 11 as the starting point and the second register 12 as the end point is the first timing path, and the timing path with the third register 13 as the starting point and the second register 12 as the end point is the second timing path. After executing the timing analysis command to obtain the timing report, if the timing report indicates that there is a timing violation in the first timing path, then you can choose to use the second timing path for timing optimization processing to resolve the timing violation of the first timing path.

[0132] Furthermore, in an embodiment of the present application, since the third register 13 is a replica register of the first register 11, in order to ensure consistency during the timing optimization circuit, it is necessary to ensure that the output port of the third register 13 is connected to the input port of the second register 12, and at the same time, it is also necessary to ensure that all input ports of the third register 13 are correspondingly connected to all input ports of the first register 11.

[0133] It can be understood that in the embodiments of the present application, compared with the original circuit with the timing path having a timing violation, the timing optimization circuit disconnects the input port (such as the D port) of the second register and the output port (such as the Q port) of the first register. Compared with the first register, the cloned third register is placed at a physical position closer to the second register. At the same time, all the input ports (such as the D port, the CP port, the E port, and the TE port) of the third register can be connected to the ports with the same name corresponding to the first register. Furthermore, it is necessary to connect the input port (such as the D port) of the second register and the output port (such as the Q port) of the third register, thereby completing the establishment of the second timing path for timing optimization processing.

[0134] Furthermore, in the embodiments of the present application, Fig.15 Schematic diagram of the chip structure Figure 2 ,like Fig.15 As shown, the timing optimization circuit 10 may further include a clock buffer 14 corresponding to the first register 11. The clock buffer 14 may be a clock buffer equivalent to the first register 11 and in the same clock domain.

[0135] Correspondingly, in an embodiment of the present application, the clock port of the third register 13 in the timing optimization circuit 10 can also be connected to the back end of the clock buffer 14 corresponding to the first register 11, that is, the clock port (CP port) of the third register can be connected to the back end of an equivalent clock buffer in the same clock domain.

[0136] Further, in the embodiments of the present application, Fig.15 As shown, the timing optimization circuit 10 may further include a register cluster 15 , wherein input ports of the register cluster 15 are all connected to output ports of the first register 11 .

[0137] It should be noted that, in an embodiment of the present application, the back end of the first register in the timing optimization circuit may also be connected to multiple registers, that is, the back end of the first register is connected to a register cluster, and the fanout is large. At this time, even if there is a timing violation in the timing path between the first register and the second register, the timing optimization circuit proposed in the present application uses the cloned third register to construct a second timing path for converging the timing violation (that is, the timing path between the third register and the second register), which can accurately complete the timing convergence without affecting other registers in the register cluster at the back end of the first register, reducing the scope of influence, and not causing other timing problems.

[0138] It can be understood that, in the embodiments of the present application, a prerequisite for achieving timing closure by the timing optimization circuit may include the existence of a timing margin in the previous stage of the first register.

[0139] Accordingly, in an embodiment of the present application, the prerequisite for achieving timing closure by the timing optimization circuit may also include that there is no timing margin in the next stage of the second register. However, the present application does not impose strict restrictions on whether there is a timing margin in the next stage of the second register, that is, even if there is a timing margin in the next stage of the second register, the timing optimization circuit may be used to achieve timing closure.

[0140] In summary, the chip provided with a timing optimization circuit proposed in the embodiment of the present application can make full use of the timing margin of the previous level of the first register, and converge the timing violation problem from the first register to the second register by cloning the third register of the first register, and during this timing optimization process, it will not affect the timing of the register cluster behind the first register. It can be seen that the timing optimization circuit proposed in the embodiment of the present application is used for timing optimization processing, which can separate the timing paths with violations from the intricate timing network, and achieve one by one, thereby minimizing the impact on the timing of the entire chip.

[0141] The embodiment of the present application provides a chip, the chip is provided with a timing optimization circuit, the timing optimization circuit includes: a first register, a second register, a third register, the third register is a replica register of the first register; the path distance between the first register and the second register is greater than the path distance between the third register and the second register; when the timing report obtained by executing the timing analysis command indicates that there is a timing violation in the first timing path, the second timing path is used for timing optimization processing; the path starting point of the first timing path is the first register, and the path end point is the second register; the path starting point of the second timing path is the third register, and the path end point is the second register. That is to say, in the present application, when a timing path with the first register as the path starting point is optimized, a corresponding new timing path can be constructed by cloning the third register of the first register, and the timing convergence effect can be achieved by using the characteristic that the third register is closer to the second register at the end of the path. Such a timing optimization method can not only solve the timing problem efficiently and accurately, but also will not interfere with the timing of other registers connected to the back end of the first register, reducing the scope of influence, thereby greatly improving the timing optimization effect, thereby shortening the time of chip back-end design, and effectively improving the design efficiency and performance of the chip.

[0142] Based on the above embodiment, another embodiment of the present application provides an electronic device, Fig.16 Schematic diagram of the structure of electronic equipment Figure 1 ,like Fig.16 As shown, the electronic device 30 may include a chip 20, in which a timing optimization circuit 10 is configured, wherein the timing optimization circuit 10 may include: a first register 11, a second register 12, and a third register 13, wherein the third register 13 is a replica register of the first register 11; and the path distance between the first register 11 and the second register 12 is greater than the path distance between the third register 13 and the second register 12.

[0143] It can be understood that in the embodiments of the present application, the electronic device 30 can be various electronic devices with communication functions, including but not limited to mobile electronic devices such as mobile phones, laptop computers, digital broadcast receivers, personal digital assistants (PDA), tablet computers (PAD), portable multimedia players (PMP), vehicle-mounted electronic devices (such as vehicle-mounted navigation electronic devices), etc., as well as fixed electronic devices such as digital televisions (TV), desktop computers, etc.

[0144] It should be noted that, in the embodiment of the present application, the third register 13 may be a replica register of the first register 11 , that is, the third register 13 may be a register cloned based on the first register 11 .

[0145] It can be understood that in an embodiment of the present application, the delay can be increased by shortening the timing path, wherein the path distance between the first register 11 and the second register 12 in the timing optimization circuit 10 can be set to be greater than the path distance between the third register 13 and the second register 12.

[0146] It can be understood that in the embodiments of the present application, compared with the first register 11, the cloned register (third register 13) corresponding to the first register 11 in the timing optimization circuit can be arranged at a physical position closer to the second register 12, thereby ensuring that the path distance between the third register 13 and the second register 12 is smaller than the path distance between the first register 11 and the second register 12.

[0147] It should be noted that, in an embodiment of the present application, the timing path with the first register 11 as the starting point and the second register 12 as the end point is the first timing path, and the timing path with the third register 13 as the starting point and the second register 12 as the end point is the second timing path. After executing the timing analysis command to obtain the timing report, if the timing report indicates that there is a timing violation in the first timing path, then you can choose to use the second timing path for timing optimization processing to resolve the timing violation of the first timing path.

[0148] Furthermore, in an embodiment of the present application, since the third register 13 is a replica register of the first register 11, in order to ensure consistency during the timing optimization circuit, it is necessary to ensure that the output port of the third register 13 is connected to the input port of the second register 12, and at the same time, it is also necessary to ensure that all input ports of the third register 13 are correspondingly connected to all input ports of the first register 11.

[0149] Furthermore, in the embodiments of the present application, Fig.17 Schematic diagram of the structure of electronic equipment Figure 2 ,like Fig.17 As shown, the timing optimization circuit 10 may further include a clock buffer 14 corresponding to the first register 11. The clock buffer 14 may be a clock buffer equivalent to the first register 11 and in the same clock domain.

[0150] Correspondingly, in an embodiment of the present application, the clock port of the third register 13 in the timing optimization circuit 10 can also be connected to the back end of the clock buffer 14 corresponding to the first register 11, that is, the clock port (CP port) of the third register can be connected to the back end of an equivalent clock buffer in the same clock domain.

[0151] Further, in the embodiments of the present application, Fig.17 As shown, the timing optimization circuit 10 may further include a register cluster 15 , wherein input ports of the register cluster 15 are all connected to output ports of the first register 11 .

[0152] It should be noted that, in an embodiment of the present application, the back end of the first register in the timing optimization circuit may also be connected to multiple registers, that is, the back end of the first register is connected to a register cluster, and the fanout is large. At this time, even if there is a timing violation in the timing path between the first register and the second register, the timing optimization circuit proposed in the present application uses the cloned third register to construct a second timing path for converging the timing violation (that is, the timing path between the third register and the second register), which can accurately complete the timing convergence without affecting other registers in the register cluster at the back end of the first register, reducing the scope of influence, and not causing other timing problems.

[0153] It can be understood that, in the embodiments of the present application, a prerequisite for achieving timing closure by the timing optimization circuit may include the existence of a timing margin in the previous stage of the first register.

[0154] Accordingly, in an embodiment of the present application, the prerequisite for achieving timing closure by the timing optimization circuit may also include that there is no timing margin in the next stage of the second register. However, the present application does not impose strict restrictions on whether there is a timing margin in the next stage of the second register, that is, even if there is a timing margin in the next stage of the second register, the timing optimization circuit may be used to achieve timing closure.

[0155] In summary, the electronic device including a chip provided with a timing optimization circuit proposed in the embodiment of the present application can make full use of the timing margin of the previous level of the first register, and converge the timing violation problem from the first register to the second register by cloning the third register of the first register, and in this timing optimization process, it will not affect the timing of the register cluster behind the first register. It can be seen that the timing optimization process using the timing optimization circuit proposed in the embodiment of the present application can separate the timing paths with violations from the intricate timing network, and achieve the goal of defeating them one by one, thereby minimizing the impact on the timing of the entire chip.

[0156] An embodiment of the present application provides an electronic device, which includes a chip provided with a timing optimization circuit, and the timing optimization circuit includes: a first register, a second register, and a third register, wherein the third register is a replica register of the first register; the path distance between the first register and the second register is greater than the path distance between the third register and the second register; when the timing report obtained by executing the timing analysis command indicates that there is a timing violation in the first timing path, the second timing path is used for timing optimization processing; the path starting point of the first timing path is the first register, and the path end point is the second register; the path starting point of the second timing path is the third register, and the path end point is the second register. That is to say, in the present application, when performing timing optimization on a timing path with the first register as the path starting point, a corresponding new timing path can be constructed by cloning the third register of the first register, and the timing convergence effect can be achieved by utilizing the characteristic that the third register is closer to the second register at the end point of the path. Such a timing optimization method can not only solve the timing problem efficiently and accurately, but also will not interfere with the timing of other registers connected to the back end of the first register, thus reducing the scope of influence. This can greatly improve the timing optimization effect, thereby shortening the chip back-end design time and effectively improving the chip design efficiency and performance.

[0157] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of hardware embodiments, software embodiments, or embodiments in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) that contain computer-usable program code.

[0158] The present application is described with reference to implementation flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the process in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0159] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which is implemented in the implementation flow diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0160] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for executing the steps in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0161] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application.

Claims

1. A timing optimization circuit, characterized in that: The timing optimization circuit includes: a first register, a second register, and a third register, wherein the third register is a replica register of the first register; a path distance between the first register and the second register is greater than a path distance between the third register and the second register; an output port of the third register is connected to an input port of the second register; and all input ports of the third register are correspondingly connected to all input ports of the first register; When the timing report obtained by executing the timing analysis command indicates that there is a timing violation in the first timing path, the second timing path is used for timing optimization processing; wherein the path starting point of the first timing path is the first register, and the path end point is the second register; the path starting point of the second timing path is the third register, and the path end point is the second register.

2. The timing optimization circuit according to claim 1, characterized in that: The timing optimization circuit also includes a clock buffer corresponding to the first register, wherein: The clock port of the third register is connected to the back end of the clock buffer.

3. The timing optimization circuit according to claim 1, characterized in that: There is a timing margin in the previous stage of the first register.

4. The timing optimization circuit according to claim 3, characterized in that: There is no timing margin in the subsequent stage of the second register.

5. The timing optimization circuit according to claim 1, characterized in that: The timing optimization circuit also includes a register cluster, wherein: The input ports of the register cluster are all connected to the output ports of the first register.

6. A timing optimization method, characterized in that: The timing optimization method is applied to a timing optimization circuit, the timing optimization circuit comprising: a first register, a second register, and a third register, wherein the third register is a replica register of the first register; the path distance between the first register and the second register is greater than the path distance between the third register and the second register; the output port of the third register is connected to the input port of the second register; all input ports of the third register are correspondingly connected to all input ports of the first register; the method comprises: Execute the timing analysis command to obtain the timing report; When the timing report indicates that there is a timing violation in the first timing path, timing optimization processing is performed through the second timing path; wherein the path starting point of the first timing path is the first register, and the path end point is the second register; the path starting point of the second timing path is the third register, and the path end point is the second register.

7. The timing optimization method according to claim 6, characterized in that: The timing optimization circuit also includes a clock buffer corresponding to the first register, wherein: The clock port of the third register is connected to the back end of the clock buffer.

8. The timing optimization method according to claim 6, characterized in that: There is a timing margin in the previous stage of the first register.

9. The timing optimization method according to claim 8, characterized in that: There is no timing margin in the subsequent stage of the second register.

10. The timing optimization method according to claim 6, characterized in that: The timing optimization circuit also includes a register cluster, wherein: The input ports of the register cluster are all connected to the output ports of the first register.

11. A chip, characterized in that: The chip comprises the timing optimization circuit as claimed in any one of claims 1 to 5.

12. An electronic device, characterized in that: The electronic device comprises the chip according to claim 11.

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