A high-efficiency capacitance extraction method based on machine learning

Abstract

The present invention discloses a high-efficiency capacitance extraction method based on machine learning, which involves using a machine learning model to extract parasitic capacitance to improve the efficiency of parameter extraction; universally representing the interconnect structure through a grid-based data representation; reducing the workload of parameter extraction and enhancing the robustness of the technology for different semiconductor processes with the idea of ​​adaptive extraction window; establishing a capacitance extraction machine learning model for a two-dimensional interconnect structure, extracting grid parameters for the target interconnect structure and inputting them into the machine learning model to obtain parasitic capacitance parameters. Compared with existing capacitance extraction technologies, the capacitance extractor has achieved excellent performance in accuracy, speed, and time and space consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of parasitic capacitance parameter extraction, and in particular to a high-efficiency capacitance extraction method based on machine learning. Background Art

[0002] With the continuous development of semiconductor technology and the continuous increase in circuit scale, the parasitic capacitance between conductor interconnects has an increasingly greater impact on the estimated timing. Especially under advanced processes, interconnects cannot be simulated as simple rectangular metal wires. The accuracy and complexity of the interconnect model have been greatly improved, which has also led to a rapid increase in the difficulty of capacitor parameter extraction. The extraction of parasitic capacitance of interconnects is the basis for important circuit index analysis such as circuit timing analysis, power consumption analysis, signal integrity analysis, and power integrity analysis. Accurate and fast parasitic capacitance extractors are crucial to ensuring chip design quality, meeting stringent power consumption, performance, and area index requirements, and shortening the design cycle. This requires researchers to develop more advanced high-performance solvers to meet current and future chip design needs.

[0003] The parasitic capacitance extractor calculates the parasitic capacitance between interconnects by receiving information such as the layout of the circuit interconnects (including top view and cross-sectional view), interconnect material parameters, and surrounding electromagnetic parameters. The extractor often determines a conductor as the main conductor and calculates the self-capacitance of the main conductor and the coupling capacitance between the main conductor and other conductors. With the development of machine learning technology, it has been applied in parasitic parameter extraction technology with good performance. Among them, the XGBoost machine learning model is flexible, efficient, and lightweight, and shows great potential in specific applications in various fields.

[0004] The existing technology is mainly divided into three steps. First, the capacitance of massive interconnect structures is accurately calculated and the set parameters are extracted to form a pattern library. Then, the geometric parameters of the target interconnect structure that needs to be calculated are extracted. Finally, the geometric parameters of the target structure are matched with the items in the pattern library to calculate the capacitance.

[0005] The main deficiencies of the existing technology are: 1. The establishment of a pattern library faces huge challenges as semiconductor process technology becomes increasingly complex. Advanced process structures such as low-dielectric constant dielectrics, non-vertical interface conductors, and bubble dielectrics lead to a decrease in the accuracy of interconnect modeling and a significant increase in modeling time. 2. The increase in chip scale means that the workload of geometric parameter extraction for the target interconnect structure will increase significantly, which will take up a lot of computing time and space. 3. The existing method may have a pattern mismatch, that is, the target interconnect structure cannot find a matching pattern in the pattern library and can only obtain an approximate solution. The accumulation of these errors will greatly affect the accuracy of parasitic capacitance extraction.

[0006] Based on the above problems, in order to improve the efficiency and versatility of parasitic capacitance extraction technology, a high-efficiency capacitance extraction method based on machine learning is proposed. Summary of the invention

[0007] The purpose of the present invention is to solve the problem of large error and cumbersome process of the existing full-chip extraction method based on pattern matching. Through a new grid-based data representation and the idea of ​​adaptive extraction window, a machine learning method for establishing a neural network capacitance model for a two-dimensional structure in full-chip capacitance extraction is proposed, and a high-efficiency capacitance extractor based on FasterCap and combined with the XGBoost machine learning model is designed. The total capacitance error and coupling capacitance error generated by this method are within a reasonable range, showing excellent performance and more versatility.

[0008] The objective of the present invention is achieved through the following technical solutions:

[0009] A high-efficiency capacitance extraction method based on machine learning, the method comprising:

[0010] Dataset preparation stage: Randomly generate a sufficient number of input samples of different conductor arrangements under different process standards, input them into the FasterCap tool after data preprocessing, and use FasterCap output data as XGBoost labels; at the same time, regard the two-dimensional cross-sectional structure as an image, use adaptive window extraction and gridding methods to represent any arrangement of any number of conductors as a corresponding two-dimensional matrix form, and obtain the input of XGBoost from the randomly generated input samples;

[0011] Training machine learning models: XGBoost input and XGBoost labels are combined into a data set. Two XGBoost machine learning models for self-capacitance and coupling capacitance are trained through a large number of data sets.

[0012] Problem solving: The two-dimensional cross-sectional structure of the chip whose capacitance is to be extracted is used as the input of the capacitance extractor according to the same adaptive window extraction and gridding method. The main conductor self-capacitance and the coupling capacitance between the conductor and the adjacent conductor are obtained at the output end of the capacitance extractor to realize the parasitic capacitance extraction of the entire chip.

[0013] Furthermore, the size of the adaptive window is determined by the coupling capacitance between the ambient conductor and the main conductor being reduced to 1% of the self-capacitance of the main conductor during the simulation experiment.

[0014] Furthermore, a structural model with three metal layers is considered when representing the gridded data, with the main conductor located at the center of the middle layer and the number of conductors in each layer not fixed.

[0015] Furthermore, the grid is evenly divided, and each conductor layer is represented as a vector x according to the density, and the information of the main conductor and the ambient conductor is included in it through the following encoding method:

[0016] If the dominant body covers the ith grid, then x i =d i +1;

[0017] If the ambient conductor covers the ith grid, then let x i =-d i ;

[0018] Among them, d i Represents the density of the extraction window.

[0019] Furthermore, the method of extracting capacitance using XGBoost machine learning is implemented through offline training.

[0020] The beneficial effect of the present invention is that the present invention provides a high-efficiency capacitance extraction method based on machine learning, and the proposed grid representation method based on an adaptive window selects a capacitance extraction window size that matches the characteristic size according to the smallest possible characteristic size, which can effectively represent any arrangement of any number of conductors, and can successfully mark important information such as the main conductor and the corresponding environmental conductor for which mutual capacitance needs to be calculated. The extraction of the adaptive window reduces the number of grids by 3 or 4 orders of magnitude, and the grid vector using the "conductor occupying grid ratio" as an element has a higher information entropy than the pixel representation, which will lead to a simpler machine learning model input and a more feasible machine learning architecture, and then the self-capacitance and mutual capacitance of the whole chip can be quickly and accurately extracted through the machine learning model. This preprocessing method is a standardized process that can batch process multiple inputs in the form of executable scripts, and the processing process is independent of the input content. The time complexity and space complexity of the process with respect to the number of conductors are both O(1), which is very suitable for large-scale, repeated capacitance extraction processes. In addition, the "grid data representation" has strong scalability and adjustability. For different processes, the size and number of grids can be adjusted to be suitable for the capacitance extraction method based on the XGBoost machine learning model proposed by us. Under ultra-large-scale integrated circuits and advanced processes, compared with the traditional full-chip extraction method based on pattern matching, the capacitance extractor based on machine learning proposed in the present invention has high accuracy and speed, can quickly calculate the capacitance parameters of the entire chip with very small errors, occupies less memory and greatly reduces energy consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a flow chart of the present invention;

[0022] Figure 2It is a two-dimensional metal layer structure diagram of the chip of the present invention;

[0023] Figure 3 is an example diagram of the grid representation method proposed by the present invention;

[0024] Figure 4 This is a graph showing the result of capacitance extraction based on machine learning in an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The specific implementation modes of the present invention are further described in detail below with reference to the accompanying drawings.

[0026] like Figure 1-4 As shown, the present invention provides a high-efficiency capacitance extraction method based on machine learning, and the specific implementation steps are:

[0027] 1) Dataset preparation stage

[0028] Randomly generate a sufficient number of input samples of different conductor arrangements under different process standards, and generate a machine learning data set in the following way:

[0029] 1.1) After data preprocessing, the randomly generated samples are input into the FasterCap tool, and the dielectric parameters are reasonably set and FasterCap is calculated. The capacitance matrix obtained can obtain a more accurate capacitance value after certain data processing. The difference between the capacitance value and the test sample data is less than 2%. Therefore, it is considered that the calculation accuracy of FasterCap is acceptable and can be used as a reference tool to generate data set labels for training XGBoost machine learning models.

[0030] 1.2) The two-dimensional cross-sectional structure is regarded as an image. Since the influence of the coupling capacitance between the main conductor and the relatively far conductor can be ignored, the extraction window size is set according to the distance at which the coupling capacitance between the ambient conductor and the main conductor is less than 1% of the self-capacitance of the main conductor.

[0031] like Figure 2 , consider the structural model of three metal layers, the main conductor is located in the center of the middle layer, and the number of conductors in each layer is not fixed. The conductor pattern can be a rectangle or connected rectangles (connected in the vertical direction to approximate the trapezoid under advanced technology). This model can be easily extended to structures with more than three metal layers. The width of the extraction window is evenly divided into L1 grid units, and the height is evenly divided into L2 grid units. Therefore, the distribution of conductors in the extraction window area can be described by an L1×L2 dimensional vector. Then the density of the extraction window is expressed as: Vector element d i The value of is the density, which is the fraction of a grid cell that is occupied by a conductor.

[0032] Assuming that the structure includes n conductors, a self-capacitance and n-1 coupling capacitances need to be extracted, but this grid-based representation cannot identify the main conductor. In order to encode more information about the main conductor and the ambient conductor, the present invention modifies it. If the main conductor covers the i-th grid, then there is x i =d i +1. To calculate the coupling capacitance between the main conductor and the ambient conductor, in addition to adding 1 to the element corresponding to the cell overlapping the main cell, if the ambient conductor covers the i-th grid, let x i =-d i .like Figure 3 As shown, the first line is the density vector d, the second line is the eigenvector used to calculate the self-capacitance of the main conductor, and the third, fourth and fifth lines are the eigenvectors used to calculate the coupling capacitance between the main conductor and the environmental conductor.

[0033] 2) Training machine learning models

[0034] Since the total capacitance and coupling capacitance differ by several orders of magnitude and have different accuracy requirements, in order to ensure the overall accuracy of capacitance extraction, the present invention trains two XGBoost machine learning models of self-capacitance and coupling capacitance respectively through the XGBoost data set composed of the input and labels obtained above.

[0035] XGBoost uses the forward distribution algorithm for greedy learning during training. Each iteration learns a CART tree to fit the residual between the prediction results of the previous t-1 trees and the true value of the training sample. When the training is completed and k trees are obtained, the score of a sample needs to be predicted. It will fall into a corresponding leaf node in each tree according to the characteristics of the sample. Each leaf node corresponds to a score. Finally, you only need to add up the scores corresponding to each tree to get the predicted value of the sample.

[0036] For each expansion, all possible solutions need to be enumerated. For a specific split, calculate the sum of the derivatives of the left subtree and the sum of the derivatives of the right subtree of this split, and compare them with the sum before the split. Traverse all splits and select the one with the largest change as the most appropriate split.

[0037] In the present invention, the library function of the XGBoost library is used to train the model. First, the training set and the test set are reasonably divided, and then the two XGBoost models for self-capacitance and mutual capacitance extraction are trained respectively through parameter tuning. The specific method of parameter tuning is as follows:

[0038] 2.1) Determine the learning rate and the number of trees: Choose a higher learning rate. Generally, the learning rate is 0.1. However, for different problems, the ideal learning rate sometimes fluctuates between 0.05 and 0.3. Choose the ideal number of decision trees corresponding to this learning rate.

[0039] 2.2) For a given learning rate and number of decision trees, perform decision tree specific parameter tuning. Max_depth and min_weight parameter tuning: tune these two parameters first because they have a great impact on the final result; gamma parameter tuning: the purpose is to reduce the risk of overfitting, and the range can be selected from 0 to 0.5; adjust the sample sampling methods subsample and colsample_bytree. Use a grid search method for the above parameters, first adjust the parameters in a large range, and then fine-tune them in a small range.

[0040] 2.3) Tuning the regularization parameters (lambda, alpha) of xgboost. These parameters can reduce the complexity of the model and thus improve the performance of the model.

[0041] 2.4) Reduce the learning rate: Use a lower learning rate and use more decision trees. The present invention uses the CV function in XGBoost to perform this step.

[0042] 3) The two-dimensional structure of the chip whose capacitance is to be extracted is extracted using the same adaptive window extraction and gridding method, and input into the trained XGBoost model to solve the main conductor self-capacitance and the coupling capacitance between the adjacent conductors, thereby realizing the parasitic capacitance extraction of the entire chip.

[0043] The model trained by the present invention is used to extract capacitance from chips with different conductor arrangements under different process standards under ultra-large-scale integrated circuits and advanced processes, which has the characteristics of fast running speed and small memory usage. Since the XGBoost machine learning model adopts an offline training method, the training time will not affect the time complexity of the capacitance extractor. At the same time, the memory consumption during operation and the storage space required for the trained model are very small.

[0044] This example performs capacitance extraction on a chip under the Input_3 process standard, where net0 is the main conductor, and net1 and net2 are adjacent conductors. The results and deviations are shown in the figure. Figure 4 As shown, it can be seen that the self-capacitance result is relatively accurate.

[0045] It should be noted that the above embodiments are only used to explain the present invention rather than to limit the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A high-efficiency capacitance extraction method based on machine learning, It is characterized in that The method includes: Dataset preparation stage: Randomly generate a sufficient number of input samples of different conductor arrangements under different process standards, input them into the FasterCap tool after data preprocessing, and use FasterCap output data as XGBoost labels; at the same time, regard the two-dimensional cross-sectional structure as an image, use adaptive window extraction and gridding methods to represent any arrangement of any number of conductors as a corresponding two-dimensional matrix form, and obtain the input of XGBoost from the randomly generated input samples; Training machine learning models: XGBoost input and XGBoost labels are combined into a data set. Two XGBoost machine learning models for self-capacitance and coupling capacitance are trained through a large number of data sets. Problem solving: The two-dimensional cross-sectional structure of the chip whose capacitance is to be extracted is used as the input of the capacitance extractor according to the same adaptive window extraction and gridding method. The main conductor self-capacitance and the coupling capacitance between the conductor and the adjacent conductor are obtained at the output end of the capacitance extractor to realize the parasitic capacitance extraction of the entire chip.

2. According to claim 1, a high-efficiency capacitance extraction method based on machine learning, It is characterized in that The size of the adaptive window is determined by the fact that the coupling capacitance between the ambient conductor and the main conductor is reduced to 1% of the self-capacitance of the main conductor during the simulation experiment.

3. According to claim 1, a high-efficiency capacitance extraction method based on machine learning, It is characterized in that The structural model of three metal layers is considered when gridding data, the main conductor is located in the center of the middle layer, and the number of conductors in each layer is not fixed.

4. According to claim 1, a high-efficiency capacitance extraction method based on machine learning, It is characterized in that The grid is divided uniformly, and each conductor layer is represented as a vector x according to the density. The information of the main conductor and the ambient conductor is included in it through the following encoding method: If the dominant body covers the ith grid, then x i =d i +1; If the ambient conductor covers the ith grid, then let x i =-d i ; Among them, d i Represents the density of the extraction window.

5. According to claim 1, a high-efficiency capacitance extraction method based on machine learning, It is characterized in that The method of extracting capacitance using XGBoost machine learning is implemented through offline training.

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