Non-volatile memory, storage system and operating method suitable for neural networks

Abstract

Some embodiments of the present application provide a non-volatile memory, a storage system and an operating method suitable for a neural network. The non-volatile memory comprises a peripheral circuit configured to: apply a bit line voltage to a bit line connected to a storage cell pair, the bit line voltage being one input of a neuron in the neural network; apply a read voltage to a word line connected to the storage cell pair; and determine an output of the neuron based on a conductance difference of two storage cells in the storage cell pair, the conductance difference being a weight corresponding to the input of the neuron.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and more particularly, to a non-volatile memory applicable to a neural network, a non-volatile memory system, and an operation method of the non-volatile memory for executing the neural network. BACKGROUND

[0002] The rapid development of artificial neural networks (referred to as neural networks) has led to a new wave of research in artificial intelligence. In order to accelerate the inference and training speed of neural networks and enable neural networks to be deployed on more terminal devices, it is necessary to improve the computing capability and reduce the power consumption at the hardware level.

[0003] The basic principle of a neural network is to multiply and add an input vector and synaptic weights (referred to as weights) stored by an abstract "neuron" and then output after a nonlinear activation, and to fit a complex function relationship through the mutual connection of multiple layers of "neurons".

[0004] However, as the parameter scale and operation amount of a neural network rapidly increase, the hardware platform of the neural network faces the problem of mismatch between the memory bandwidth and the operation speed of a computing unit caused by massive data throughput. SUMMARY

[0005] The embodiments of the present application provide a non-volatile memory applicable to a neural network, a non-volatile memory system, and an operation method of the non-volatile memory for executing the neural network, which can at least partially solve the above problems in the related art.

[0006] One aspect of the present application provides a non-volatile memory applicable to a neural network, the non-volatile memory comprising: a plurality of channel structures and an isolation structure, along an extension direction parallel to the channel structures, the channel structures are divided into at least two sub-channel structures by the isolation structure, two sub-channel structures in the same channel structure correspond to adjacent storage strings, a storage cell array in the plurality of storage strings is divided into storage cell pairs, two storage cells in each storage cell pair are located in two storage strings and connected to the same word line, the two storage strings are connected to two bit lines respectively, a plurality of storage cell pairs connected to the same word line and located in different storage strings correspond to one neuron in the neural network; and a peripheral circuit configured to: apply a bit line voltage to a bit line connected to the storage cell pair, the bit line voltage serving as one input of the neuron in the neural network; apply a read voltage to a word line connected to the storage cell pair; and determine an output of the neuron based on a conductance difference of two storage cells in the storage cell pair, the conductance difference serving as a weight corresponding to the input of the neuron.

[0007] In some embodiments, the peripheral circuit is further configured to perform a program operation on at least one of the pair of memory cells to adjust the conductance difference value.

[0008] In some embodiments, the plurality of memory strings constitute a memory cell array, the memory cell array comprises a plurality of two-dimensional memory cell arrays, the plurality of memory strings in each two-dimensional memory cell array are connected to a same top select line, and each two-dimensional memory cell array comprises the pair of memory cells, the peripheral circuit is further configured to determine, within a predetermined time period, an output of a neuron corresponding to the pair of memory cells located in different two-dimensional memory cell arrays.

[0009] In some embodiments, the plurality of memory strings constitute a memory cell array, the memory cell array comprises a plurality of two-dimensional memory cell arrays, the plurality of memory strings in each two-dimensional memory cell array are connected to a same top select line, and each two-dimensional memory cell array comprises the pair of memory cells, the peripheral circuit is further configured to adjust, within a predetermined time period, a conductance difference value of the pair of memory cells located in different two-dimensional memory cell arrays.

[0010] In some embodiments, the isolation structure extends along a direction in which the plurality of channel structures are arranged away from one end of the bit line.

[0011] In some embodiments, the memory cell is a floating floating gate type memory cell or a charge trapping type memory cell.

[0012] Another aspect of the embodiments of the present application provides a non-volatile storage system suitable for a neural network, the non-volatile storage system comprising: at least one non-volatile memory as described in any of the preceding embodiments; and a controller connected to the at least one non-volatile memory and configured to control the peripheral circuit in the non-volatile memory.

[0013] Another aspect of the embodiments of the present application also provides an operation method of a non-volatile memory for executing a neural network, the non-volatile memory comprising a plurality of channel structures and an isolation structure, the channel structures are divided into at least two sub-channel structures by the isolation structure along a direction parallel to an extension direction of the channel structures, two sub-channel structures in a same channel structure correspond to adjacent memory strings, memory cells in the plurality of memory strings are divided into pairs of memory cells, two memory cells in each pair of memory cells are located in two memory strings and connected to a same word line, the two memory strings are connected to two bit lines respectively, a plurality of pairs of memory cells corresponding to the same word line and located in different memory strings correspond to a neuron in the neural network, the operation method comprising: applying a bit line voltage to a bit line connected to the pair of memory cells, the bit line voltage as an input of the neuron in the neural network; applying a read voltage to a word line connected to the pair of memory cells; and determining an output of the neuron based on a conductance difference value of the two memory cells in the pair of memory cells, the conductance difference value as a weight corresponding to the input of the neuron.

[0014] In some embodiments, the operation method further includes: performing a programming operation on at least one of the storage cell pairs to adjust the conductance difference value.

[0015] In some embodiments, the plurality of storage strings constitute a storage cell array, the storage cell array includes a plurality of two-dimensional storage cell arrays, the plurality of storage strings in each two-dimensional storage cell array are connected to a same top selection line, and each two-dimensional storage cell array includes the storage cell pairs, and determining the output of the neuron includes: determining, within a predetermined time period, the output of the neuron corresponding to the storage cell pairs located in different two-dimensional storage cell arrays.

[0016] In some embodiments, the plurality of storage strings constitute a storage cell array, the storage cell array includes a plurality of two-dimensional storage cell arrays, the plurality of storage strings in each two-dimensional storage cell array are connected to a same top selection line, and each two-dimensional storage cell array includes the storage cell pairs, and adjusting the conductance difference value includes: adjusting, within a predetermined time period, the conductance difference value of the storage cell pairs located in different two-dimensional storage cell arrays.

[0017] In addition, according to at least one embodiment of the present application, the non-volatile memory suitable for a neural network, the non-volatile storage system and the operation method for performing the neural network provided by the embodiments of the present application utilize hardware to implement the forward propagation process or the inference process of the neural network for the conductance difference value of the storage cell pairs in the storage cell array of the non-volatile memory, which has advantages in unit storage density and large capacity, is conducive to the implementation of a larger scale of deep neural network, and thus supports more complex neural network function implementation. BRIEF DESCRIPTION OF DRAWINGS

[0018] Other characteristics, objects and advantages of the present application will become more apparent from the following detailed description of non-restrictive embodiments, made with reference to the attached drawings. Among them:

[0019] Figure 1 is a functional block diagram of a non-volatile storage system connected to a host according to an embodiment of the present application;

[0020] Figure 2 is a functional block diagram of a non-volatile memory according to an embodiment of the present application;

[0021] Figure 3 is an equivalent circuit diagram of a three-dimensional storage cell array according to an embodiment of the present application;

[0022] Figure 4A is a physical structure schematic diagram of adjacent storage strings according to an embodiment of the present application;

[0023] Figure 4B is according to Figure 4A along a plane A is a top view schematic diagram of a plurality of memory strings taken along a plane;

[0024] Figure 4C is a top view schematic diagram of adjacent memory strings according to another embodiment of the present application;

[0025] Figure 5 is a schematic diagram of a three-layer neural network structure according to an embodiment of the present application;

[0026] Figure 6 is a flowchart of a training process of a neural network according to an embodiment of the present application;

[0027] Figure 7 is a flowchart of an operating method of a non-volatile memory for executing a neural network according to an embodiment of the present application;

[0028] Figure 8 is according to Figure 3 is an equivalent circuit diagram of a two-dimensional memory cell array in a three-dimensional memory cell array shown;

[0029] Figure 9 is a waveform diagram of voltages applied to n word lines for determining an output of a neuron according to an embodiment of the present application;

[0030] Figure 10 is a schematic diagram of an operating method of a non-volatile memory for executing a neural network according to another embodiment of the present application; and

[0031] Figure 11 is a plot of conductance of a memory cell versus time of performing a program operation according to an embodiment of the present application. DETAILED DESCRIPTION

[0032] For a better understanding of the present application, various aspects of the present application will be described in greater detail below with reference to the accompanying drawings. It is to be understood that the detailed description is merely exemplary of the application and is not intended to limit the scope of the application in any way. Throughout the specification, like reference numerals refer to like elements. The expression “and / or” includes any and all combinations of one or more of the associated listed items.

[0033] It is noted that, in this specification, the expressions first, second, third, etc. are merely used to separate one feature from another feature, and do not indicate any limitation on the features, especially do not indicate any sequential order. Therefore, a first part discussed in the present application can also be called a second part, a first channel structure can also be called a second structure, and vice versa, without departing from the teachings of the present application.

[0034] In the drawings, the thicknesses of components, sizes, and shapes can be exaggerated for clarity. The drawings are merely schematic and are not drawn to scale. As used in this document, the term "substantially" means that the recited characteristic, parameter, or value need not be achieved exactly, but that deviations, within measurement error, are contemplated. When the term "substantially" is used in reference to an amount or value, it should be understood that the exact amount or value need not be achieved, but that deviations, typically due to measurement error, are acceptable.

[0035] It should also be understood that any reference to a method comprising steps is intended to mean that the method can comprise the steps in the order recited, or one or more of the steps can be omitted, or subsumed in an additional step, or the steps can be executed in a different order, or one or more of the steps can be executed in parallel.

[0036] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.

[0037] It should be noted that the embodiments and features of the embodiments in the present application can be combined with each other, as long as there is no conflict. In addition, the specific steps in the methods described in the present application are not necessarily limited to the order described, but can be performed in any order or in parallel, unless expressly limited or contrary to the context. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0038] In addition, when "connected" or "coupled" is used in the present application, it can mean direct contact or indirect contact between the corresponding components, unless there is an explicit other limitation or it can be derived from the context.

[0039] Figure 1 is a functional block diagram of a nonvolatile storage system 10 connected to a host 20 according to an embodiment of the present application. As shown in FIG. 1, the nonvolatile storage system 10 includes a controller 100, a nonvolatile memory 200, and a bus 300. Figure 1As shown, the electronic device composed of the host 20 and the nonvolatile storage system 10 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle-mounted computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other appropriate electronic device.

[0040] The host 20 can include a processor of the electronic device and be configured to control the overall operation of the nonvolatile storage system 10 and transmit or receive data to and from the nonvolatile storage system 10. The host 20 can be a central processing unit (CPU) or can be a system-on-chip (SoC), for example, an application processor (AP).

[0041] The nonvolatile storage system 10 can store data accessed by the host 20. According to an interface protocol by which the nonvolatile storage system 10 is connected to the host 20, the nonvolatile storage system 10 can be configured as a universal flash storage (UFS) system, a solid state disk (SSD), a multimedia card in the form of an RS-MMC and a micro- MMC, a secure digital card in the form of an SD, a mini-SD, and a micro-SD, a storage system of a personal computer memory card international association (PCMCIA) card type, a storage system of a peripheral component interconnect (PCI) type, a storage system of a high-speed PCI (PCI-E) type, a compact flash (CF) card, a smart media card, or a memory stick, or any other appropriate storage system.

[0042] As shown, the nonvolatile storage system 10 can include one or more nonvolatile memories 110 for storing data and a controller 120 for controlling the nonvolatile memories 110. Figure 1

[0043] The controller 120 is coupled to the nonvolatile memories 110 and the host 20 and is configured to control the operation of the nonvolatile memories 110, manage data stored in the nonvolatile memories 110, and communicate with the host 20. The controller 120 can include, for example, a host interface 121, a processor 122, and a flash interface 123.

[0044] ​The host interface 121 in the controller 120 can communicate with the host 20 according to a specific communication protocol. The interface protocol of the host interface 121 can include any one of a Universal Flash Storage (UFS) protocol, a Serial Advanced Technology Attachment (SATA) protocol, a Peripheral Component Interconnect (PCI) protocol and a PCI Express (PCI-E) protocol, a Universal Serial Bus (USB) protocol, a Multi Media Card (MMC) protocol, a Parallel Advanced Technology Attachment (PATA) protocol, a Small Computer System Interface (SCSI) protocol, a Serial Attached SCSI (SAS) protocol, etc.

[0045] The processor 122 in the controller 120 can include one or more ARM cores, for example. The processor 122 can control the inherent operation of the non-volatile memory 110 by driving firmware called a Flash Translation Layer (FTL), for example, and provide compatibility to the host 20. In addition, the processor 122 can also perform functions such as Wear Leveling, Garbage Collection, Bad Block Management, etc. by driving other firmware, for example.

[0046] The flash interface 123 in the controller 120 can be responsible for managing data to be read from and written to the non-volatile memory 110 according to a flash command conforming to an ONFI or Toggle standard, for example. For each non-volatile memory 110, a command, an address, and data can be transmitted thereto through the flash interface 123, for example. For a plurality of non-volatile memories 110, a specific non-volatile memory 110 can be selected by a strobe signal, for example, before transmitting a command, an address, and data.

[0047] Each non-volatile memory 110 can be referred to as a die, and can also be referred to as a storage grain. Each die can be the smallest basic management unit of a flash communication. Exemplarily, the non-volatile memory 110 can be a 3D NAND type memory. One non-volatile memory 110 or a plurality of non-volatile memories 110 can be integrated into one package. For example, 4 to 8 non-volatile memories 110 can be packaged together. It should be noted that the number of the plurality of non-volatile memories 110 packaged can be designed according to the capacity requirement, and the specific number is not limited in the present application.

[0048] Figure 2 is a functional block diagram of a non-volatile memory 210 according to an embodiment of the present application. The non-volatile memory 210 can be a 3D NAND type memory, for example. Figure 1 is an example of the plurality of non-volatile memories 110 shown. As shown in Figure 2As shown, the non-volatile memory 210 can include a three-dimensional memory cell array 220 and peripheral circuitry such as a page buffer 231, a row decoder 232, a column decoder 233, a voltage generator 234, a logic control module 235, an I / O module 236, and a data bus 237. It should be understood that the operations performed by the above-described circuit modules described in this application can be performed by the processing circuit. Alternatively, the processing circuit can include, but is not limited to, hardware of a logic circuit or a hardware / software combination of a processor executing software.

[0049] The three-dimensional memory cell array 220 can include a plurality of memory cells arranged in a three-dimensional array. The plurality of memory cells can be connected to a plurality of bit lines (BLs) and a plurality of word lines (WLs) in a predetermined connection manner. Illustratively, each memory cell can be any one of a single-layer memory cell (SLC) capable of storing one bit of data, a two-layer memory cell (MLC) capable of storing two bits of data, a three-layer memory cell (TLC) capable of storing three bits of data, and a four-layer memory cell (QLC) capable of storing four bits of data. For example, a plurality of SLC memory cells connected to the same word line correspond to one page.

[0050] The page buffer (or referred to as a "sense amplifier") 231 can be configured to read data from or program (write) data to the three-dimensional memory cell array 220 according to a control signal from the logic control module 235. In one example, the page buffer 231 can store data to be programmed to a page in the three-dimensional memory cell array 220. In another example, the page buffer 231 can sense a low-power signal of data stored in a memory cell of the three-dimensional memory cell array 220 in a read operation, and amplify a small voltage swing to an identifiable logic level.

[0051] The row decoder 232 can be configured to be controlled by the logic control module 235 and select a page in the three-dimensional memory cell array 220. For example, the row decoder 232 can be configured to select a corresponding page by driving a word line using a voltage generated by the voltage generator 234.

[0052] The column decoder 233 can be configured to be controlled by the logic control module 235 and select a corresponding bit line by applying a bit line voltage generated by the voltage generator 234.

[0053] The voltage generator 234 can be configured to be controlled by the logic control module 235 and generate a word line voltage (e.g., a charging voltage, a ground voltage, a read voltage, a program voltage, a pass voltage, a verify voltage, etc.), a bit line voltage, and a source line voltage to be provided to the three-dimensional memory cell array 220, etc.

[0054] The logic control module 235 can be coupled to each of the peripheral circuit modules described above, and configured to control the operation of the respective peripheral circuit modules. The logic control module 235 can control the operation method of the neural network to be described below.

[0055] The I / O module 236 can be coupled to the logic control module 235 to forward the control commands received from the host 20 (referenced Figure 1 ) or the controller 120 (referenced Figure 1 ) to the logic control module 235, and forward the status information received from the logic control module 235 to the controller 120 (referenced Figure 1 ). The I / O module 236 can also be coupled to the column decoder 233 via the data bus 237 to buffer and forward data to and from the three-dimensional memory cell array 220.

[0056] Figure 3 is an equivalent circuit diagram of a three-dimensional memory cell array 320 according to an embodiment of the present application. The three-dimensional memory array 320 can be an example of a portion of the three-dimensional memory array 220 shown above. For example, Figure 2 The three-dimensional memory cell array 320 shown above can be referred to as a memory block. Figure 3

[0057] As shown in Figure 3 , the memory block can include a plurality of memory strings (e.g., Str11 + , Str12 + , Str13 + , and Strm3 - , etc.). The plurality of memory strings Str11 + ~ Strm3 - may be arranged in a two-dimensional array with respect to the xy plane. Each memory string (e.g., Str11 + ) can extend in the z direction, and can in turn include a top select transistor TST1 + , memory cells MC1 + ~ MCn + , and a bottom select transistor BST1 + connected in series with each other. Exemplarily, for each memory string (e.g., Str11 + ), one or more dummy memory cells (not shown) can also be provided between the top select transistor TST1 + and the memory cells MC1 + , and one or more dummy memory cells (not shown) can also be provided between the memory cells MCn + and the bottom select transistor BST1 + . It is noted that each memory string (e.g., Str11​+ ) includes a selection transistor (eg, TST1 + and BST1 + ), storage unit (e.g., MC1 + ~MCn + ) and the number of dummy storage units are not specifically limited in this application.

[0058] In one example, multiple storage strings Str11 in a storage block + ~Strm3 - One end of the memory string Str11 can be connected to the common source line ACS. + ~Strm3 - Each bottom selection transistor (for example, BST1 + ) can be connected to a common source line ACS.

[0059] In one example, each storage string Str11 + ~Strm3 - A plurality of memory cells (e.g., MC1) are located at (approximately) the same height from the common source line ASC. + 、MC1 - The gate terminals of the plurality of memory cells (e.g., MC1, MC2, MC3, MC4, MC5, MC6, MC7, MC8, MC9, MC10, MC11, MC12, MC13, MC14, MC15, MC16, MC17, MC18, MC19, MC20, MC21, MC22, MC23, MC24, + 、MC1 - etc.) can be controlled by the word line (eg, WL1) to which multiple memory cells (eg, MC1) are connected. + 、MC1 - etc.) may constitute one page, so that, for example, a memory block includes a plurality of pages corresponding to the plurality of word lines WL1-WLn.

[0060] In one example, a plurality of storage strings (eg, Str11, Str21, Str31, Str41, Str51, Str61, Str71, Str81, Str91, Str101, Str112, Str113, Str114, Str125, Str126, Str130, Str131, Str132, Str133, Str134, Str135, Str136, Str137, Str138, Str140, Str141, Str142, Str143, Str144, Str145, Str146, Str147, Str148, Str149, Str150, Str151 + Str11 - , Strm1 + , Strm1 - ) are located at (approximately) the same height from the common source line ACS. + ) can be connected to the same top selection line (eg, TSL1), so that, for example, the memory block includes a plurality of top selection lines TSL1, TSL2, and TSL3 arranged along the y direction.

[0061] In one example, a plurality of storage strings (eg, Str11, Str21, Str31, Str41, Str51, Str61, Str71, Str81, Str91, Str101, Str112, Str113, Str114, Str125, Str126, Str130, Str131, Str132, Str133, Str134, Str135, Str136, Str137, Str138, Str140, Str141, Str142, Str143, Str144, Str145, Str146, Str147, Str148, Str149, Str150, Str151+ Str11 - , Strm1 + , Strm1 - ) are located at (approximately) the same height from the common source line ACS. + ) can be connected to the same bottom select line (e.g., BSL1), so that, for example, a memory block includes multiple bottom select lines BSL1, BSL2, and BSL3 arranged along the y-direction. In another example, the gate terminals of multiple bottom select transistors in each memory string that are located at (approximately) the same height from the common source line ACS can be connected to each other and to the same bottom select line, so that, for example, a memory block includes one bottom select line (not shown).

[0062] In one example, a plurality of storage strings (eg, Str11) arranged along the y direction + 、St12 + Str13 + ) can be connected to the same bit line (e.g., BL1 + ). For example, each storage string Str11 + 、St12 + Str13 + Each top selection transistor (e.g., TST1) located at the end + ) can be connected to the bit line BL1 + , so that, for example, a memory block includes a plurality of bit lines BL1 arranged along the x direction + BL1 - ~BLm + BLm - .

[0063] The physical structure of adjacent memory strings in a three-dimensional memory cell array is exemplarily described below. Figure 4A It is a schematic diagram of the physical structure of adjacent storage strings according to an embodiment of the present application. Figure 4B is based on Figure 4A Schematic top view of a plurality of memory strings taken along plane A.

[0064] like Figure 4AAs shown, the channel structure can include two sub-channel structures 411, 412, and the shape of each sub-channel structure (e.g., 411) can be, for example, a (roughly) semi-cylinder, and the extension direction (z direction) of the sub-channel structure 411 can be the direction in which a plurality of memory cells in a memory string are arranged. The sub-channel structure 411 can include, in sequence along a direction perpendicular to the side surface direction, a charge blocking layer 401, a charge trapping layer 402, a tunneling layer 403, and a channel layer 404. Among them, the charge blocking layer 401, the charge trapping layer 402, and the tunneling layer 403 can be referred to as a functional layer 405. For example, the materials of the charge blocking layer 401, the charge trapping layer 402, and the tunneling layer 403 can be, in sequence, silicon oxide, silicon nitride, and silicon oxynitride. The material of the channel layer 404 can be polysilicon. It should be noted that the shape of the sub-channel structure is not limited thereto, and can also be, for example, a semi-elliptical cylinder, a prism, or other irregular shapes.

[0065] The isolation structure 420 can be arranged along a direction perpendicular to the extension direction (z direction) of the sub-channel structures 411, 412 to separate the two sub-channel structures 411 and 412. For example, from the xy plane, the top surface shape of the isolation structure 420 can be a rectangle arranged between the two semi-circular top surfaces of the two sub-channel structures 411, 412. For example, the two semi-circular top surfaces of the sub-channel structures 411, 412 can be symmetrically arranged with respect to the rectangular top surface of the isolation structure 420. Further, the top surface of the isolation structure 420 can extend along the extension direction (z direction) of the sub-channel structure 411 or 412, so that the sub-channel structures 411, 412 are physically separated by the isolation structure 420. For example, the material of the isolation structure 420 can include dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride to achieve electrical isolation between the two sub-channel structures 411, 412.

[0066] In one example, the word lines WL1-WLn can be arranged in sequence along the extension direction (z direction) of the sub-channel structures 411 or 412. Each word line (e.g., WL2) can surround a portion of the sub-channel structure 411 or 412 in the extension direction thereof. For example, the material of each word line (e.g., WL1-WLn) can include tungsten, doped polysilicon, or any suitable conductive material.

[0067] In one example, each word line (e.g., WL2) and the portion of the functional layer 405 and the channel layer 404 corresponding to the word line WL2 together form a memory cell. For example, applying a voltage to the word line WL2 can cause the charges (e.g., electrons) in the channel layer 404 to be injected into the charge trapping layer 402, or through the cooperation of the word line WL2 and other control lines, the charges in the charge trapping layer 402 to be returned to the channel layer 404. For example, the voltage applied to the word line WL2 can be a positive voltage, a negative voltage, or a voltage of zero volts. Figure 4AAs shown, the plurality of memory cells arranged in the z direction share the channel layer 404, in other words, the plurality of memory cells can be arranged in series in the z direction (similar to a NAND gate).

[0068] It is noted that, as mentioned above, for a memory cell, the charge trapping layer 402 made of a dielectric material (e.g., silicon nitride) can be similar to a trap such that it is difficult for a charge to escape after being injected into the charge trapping layer 402, and thus such a memory cell can be referred to as a charge trapping type memory cell. In another example, the functional layer can include, in sequence, a charge blocking layer, a floating gate layer, and a tunneling layer, the floating gate layer can be made of, for example, a conductive material, and the charge blocking layer and the tunneling layer made of a dielectric material and located on both sides of the floating gate layer can enable a charge to be preserved in the floating gate layer without escaping after the charge is injected into the floating gate layer, and thus such a memory cell can be referred to as a floating floating gate type memory cell.

[0069] In some examples, as shown in FIG. 4A, the isolation structure 420 extends along the direction (e.g., the x direction) in which the plurality of channel structures (e.g., the channel structures include the sub-channel structures 411 and 412) are arranged at one end away from the bottom of the bit line (e.g., the bottom shown in FIG. 4A). Figure 4A and Figure 4B It is noted that, for the sub-channel structures (e.g., 411 and 412) included in a channel structure, the isolation structure 420 can enable the bottom select transistors located in the two sub-channel structures (e.g., 411 and 412) to be individually used as an element. On the other hand, the isolation structure 420 extending in the direction (e.g., the x direction) insulates and isolates the bottom select lines (e.g., BSL1 and BSL2) at one end away from the bottom of the bit line (e.g., the bottom shown in FIG. 4A), such that the plurality of bottom select transistors on both sides of the isolation structure 420 extending in the direction (e.g., the x direction) can be individually controlled by the two bottom select lines (e.g., BSL1 and BSL2), respectively. Figure 4A Figure 4A

[0070] Figure 4C is a top view schematic diagram of the physical structure of adjacent memory strings according to another embodiment of the present application. As shown in FIG. 4B, the isolation structure 420 extends along the direction (e.g., the x direction) in which the plurality of channel structures (e.g., the channel structures include the sub-channel structures 411 and 412) are arranged at one end away from the bottom of the bit line (e.g., the bottom shown in FIG. 4B). Figure 4C ​​As shown, the isolation structure 420' can separate the four sub-channel structures 411', 412', 413', 414' from each other along a direction (z direction) perpendicular to the extension direction of the sub-channel structures 411', 412', 413', 414'. Exemplarily, from the xy plane, the top surface shape of the isolation structure 420' can be, for example, a cross shape, and the top surface shape of the four sub-channel structures 411', 412', 413', 414' can be, for example, (approximately) 1 / 4 circle shape. The four sub-channel structures 411', 412', 413', 414' can be respectively arranged between adjacent intersections of the cross shape. Further, the top surface of the isolation structure 420' can extend along the extension direction (z direction) of the sub-channel structures (e.g., 411'), so that the sub-channel structures 411', 412', 413', 414' are physically separated by the isolation structure 420'. When the material of the isolation structure 420' is a dielectric material, electrical isolation between the sub-channel structures 411', 412', 413', 414' can be achieved.

[0071] It can be understood that, Figures 4A to 4C Exemplary cases of the channel structure including two sub-channel structures and four sub-channel structures are respectively shown. However, the channel structure can also include other numbers of sub-channel structures, such as 3, 5, 6, 7, etc.

[0072] In one example, the functional layers and the channel layer of the multiple sub-channel structures in the channel structure can be formed in the same process (e.g., a thin film deposition process), so that the physical structure difference (e.g., the thin film thickness difference of the functional layers and / or the channel layer) of the multiple sub-channel structures included in the same channel structure is small.

[0073] The neural network is exemplarily described below. The neural network can be composed of an input layer, an output layer, and one or more hidden layers between the input layer and the output layer, each layer including one or more neurons. According to the connection relationship of the neurons in the neural network, the input traverses each layer in a mathematical transformation manner and is converted into the probability of each output.

[0074] Figure 5 is a schematic diagram of a three-layer neural network structure 500 according to an embodiment of the present application. Figure 5 An input layer with three input neurons (I1, I2, I3), an output layer with two output neurons (O1, O2), and a hidden layer with four hidden neurons (H1, H2, H3, H4) are shown. The circles in the neural network 500 represent neurons, and the connecting lines represent the variable weights between each neuron of the previous layer and one neuron of the current layer. A neuron (e.g., a hidden neuron H1) can be implemented as a mathematical function that receives multiple inputs (I1, I2, I3) and adds them up after weighting to produce an output (O1).H1 =I1ω1+I2ω2+I3ω3). Further, the output O generated by the hidden neuron (for example, H1) H1 The output of each output neuron (e.g., O1) can be used as an input to the output neuron. The output generated by the output neuron can be used as the output of the neural network 500.

[0075] In some embodiments, the weights (e.g., ω1, ω2, ω3) can be adjusted using a training process. In addition, neurons (e.g., hidden neurons or output neurons) can have a threshold value, so that when the weighted input accumulation value exceeds the threshold value, an output (i.e., the input of the next layer or the output of the neural network) is generated. Optionally, the output of the neuron can be calculated using some nonlinear functions (e.g., Sigmoid function). Although Figure 5 One hidden layer is shown, but a complex deep neural network (DNN) may have many such hidden layers.

[0076] Trained neural networks can be used to solve problems such as pattern recognition. For example, a trained neural network can be used to infer the type of fruit in an image. Figure 6 Flowchart of the training process of the neural network according to the embodiment of the present application. For example, the training process can be based on supervised learning rules. Figure 5 The neural network 500 is shown illustrating the training process 600 in detail.

[0077] In step 601, input neurons I1, I2, I3 (refer to Figure 5 ) receives training input. For example, the training input is a set of images, each of which includes a fruit category to be identified.

[0078] In step 602, the current weights can be used to connect the input neurons I1, I2, and I3 to the hidden neurons H1, H2, H3, and H4 of the next layer. Further, the hidden neurons H1, H2, H3, and H4 are connected to the output neurons O1 and O2 of the next layer, and the outputs of the hidden neurons H1, H2, H3, and H4 are used as the inputs of the output neurons O1 and O2 of the next layer. Further, the outputs of the output neurons O1 and O2 are used as the outputs of the neural network 500. In other words, the training input from the input layer traverses all hidden layers in this way until it propagates to the output layer. Exemplarily, as described above, in the example of using a neural network to identify fruit categories, the hidden layer and the output layer use the current weights to calculate the probability that the fruit in the image is of a specific category, and the label of the target fruit category is returned at step 603.

[0079] In step 604, it is determined whether the probability of the specific fruit category output by the neural network meets the requirements of sufficiently accurate labels using the current weights, and if so, training is completed (step 605). If the result is not accurate enough, the neural network adjusts the weights at step 606 and then loops back to step 604 to run the input data again using the adjusted weights.

[0080] When the weights of the neural network are determined in step 605, the weights can be used to infer the category of the fruit in the image as described above, and the determined weights can be stored in the three-dimensional memory cell array 320 (see Figure 3 )middle.

[0081] Figure 7 7 is a flowchart of a method 700 for operating a non-volatile memory for executing a neural network according to an embodiment of the present application. Figure 8 is based on Figure 3 The equivalent circuit diagram of the two-dimensional memory cell array 820-1 in the three-dimensional memory cell array 320 is shown below. Figure 7 and Figure 8 The operation method 700 is described as an example. The operation method 700 can be used, for example, Figure 8 A portion of the exemplary three-dimensional memory cell array 320 (ie, the two-dimensional memory cell array 820 - 1 ) is used to perform a forward propagation or inference process during the training process of a neural network.

[0082] like Figure 8 As shown, the two-dimensional storage cell array 820-1 can be equivalent to a neural network (for example, Figure 5 For each memory string in the two-dimensional memory cell array 820-1, it can be controlled by the same top selection line TSL1 so that Figure 8 Multiple storage strings Str11 are shown + ~Strm1 - Able to connect to multiple bit lines (e.g., BL1) under the control of the same top select line TSL1 + BL1 - ~Blm + BLm - ) is connected.

[0083] In step 701, Figure 8 As shown, the same word line (eg, WL1) is connected and located in different memory strings (eg, Str11 + ~Strm1 - ) on multiple memory cells (e.g., MC1 + ~MCm -) may correspond to a neuron in the current layer. The two-dimensional memory cell array 820-1 may correspond to n neurons in the current layer. + ~MCm - ) can correspond to m storage unit pairs, that is, storage unit pair MC1 + and MC1 - ~ Storage unit pair MCm + and MCm - .

[0084] Furthermore, a plurality of bit lines (eg, BL1 + ~BLm - ) can be divided into multiple bit line pairs, for example, bit line pair BL1 + and BL1 - ~Bit line pair BLm + and BLm - In this step, each bit line pair (eg, BL1 + and BL1 - ) Apply bit line voltage V BL , each bit line pair (e.g., BL1 + and BL1 - ) The applied bit line voltage V BL It can correspond to multiple inputs of a neuron in the current layer. In other words, the bit line voltage V applied to each bit line pair BL It can correspond to an input of a neuron in the current layer. For example, for a neuron in the current layer, it can receive m inputs (ie, the bit line voltage V on m bit line pairs). BL Optionally, each bit line pair (eg, BL1 + and BL1 - ) The two bit lines are applied with bit line voltage V BL In another example, each bit line pair BL1 may be first + and BL1 - ~BLm + and BLm - The middle m bit lines BL1 + BL2 + ~BLm + Apply bit line voltage V BL (m inputs), and then to each bit line pair BL1 + and BL1 - ~BLm + and BLm - The middle m bit lines BL1 - BL2 - ~BLm - Apply the bit line voltage V again BL(m inputs).

[0085] In step 702, the storage unit pair (e.g., MC1 + and MC1 - ) is connected to the word line WL1 + , and the conductance difference G1 - -G1 + of the storage unit pair is taken as a weight corresponding to an input of the neuron (i.e., the bit line voltage V - applied to the bit line pair BL1 BL1 and BL1 + ). It should be noted that, as described above, for the floating floating gate type or charge trapping type storage unit, the conductance value (i.e., the reciprocal of the resistance value) of each storage unit is different according to the amount of charge injected into the charge trapping layer or the floating gate layer. In this step, according to the above characteristics of the storage unit and the electrical connection characteristics of the storage unit array, the current flowing through the two storage units in the storage unit pair is sensed by applying a read voltage to the word line connected to the storage unit pair, so as to provide an execution condition for determining the output of the neuron in the subsequent step 703.

[0086] Figure 9 is a waveform diagram of the voltage applied to the n word lines for determining the output of the neuron according to the embodiment of the present application. As shown in Figure 9 , the read pulse voltage Vread (gray) is sequentially applied to the word lines WL1 to WLn to sequentially determine the current difference of each storage unit pair connected to the word line WL1 (e.g., the current difference of the storage unit pair MC1 - and MC1 + to the current difference of the storage unit pair MCm - and MCm + ) until the current difference of each storage unit pair connected to the word line WLn. In one example, since the bit line voltage V - ~V + has been applied to the bit line BL1 - ~BLm BL1+ connected to each storage string Str11 BLm- ~Strm1 + in step 701, when the read pulse voltage Vread is applied to the word line WL1 at time t1, the sensing circuit (not shown) connected to one end (e.g., the end not connected to the bit line) of each storage string Str11 - ~Strm1 + is able to sense the current flowing through the plurality of storage strings Str11 - ~Strm1 + in which the storage unit pair MC1 - and MC1 + connected to the word line WL1.~Strm1 - The current value.

[0087] In step 703, each memory cell pair (eg, MC1) may be subjected to a subtractor (not shown) for example. + and MC1 - ) where the two storage strings (for example, Str11 + and Str11 - ) in the current value (for example, I MC1+ and I MC1- ) is subjected to differential processing (i.e., I MC1+ -I MC1- ), so that each input (for example, V BL1+ and V BL1- ) and the corresponding weights (e.g., G 1+ -G 1- ) (i.e., I MC1+ -I MC1- =G 1+ ×V MC1+ G 1- ×V MC1- In other words, since word line WL1 connects multiple memory cell pairs MC1 + and MC1 - ~MCm + and MCm - , multiple inputs (e.g., V BL1+ ~V BLm- ) and the corresponding multiple weights (for example, (G 1+ -G 1- )~(G m+ -G m- )) (i.e., (G 1+ ×V MC1+ G 1- ×V MC1- )~(G m+ ×V MCm+ G m- ×V MCm- )) can be determined. Further, the above products can be added together by sensing the total current in the common source line ACS to determine the output of the neuron corresponding to the word line WL1 (ie, ), thereby determining the n outputs of the n neurons in the current layer of the neural network.

[0088] In one example, during the time t1 when the read pulse voltage Vread is applied to the word line WL1, the bias pulse voltage Vbias may be applied to the word lines WL2 to WLm. For example, the bias pulse voltage Vbias is greater than the read pulse voltage Vread. In other words, for the memory string Str11 + For example, the memory cell MC1 + Can be called a selected storage unit, storage string Str11 + Except for the memory cell MC1 + The other memory cells except MC1 can be called unselected memory cells. When the bias pulse voltage Vbias applied to the unselected memory cells is greater than the selected memory cell MC1, + When the read pulse voltage Vread is applied, the current flowing through the selected memory cell MC1 can be sensed. + The current can effectively avoid the influence of unselected storage cells, thereby improving the accuracy of obtaining neuron output.

[0089] It should be noted that Figure 9 The voltage waveforms of the word lines WL1~WLn shown are only exemplary. In other examples, from a time domain perspective, the read pulse voltage Vread may not be applied to the word lines WL1~WLn one by one. In other words, the read pulse voltage Vread may omit any one or more word lines from being applied with the read pulse voltage Vread, so that the storage cell pairs connected to the one or more word lines do not correspond to a neuron in the current layer of the neural network.

[0090] In some examples, as described above, the isolation structure 420 is located away from the bit line (eg, Figure 4A When one end of the isolation structure 420 (shown as the bottom) extends along the direction (e.g., the x-direction) in which multiple channel structures (e.g., the channel structure includes sub-channel structures 411 and 412) are arranged, the multiple bottom select transistors on both sides of the extension direction (e.g., the x-direction) of the isolation structure 420 can be independently controlled by two bottom select lines (e.g., BSL1 and BSL2). When executing a neural network output using a memory cell array of a non-volatile memory, this can be achieved by performing a read operation on the non-volatile memory. Thus, when the top select transistor corresponding to the top select line TSL1 is turned on to control the two-dimensional memory cell array to perform a read operation (i.e., determine the output of the current layer of the neural network), the bottom select transistor corresponding to the bottom select line BSL1 can be turned off. This avoids read disturbance caused by the connection of each memory string to the common source line ACS during the read operation, thereby improving the accuracy of the neural network.

[0091] In an exemplary embodiment of the present application, the conductance difference of a pair of storage cells in a storage cell array whose hardware is a non-volatile memory is used to represent the weight of a neuron to implement a neural network algorithm. This allows the conductance of the two storage cells in the storage cell pair to be adjusted independently (for example, increased or decreased). At the same time, the weight range can be increased to accommodate more weight states, which is conducive to the realization of more sophisticated neural network operations. On the other hand, the weight can be negative, so that the weight can represent richer functions such as neural inhibition. It has advantages in unit storage density and large capacity, which is conducive to the execution of larger-scale deep neural networks, thereby supporting the implementation of more complex neural network functions.

[0092] In addition, since the weight corresponding to an input in the neurons of the current layer can be represented by the conductance difference of a memory cell pair, the physical structure difference between the two memory cells in the memory cell pair (for example, the thickness of the layer) may affect the consistency of the conductance characteristics presented by the memory cells, thereby affecting the accuracy of the conductance difference corresponding to the memory cell pair. Figure 4A or Figure 4C By exemplifying the physical structure of adjacent memory strings and treating two memory cells in adjacent memory strings connected to the same word line as a memory cell pair, the impact of physical structural differences between the two memory cells in the memory cell pair on the accuracy of their conductance difference can be effectively reduced, thereby improving the accuracy of executing the operation method 700 and the anti-interference characteristics of the neural network. Furthermore, the unit density of the memory cells can be increased, thereby doubling the weight density of the neurons represented by the conductance difference of the memory cell pair.

[0093] Figure 10 FIG is a schematic diagram of an operating method of a non-volatile memory for executing a neural network according to another embodiment of the present application. Figure 10 As shown, multiple memory cells in multiple memory strings connected to the top selection line TSL1 can form a two-dimensional memory cell array (for example, the first memory cell array 1020-1). Similarly, multiple memory strings in the second memory cell array 1020-2 can be connected to one top selection line, multiple memory strings in the third memory cell array 1020-3 can be connected to another top selection line, and multiple memory strings in the p-th memory cell array can be connected to yet another top selection line. In other words, the first memory cell array 1020-1, the second memory cell array 1020-2, the third memory cell array 1020-3 to the p-th memory cell array 1020-p can be controlled by p top selection lines respectively. Among them, the first memory cell array 1020-1 can be connected to Figure 8 A portion of the exemplary three-dimensional memory cell array is the same.

[0094] In one example, for the first memory cell array 1020-1, a plurality of memory strings Str11 + ~Strm1 - in the first memory cell array 1020-1 can receive a bit line voltage (e.g., V BL1+ ~V BLm- ). That is, as detailed above, each neuron in the first memory cell array 1020-1 can be part of a plurality of neurons in a current layer of a neural network, and can generate a corresponding output in a predetermined time (e.g., a first time period).

[0095] Further, by applying a turn-on voltage to a top select line corresponding to one or more of the second memory cell array 1020-2 to the pth memory cell array, at least part of the memory cell arrays can be part of a plurality of neurons in a current layer of a neural network, and can generate a corresponding output in parallel in a predetermined time (i.e., a first time period), thereby effectively improving the operation efficiency of performing a forward propagation or inference process in a neural network algorithm using non-volatile memory.

[0096] As shown above, in the training process of a neural network, if the probability of the output of the neural network does not satisfy a label that is accurate enough, each weight in the neural network needs to be adjusted. Further, since the conductance difference (e.g., G 1+ -G 1- ) of a memory cell pair is the corresponding weight in each neuron, the adjustment of the conductance difference of the memory cell pair can be achieved by adjusting the conductance of one or both memory cells in the memory cell pair. It is noted that the adjustment of each weight in the neural network by whether the probability of the output of the neural network satisfies a label that is accurate enough can be referred to as backward propagation (BP) of the neural network.

[0097] Figure 11 is a graph of the conductance of a memory cell according to an embodiment of the present application versus time of performing a program operation. As shown in Figure 11 , as the time of performing a program operation on the memory cell increases, the conductance of the memory cell decreases. Specifically, for example, as the time of performing a program operation on the memory cell increases, more charge in the channel layer of the memory cell is injected into the charge trapping layer 402 (see Figure 4A), thereby causing the conductance of the memory cell to decrease, i.e., the conductance of the memory cell is adjusted. In another example, the conductance of the memory cell can also be adjusted by increasing the pulse strength of the program operation performed on the memory cell, causing more charge in the channel layer of the memory cell to be injected into the charge trapping layer 402 (see Figure 4A ), to adjust the conductance of the memory cell.

[0098] Reference is made below to Figure 8 , which illustrates a partial three-dimensional memory cell array, one of the memory cells MC1 + is selected for performing a program operation.

[0099] In one example, the memory cell MC1 + may be referred to as a selected memory cell. When performing a program operation on the selected memory cell, a program voltage (e.g., 15-20V) can be applied to the word line WL1 connected thereto, and the top select transistor TST1 + on the memory string Str11 + on which the memory cell MC1 + is located is turned on, and a ground voltage is applied to the bit line BL1 + connected to the memory string Str11 + on which the memory cell MC1 + is located. Under the action of the high voltage of the word line WL1, charges (e.g., electrons) are injected into the charge trapping layer after tunneling, so as to adjust the conductance of the memory cell MC1 + . Optionally, the other bit lines BL1 - ~ BLm - may be applied with a program inhibit voltage (e.g., 2V) to hinder the tunneling effect of the charges, so as to inhibit the memory cells MC1 - ~ MCm - in the memory string Str11 - ~ Strm1 - from being programmed. It is to be noted that the conductance adjustment of the memory cell MC1 + may be performed within a predetermined time (e.g., a second time period).

[0100] In one example, again referring to Figure 10 , the conductance of the memory cells in one or more of the second memory cell array 1020-2 to the pth memory cell array can be adjusted in parallel, e.g., within a second time period, thereby effectively improving the operation efficiency of the back propagation in the neural network algorithm performed using the non-volatile memory.

[0101] The above description is merely illustrative of the embodiments of the present application and the principles of the applications. It will be appreciated that those skilled in the art will readily be able to devise numerous other embodiments that, although not explicitly described herein, embody the principles of the application and are included within its spirit and scope. Therefore, the technical scope of the present application, which is defined by the claims, should not be limited to the above-described embodiments and their equivalent technical features.

Claims

1. A non-volatile memory suitable for use in a neural network, characterized in that, The non-volatile memory comprises: a plurality of channel structures and isolation structures, along an extension direction parallel to the channel structures, the channel structures are divided into at least two sub-channel structures by the isolation structures, two sub-channel structures in the same channel structure correspond to adjacent memory strings, memory cells in a plurality of memory strings are divided into memory cell pairs, two memory cells in each memory cell pair are located in two memory strings and connected to the same word line, the two memory strings are connected to two bit lines respectively, a plurality of memory cell pairs connected to the same word line and located in different memory strings correspond to a neuron in the neural network; and a peripheral circuit configured to: apply a bit line voltage to a bit line connected to the memory cell pair, the bit line voltage as an input of a neuron in the neural network; apply a read voltage to a word line connected to the memory cell pair; and determine an output of the neuron based on a conductance difference of two memory cells in the memory cell pair, the conductance difference as a weight corresponding to the input of the neuron, the output of the neuron is a sum of current differences of a plurality of memory cell pairs. The peripheral circuit is further configured to:

2. The nonvolatile memory of claim 1, wherein, perform a programming operation on at least one memory cell in the memory cell pair to adjust the conductance difference. A plurality of the memory strings constitute a memory cell array, the memory cell array comprises a plurality of two-dimensional memory cell arrays, a plurality of memory strings in each two-dimensional memory cell array are connected to the same top selection line, and each two-dimensional memory cell array comprises the memory cell pair, the peripheral circuit is further configured to:

3. The nonvolatile memory of claim 1, wherein, determine outputs of neurons corresponding to the memory cell pair located in different two-dimensional memory cell arrays within a predetermined time period. A plurality of the memory strings constitute a memory cell array, the memory cell array comprises a plurality of two-dimensional memory cell arrays, a plurality of memory strings in each two-dimensional memory cell array are connected to the same top selection line, and each two-dimensional memory cell array comprises the memory cell pair, the peripheral circuit is further configured to:

4. The nonvolatile memory of claim 2, wherein, adjust the conductance difference of the memory cell pair located in different two-dimensional memory cell arrays within a predetermined time period. The isolation structure extends along the direction in which a plurality of channel structures are arranged away from one end of the bit line.

5. The nonvolatile memory of claim 1, wherein, The memory cell is a floating floating gate type memory cell or a charge trapping type memory cell.

6. The nonvolatile memory according to any one of claims 1 to 5, wherein, The non-volatile memory comprises:

7. A non-volatile storage system suitable for a neural network, characterized in that: The non-volatile memory of any one of claims 1 to 6; and a controller connected to at least one of the non-volatile memories and configured to control the peripheral circuit in the non-volatile memory. ​ 8. An operating method of a nonvolatile memory for performing a neural network, the operating method comprising: The non-volatile memory includes a plurality of channel structures and isolation structures, the channel structures are divided into at least two sub-channel structures by the isolation structures along the extension direction parallel to the channel structures, two sub-channel structures in the same channel structure correspond to adjacent storage strings, storage cells in a plurality of storage strings are divided into storage cell pairs, two storage cells in each storage cell pair are located in two storage strings and connected to the same word line, the two storage strings are connected to two bit lines respectively, a plurality of storage cell pairs connected to the same word line and located in different storage strings correspond to a neuron in the neural network, wherein the operation method comprises: applying a bit line voltage to the bit line connected to the storage cell pair, the bit line voltage as an input of a neuron in the neural network; applying a read voltage to the word line connected to the storage cell pair; and determining the output of the neuron based on the conductance difference of the two storage cells in the storage cell pair, the conductance difference as the weight corresponding to the input of the neuron, the output of the neuron is the sum of the current difference of a plurality of storage cell pairs.

9. The operating method of claim 8, wherein, The operation method further comprises: performing a programming operation on at least one storage cell in the storage cell pair to adjust the conductance difference.

10. The operating method of claim 8, wherein, A plurality of the storage strings constitute a storage cell array, the storage cell array includes a plurality of two-dimensional storage cell arrays, a plurality of storage strings in each two-dimensional storage cell array are connected to the same top selection line, and each two-dimensional storage cell array includes the storage cell pair, determining the output of the neuron comprises: determining the output of the neuron corresponding to the storage cell pair located in different two-dimensional storage cell arrays within a predetermined time period.

11. The operating method of claim 9, wherein, A plurality of the storage strings constitute a storage cell array, the storage cell array includes a plurality of two-dimensional storage cell arrays, a plurality of storage strings in each two-dimensional storage cell array are connected to the same top selection line, and each two-dimensional storage cell array includes the storage cell pair, adjusting the conductance difference comprises: adjusting the conductance difference of the storage cell pair located in different two-dimensional storage cell arrays within a predetermined time period.

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