Method of manufacturing trench gate mosfet

Abstract

The application discloses a trench gate MOSFET manufacturing method. The trench gate MOSFET comprises an active region and a terminal region surrounding the active region. The manufacturing method comprises the following steps: forming a shielding dielectric and a terminal dielectric by using a dielectric layer, forming a shielding gate and a terminal conductor by using a first conductive layer, and forming a control gate and a gate dielectric, wherein the gate dielectric and the shielding dielectric are respectively located on the upper inner wall and the lower inner wall of a first groove, and the control gate and the shielding gate are respectively filled in the upper space and the lower space of the first groove. The part of the dielectric layer on the epitaxial layer is sequentially thinned and first etched, so as to separate the dielectric layer into the shielding dielectric and the terminal dielectric, and the shielding dielectric is second etched to reach the height corresponding to the top end of the shielding gate. The manufacturing method can improve the voltage resistance performance, product yield and reliability of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to semiconductor technology, and more particularly, to a manufacturing method of trench gate MOSFET. BACKGROUND

[0002] Metal oxide semiconductor field effect transistor (MOSFET) has been widely used as a power semiconductor device, for example, as a switch in a power converter. Depending on the current path, power MOSFET can be classified into two types: planar device and vertical device. Trench gate MOSFET is further developed on the basis of vertical structure MOSFET.

[0003] Trench gate MOSFET includes a trench formed in an active region. In the active region, the upper and lower parts of the trench form a control gate and a shield gate, respectively. The control gate is located above the shield gate, and the two are separated by an insulating layer. A gate dielectric is formed on the inner wall of the upper part of the trench, and the control gate and the gate dielectric form a gate stack, so that the channel region adjacent to the trench and extending vertically can be controlled. A shielding dielectric is formed on the inner wall of the lower part of the trench, and the shielding gate provides additional electric field control capability via the shielding dielectric to achieve charge balance. Therefore, in the active region, the trench gate MOSFET can maintain a substantially uniform electric field in the drift region by using the shielding gate to increase the breakdown voltage of the device. Under the same breakdown voltage, the drift region of the trench gate MOSFET can have a higher doping concentration, so that the trench gate MOSFET can reduce the on-resistance while having faster switching speed and lower switching loss.

[0004] The trench MOSFFET can also include a trench formed in a termination region. In the termination region, a termination dielectric is formed on the inner wall of the trench, and a termination conductor is filled in the trench. The termination region surrounds the active region for achieving charge balance at the edge of the active region. Therefore, the trench gate MOSFET can maintain a substantially uniform electric field in the drift region by using the termination region to increase the breakdown voltage of the device.

[0005] However, the manufacturing method of the existing trench gate MOSFET is prone to cause structural defects in the shield gate of the active region and the termination dielectric of the termination region during the process. Therefore, it is desirable to further improve the manufacturing method of the trench gate MOSFET to improve the voltage withstanding performance, product yield and reliability of the device. SUMMARY

[0006] Therefore, the purpose of the present application is to provide a manufacturing method of trench gate MOSFET, which adopts the way of etching the dielectric layer multiple times to avoid over-etching of the termination dielectric of the termination region, and forms a photoresist mask in the trench of the active region to protect the end topography of the shield gate, thereby improving the voltage withstanding performance, product yield and reliability of the device.

[0007] According to an aspect of the present application, there is provided a manufacturing method of a trench gate MOSFET, the trench gate MOSFET comprising an active region and a termination region surrounding the active region, the manufacturing method comprising:

[0008] forming a plurality of trenches extending from a surface of a semiconductor substrate to an interior of the semiconductor substrate, the semiconductor substrate comprising a stacked semiconductor substrate and an epitaxial layer, the plurality of trenches comprising a first trench located in the active region and a second trench located in the termination region;

[0009] forming a shielding dielectric and a termination dielectric using a dielectric layer, the shielding dielectric being located on an inner wall of a lower portion of the first trench, the termination dielectric being located on an inner wall of the second trench;

[0010] forming a shielding gate and a termination conductor using a first conductive layer, the shielding gate filling a space of a lower portion of the first trench, the termination conductor filling a space of an interior of the first trench; and

[0011] forming a control gate and a gate dielectric on an upper portion of the first trench, the gate dielectric being located on an inner wall of an upper portion of the first trench, the control gate filling a space of an upper portion of the first trench,

[0012] wherein the step of forming the shielding dielectric and the termination dielectric comprises sequentially thinning and first etching a portion of the dielectric layer located on the epitaxial layer, thereby separating the dielectric layer into the shielding dielectric and the termination dielectric, and second etching the shielding dielectric to a height corresponding to a top end of the shielding gate.

[0013] Preferably, the second etching has the same selectivity as the first etching, and an etching rate of the second etching is greater than an etching rate of the first etching.

[0014] Preferably, the etching rate of the second etching is more than 10 times the etching rate of the first etching.

[0015] Preferably, the second etching uses a buffered oxide etchant, and the first etching uses a hydrofluoric acid solution.

[0016] Preferably, the portion of the dielectric layer located on the epitaxial layer is thinned to 30-40 nm.

[0017] Preferably, before the first etching step, a first photoresist mask is formed, the first photoresist mask shielding the termination region and exposing the active region, and the first etching removes a portion of the dielectric layer located on a surface of the epitaxial layer.

[0018] Preferably, in the first etching step, the terminal dielectric comprises a portion between the first photoresist mask and the surface of the epitaxial layer, and the dielectric layer is etched between the first photoresist mask and the surface of the epitaxial layer to form an end of the terminal dielectric, the end of the terminal dielectric being at a distance greater than a predetermined distance from the second trench.

[0019] Preferably, between the first etching step and the second etching step, a second photoresist mask is formed, a first portion of the second photoresist mask shielding the terminal region and exposing the active region, and covering the end of the terminal dielectric.

[0020] Preferably, a second portion of the second photoresist mask at least partially fills the first trench, thereby protecting the surface of the shield gate in the second etching step.

[0021] Preferably, the second etching unidirectionally etches along the inner wall of the trench, and the second etching stops at a height greater than or equal to the top end of the shield gate.

[0022] Preferably, in the first trench, the gate dielectric covers the top end of the shield gate, serving as an insulating layer separating the control gate and the shield gate.

[0023] Preferably, after the step of forming the control gate and the gate dielectric, further comprising:

[0024] forming a body region in the epitaxial layer;

[0025] forming a source region in the body region;

[0026] forming an interlayer dielectric layer above the epitaxial layer and the control gate;

[0027] forming a conductive via in the interlayer dielectric layer;

[0028] forming a source contact on the interlayer dielectric layer, the source contact being electrically connected to the source region via the conductive via; and

[0029] forming a drain contact on the back surface of the semiconductor substrate,

[0030] wherein the body region and the source region are adjacent to the first trench, and the control gate and the body region are separated from each other by the gate dielectric.

[0031] The manufacturing method of the trench gate MOSFET according to the embodiment of the present application divides the single etching for forming the shielding dielectric into a first etching and a second etching, which are performed in sequence. The first etching is used to separate the dielectric layer into the shielding dielectric and the terminal dielectric. The second etching is performed on the shielding dielectric to reach a height corresponding to the top end of the shielding gate. The manufacturing method significantly reduces the undercut of the terminal dielectric end portion by the first etching, and shields the terminal region in the second etching step to protect the terminal dielectric end portion. Thus, the undercut of the terminal dielectric end portion can be prevented from extending into the second trench to form a hole, which causes a short circuit between the control gate and the terminal conductor, thereby improving the voltage resistance performance, product yield and reliability of the device.

[0032] In a preferred embodiment, after the first etching of the dielectric layer, a photoresist mask is reformed. A first part of the photoresist mask shields the terminal region to protect the terminal dielectric end portion, and a second part at least partially fills the second trench to protect the surface of the shielding gate in the second etching step. Due to the shielding effect of the photoresist mask in the second trench, the second etching is unidirectional along the vertical direction of the inner wall of the trench, which is beneficial to accurately control the etching to stop at a height substantially the same as or slightly higher than the shielding gate. Thus, over-etching of the shielding dielectric can be avoided. After the second etching, the top end of the shielding gate is substantially flush with or slightly lower than the top of the shielding dielectric, which has met the structural design requirements of the trench gate MOSFET. Therefore, it is not necessary to further etch the shielding gate by dry etching, and a sharp end of the shielding gate will not be formed in the dry etching step. Thus, the sharp end of the shielding gate can be prevented from causing sharp end discharge to break down the dielectric layer between the control gate and the shielding gate, thereby improving the voltage resistance performance, product yield and reliability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0033] The above and other objects, features and advantages of the present application will become more apparent from the following description of the embodiments of the present application taken with reference to the accompanying drawings, in which:

[0034] Figure 1 shows a schematic cross-sectional view of a trench gate MOSFET;

[0035] Figures 2a to 2c shows a schematic cross-sectional view of main stages of a manufacturing method of a trench gate MOSFET according to the prior art; and

[0036] Figures 3a to 3o shows a schematic cross-sectional view of each stage of a manufacturing method of a trench MOSFET according to an embodiment of the present application. DETAILED DESCRIPTION

[0037] The present application will be described in more detail with reference to the drawings. Like elements in the various drawings are denoted by like reference numerals. Each portion in the drawings is not drawn to scale for the sake of clarity. Further, certain known elements can not be shown. For the sake of simplicity, a semiconductor structure obtained after a number of steps can be described in one drawing.

[0038] It is to be understood that when a layer, a region is referred to as being "on" or "above" another layer, another region, it can be directly on the other layer, the other region or intervening layers or regions can also be present. Also, it is to be understood that when a device is inverted, the layer, the region will be "under" or "below" the other layer, the other region.

[0039] If for the sake of description, a layer, a region is referred to as being "directly on" or "directly above" another layer, another region, the expression "A is directly on B" or "A is directly above B" will be used herein. In the present application, "A is directly in B" means that A is in B and A is directly adjacent to B, not that A is in a doped region formed in B.

[0040] In the present application, the term "semiconductor structure" refers to a collective term for the entire semiconductor structure formed in each step of manufacturing a semiconductor device, including all layers or regions that have been formed.

[0041] Many specific details of the present application are described below in order to provide a thorough understanding of the present application. However, as will be understood by one skilled in the art, the present application can be practiced without many of the specific details.

[0042] The present application can take various forms, some of which will be described below.

[0043] Figure 1 A schematic cross-sectional view of a trench gate MOSFET is shown.

[0044] The trench gate MOSFET 100 has a termination area TA surrounding an active area AA. The trench gate MOSFET 100 includes a plurality of trenches in the active area AA and a plurality of trenches in the termination area TA, and trench structures different from each other are formed in the trenches of the active area AA and the termination area TA.

[0045] The semiconductor substrate 101 is composed of, for example, silicon, and is of a first doping type. The first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type. To form an N-type semiconductor layer or region, N-type dopants (e.g., P, As) can be implanted in the semiconductor layer and region. To form a P-type semiconductor layer or region, P-type dopants (e.g., B) can be implanted in the semiconductor layer and region. In one embodiment, the semiconductor substrate 101 is N+ doped.

[0046] An epitaxial layer 102 of the first doping type is formed on a surface of the semiconductor substrate 101. The epitaxial layer 102 is composed of, for example, silicon. The epitaxial layer 102 is a lightly doped layer with respect to the semiconductor substrate 101. In one embodiment, the epitaxial layer 102 is N- doped.

[0047] A body region 111 of the second doping type is formed in the epitaxial layer 102, and a source region 112 of the first doping type is formed in the body region 111. In one embodiment, the body region 111 is, for example, P- doped, and the source region 112 is, for example, N+ doped.

[0048] A trench extends from a surface of the epitaxial layer 102 into the interior. The trench is formed by, for example, etching the epitaxial layer 102 and the semiconductor substrate 101. Figure 1 In the illustrated embodiment, the trench terminates in the epitaxial layer 102. However, in alternative embodiments, the trench can pass through the epitaxial layer 102 and terminate in the semiconductor substrate 101.

[0049] In the active area AA, a control gate 110 and a shield gate 106 are formed on the upper and lower portions, respectively, of the trench. The control gate 110 is located above the shield gate 106, and the two are separated from each other by an insulating layer. A gate dielectric 109 is formed on the inner wall of the upper portion of the trench, and the control gate 110 and the gate dielectric 109 form a gate stack. A shield dielectric 105 is formed on the inner wall of the lower portion of the trench, and the shield gate 106 and the shield dielectric 105 form a shield stack.

[0050] The control gate 110 and the shield gate 106 are composed of an electrically conductive material, for example, doped polysilicon. The gate dielectric 109 and the shield dielectric 105 are composed of an insulating material, for example, silicon oxide. The thickness of the gate dielectric 109 is, for example, 20 to 100 nanometers, and the thickness of the shield dielectric 105 is, for example, 100 to 1000 nanometers.

[0051] In the present embodiment, the gate dielectric 109 serves as the insulating layer that separates the control gate 110 and the shield gate 106.

[0052] In the termination area TA, a termination dielectric 108 is formed on the inner wall of the trench, and a termination conductor 107 is filled in the trench.

[0053] The terminating conductor 107 is composed of a conductive material, such as doped polycrystalline silicon. The terminating dielectric 108 is composed of an insulating material, such as silicon oxide. The thickness of the terminating dielectric 108 is, for example, 100 to 1000 nanometers.

[0054] An interlayer dielectric layer 113 covers the control gate 110 and the source region 112, and the source contact 121 is connected to the source region 112 via a conductive channel 114 in the interlayer dielectric layer 113. The drain contact 122 is located on the back side of the semiconductor substrate 101.

[0055] The interlayer dielectric layer 113 is composed of an insulating material, such as silicon oxide. The source contact 121, drain contact 122, and conductive channel 114 are composed of a conductive material, such as any metal or alloy like silver, copper, aluminum, titanium, or nickel.

[0056] In the active region AA of the trench gate MOSFET 100, the upper part of the trench is adjacent to the body region 111 and the source region 112, allowing the control gate 110 to control the vertically extending channel region in the body region 111 adjacent to the trench. The lower part of the trench is adjacent to the epitaxial layer 102, and the shielding gate 106 provides additional electric field control capability to achieve charge balance in the drift region of the epitaxial layer 102 via the shielding dielectric 106. In the termination region TA of the trench gate MOSFET 100, the termination conductor 107 provides additional electric field control capability to achieve charge balance in the channel region and drift region of the epitaxial layer 102 via the termination dielectric 108.

[0057] Figures 2a to 2c A schematic cross-sectional view showing the main stages of a trench gate MOSFET manufacturing method according to the prior art.

[0058] exist Figure 2a Prior to the steps shown, a shielding grid 106 has been formed in the trench of the active region, and a terminal conductor 107 has been formed in the trench of the terminal region. Figure 2c Following the portion shown, the gate dielectric 109 and control gate 110 will continue to be formed in the trench of the active region.

[0059] See Figure 2a The photoresist mask PR1 covers the terminal area and exposes the active area. In the active area, a selective first wet etching is performed using the photoresist mask PR1, and a second etching of the shielding gate 106 is performed relative to the dielectric layer 11. The top of the shielding gate 106 is located below the trench opening, so that the shielding gate 106 is located in the lower part of the trench.

[0060] See Figure 2b, the photoresist mask PR1 is still retained. In the active region, a selective second wet etching is performed using the photoresist mask PR1 to remove the exposed portions of the dielectric layer 11 with respect to the epitaxial layer 102 and the shield gate 106. The second wet etching is required to not only remove the portions of the dielectric layer 11 on the surface of the epitaxial layer 102, but also remove the portions of the dielectric layer 11 on the inner walls of the upper portion of the trench. This etching step patterns the dielectric layer 11 to form the shield dielectric 105 on the inner walls of the trench in the active region and the termination dielectric 108 on the inner walls of the trench in the termination region.

[0061] In this etching step, in order to remove the dielectric layer on the inner walls of the upper portion of the trench, a long etching time is used, thus over-etching the dielectric layer 11.

[0062] On the one hand, due to the over-etching of the dielectric layer 11, the top end of the shield dielectric 105 is slightly lower than the top end of the shield gate 106.

[0063] On the other hand, due to the over-etching of the dielectric layer 11, the etchant etches laterally via the end of the photoresist mask PR1 in contact with the dielectric layer 11, and the dielectric layer 11 under the photoresist mask PR1 is undercut. The undercutting of the dielectric layer 11 extends into the trench in the termination region, causing a hole 13 to appear at the top end of the termination dielectric 108. In the subsequent step of forming the control gate, the conductive material of the control gate fills the hole, causing a short circuit between the control gate and the termination conductor.

[0064] Referring to Figure 2c , the photoresist mask PR1 is still retained. In the active region, a first dry etching is performed using the photoresist mask PR1 to etch the shield gate 106 with respect to the shield dielectric 105. The first dry etching is used to reduce the height of the shield gate 106 so that the top end of the shield gate 106 is approximately aligned with the top end of the shield dielectric 105.

[0065] In this etching step, due to the top end of the shield dielectric 105 being slightly lower than the top end of the shield gate 106, the top end and the inner walls of the protruding portion of the shield gate 106 above the shield dielectric 105 are etched at the same time, thus finally forming a sharp tip 14.

[0066] The manufacturing method of the trench gate MOSFET according to the prior art described above produces structural defects in the shield gate in the active region and the termination dielectric in the termination region. In the working state of the trench gate MOSFET, the sharp tip of the shield gate produces a sharp tip discharge, which can break down the dielectric layer between the control gate and the shield gate, and the hole in the termination dielectric also provides a short circuit path between the control gate and the termination conductor, causing the device performance to deteriorate or even fail.

[0067] Figures 3a to 3o Schematic cross-sectional views showing various stages of a manufacturing method of a trench MOSFET according to an embodiment of the present application.

[0068] like Figure 3a As shown, multiple trenches are formed in a semiconductor substrate, which includes a stacked semiconductor substrate 101 and an epitaxial layer 102. A dielectric layer 11 is formed on the surface of the epitaxial layer 102 and in the multiple trenches, and a conductive layer 12 is formed on the dielectric layer 11. The dielectric layer 11 covers the inner walls and bottom of the trenches, and the conductive layer 12 fills the internal space of the trenches.

[0069] The semiconductor substrate 101 is primarily made of, for example, single-crystal silicon, and the epitaxial layer 102 is also primarily made of single-crystal silicon. The epitaxial layer 102 can be formed using known epitaxial growth processes, such as vapor phase epitaxy, liquid phase epitaxy, and molecular beam epitaxy. Both the semiconductor substrate 101 and the epitaxial layer 102 are of a first doping type, and the epitaxial layer 102 is lightly doped relative to the semiconductor substrate 101. In one embodiment, the semiconductor substrate 101 is N+ doped, and the epitaxial layer 102 is N- doped.

[0070] Further, for example, a sacrificial oxide layer (not shown) is formed on the surface of the semiconductor structure. A photoresist layer is then formed on the sacrificial oxide layer, followed by etching. This etching can be performed using dry etching methods such as ion milling, plasma etching, reactive ion etching, laser ablation, or selective wet etching using an etchant solution, etching downwards from an opening in the photoresist mask to form an opening in the sacrificial oxide layer, thereby patterning the sacrificial oxide layer into a hard mask. Due to the selectivity of the etching, the etching can stop at the surface of the epitaxial layer 102. After forming the hard mask, the photoresist layer is removed by dissolving or ashing in a solvent.

[0071] Using a hard mask, the epitaxial layer 102 is further etched using the known etching process described above, thereby forming a trench in the epitaxial layer 102. This trench extends from the surface of the epitaxial layer 102 into the epitaxial layer 102. The depth of the trench can be controlled, for example, by controlling the etching time. In the embodiment shown in FIG2, the trench terminates in the epitaxial layer 102. However, in an alternative embodiment, the trench may extend through the epitaxial layer 102 and terminate in the semiconductor substrate 101. After the trench is formed, the hard mask can be removed relative to the epitaxial layer 102 using a selective etchant.

[0072] Furthermore, a conformal dielectric layer 11 is formed on the surface of the semiconductor structure using known deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). In one embodiment, the dielectric layer 11 is an oxide layer (e.g., silicon oxide) with a thickness of approximately 100 to 1000 nanometers. The dielectric layer 11 covers the surface of the epitaxial layer 102 and the inner walls of the trench. In an alternative embodiment, instead of the deposition process, thermal oxidation can be used to oxidize the exposed portion of the epitaxial layer 102 to form the dielectric layer 11.

[0073] Furthermore, a conductive layer 12 (e.g., doped polysilicon) is formed on the surface of the semiconductor structure using known deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electron beam evaporation (EBM), sputtering, etc.

[0074] like Figure 3b As shown, the conductive layer 12 is planarized to obtain a flat surface.

[0075] In this step, mechanical planarization (e.g., chemical mechanical polishing) is used to remove the portion of the conductive layer 12 located outside the trench. In one embodiment, the mechanical planarization uses the dielectric layer 11 as a stop layer, thereby re-exposing the surface of the dielectric layer 11, with the conductive layer 12 flush with the surface of the dielectric layer 11. In an alternative embodiment, by controlling the processing time, the mechanical planarization removes a portion of the conductive layer 12, thereby thinning the conductive layer 12 so that its surface is slightly higher than the surface of the dielectric layer 11, i.e., a thin layer of the conductive layer 12 is still retained outside the trench.

[0076] If the conductive layer 12 formed by deposition has the desired surface flatness, the planarization step can be omitted. If a thin layer of conductive layer 12 remains outside the trench after planarization, the portion of conductive layer 12 outside the trench can be removed in a subsequent second etching step.

[0077] After removing the portion of the conductive layer 12 located outside the trench, the remaining portion of the conductive layer 12 located in the active region trench forms a shielding gate 106, and the remaining portion located in the terminal region trench forms a terminal conductor 107.

[0078] like Figure 3c As shown, a second etching is performed on the shielding gate 106 and the terminal conductor 107 to reduce the height of the conductive layer.

[0079] In this step, a selective etchant is used for wet etching to remove a portion of the shielding gate 106 and the terminating conductor 107 relative to the dielectric layer 11. By controlling the etching time, the height of the shielding gate 106 and the terminating conductor 107 can be controlled so that the tops of the shielding gate 106 and the terminating conductor 107 are flush with or slightly lower than the epitaxial layer surface 102.

[0080] like Figure 3d As shown, the dielectric layer 11 is planarized to reduce the thickness of the dielectric layer.

[0081] In this step, mechanical planarization (e.g., chemical mechanical polishing) is used to remove a portion of the dielectric layer 11. The dielectric layer 11 is thinned by controlling the processing time. The surface of the dielectric layer 11 is slightly higher than the surface of the epitaxial layer 102; that is, a thin layer of the dielectric layer 11 is still retained outside the trenches (the portion located on the epitaxial layer). For example, the thickness of this thin layer of the dielectric layer 11 is reduced from 600 nanometers to 30 to 40 nanometers.

[0082] like Figure 3e As shown, a photoresist mask PR1 is formed to block the trenches in the terminal area.

[0083] In this step, a known photolithography process is used to coat a semiconductor structure with photoresist, expose and develop it, forming an opening pattern in the photoresist layer to form a photoresist mask. The photoresist mask PR1 covers the terminal region and exposes the active region.

[0084] like Figure 3f As shown, the shielding gate 106 is etched a second time to reduce the height of the shielding gate.

[0085] In this step, a selective etchant is used for wet etching to remove a portion of the shielding gate 106 relative to the dielectric layer 11. By controlling the etching time, the height of the shielding gate 106 can be controlled, thereby obtaining the upper trench space corresponding to the design parameters of the control gate. After this second etching step, the portion of the dielectric layer 11 located above the trench is exposed again.

[0086] like Figure 3g As shown, the dielectric layer 11 is first etched to remove the portion of the dielectric layer 11 located outside the trench.

[0087] The aforementioned Figure 3d In the steps shown, mechanical planarization is used to thin the dielectric layer 11, and the portion of the dielectric layer 11 located outside the trench has a thickness of approximately 30 to 40 nanometers.

[0088] In this step, the first etching is used to remove the portion of the dielectric layer 11 outside the trench. For example, a solution of hydrofluoric acid with a volume ratio of 80-120: 1 is used as the etchant, and the etching rate is 29±3 angstroms per minute. The etching time is set according to the thickness of the dielectric layer 11, for example, the etching time of about 10-15 minutes can be used to remove the dielectric layer with a thickness of about 300-450 angstroms. Due to the selectivity of the etchant, the dielectric layer 11 is removed relative to the epitaxial layer 102. Due to the first etching characteristics of the etchant (i.e., the etching rate is small), by controlling the etching time, the portion of the dielectric layer 11 outside the trench can be completely removed.

[0089] After removing the portion of the dielectric layer 11 outside the trench, the remaining portion of the dielectric layer 11 in the active region trench forms a shielding dielectric 105, and the remaining portion of the dielectric layer 11 in the termination region trench forms a termination dielectric 108.

[0090] Further, since the portion of the shielding dielectric 105 inside the active region trench has a thickness of about 600 nanometers, only a small amount is removed in the etching step, and thus it remains on the upper portion of the active region trench. Due to the protection of the photoresist mask PR1, the termination dielectric 108 in the termination region trench is not affected by etching.

[0091] Further, the etchant used in the first etching etches laterally through the end of the epitaxial layer 102 in contact with the photoresist mask PR1, and the undercut 13 occurs to the dielectric layer 11 under the photoresist mask PR1. However, since the dielectric layer 11 has been previously thinned, and the first etching only needs to remove the thin layer of the dielectric layer 11 on the surface of the epitaxial layer 102, both the etching rate and the etching time are significantly reduced. Therefore, the lateral extension of the etchant is difficult to reach the termination region trench, and the end of the termination dielectric formed by the undercut at the end of the first photoresist mask is greater than a predetermined distance from the termination region trench. Only a very small gap is formed under the end of the photoresist mask PR1 (or the end of the photoresist mask PR1 is suspended), and the termination dielectric in the termination region trench is not affected by etching.

[0092] Further, since the undercut in the first etching step has damaged the coverage ability of the photoresist mask PR1 to a certain extent, a new photoresist mask needs to be formed to shield the termination region in the subsequent steps.

[0093] In this embodiment, after the first etching, the photoresist mask PR1 is removed by dissolving or ashing in a solvent. In an alternative embodiment, the photoresist mask PR1 can be retained to form a mask stack with the subsequently formed photoresist mask to shield the termination region.

[0094] As Figure 3h and 3iThe photoresist mask PR2 is formed to cover the trench of the termination region.

[0095] In this step, a known photolithography process is used to form an opening pattern in the photoresist layer to form a photoresist mask. The photoresist mask PR2 covers the termination region and exposes the active region.

[0096] Unlike the photoresist mask PR1, the photoresist mask PR2 completely covers the end of the dielectric layer on the surface of the epitaxial layer 102, thus effectively avoiding the undercut of the end of the dielectric layer in the subsequent etching step. By controlling the exposure time in the photolithography process, or alternatively, using a gray-tone mask plate for exposure, a portion of the photoresist mask PR2 remains in the active region trench and exposes the surface of the epitaxial layer outside the active region. The photoresist mask PR2 can either fill the active region trench or partially fill the active region trench, as long as it serves to shield the shield gate 106 in the active region trench.

[0097] As shown in FIG. 2B, the photoresist mask PR2 is formed to cover the trench of the termination region. Figure 3j and 3k As shown in FIG. 2B, the photoresist mask PR2 is formed to cover the trench of the termination region.

[0098] In this step, a selective etchant is used for wet etching to remove a portion of the shield dielectric relative to the epitaxial layer 102 and the shield gate 106. Thus, by controlling the etching time, the etching stops at approximately the same height or slightly higher than the shield gate 106, thereby obtaining a space above the trench corresponding to the design parameters of the control gate.

[0099] In this embodiment, the shielding effect of the photoresist mask PR2 in the active region trench plays an important role in improving the morphology of the shield gate 106. On the one hand, due to the shielding effect of the photoresist mask PR2, the second etching of the shield dielectric 105 mainly extends vertically downward along the inner wall of the trench, without lateral etching. The use of one-way vertical etching is beneficial to accurately control the position of the etching stop, which stops at approximately the same height or slightly higher than the shield gate 106, thus avoiding over-etching of the shield dielectric 105. On the other hand, due to the shielding effect of the photoresist mask PR2 in the active region trench, the end of the shield gate 106 can still maintain a flat surface and will not form a sharp tip due to etching.

[0100] In this embodiment, a BOE solution (i.e., an abbreviation of "buffered oxide etchant") is used as the etchant. The second etching of the shield gate 106 has the same etching selectivity as the first etching of the dielectric layer 11, but the etching rate of the second etching of the shield gate 106 is more than 10 times the etching rate of the first etching of the dielectric layer 11. Through repeated experiments and verifications by the inventors, the etching conditions are set as follows: the volume ratio of ammonium fluoride to hydrofluoric acid is 7:1, and the etching rate is 910±10 angstroms per minute. The etching conditions can achieve a relatively accurate etching effect. The etching time is set according to the height of the shielding dielectric 105 to be controlled, for example, the rinse time of about 12 to 13 minutes can remove the dielectric material with a height of about 1.1 to 1.2 microns.

[0101] After the second etching of the shielding dielectric 105, the top end of the shield gate 106 is substantially flush with or slightly lower than the top of the shielding dielectric 105, which has met the structural design requirements of the trench gate MOSFET. Therefore, the manufacturing method of the trench gate MOSFET according to the present embodiment does not need to further use the dry etching step to etch the shield gate 106, and the tip of the shield gate 106 will not be formed in the dry etching step. Figure 2c

[0102] After the second etching of the shielding dielectric 105, the photoresist mask PR2 is removed by dissolving or ashing in a solvent.

[0103] As shown in FIG. 1C, a gate dielectric 109 is formed in the upper portion of the active region trench. Figure 3l

[0104] In this step, a conformal dielectric layer is formed on the surface of the semiconductor structure as the gate dielectric 109 by the deposition process known in the art. In one embodiment, the gate dielectric 109 is composed of an insulating material, for example, silicon oxide. The thickness of the gate dielectric 109 is, for example, 20 to 100 nanometers. The gate dielectric 109 covers the surface of the epitaxial layer 102 and the inner wall in the upper portion of the active region trench. In an alternative embodiment, instead of the deposition process, the exposed portion of the epitaxial layer 102 is oxidized to form the gate dielectric 109 by thermal oxidation.

[0105] In this embodiment, the gate dielectric 109 also serves as an insulating layer separating the control gate 110 and the shield gate 106.

[0106] As shown in FIG. 1C, a gate dielectric 109 is formed in the upper portion of the active region trench. Figure 3m 3n As shown in FIG. 1C, a gate dielectric 109 is formed in the upper portion of the active region trench.

[0107] ​​​In this step, a conductive layer 15 (e.g., doped polysilicon) is formed on the surface of the semiconductor structure by a known deposition process described above. The conductive layer 15 covers the surface of the gate dielectric 109 and fills the active region trench. A portion of the conductive layer 15 is removed with respect to the gate dielectric 109 using a selective etchant in a wet etch process. By controlling the etch time, the portion of the conductive layer 15 outside the active region trench can be removed so that the portion of the conductive layer 15 filling the active region trench forms a control gate 110. The top end of the control gate 110 is flush with or slightly below the epitaxial layer surface 102.

[0108] As shown in FIG. 1C, a source region of the trench gate MOSFET and a corresponding source / drain contact are formed. Figure 3o A first ion implantation is performed to form a body region 111 of a second doping type in the epitaxial layer 102 using a conventional implantation technique. In one embodiment, the body region 111 is P-doped. Further, a second ion implantation is performed to form a source region 112 of a first doping type in the body region 111 using a conventional source implant. In one embodiment, the source region is N+-doped. By controlling the parameters of the ion implantation, such as implant energy and dose, a desired depth and a desired doping concentration can be achieved. Using an additional photoresist mask, the lateral extension of the body region 111 and the source region 112 can be controlled. In a preferred embodiment, the body region 111 and the source region 112 are respectively adjacent to the active region trench, and the control gate 110 is separated from the body region 111 and the source region 112 by the gate dielectric 109.

[0109] Subsequently, an interlayer dielectric layer 113 is formed on the surface of the semiconductor structure by a known deposition process described above, and if desired, further planarized (e.g., chemical mechanical polishing) to obtain a flat surface. The interlayer dielectric layer 113 covers the top surface of the source region 112 and the control gate 110.

[0110] Subsequently, a photoresist mask is formed, for example, on the surface of the semiconductor structure. The interlayer dielectric layer 113 is patterned to form a via hole to the source region 112 by an etching process described above. Further, a third conductor layer is formed by a known deposition process described above to at least fill the via hole. Then, using the interlayer dielectric layer 113 as a stop layer, a mechanical planarization (e.g., chemical mechanical polishing) is performed to remove the portion of the third conductor layer outside the via hole, forming an electrically conductive via to the source region 112. Further, a source contact 121 is formed on the interlayer dielectric layer 113 by a known deposition process described above. Further, a drain contact 122 is formed on the surface of the semiconductor substrate 101 opposite to the surface of the epitaxial layer 102 by a known deposition process described above.

[0111]

[0112] ​In the above description, the patterning, etching, and other technical details of each layer are not described in detail. However, those skilled in the art should understand that the layers, regions, and the like with desired shapes can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0113] It should be noted that the relational terms herein such as first and second and the like are used solely to distinguish one from another entity or action, without necessarily requiring or implying any actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, an element defined by an "including a" does not exclude the existence of additional identical or similar elements in the process, method, article, or apparatus that includes the element.

[0114] In accordance with the embodiments of the present application as described above, these embodiments do not describe all the details of the application, nor limit the application to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above description. The description of the embodiments is chosen and described in order to explain the principles of the application and its practical application, so that those skilled in the art can well use the application and make modifications and use on the basis of the application. The application is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a trench-gate MOSFET, the trench-gate MOSFET comprising an active region and a termination region surrounding the active region, the method comprising: forming a plurality of trenches extending from a surface of a semiconductor substrate to an interior of the semiconductor substrate, the semiconductor substrate comprising a semiconductor substrate and an epitaxial layer stacked, the plurality of trenches comprising a first trench in the active region and a second trench in the termination region; forming a shielding dielectric and a termination dielectric using a dielectric layer, the shielding dielectric being on an inner wall of a lower portion of the first trench, the termination dielectric being on an inner wall of the second trench; forming a shielding gate and a termination conductor using a first conductive layer, the shielding gate filling a space of a lower portion of the first trench, the termination conductor filling a space of an interior of the first trench; and forming a control gate and a gate dielectric on an upper portion of the first trench, the gate dielectric being on an inner wall of an upper portion of the first trench, the control gate filling a space of an upper portion of the first trench, wherein the step of forming the shielding dielectric and the termination dielectric comprises sequentially thinning and first etching a portion of the dielectric layer on the epitaxial layer to separate the dielectric layer into the shielding dielectric and the termination dielectric, and second etching the shielding dielectric to a height corresponding to a top end of the shielding gate; before the first etching step, forming a first photoresist mask that shields the termination region and exposes the active region; the first etching removes a portion of the dielectric layer on a surface of the epitaxial layer; in the first etching step, the termination dielectric comprises a portion between the first photoresist mask and the surface of the epitaxial layer, and the dielectric layer is undercut between the first photoresist mask and the surface of the epitaxial layer to form an end of the termination dielectric, the end of the termination dielectric being at a distance greater than a predetermined distance from the second trench; between the first etching step and the second etching step, forming a second photoresist mask, a first portion of the second photoresist mask shielding the termination region and exposing the active region, and covering the end of the termination dielectric; a second portion of the second photoresist mask at least partially filling the first trench to protect a surface of the shielding gate in the second etching step. The second etching has the same selectivity as the first etching, and the etching rate of the second etching is greater than the etching rate of the first etching.

2. The manufacturing method according to claim 1, wherein, The etching rate of the second etching is more than 10 times the etching rate of the first etching.

3. The manufacturing method according to claim 2, wherein, The second etching uses a buffered oxide etchant, and the first etching uses a hydrofluoric acid solution.

4. The manufacturing method according to claim 3, wherein, The portion of the dielectric layer on the epitaxial layer is thinned to 30-40 nm.

5. The manufacturing method according to claim 1, wherein, The second etching unidirectionally etches along the inner wall of the trench, and the second etching stops at a height greater than or equal to the top end of the shielding gate.

6. The production method according to claim 1, wherein In the first trench, the gate dielectric covers the top end of the shielding gate, and serves as an insulating layer separating the control gate and the shielding gate.

7. The production method according to claim 1, wherein ​ 8. The manufacturing method of claim 1, further comprising after the step of forming the control gate and the gate dielectric: forming a body region in the epitaxial layer; forming a source region in the body region; forming an interlayer dielectric layer over the epitaxial layer and the control gate; forming a conductive via in the interlayer dielectric layer; forming a source contact on the interlayer dielectric layer, the source contact electrically connected to the source region via the conductive via; and forming a drain contact on a backside of the semiconductor substrate, wherein the body region and the source region are adjacent to the first trench, and the control gate is separated from the body region by the gate dielectric.

9. The manufacturing method of claim 1, further comprising after the step of forming the control gate and the gate dielectric: forming a body region in the epitaxial layer; forming a source region in the body region; forming an interlayer dielectric layer over the epitaxial layer and the control gate; forming a conductive via in the interlayer dielectric layer; forming a source contact on the interlayer dielectric layer, the source contact electrically connected to the source region via the conductive via; and forming a drain contact on a backside of the semiconductor substrate, wherein the body region and the source region are adjacent to the first trench, and the control gate is separated from the body region by the gate dielectric.

10. The manufacturing method of claim 1, further comprising after the step of forming the control gate and the gate dielectric: forming a body region in the epitaxial layer; forming a source region in the body region; forming an interlayer dielectric layer over the epitaxial layer and the control gate; forming a conductive via in the interlayer dielectric layer; forming a source contact on the interlayer die

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