Contact for stranded conductive wire within a memory array

Abstract

This application relates to contacts for stranded conductive lines within a memory array. Apparatus, systems, and methods for forming stranded conductive lines are described herein. One method includes forming a first and second row of a first number of vertical conductive line contacts, the conductive line contacts in each row aligned in a first horizontal direction, and the first row spaced apart from the second row in a second horizontal direction; forming a number of conductive lines having a curved portion, each conductive line contacting alternating conductive line contacts of the first and second row of the first number of vertical conductive line contacts; and forming a second number of conductive lines having one or more curved portions, each conductive line contacting remaining ones of the conductive line contacts of the first and second row of the first number of vertical conductive line contacts not contacted by the first number of conductive lines.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to memory devices, and more particularly to forming contacts for twisted conductive lines within a vertically stacked array of memory cells of a three-dimensional (3D) semiconductor memory device. BACKGROUND

[0002] Memory is typically implemented in electronic systems such as computers, cellular phones, handheld devices, etc. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), and synchronous dynamic random access memory (SDRAM). Non-volatile memory can provide persistent data by retaining stored data when unpowered and can include NAND flash memory, NOR flash memory, nitride read-only memory (NROM), phase change memory (e.g., phase change random access memory), resistive memory (e.g., resistive random access memory), cross point memory, ferroelectric random access memory (FeRAM), etc.

[0003] As design rules shrink, less semiconductor space is available for fabricating memory including DRAM arrays. A corresponding memory cell for a DRAM can include an access device, such as a transistor, having first and second source / drain regions separated by a channel region. A gate can be opposite the channel region and separated from the channel region by a gate dielectric. An access line, such as a word line, is electrically connected to the gate of the DRAM cell. The DRAM cell can include a storage node, such as a capacitor cell, coupled to the access device. The access device can be activated (e.g., to select the cell) by the access line coupled to the access transistor. The capacitor can store a charge corresponding to a data value (e.g., a logic "1" or "0") for the corresponding cell. SUMMARY

[0004] In one aspect, the application provides a method for forming conductive lines within a vertically stacked array of memory cells, comprising: forming a first row and a second row of a first number of vertical conductive line contacts, wherein the vertical contacts in each row are aligned in a first horizontal direction, and the first row is spaced apart from the second row in a second horizontal direction; forming a first number of conductive lines having one or more curved portions, each conductive line contacting alternating ones of the conductive line contacts of the first row and the second row of the first number of vertical conductive line contacts; and forming a second number of conductive lines having one or more curved portions, each conductive line contacting remaining ones of the conductive line contacts of the first row and the second row of the first number of vertical conductive line contacts that are not contacted by the first number of conductive lines.

[0005] In another aspect, the application provides a method for forming conductive lines within a vertically stacked array of memory cells, comprising: forming a number of tiers, each tier comprising at least one of a conductive material and a dielectric material; forming a first and a second row of a first number of vertically oriented conductive line contacts, wherein the conductive contacts in each row are arranged in a first horizontal direction, and the first row is spaced apart from the second row in a second horizontal direction; forming a first number of horizontally oriented conductive lines having one or more curved portions, each conductive line contacting alternating ones of the conductive line contacts of the first and second rows of the first number of vertically conductive line contacts and one or more of the number of tiers; and forming a second number of conductive lines having one or more curved portions, each conductive line contacting remaining ones of the conductive line contacts of the first and second rows of the first number of vertically conductive line contacts not contacted by the first number of conductive lines.

[0006] In yet another aspect, the application provides a semiconductor memory device, comprising: a vertically stacked array of memory cells comprising: a horizontal array of conductive line contacts, wherein: a first and a second row of a first number of vertically conductive line contacts are arranged in a first horizontal direction, and the first row is spaced apart from the second row in a second horizontal direction; a first horizontal conductive line having one or more curved portions contacts alternating ones of the conductive line contacts of the first and second rows of the first number of vertically conductive line contacts; and a second horizontal conductive line above the first conductive line having one or more curved portions, each conductive line contacting remaining ones of the conductive line contacts of the first and second rows of the first number of vertically conductive line contacts not contacted by the first horizontal conductive line. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1A is a schematic illustration of a vertical three-dimensional (3D) memory according to embodiments of the present disclosure.

[0008] Figure 1B is a perspective view of a portion of a digit line and body contact for a semiconductor device according to embodiments of the present disclosure.

[0009] Figure 2A is a schematic illustration of a vertical three-dimensional (3D) memory according to embodiments of the present disclosure.

[0010] Figure 2B is a perspective view of a portion of a three-node access device in a vertical three-dimensional (3D) memory array according to embodiments of the present disclosure.

[0011] Figure 3To illustrate a perspective view of a portion of a three-node access device in a vertical three-dimensional (3D) memory cell according to embodiments of the present disclosure.

[0012] Figure 4 An example process for generating a single-crystalline silicon stack for a vertical three-dimensional (3D) memory according to embodiments of the present disclosure is described.

[0013] Figures 5A-5B A portion of a semiconductor memory device having a plurality of contacts of twisted conductive lines according to one or more embodiments of the present disclosure is described.

[0014] Figures 6A-6I A process of forming twisted conductive lines for a semiconductor memory device according to one or more embodiments of the present disclosure is described.

[0015] Figure 7 A block diagram of an apparatus in the form of a computer system including a memory device according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0016] Embodiments of the present disclosure describe contacts for twisted conductive lines within a memory array.

[0017] In vertically stacked memory array structures, it can be advantageous to place one or more conductive lines (e.g., bit lines, word lines, access lines, digit lines) near another conductive line to relax spatial constraints. This also allows for improved contact patterns for vertical contacts that connect the conductive lines to underlying circuitry, such as a sense amplifier. However, doing so often results in parasitic capacitance between the two conductive lines, which in turn causes noise experienced by the sense portion of the semiconductor memory device (e.g., the sense amplifier). Forming the conductive lines in a twisted manner can reduce such capacitance and noise. However, it can be challenging to minimize the space between twisted conductive lines formed in this manner.

[0018] However, as disclosed in embodiments of the present disclosure, it is possible to form twisted conductive lines using a space-minimizing approach, thus improving the overall design of the semiconductor memory device. For example, the distance between conductive line contacts in a horizontal direction can be reduced. Embodiments of the present disclosure describe systems, methods, and apparatuses for relaxing spatial constraints of a portion of a semiconductor memory device when forming twisted conductive lines.

[0019] This can be accomplished, for example, by first forming a number of horizontal rows of vertical lower conductive contacts, where each pair of rows is similar to a curved or sinusoidal shape, and forming a lower conductive line on each pair of horizontal rows. A dielectric material can then be deposited over and around the lower conductive lines and selectively etched and filled to form rows of upper conductive contacts aligned with the pairs of rows of lower conductive contacts. The length of the upper conductive contacts can be longer than the length of the lower conductive contacts. Thus, the conductive lines formed on the upper conductive contacts can be over the lower conductive lines that have been formed.

[0020] Advantages of the systems, devices and methods described herein can include less spatial constraints, improved accuracy in conductive line formation, and reduced noise.

[0021] The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number and the remaining digits identify the elements or components in the figure. Similar elements or components between different figures can be identified by the use of similar digits. For example, element 104 can be referred to as element "04" in Figure 2A , and similar elements can be indicated as 204 in Figure 2B . Multiple similar elements between different figures can be referred to by suffixing the element number with a dash and a second number or letter. For example, 302-1 can refer to element 302-1 in Figure 3 , and 302-2 can refer to element 302-2, which can be similar to element 302-1. Such similar elements can generally be referred to without the suffix, e.g., 302-1 and 302-2, or other similar elements, can generally be referred to as 302.

[0022] Figure 1A Block diagram of a device according to embodiments of the disclosure. Figure 1A Circuit diagram illustrating a cell array of a three-dimensional (3D) semiconductor memory device according to embodiments of the disclosure. Figure 1A The cell array can have a plurality of sub-cell arrays 101-1, 101-2,..., 101-N. The sub-cell arrays 101-1, 101-2,..., 101-N can be arranged along a second direction (D2) 105. Each of the sub-cell arrays, e.g., sub-cell array 101-2, can include a plurality of access lines 107-1, 107-2,..., 107-Q (which can also be referred to as word lines). Further, each of the sub-cell arrays, e.g., sub-cell array 101-2, can include a plurality of digit lines 103-1, 103-2,..., 103-Q (which can also be referred to as bit lines, data lines, or readout lines). In Figure 1AIn particular, it is noted that access lines 107-1, 107-2,..., 107-Q extend in a first direction (D1) 109, and that digit lines 103-1, 103-2,..., 103-Q extend in a third direction (D3) 111. According to embodiments, the first direction (D1) 109 and the second direction (D2) 105 can be considered to be in a horizontal ("X-Y") plane. The third direction (D3) 111 can be considered to be in a vertical ("Z") plane. Thus, according to embodiments described herein, digit lines 103-1, 103-2,..., 103-Q extend in a vertical direction, such as the third direction (D3) 111.

[0023] A memory cell, such as 110, can include an access device, such as an access transistor, and a storage node at an intersection of each access line 107-1, 107-2,..., 107-Q and each digit line 103-1, 103-2,..., 103-Q. Access lines 107-1, 107-2,..., 107-Q and digit lines 103-1, 103-2,..., 103-Q can be used to write to or read from a memory cell. Access lines 107-1, 107-2,..., 107-Q can conductively interconnect memory cells along horizontal rows of each subcell array 101-1, 101-2,..., 101-N, and digit lines 103-1, 103-2,..., 103-Q can conductively interconnect memory cells along vertical columns of each subcell array 101-1, 101-2,..., 101-N. One memory cell, such as 110, can be located between one access line, such as 107-2, and one digit line, such as 103-2. Each memory cell can be uniquely addressed via a combination of access lines 107-1, 107-2,..., 107-Q and digit lines 103-1, 103-2,..., 103-Q.

[0024] Access lines 107-1, 107-2,..., 107-P can be or include conductive patterns (e.g., metal lines) disposed on and spaced apart from a substrate. Access lines 107-1, 107-2,..., 107-Q can extend in the first direction (D1) 109. Access lines 107-1, 107-2,..., 107-Q in one subcell array, such as 101-2, can be spaced apart from one another in a vertical direction, such as the third direction (D3) 111.

[0025] Digit lines 103-1, 103-2,..., 103-Q can be or include conductive patterns (e.g., metal lines) extending in a vertical direction with respect to a substrate, such as the third direction (D3) 111. Digit lines in one subcell array, such as 101-2, can be spaced apart from one another in the first direction (D1) 109.

[0026] For example, the gate of a memory cell in memory cell 110 may be connected to an access line, such as 107-2, and a first conductive node of a first source / drain region of an access device, such as a transistor, in memory cell 110 may be connected to a digital line, such as 103-2. Each of the memory cells, such as memory cell 110, may be connected to a storage node, such as a capacitor. A second conductive node of a second source / drain region of an access device, such as a transistor, in memory cell 110 may be connected to a storage node, such as a capacitor. Although the references to first and second source / drain regions are used herein to designate two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as “first” and / or “second” have a particular meaning. It is only intended that one of the source / drain regions is connected to a digital line, such as 103-2, and the other may be connected to a storage node.

[0027] Figure 1B This illustration depicts a three-dimensional (3D) semiconductor memory device according to some embodiments of the present disclosure, such as... Figure 1A The sub-cell array 101-2 shown is a perspective view of the vertically oriented stacking of memory cells in the array.

[0028] like Figure 1B As shown, substrate 100 may have a bonding formed thereon. Figure 1A One of the described arrays of sub-cells, such as 101-2. For example, substrate 100 may be or include a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc. However, the embodiments are not limited to these examples.

[0029] like Figure 1B As shown in the example embodiments, a vertically oriented stack of memory cells extending in, for example, a third vertical direction (D3) 111 can be fabricated on the substrate 100, such as... Figure 1A The memory cell 110 in the memory. According to some embodiments, the vertically oriented stacking of the memory cells can be manufactured such that each memory cell, for example Figure 1A The memory cells 110 are formed in multiple vertical levels, such as a first level (L1), a second level (L2), and a third level (L3). Repeating vertical levels L1, L2, and L3 can be arranged along, for example... Figure 1AThe vertical arrangement of the third direction (D3) 111, e.g., "stacking," shown in FIG. 1 1 1 can be separated from the substrate 100 by an insulator material 120. Each of the repeating vertical levels LI, L2, and L3 can include a plurality of discrete components, e.g., regions, of horizontally oriented access devices 130, e.g., transistors, and storage nodes, e.g., capacitors, including access line 107-1, 107-2,..., 107-Q connections and digit line 103-1, 103-2,..., 103-Q connections. The plurality of discrete components of horizontally oriented access devices 130, e.g., transistors, can be formed in a plurality of iterations of vertically repeating layers within each level, as described below in connection with FIGS. 1 1 1-1 15. Figure 4 More particularly described, and as can be similarly described in connection with Figure 1A extend horizontally in the second direction (D2) 105 shown in FIG. 1 05.

[0030] The plurality of discrete components of laterally oriented access devices 130, e.g., transistors, can include a first source / drain region 121 and a second source / drain region 123 laterally extending in the second direction (D2) 105 and formed in a body of the access device, separated by a channel region 125. In some embodiments, the channel region 125 can include silicon, germanium, silicon germanium, and / or indium gallium zinc oxide (IGZO). In some embodiments, the first source / drain region 121 and the second source / drain region 123 can include n-type dopant regions formed in a p-type doped body of the access device to form an n-type conductivity transistor. In some embodiments, the first source / drain region 121 and the second source / drain region 123 can include p-type dopants formed within an n-type doped body of the access device to form a p-type conductivity transistor. By way of example, but not by way of limitation, the n-type dopant can include phosphorus (P) atoms, and the p-type dopant can include boron (B) atoms formed in an oppositely doped body region of a polysilicon semiconductor material. However, embodiments are not limited to these examples.

[0031] The storage nodes 127, e.g., capacitors, can be connected to one respective end of the access devices. As Figure 1B As shown in FIG. 1 1 1, the storage nodes 127, e.g., capacitors, can be connected to the second source / drain region 123 of the access devices. The storage nodes can be or include memory elements capable of storing data. Each of the storage nodes can be a memory element using one of a capacitor, a magnetic tunnel junction pattern, and / or a variable resistance body including a phase change material, etc. However, embodiments are not limited to these examples. In some embodiments, each access device associated with a unit cell of memory cells 1 10, e.g., in FIG. 1 05, can similarly extend in the second direction (D2) 105 similar to Figure 1A The storage nodes associated with each access device of a unit cell of memory cells 1 10, e.g., in FIG. 1 05, can similarly extend in the second direction (D2) 105 similar to Figure 1A The storage nodes 127, e.g., capacitors, can extend in the second direction (D2) 105 shown in FIG. 1 05.

[0032] As shown in Figure 1B The plurality of horizontally oriented access lines 107-1, 107-2,..., 107-Q extend in a first direction (D1) 109 similar to the first direction (D1) 109 in Figure 1A The plurality of horizontally oriented access lines 107-1, 107-2,..., 107-Q can be similar to the access lines 107-1, 107-2,..., 107-Q shown in Figure 1A The plurality of horizontally oriented access lines 107-1, 107-2,..., 107-Q can be similar to the access lines 107-1, 107-2,..., 107-Q shown in

[0033] Within each of the vertical levels (LI) 113-1, (L2) 113-2, and (L3) 113-P, for example Figure 1A The horizontally oriented memory cells of the memory cells 110 in can be horizontally spaced apart from one another in the first direction (D1) 109. However, the plurality of discrete components of the horizontally oriented access devices 130 extending laterally in the second direction (D2) 105, such as the first and second source / drain regions 121, 123 separated by the channel region 125, and the plurality of horizontally oriented access lines 107-1, 107-2,..., 107-Q extending laterally in the first direction (D1) 109 can be formed within different vertical layers within each level. For example, the plurality of horizontally oriented access lines 107-1, 107-2,..., 107-Q extending in the first direction (D1) 109 can be formed on a top surface opposite and electrically coupled to the channel region 125, separated from the channel region 125 by a gate dielectric, and orthogonal to the horizontally oriented access devices 130, such as transistors, extending laterally in the second direction (D2) 105. In some embodiments, the plurality of horizontally oriented access lines 107-1, 107-2,..., 107-Q extending in the first direction (D1) 109 are formed in a higher vertical layer within a level, such as within level (LI), that is further from the substrate 100 than a layer in which discrete components of the horizontally oriented access devices, such as the first and second source / drain regions 121, 123 separated by the channel region 125, are formed.

[0034] AsFigure 1B As shown in the example embodiment of FIG. 1, the digit lines 103-1, 103-2,..., 103-Q extend in a vertical direction relative to the substrate 100, e.g., in the third direction (D3) 111. Further, as shown in the example embodiment of FIG. 1, the digit lines 103-1, 103-2,..., 103-Q can be spaced apart from each other in the first direction (D1) 109 in one of the subunit arrays 101-2 in the memory array 101. Figure 1B As shown in the example embodiment of FIG. 1, the digit lines 103-1, 103-2,..., 103-Q extend in a vertical direction relative to the substrate 100, e.g., in the third direction (D3) 111. Further, as shown in the example embodiment of FIG. 1, the digit lines 103-1, 103-2,..., 103-Q can be spaced apart from each other in the first direction (D1) 109 in one of the subunit arrays 101-2 in the memory array 101. Figure 1A As shown in the example embodiment of FIG. 1, the digit lines 103-1, 103-2,..., 103-Q extend in a vertical direction relative to the substrate 100, e.g., in the third direction (D3) 111. Further, as shown in the example embodiment of FIG. 1, the digit lines 103-1, 103-2,..., 103-Q can be spaced apart from each other in the first direction (D1) 109 in one of the subunit arrays 101-2 in the memory array 101.

[0035] For example, the first vertically extending digital line, such as 103-1, may be adjacent to the sidewall of the first source / drain region 121 of the first horizontally oriented access device 130, such as a transistor, in the first level (L1) 113-1, the sidewall of the first source / drain region 121 of the first horizontally oriented access device 130, such as a transistor, in the second level (L2) 113-2, and the sidewall of the first source / drain region 121 of the first horizontally oriented access device 130, such as a transistor, in the third level (L3) 113-P, etc. Similarly, the second vertically extending digital line, such as 103-2, may be adjacent to the sidewall of the first source / drain region 121 of the second horizontally oriented access device 130, such as a transistor, in the first level (L1) 113-1, and spaced apart from the first horizontally oriented access device 130 in the first level (L1) 113-1 in the first direction (D1) 109. The second vertically extending digital line, such as 103-2, may also be adjacent to the sidewall of the first source / drain region 121 of the second horizontally oriented access device 130, such as a transistor, in the second level (L2) 113-2, and the sidewall of the first source / drain region 121 of the second horizontally oriented access device 130, such as a transistor, in the third level (L3) 113-P, etc. The embodiments are not limited to a specific number of levels.

[0036] The vertically extending digital lines 103-1, 103-2, ..., 103-Q may include conductive materials, such as doped semiconductor materials, conductive metal nitrides, metals, and / or metal-semiconductor compounds. The digital lines 103-1, 103-2, ..., 103-Q may correspond to... Figure 1A The described digital line (DL).

[0037] like Figure 1B As shown in the example embodiments, the conductive body contact may be formed to extend along the end surface of a horizontally oriented access device 130 of, for example, a transistor in a first direction (D1) 109 along each of the levels (L1) 113-1, (L2) 113-2, and (L3) 113-P above the substrate 100. The body contact may be connected to, for example... Figure 1A The body of the horizontally oriented access device 130 (e.g., transistor) in each memory cell of the memory cell 110. Figure 3 (As shown in 336), for example, the body region. The body contacts may include conductive materials, such as one of doped semiconductor materials, conductive metal nitrides, metals, and / or metal-semiconductor compounds.

[0038] although Figure 1BThe insulating material can fill other spaces in the vertically-stacked array of memory cells, although not shown. For example, the insulating material can include one or more of a silicon oxide material, a silicon nitride material, and / or a silicon oxynitride material, among others. However, embodiments are not limited to these examples.

[0039] Figure 2A A block diagram of a device according to embodiments of the disclosure. Figure 2A A circuit diagram illustrating a cell array of a three-dimensional (3D) semiconductor memory device according to embodiments of the disclosure is shown. Figure 2A The cell array can have a plurality of sub-cell arrays 201-1, 201-2,..., 201-N. The sub-cell arrays 201-1, 201-2,..., 201-N can be arranged along a second direction (D2) 205. Each of the sub-cell arrays (e.g., sub-cell array 201-2) can include a plurality of access lines 203-1, 203-2,..., 203-Q (which can also be referred to as word lines). In addition, each of the sub-cell arrays (e.g., sub-cell array 201-2) can include a plurality of digit lines 207-1, 207-2,..., 207-Q (which can also be referred to as bit lines, data lines, or sense lines). In Figure 2A In the sub-cell array 201-2, the digit lines 207-1, 207-2,..., 207-Q are shown to extend in a first direction (D1) 209, and the access lines 203-1, 203-2,..., 203-Q are shown to extend in a third direction (D3) 211.

[0040] The first direction (D1) 209 and the second direction (D2) 205 can be considered to be in a horizontal (“X-Y”) plane. The third direction (D3) 211 can be considered to be in a vertical (“Z”) direction (e.g., transverse to the X-Y plane). Thus, according to embodiments described herein, the access lines 203-1, 203-2,..., 203-Q extend in a vertical direction (e.g., the third direction (D3) 211).

[0041] A memory cell (e.g., 210) can include an access device (e.g., an access transistor) and a storage node located at an intersection of each access line 203-1, 203-2,..., 203-Q and each digit line 207-1, 207-2,..., 207-Q. An access line 203-1, 203-2,..., 203-Q and a digit line 207-1, 207-2,..., 207-Q can be used to write to or read from a memory cell. Digit lines 207-1, 207-2,..., 207-Q can conductively interconnect memory cells along a horizontal column of each subcell array 201-1, 201-2,..., 201-N, and access lines 203-1, 203-2,..., 203-Q can conductively interconnect memory cells along a vertical row of each subcell array 201-1, 201-2,..., 201-N. One memory cell, e.g., 210, can be located between one access line (e.g., 203-2) and one digit line (e.g., 207-2). Each memory cell can be uniquely addressed by a combination of an access line 203-1, 203-2,..., 203-Q and a digit line 207-1, 207-2,..., 207-Q.

[0042] Digit lines 207-1, 207-2,..., 207-Q can be or include conductive patterns (e.g., metal lines) disposed on and spaced apart from a substrate. Digit lines 207-1, 207-2,..., 207-Q can extend in a first direction (D1) 209. Digit lines 207-1, 207-2,..., 207-Q in one subcell array (e.g., 201-2) can be spaced apart from one another in a vertical direction (e.g., in a third direction (D3) 211).

[0043] Access lines 203-1, 203-2,..., 203-Q can be or include conductive patterns (e.g., metal lines) extending in a vertical direction (e.g., in a third direction (D3) 211) relative to a substrate. Access lines in one subcell array (e.g., 201-2) can be spaced apart from one another in a first direction (D1) 209.

[0044] The gate of a memory cell (e.g., memory cell 210) may be connected to an access line (e.g., 203-2), and the first conductive node (e.g., a first source / drain region) of the access means (e.g., a transistor) of memory cell 210 may be connected to a digital line (e.g., 207-2). Each of the memory cells (e.g., memory cell 210) may be connected to a storage node (e.g., a capacitor). The second conductive node (e.g., a second source / drain region) of the access means (e.g., a transistor) of memory cell 210 may be connected to a storage node (e.g., a capacitor). For example, the storage node of the capacitor may be formed of a ferroelectric and / or dielectric material, such as zirconium oxide (ZrO2), hafnium oxide (HfO2), lanthanum oxide (La2O3), lead zirconate titanate (PZT, Pb[Zr(x)Ti(1-x)]O3), barium titanate (BaTiO3), aluminum oxide (e.g., Al2O3), combinations of these with or without dopants, or other suitable materials.

[0045] Although this paper uses the references of first and second source / drain regions to denote two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as "first" and / or "second" have a specific meaning. It is only desired that one of the source / drain regions is connected to a digital line (e.g., 207-2), and the other can be connected to a memory node.

[0046] Figure 2B The illustration shows a three-dimensional (3D) semiconductor memory device according to some embodiments of the present disclosure (e.g., Figure 2A The perspective view shown is a portion of the sub-cell array 201-2 as a vertically oriented stack of memory cells in the array. Figure 3 Explanation and display Figure 2B The unit cell of the 3D semiconductor memory device shown in the image (e.g.) Figure 2A A perspective view of the memory cell 210 shown in the image.

[0047] like Figure 2B As shown, bonding can be formed on substrate 200. Figure 2A One of the described array of sub-cells (e.g., 201-2). For example, substrate 200 may be or include a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc. However, the embodiments are not limited to these examples.

[0048] like Figure 2B As shown in the example embodiments, memory cells extending in a vertical direction (e.g., third direction (D3) 211) can be fabricated on the substrate 200. Figure 2A The memory cells 210 in the memory are vertically stacked. According to some embodiments, the vertical stacking of the memory cells can be manufactured such that each memory cell (e.g., Figure 2AThe memory cells 210 are formed on multiple vertical levels (e.g., a first level (L1), a second level (L2), and a third level (L3)). Repeating vertical levels L1, L2, and L3 can be arranged vertically (e.g., along the vertical direction). Figure 2A The third-party (D3) 211) arrangement shown in the diagram (e.g., "stacked") can be separated from the substrate 200 by an insulating material 220. Each of the repeating vertical levels L1, L2, and L3 may include multiple discrete components (e.g., regions) of laterally oriented access devices 230 (e.g., transistors) and memory nodes (e.g., capacitors), the memory nodes including access lines 203-1, 203-2, ..., 203-Q connectors and digital lines 207-1, 207-2, ..., 207-Q connectors. The multiple discrete components of the laterally oriented access devices 230 (e.g., transistors) may be formed in multiple iterations of the vertical repeating layers within each level, as described below. Figure 4 A more detailed description, and may be available in similar formats. Figure 2A The second direction (D2) 205 shown in the figure extends horizontally on the second direction (D2) 205.

[0049] Multiple discrete components of a laterally oriented access device 230 (e.g., a transistor) may include a first source / drain region 221 and a second source / drain region 223, separated by a channel region 225, extending laterally in a second direction (D2) 205 and formed within the body of the access device. In some embodiments, the channel region 225 may include silicon, germanium, silicon-germanium, and / or indium gallium zinc oxide (IGZO). In some embodiments, the first source / drain region 221 and the second source / drain region 223 may include n-type dopant regions formed within the p-type doped body of the access device to form n-type conductive transistors. In some embodiments, the first source / drain region 221 and the second source / drain region 223 may include p-type dopant formed within the n-type doped body of the access device to form p-type conductive transistors. By way of example, but not limitation, the n-type dopant may include phosphorus (P) atoms, and the p-type dopant may include boron (B) atoms formed in a relatively doped body region of a polycrystalline silicon semiconductor material. However, the embodiments are not limited to these examples.

[0050] Storage node 227 (e.g., a capacitor) can be connected to a corresponding terminal of the access device. For example... Figure 2B As shown, storage node 227 (e.g., a capacitor) can be connected to the second source / drain region 223 of the access device. Storage nodes can be or include memory elements capable of storing data. Each of the storage nodes can be a memory element using one of a capacitor, a magnetic tunneling junction pattern, and / or a variable resistor body including a phase change material. However, embodiments are not limited to these examples. In some embodiments, with unit cells (e.g. Figure 2AEach memory node associated with an access device in memory cell 210 can be similarly located in a memory node with a memory access device ... Figure 2A The second direction (D2)205 shown in the figure extends on the second direction (D2)205.

[0051] like Figure 2B As shown, multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-Q are similar to... Figure 2A Extending along the first direction (D1) 209. Multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-Q can be similar to... Figure 2A The digital lines 207-1, 207-2, ..., 207-Q shown are illustrated. Multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-Q may be arranged (e.g., "stacked") along a third direction (D3) 211. The multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-Q may include conductive materials. For example, conductive materials may include one or more of the following: doped semiconductors (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), and / or metal-semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). However, the embodiments are not limited to these examples.

[0052] In each of the vertical hierarchies (L1)213-1, (L2)213-2, and (L3)213-P, the horizontally oriented memory cells (e.g.) Figure 2A The memory cells 210 in the memory may be horizontally spaced apart from each other in the first direction (D1) 209. However, as described below... Figure 4More detail, the plurality of discrete components of the laterally oriented access devices 230 that extend laterally in the second direction (D2) 205 (e.g., the first source / drain region 221 and the second source / drain region 223 separated by the channel region 225), and the plurality of horizontally oriented digit lines 207-1, 207-2,..., 207-Q that extend in the first direction (D1) 209 can be formed in different vertical layers within each level. For example, the plurality of horizontally oriented digit lines 207-1, 207-2,..., 207-Q that extend in the first direction (D1) 209 can be disposed on and in electrical contact with a top surface of the first source / drain region 221 and orthogonal to the laterally oriented access devices 230 (e.g., transistors) that extend laterally in the second direction (D2) 205. In some embodiments, the plurality of horizontally oriented digit lines 207-1, 207-2,..., 207-Q that extend in the first direction (D1) 209 are formed in a higher vertical layer within a level (e.g., within the level (LI)) that is further from the substrate 200 than a layer in which the discrete components of the laterally oriented access devices (e.g., the first source / drain region 221 and the second source / drain region 223 separated by the channel region 225) are formed. In some embodiments, the plurality of horizontally oriented digit lines 207-1, 207-2,..., 207-Q that extend in the first direction (D1) 209 can be connected to the top surface of the first source / drain region 221 directly and / or through additional contacts that include metal silicide.

[0053] As Figure 2B shown in example embodiments, the access lines 203-1, 203-2,..., 203-Q extend in a vertical direction relative to the substrate 200 (e.g., in the third direction (D3) 211). Further, as shown in Figure 2B , the access lines 203-1, 203-2,..., 203-Q in one subcell array (e.g., the subcell array 201-2 in Figure 2A may be spaced apart from each other in the first direction (D1) 209. The access lines 203-1, 203-2,..., 203-Q can be disposed to extend vertically in the third direction (D3) 211 relative to the substrate 200 between a pair of laterally oriented access devices 230 (e.g., transistors) that extend laterally in the second direction (D2) 205, but adjacent to each other in the first direction (D1) 209 on a level (e.g., the first level (LI)). Each of the access lines 203-1, 203-2,..., 203-Q can extend vertically in the third direction (D3) on a sidewall of a respective one of the plurality of laterally oriented access devices 230 (e.g., transistors) in the vertical stack.

[0054] For example, and as Figure 3As shown in more detail, a first one of the vertically-extending access lines (e.g., 203-1) can be adjacent to a sidewall of a channel region 225 of a first one of the laterally-oriented access devices 230 (e.g., transistors) in the first level (LI) 213-1, a sidewall of a channel region 225 of a first one of the laterally-oriented access devices 230 (e.g., transistors) in the second level (L2) 213-2, a sidewall of a channel region 225 of a first one of the laterally-oriented access devices 230 (e.g., transistors) in the third level (L3) 213-P, etc. Similarly, a second one of the vertically-extending access lines (e.g., 203-2) can be adjacent to a sidewall of a channel region 225 of a second one of the laterally-oriented access devices 230 (e.g., transistors) in the first level (LI) 213-1, spaced apart from the first one of the laterally-oriented access devices 230 (e.g., transistors) in the first level (LI) 213-1 in the first direction (Dl) 209, and adjacent to a sidewall of a channel region 225 of a second one of the laterally-oriented access devices 230 (e.g., transistors) in the second level (L2) 213-2, and a sidewall of a channel region 225 of a second one of the laterally-oriented access devices 230 (e.g., transistors) in the third level (L3) 213-P, etc. Embodiments are not limited to a particular number of levels.

[0055] The vertically-extending access lines 203-1, 203-2,..., 203-Q can comprise an electrically conductive material, such as one of a doped semiconductor material, an electrically conductive metal nitride, a metal, and / or a metal-semiconductor compound. The access lines 203-1, 203-2,..., 203-Q can correspond to the word lines (WL) described in connection with Figure 2A

[0056] As shown in the example embodiment of FIG. 3A, the electrically conductive body contact 295 can be formed to extend along an end surface of the laterally-oriented access device 230 (e.g., transistor) in each level (LI) 213-1, (L2) 213-2, and (L3) 213-P above the substrate 200 in the first direction (Dl) 209. The body contact 295 can be connected to a body (e.g., body region) of the laterally-oriented access device 230 (e.g., transistor) in each memory cell (e.g., memory cell 210) in the array 220, as shown at 336 in FIG. 3B. The body contact 295 can comprise an electrically conductive material, such as one of a doped semiconductor material, an electrically conductive metal nitride, a metal, and / or a metal-semiconductor compound. Figure 2B Figure 2A Figure 3

[0057] Although the embodiments are not limited to a particular number of levels, the vertically-extending access lines 203-1, 203-2,..., 203-Q can be formed to extend along an end surface of the laterally-oriented access device 230 (e.g., transistor) in each level (LI) 213-1, (L2) 213-2, and (L3) 213-P above the substrate 200 in the first direction (Dl) 209. The body contact 295 can be connected to a body (e.g., body region) of the laterally-oriented access device 230 (e.g., transistor) in each memory cell (e.g., memory cell 210) in the array 220, as shown at 336 in FIG. 3B. The body contact 295 can comprise an electrically conductive material, such as one of a doped semiconductor material, an electrically conductive metal nitride, a metal, and / or a metal-semiconductor compound. Figure 2B ​​​​Not shown, but insulating material may fill other spaces in a vertically stacked array of memory cells. For example, the insulating material may include one or more of silicon oxide, silicon nitride, and / or silicon oxynitride. However, the embodiments are not limited to these examples.

[0058] Figure 3 A more detailed description of vertically stacked memory cell arrays according to some embodiments of the present disclosure (e.g.) Figure 2A The unit cells (e.g., within the sub-cell array 201-2) in the sub-cell array 201-2 Figure 2A (Memory unit 210 in the middle). For example Figure 3 As shown, the first source / drain region 321 and the second source / drain region 323 can be impurity-doped regions of a laterally oriented access device 330 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 can be similar to... Figure 2B The first source / drain region 221 and the second source / drain region 223 are shown in the diagram. The first and second source / drain regions may be separated by a channel 325 formed in a body (e.g., body region 326) of the semiconductor material of the laterally oriented access device 330 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 may be formed by an n-type or p-type dopant doped in the body region 326. The embodiments are not limited thereto.

[0059] For example, in an n-type conductive transistor configuration, the body region 326 of the laterally oriented access device 330 (e.g., a transistor) may be formed of a lightly doped (p-)p-type semiconductor material. In some embodiments, the body region 326 and the channel 325 separating the first source / drain region 321 and the second source / drain region 323 may comprise a lightly doped p-type (e.g., a lower dopant concentration (p-)) polysilicon material composed of boron (B) atoms as an impurity dopant for the polysilicon. The first source / drain region 321 and the second source / drain region 323 may also comprise metals and / or metal composites formed using atomic layer deposition processes, containing ruthenium (Ru), molybdenum (Mo), nickel (Ni), titanium (Ti), copper (Cu), highly doped degenerate semiconductor materials, and / or indium oxide (In₂O₃) or indium tin oxide (In₂O₃). 2-x Sn x At least one of O3). However, the embodiments are not limited to these examples.

[0060] As used herein, degenerate semiconductor materials refer to semiconductor materials, such as polycrystalline silicon, containing high levels of doping with significant interactions between dopants (e.g., phosphorus (P), boron (B), etc.). In contrast, non-degenerate semiconductors contain moderate levels of doping, where dopant atoms are well separated from each other in the semiconductor host lattice with negligible interactions.

[0061] In this example, the first source / drain region 321 and the second source / drain region 323 may include highly doped n-type conductive impurities (e.g., highly doped (n+)) doped into the first source / drain region 321 and the second source / drain region 323. In some embodiments, the highly doped n-type conductive first drain region 321 and the second drain region 323 may include a high concentration of phosphorus (P) atoms deposited therein. However, the embodiments are not limited to this example. In other embodiments, the laterally oriented access device 330 (e.g., a transistor) may have a p-type conductive configuration, in which case the conductivity type of the impurity (e.g., the dopant) will be reversed.

[0062] like Figure 3 As shown in the example embodiment, the first source / drain region 321 may occupy the upper portion of the body 326 of the laterally oriented access device 330 (e.g., a transistor). For example, the first source / drain region 321 may have a bottom surface 324 within the body 326 of the laterally oriented access device 330, which is vertically higher in a third direction (D3) 311 compared to the bottom surface of the body 326 of the laterally oriented access device 330. Therefore, the laterally oriented transistor 330 may have a lower contact element (e.g., below the first source / drain region 321 and with the body contact element) than the first source / drain region 321. Figure 2B The main body portion 326 of the electrical contact shown in Figure 295. Furthermore, as... Figure 3 As shown in the example embodiments, similar to Figure 2B The number lines 207-1, 207-2, ..., 207-Q and Figure 2A The digital lines 207-1, 207-2, ..., 207-Q shown in the figure (e.g., 307-1) can be placed on the top surface 322 of the first source / drain region 321 and electrically coupled thereto.

[0063] like Figure 3 As shown in the example embodiments, the access line (e.g., similar to) Figure 2B Access lines 203-1, 203-2, ..., 203-Q and Figure 2A 203-1, 203-2, ..., 203-Q of 303-1) may extend vertically on a third direction (D3) 311 adjacent to the sidewall of the channel region 325 portion of the body 326 of the laterally oriented access device 330 (e.g., a transistor), the channel region 325 being horizontally conductive along a second direction (D2) 305 between the first source / drain region 321 and the second source / drain region 323. A gate dielectric material 304 may be inserted between the access line 303-1 (a portion of which forms the gate of the laterally oriented access device 330 (e.g., a transistor)) and the channel region 325.

[0064] The gate dielectric material 304 can include, for example, a high-k dielectric material, a silicon oxide material, a silicon nitride material, a silicon oxynitride material, etc., or combinations thereof. Embodiments are not limited in this context. For example, in a high-k dielectric material example, the gate dielectric material 304 can include one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, etc.

[0065] Figure 4 An example process for producing a single crystal silicon stack for vertical three-dimensional (3D) memory is described, for example, in FIGS. 1-3 and in accordance with a number of embodiments of the present disclosure. The vertical stack includes a plurality of layers of single crystal silicon germanium 430 and single crystal silicon 432 formed on a substrate 437.

[0066] As discussed above, this can be accomplished, for example, by providing a thin single crystal silicon germanium layer as a seed layer, and then heating the layer to grow the single crystal silicon germanium layer thickness by epitaxial growth. Once the desired layer thickness is formed, a silicon layer can be formed into the surface of the silicon germanium layer. As with the silicon germanium layer, this can be accomplished, for example, by providing a thin single crystal silicon layer as a seed layer, and then heating the layer to grow the single crystal silicon layer thickness by epitaxial growth.

[0067] For example, the single crystal silicon germanium 430 can be grown epitaxially by flowing a silicon-based gas over a thin seed layer of single crystal silicon germanium of a first layer formed on a surface of the substrate 437, and for subsequent single crystal silicon germanium layers, over a thin seed layer of single crystal silicon germanium formed on a surface of an exposed single crystal silicon layer of the vertical stack. For example, disilane (Si2H6) gas can be utilized to grow single crystal silicon germanium epitaxially from an exposed surface of a thin layer of single crystal silicon germanium that has been deposited as a seed for epitaxial growth of single crystal silicon germanium. However, embodiments are not limited in this context. For example, dichlorosilane (SiH2Cl2) gas can be flowed over a seed layer to grow single crystal silicon germanium 430 epitaxially onto an exposed surface of the seed layer.

[0068] To form a single crystal silicon layer on a previously formed single crystal silicon germanium layer, depending on the silicon germanium concentration, if silicon is x amount and germanium is y amount, and if y is less than x, then the silicon / silicon germanium has a smaller lattice mismatch relative to the lattice of single crystal silicon, as discussed above. This allows single crystal silicon to grow on top of the single crystal silicon germanium with a single crystal structure. If a thin layer of single crystal silicon is applied to the surface of the single crystal silicon germanium, the entire single crystal silicon layer acts as a seed for growth of the single crystal silicon layer.

[0069] The processes and parameters for forming the monocrystalline silicon layer are similar to those described above with respect to the monocrystalline silicon germanium layer. For example, the monocrystalline silicon 432 can be epitaxially grown by flowing a silicon-based gas over a thin seed layer of monocrystalline silicon formed on the surface of the previously formed vertically stacked exposed monocrystalline silicon germanium layer. For example, disilane (Si2H6) gas can be utilized to epitaxially grow monocrystalline silicon from the exposed surface of the thin layer of monocrystalline silicon that has been deposited as a seed for epitaxial growth of the monocrystalline silicon layer.

[0070] However, embodiments are not limited thereto. For example, dichlorosilane (SiH2Cl2) gas can be flowed over the seed layer to epitaxially grow monocrystalline silicon 432 onto the exposed surface of the monocrystalline silicon seed layer.

[0071] In some embodiments, similar to the formation of the monocrystalline silicon germanium layer, the flow of the silicon-based gas over the monocrystalline silicon seed layer at a selected temperature, for example, between 300 °C to 1100 °C, can cause the monocrystalline silicon 432 to epitaxially grow at a predictable rate. Based on this predictable growth rate, the monocrystalline silicon layer can be grown to a desired height in a predetermined period of time.

[0072] This delamination can be done in alternating iterations (e.g., SiGe / Si / SiGe / Si, etc.) to produce a superlattice structure in a vertically stacked form. This unpatterned (not patterned within the layers) vertically stacked can then be attached to a CMOS wafer, as described with respect to FIG. 5. One benefit of this process is that because the vertically stacked has not yet been patterned, it does not need to be carefully aligned with the CMOS wafer. In the memory array structure of the vertically stacked, it can be advantageous to arrange conductive lines (e.g., digit lines or access lines) in a twisted manner (e.g., as shown in Figure 5A more detail in the disclosure) to relax spatial constraints. Embodiments of the present disclosure allow for the formation of such conductive lines that relax spatial constraints even further.

[0073] Figures 5A-5B Illustration of a portion of a semiconductor memory device having a plurality of contacts with twisted conductive lines in accordance with one or more embodiments of the present disclosure. Figure 5A is shown in FIG. 6. In some applications, it can be desirable to arrange the conductive lines 577 (e.g., wires) of the semiconductor device in a curved or twisted manner as shown in Figure 5A Figure 7 capacitance between the resulting noise that the circuitry 711 of the semiconductor device of Figure 5B ​direction D3 or 511) is located above another conductive line 577 (e.g., 577-1).

[0074] In some applications, it can be advantageous to reduce the distance between conductive lines 577 in the horizontal direction 509 (i.e., the distance between 577-1 and 577-3) to reduce the overall space. To accomplish this, the distance between conductive line contacts 539 in the horizontal direction 509 (i.e., the distance between 539-3 and 539-19 in the horizontal direction 509) would need to be reduced. Embodiments of the present disclosure describe systems, methods, and apparatuses for relaxing the space constraints of portions 540 of the semiconductor memory device when forming the twisted conductive lines 577.

[0075] Horizontally oriented conductive lines 577-1 and 577-2 (collectively, 577) can be any conductive line of a vertically stacked memory array structure. For example, the conductive lines 577 can be digit lines (e.g., digit lines 107-1,..., 107-Q of FIG. 1) or access lines (e.g., access lines 103-1,..., 103-Q of FIG. 1). However, embodiments of the present disclosure are not so limited. As shown in FIG. 5, the conductive lines 577 can have one or more curved portions. For example, the conductive lines 577 can be sinusoidally shaped. The shape of the lower conductive line 577-1 can be an inverse of the shape of the upper conductive line 577-2. For example, if the bottom lower conductive line 577-1 is shaped as a sine wave, then the top conductive line 577-2 can be shaped as an inverse of the sine wave. Figure 5A

[0076] Each horizontal conductive line 577 can be formed over a number of vertical conductive line contacts 539-1,..., 539-N (collectively referred to herein as 539).

[0077] The conductive contacts 539 can be formed in the array structure. In other words, the conductive contacts 539 can be formed in one or more horizontal rows r1,..., r n (collectively referred to herein as r) that extend in the horizontal direction 505. Each horizontal row r n may be offset from its previous row r n-1 ​are spaced a given distance apart. The conductive lines 577 can contact each odd numbered conductive contact in an odd numbered row and each even numbered contact in an adjacent even numbered row in an alternating fashion. For example, conductive line 577-1 can contact conductive contacts 539-1, 539-3,..., 539-7 of row r1 and 539-10, 539-12,..., 539-16 of row r2. Upper conductive line 577-2 (i.e., the conductive line vertically above 577-1) can contact each even numbered conductive contact in an odd numbered row (e.g., 539-2,..., 539-8 of r1) and each odd numbered contact in an adjacent even numbered row (e.g., 539-9, 539-11,..., 539-15 of r2). To facilitate this structure, odd numbered rows r1,..., r n-1 The odd numbered conductive line contacts in odd numbered rows r1,..., r Figure 5B and even numbered contacts in even numbered rows r2,..., rn will be shorter than the rest of the contacts 539 as illustrated in

[0078] Figure 5A The arrangement shown in FIG. 27 can be achieved by first forming the conductive line contacts 539 and then forming the conductive lines 577 onto the appropriate contacts 539. For example, conductive line 577-1 can be formed by first forming rows r1 and r2 of contacts 539-1,..., 539-16 and then successively forming a conductive material onto 539-1, 539-10, 539-3, 539-12,..., 539-7,..., 539-16 to create the curved conductive line 577-1. As stated herein, the conductive lines 577 can be formed using any conductive material. For example, the conductive material can include one or more of: a doped semiconductor (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), and / or a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). However, embodiments are not limited to these examples. In some embodiments, the conductive lines 577 can all be formed of a similar type of conductive material. The conductive contacts 639 can also be formed of a conductive material.

[0079] Figure 5B Description Figure 5A of a semiconductor memory device along line 'A'. As Figure 5BAs shown, conductive contacts 539 can be arranged such that each contact 539 extends in the vertical direction 511 and has one of two given vertical lengths. The conductive contacts 539 can alternate along the length of a given row (e.g., r2) such that the vertical lengths of contacts 539-9, 539-11, 539-13, ..., 539-15 on which conductive lines 577-2 are formed are greater than the vertical lengths of contacts 539-10, 539-12, 539-14, ..., 539-16 on which conductive lines 577-1 are formed. Therefore, the upper conductive line 577-2 can extend above the lower conductive line 577-1. This allows the conductive lines 577-2 to... Figure 5A The layout shown in the image does not cause connectivity issues.

[0080] The arranged conductive line contacts 539 can connect the conductive line 577 to other components within the semiconductor memory structure. For example, the conductive line contacts 539 can connect the conductive line 577 to a complementary metal-oxide-semiconductor (CMOS) structure.

[0081] In some embodiments, each conductive wire contact 539 may be coupled with Figure 1B The diagram shows multiple digital lines 103-1, 103-2, ..., 103-Q in contact. In this arrangement, each conductive contact 539 extends in direction D3 and contacts the top surface of the digital lines 103-1, 103-2, ..., 103-Q. For example, conductive contact 539-1 may contact the top surface of digital line 103-1. Therefore, a horizontally extending conductive line 577-1 can be connected to a vertical digital line 103-1 via conductive contact 539-1. Alternatively, each conductive contact 539 may contact... Figure 2B The vertically extending access lines 203-1, 203-2, ..., 203-Q are in contact. For example, the conductive wire contact 539-1 can contact the top surface of a pair of access lines 203-1. Therefore, the horizontally extending conductive wire 577-1 can be connected to the vertical access line 203-1 through the conductive wire contact 539-1.

[0082] Contact 539 may also connect conductive line 577 to any of the following, but embodiments of this disclosure are not limited thereto: the source / drain region of the access device (e.g., Figure 2B The source / drain regions 221 and 223), and the conductive body contacts of the semiconductor memory device (e.g., Figure 2B The conductive body contact 295), the substrate of the semiconductor memory device (e.g., Figure 2B The substrate 200), gate dielectric (e.g., Figure 3 The gate dielectric 304), the channel region of the access device (e.g., Figure 2BThe channel region 225) or any part of the circuit system of the semiconductor memory device (e.g., Figure 7 (Circuit system 711). In some embodiments, the conductive line 577 may be in direct contact with another component of the semiconductor device, such as any of the previously listed components.

[0083] Conductive line 577 can be any conductive line or wiring in a semiconductor device. For example, conductive line 577 can be a digital line (e.g., similar to...). Figure 2B The number line 207), access line or word line (e.g., similar to...) Figure 2B Access line / word line 203).

[0084] Figure 6A The steps in the process of forming stranded conductive wires for a semiconductor memory device according to several embodiments of the present disclosure are described. For example... Figure 6A As shown, one or more lower conductive lines 677 (e.g., 677-1 and 677-3) can be formed by forming a first number of vertically oriented conductive contacts 639. Each conductive contact can be in the vertical direction (i.e., Figure 6B The conductive contacts 639 extend in the direction 611) and have equal vertical lengths. The conductive contacts 639 may be formed in several rows r1, ..., r2 extending in the horizontal direction 605. n In the middle, the conductive contacts 639 of odd-numbered rows (e.g., r1) can be aligned with the conductive contacts 639 of other odd-numbered rows (e.g., r3). ​​Similarly, the conductive contacts 639 of even-numbered rows (e.g., r2) can be aligned with the conductive contacts 639 of other even-numbered rows (e.g., r3). n Alignment. Each even-numbered row can be offset in the horizontal direction 605 from its adjacent odd-numbered row. In other words, in both the first horizontal direction 605 and the vertical horizontal direction 609, each row r n Can be compared with its previous lines r n-1 Separately spaced.

[0085] Each lower conductive wire 677 may be formed onto each of the two rows r1 and r2 of conductive contacts 639. When the second row r2 of conductive contacts is offset from r1 in the horizontal direction 605, this will cause the conductive wire 677 to have one or more bends. This conductive wire may be referred to herein as a “stranded conductive wire”.

[0086] Figure 6B For along Figure 6A A cross-sectional view of line 'A'. (See diagram below.) Figure 6B As shown, one or more conductive contacts 639 may be formed along the horizontal direction 605 and extending in the vertical direction 611, wherein the vertical length of each conductive contact 639 is equal. Lower conductive lines 677-3 may be formed on the contacts 639.

[0087] Figure 6C Additional steps in the process of forming twisted conductive lines of a semiconductor memory device according to several embodiments of the disclosure are described. As Figure 6C As described in the

[0088] The dielectric material 644 can be a spacer material that isolates the conductive lines 677 that have been formed during the process of conductive line formation described herein from other dielectric materials (e.g., dielectric 663).

[0089] Figure 6D To form a cross-sectional view along line 'B' of Figure 6C As shown in the Figure 6D The conductive lines 677 (i.e., 677-3) can be formed onto the conductive line contacts 639. A first dielectric 644 can be deposited on either side of the conductive contacts 639 and the conductive lines 677. A second dielectric 663 can be deposited over and around the conductive lines 677, filling any space between the conductive lines 677 and forming a layer of dielectric material 663 over the conductive lines 677.

[0090] Figure 6E Additional steps in the process of forming twisted conductive lines of a semiconductor memory device according to several embodiments of the disclosure are described. As Figure 6E As shown in the The hard mask material 692 can be used to protect portions of the conductive lines 677 and portions of the dielectric material deposits 644, 663 (not shown) and 678 during subsequent processing steps (e.g., conductive contact and twisted conductive line formation steps) described below. In other words, the hard mask material 692 can act as a protective layer to keep the non-removed portions 640 of the semiconductor memory device intact during the removal process.

[0091] The second dielectric 663 can be etched from the region between the first dielectric 644 and the hard mask material 692. A third dielectric 678 can be formed above the memory cell array 640, such that the third dielectric 678 fills the space between the first dielectric 644 and the hard mask layer 692, a space previously occupied by the second dielectric 663. Therefore, the third dielectric 678 can occupy a region adjacent to the first dielectric 644. Although... Figure 6E Not shown Figure 6C and 6D The second dielectric material 663 is present, but embodiments of this disclosure are not limited to those in which the second dielectric material 663 is completely removed at this stage of the process. For example, the second dielectric material 663 may remain intact beneath the hard mask layer 692.

[0092] The third dielectric 678 can be selectively etched and planarized to form one or more vertical openings 680. For example... Figure 6E As shown, the vertical opening 680 can be aligned with the conductive contact 639, such that each vertical opening 680 is located in a horizontal row r1, ..., r1 extending in the horizontal direction 605. n One of them. Each vertical opening 680 may also be adjacent to the conductive contact 639 in the horizontal direction 609. Since the third dielectric 678 occupies the space above the already formed conductive line 677, the vertical opening 680 may be longer than the conductive contact 639.

[0093] Figure 6F for Figure 6E A cross-sectional view along line 'B'. (See diagram below.) Figure 6E As shown, a first dielectric material 644 adjacent to the conductive line 677 on either side can remain intact. A third dielectric material 678 can be deposited adjacent to and over the first dielectric material 644. Similar to the hard mask material 692, the third dielectric 678 may include a material suitable for protecting and maintaining the integrity of the conductive line 677 during subsequent steps of the process described herein. The third dielectric material 678 may be selectively etched to form a vertical opening 680, which is in two horizontal directions (i.e., Figure 6E Align it with the conductive contact 639 on the horizontal direction 605 or 609.

[0094] Figure 6G Additional steps in the process of forming stranded conductive wires for a semiconductor memory device according to several embodiments of the present disclosure are described. Figure 6E The hard mask material 692 can be removed from the memory cell array portion 640 of the semiconductor memory device. Conductive material can be formed on... Figure 6E and 6Feach of the vertical openings 680 of the dielectric 678 shown to form a second number of conductive contacts 672. The height (i.e., vertical length) of the conductive contacts 672 can be greater than the height of the conductive contacts 639. The upper conductive lines 677-2 and 677-4 can be formed onto the conductive contacts 672. Thus, the upper conductive lines 677-2 and 677-4 can be vertically above the lower conductive lines 677-1 and 677-3. The upper conductive lines 677-2 and 677-4 can also be above the dielectric 644. Similar to the lower conductive lines 677-1 and 677-3, the upper conductive lines 677-2 and 677-4 can have one or more curved portions. In other words, each conductive contact 672 can be spaced apart from other conductive contacts 672 on a given upper conductive line (e.g., 677-2 or 677-4) in both the first horizontal direction 605 and the second vertical horizontal direction 609. As described in connection with Figure 5A The conductive lines 677 can be shaped in any matter that contains multiple curved portions. For example, the conductive lines 677 can be shaped as a sinusoidal curve. The upper conductive lines 677-2 and 677-4 can be shaped oppositely to the lower conductive lines 677-1 and 677-3. The upper conductive lines 677-2 and 677-4 can contact each conductive contact 672 of two adjacent rows r n and r n-1 .

[0095] The conductive lines 677 can be formed within a vertically stacked memory cell array of a semiconductor memory device. For example, a method of forming a vertically stacked memory cell array can include forming a number of layers, each layer including at least one of a conductive material and a dielectric material. The conductive lines 677 can be formed within a layer of dielectric material, or the conductive contacts 639 or 672 can be in contact with a layer of dielectric material. The conductive lines 677 and / or the conductive contacts 639 and 672 can also be in contact with other components of a semiconductor memory device, such as any of the components described in connection with Figure 5A

[0096] ​In one method embodiment, a method for forming conductive lines within an array of vertically stacked memory cells includes forming a first and second row of a first number of vertical conductive line contacts, where the vertical contacts in each row are aligned in a first horizontal direction and the first row is spaced apart from the second row in a second horizontal direction; forming a first number of conductive lines having one or more curved portions, each conductive line contacting alternating conductive line contacts of the conductive line contacts of the first and second rows of the first number of vertical conductive line contacts; and forming a second number of conductive lines having one or more curved portions, each conductive line contacting the remaining conductive line contacts of the conductive line contacts of the first and second rows of the first number of vertical conductive line contacts not contacted by the first number of conductive lines. In such embodiments, the vertical conductive line contacts can be uniformly spaced apart or non-uniformly spaced apart, as discussed in greater detail below.

[0097] Although Figure 6G While four conductive lines 677-1,..., 677-4 are illustrated, embodiments of the disclosure are not so limited. For example, a semiconductor device according to the disclosure can include a greater or lesser number of conductive lines 677. Additionally, while Figure 6G While conductive lines 677 are illustrated as being formed on four conductive contacts 639 or 672, embodiments of the disclosure are not so limited. For example, conductive lines 677 according to the disclosure can be formed on a greater or lesser number of conductive contacts 672 or 639.

[0098] Additionally, Figure 6G The individual conductive contacts 672 or 639 illustrated in FIG. 8A can be replaced by a plurality (e.g., pair) of conductive contacts. In other words, in Figure 6G In each location of each conductive contact 672 or 639 illustrated in FIG. 8A, two or more conductive contacts proximate to one another can be used. For example, in some such embodiments, a pair of contacts can be positioned a first lateral distance apart from one another, and the pair can be positioned a second, greater lateral distance away from an adjacent pair of contacts.

[0099] Each of the plurality of contacts can extend vertically and parallel to a vertical digit line or access line of the array of memory cells. Further, when pairs of contacts are used, in some embodiments, one of the contacts can extend vertically on one side and the other can extend vertically on the other side of the vertical digit line or access line of the array of memory cells.

[0100] Further, while Figure 6G While conductive contacts 672 and 639 are illustrated as being uniformly spaced apart from other conductive contacts 672 or 639 in a given row r1,..., r n In some embodiments, the conductive contacts 672 or 639 can be uniformly spaced apart from one another in a given row r1,..., rn The conductive contacts 639 and 672 may be unevenly spaced. For example, given rows r1, ..., r n The conductive contacts 639 and 672 may have alternating intervals between a first lateral distance and a second lateral distance, or may have irregular distances between contacts compared to other distances between contacts in a row.

[0101] Figure 6H For along Figure 6G A cross-sectional view of line 'B'. (See diagram below.) Figure 6H As shown, the length of conductive contact 672, on which upper conductive lines 677 (e.g., conductive lines 677-2 and 677-4) are formed, can be greater than the length of conductive contact 639, on which lower conductive lines (e.g., conductive lines 677-1 and 677-3) are formed. Conductive contacts 672 and 639 can... Figure 6G Align it with the first direction 609.

[0102] The first dielectric material 644 can be used to isolate the lower conductive lines 677-1 and 677-3 and the conductive contact 639 from other components (e.g., dielectric material 678, contact 672, and conductive lines 677-2 and 677-4). The dielectric material 678 forming the conductive contact 672 can be located above and between the deposit of the first dielectric 644. The upper conductive lines 677-2 and 677-4 can be located above the lower conductive lines 677-1 and 677-3 and the third dielectric 678.

[0103] Figure 6I For along Figure 6G A cross-sectional view of line 'A'. (See diagram below.) Figure 6I As shown, conductive contacts 639 and 672 may be aligned in direction 605 but extend in vertical direction 611. The second dielectric material 663 may be adjacent to the third dielectric material 678 and cover portions of the first dielectric material 644 and the lower conductive line (e.g., conductive line 677-3), and is located below the upper conductive line (e.g., conductive line 677-4).

[0104] Figure 7 This is a block diagram of a device in the form of a computer system including a memory device, according to several embodiments of the present disclosure. Figure 7 This is a block diagram of a device in the form of a computer system 700 including a memory device 703, according to several embodiments of the present disclosure. As used herein, for example, the memory device 703, memory array 710, and / or host 702 may also be individually considered as a "device". According to an embodiment, the memory device 702 may include at least one memory array 710 having a three-node access means of vertical three-dimensional (3D) memory, as described herein.

[0105] In this example, system 700 includes a host 702 coupled to a memory device 703 via an interface 704. Computer system 700 can be a personal, desktop, camera, mobile telephone, memory card reader, or Internet of Things (IoT)-enabled device, among various other types of systems. Host 702 can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry) capable of accessing memory 703. System 700 can include separate integrated circuits, or both host 702 and memory device 703 can be on the same integrated circuit. For example, host 702 can be a system controller of a memory system that includes a plurality of memory devices 703, where system controller 705 provides access to respective memory devices 703 by another processing resource such as a central processing unit (CPU).

[0106] In the example shown in Figure 7 Host 702 is responsible for executing an operating system (OS) and / or various applications (e.g., processes) that can be loaded thereon (e.g., from memory device 703 via controller 705). The OS and / or various applications can be loaded from memory device 703 by providing access commands from host 702 to memory device 703 to access data that includes the OS and / or various applications. Host 702 can also access data utilized by the OS and / or various applications by providing access commands to memory device 703 to retrieve the data for execution of the OS and / or various applications.

[0107] For clarity, system 700 has been simplified to focus on features with particular relevance to the disclosure. Memory array 710 can be a DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and / or NOR flash array, including at least one three-node access device of three-dimensional (3D) memory. For example, memory array 710 can be an unmasked DL 4F2 array, such as a 3D-DRAM memory array. Array 710 can include memory cells arranged in rows coupled by word lines (which can be referred to herein as access lines or select lines) and columns coupled by digit lines (which can be referred to herein as sense lines or data lines). Although Figure 7 A single array 710 is shown in

[0108] The memory device 703 includes address circuitry 706 to latch address signals provided by the interface 704. The interface can include, for example, a physical interface that employs a suitable protocol (e.g., a data bus, an address bus, and a command bus, or a combined data / address / command bus). This protocol can be custom or proprietary, or the interface 704 can employ a standardized protocol, such as Peripheral Component Interconnect Express (PCIe), Gen-Z, CCIX, etc. A row decoder 708 and a column decoder 712 receive address signals and decode them to access the memory array 710. Data can be read from the memory array 710 by use of read circuitry 711 that reads a voltage and / or current change on a sense line. The read circuitry 711 can include, for example, a sense amplifier that can read and latch a page (e.g., a row) of data from the memory array 710. I / O circuitry 707 can be used for bidirectional data communication between the memory device 703 and the host 702 via the interface 704. Read / write circuitry 713 is used to write data to and read data from the memory array 710. As an example, the circuitry 713 can include various drivers, latching circuitry, etc.

[0109] The control circuitry 705 decodes signals provided by the host 702. The signals can be commands provided by the host 702. These signals can include a chip enable signal, a write enable signal, and address latch signals, which are used to control operations performed on the memory array 710, including data read operations, data write operations, and data erase operations. In various embodiments, the control circuitry 705 is responsible for executing instructions from the host 702. The control circuitry 705 can include a state machine, a sequencer, and / or some other type of control circuitry, which can be implemented in hardware, firmware, or software, or any combination of the three. In some examples, the host 702 can be a controller external to the memory device 703. For example, the host 702 can be a memory controller coupled to a processing resource of a computing device.

[0110] The term semiconductor can refer to a material, a wafer, or a substrate, and includes any base semiconductor structure, for example. A “semiconductor” should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon on a base semiconductor structure, as well as other semiconductor structures. Furthermore, when reference is made to a semiconductor, previous processing steps can have been utilized to form regions / junctions in the base semiconductor structure, and the term semiconductor can include the underlying material containing such regions / junctions.

[0111] The term dielectric can refer to a material that includes, for example, any combination of oxide materials and / or nitride materials.

[0112] The conductive lines formed using the processes described herein can have several benefits. For example, the processes described herein can allow for closer formation of conductive lines without generating excessive noise, parasitic capacitance, or connectivity issues. This can relax space constraints, reduce surface area, and improve overall performance of memory devices.

[0113] The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number and the remaining digits, if any, correspond to the numbering of the element or component within the figure. Similar (e.g., identical) elements or components between different figures can be identified by the use of similar digits. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and / or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, the proportion and the relative scale of the elements provided in the figures are intended to illustrate embodiments of the present disclosure and not to be used in a limiting sense.

[0114] As used herein, “a number of” or “an amount of” something can refer to one or more of such things. For example, a number of or an amount of memory cells can refer to one or more memory cells. A “plurality” of something means two or more. As used herein, multiple actions performed simultaneously refer to actions that at least partially overlap within a particular time period. As used herein, the term “coupled” can include electrically coupled, directly coupled, and / or directly connected (e.g., through direct physical contact) without intervening elements, or indirectly coupled and / or connected with intervening elements, or wirelessly coupled. The term coupled can further include two or more elements that cooperate or interact with each other (e.g., in a cause and effect relationship). An element coupled between two elements can be between and coupled to each of the two elements.

[0115] It should be appreciated that the term vertical accounts for variations from “perfect” vertical due to normal manufacturing, measuring, and / or assembly variations, and the meaning of the term “vertical” would be known to one of ordinary skill in the art. For example, vertical can correspond to the z-direction. As used herein, when a particular element is “adjacent to” another element, the particular element can cover the other element, can be above or lateral to the other element, and / or can be in direct physical contact with the other element. For example, lateral can refer to a horizontal direction (e.g., y-direction or x-direction) that can be perpendicular to the z-direction.

[0116] While specific embodiments have been illustrated and described herein, it will be appreciated that various adaptations and modifications of these embodiments can be made by those skilled in the art. It is intended that the disclosure encompass all such adaptations and modifications. It should be understood that the above description is merely illustrative of various examples of aspects and is not intended to limit the scope of the disclosure. Combinations of the above embodiments can be obvious to those of ordinary skill in the art in view of the foregoing description. Other embodiments can be employed without departing from the scope of the disclosure. Accordingly, the scope of various embodiments of the disclosure should be determined not with reference to the above description, but instead with reference to the appended claims, alongside the full scope of equivalents to which such claims are entitled.

Claims

1. A method for forming conductive lines within a vertically stacked memory cell array, comprising: A first row and a second row of a first number of vertical conductive wire contacts are formed, wherein the vertical contacts in each row are arranged in a first horizontal direction, and the first row is spaced apart from the second row in a second horizontal direction; A first number of conductive wires having one or more curved portions at the same level are formed, and each conductive wire sequentially contacts an alternating conductive wire contact in the first row and the second row of the first number of vertical conductive wire contacts. as well as A second number of conductive lines are formed having one or more curved portions at the same level, each conductive line contacting the remaining conductive line contacts in the first and second rows of the first number of vertical conductive line contacts that are not contacted by the first number of conductive lines.

2. The method of claim 1, further comprising forming a plurality of deposits of a first dielectric adjacent to each of the first plurality of conductive lines on either side, and forming a second dielectric between each deposit of the first dielectric.

3. The method of claim 2, further comprising forming a second number of vertical conductive wire contacts by means of: A plurality of vertical openings are formed by selectively etching the second dielectric, wherein the plurality of vertical openings are aligned with the first plurality of conductive wire contacts; and Conductive material is formed into each of the plurality of vertical openings.

4. The method according to any one of claims 1 to 3, further comprising forming a third number of horizontal conductive lines having one or more curved portions, each of the third number of conductive lines contacting each of two adjacent rows of conductive line contacts in the second number of conductive line contacts.

5. The method according to any one of claims 1 to 3, wherein the second number of conductive wire contacts is longer than the first number of conductive wire contacts.

6. The method of claim 1, further comprising forming one or more masks before depositing the second dielectric material, the one or more masks being perpendicular to the rows of the first number of conductive line contacts and located between the first number of conductive line contacts.

7. The method according to claim 1, wherein the first number of conductive lines are shaped as a sine curve.

8. The method of claim 1, wherein the second number of conductive lines are shaped in the opposite manner to the first number of conductive lines.

9. A method for forming conductive lines within a vertically stacked memory cell array, comprising: Several layers are formed, each layer containing at least one of a conductive material and a dielectric material; A first row and a second row of a first number of vertically oriented conductive wire contacts are formed, wherein the vertical contacts in each row are arranged in a first horizontal direction, and the first row is spaced apart from the second row in a second horizontal direction; A first number of horizontally oriented conductive lines are formed having one or more curved portions at the same level, each conductive line being in sequential contact with alternating conductive line contacts in the first and second rows of the first number of conductive line contacts and with one or more layers of the plurality of layers. as well as A second number of conductive wires having one or more curved portions at the same level are formed, each conductive wire contacting the remaining conductive wire contacts in the first and second rows of the first number of vertical conductive wire contacts that are not contacted by the first number of conductive wires.

10. The method of claim 9, further comprising: Several deposits of a first dielectric are formed on either side of the first plurality of conductive lines; and A second dielectric material is formed between each deposit of the first dielectric.

11. The method of claim 10, further comprising forming a second number of vertical conductive wire contacts by: A plurality of vertical openings are formed by selectively etching the second dielectric material, wherein the plurality of vertical openings are aligned with the first plurality of conductive wire contacts; and Conductive material is formed into each of the second number of vertical openings.

12. The method of claim 11, further comprising forming a third number of horizontally oriented conductive lines having one or more curved portions, each of the third number of conductive lines contacting each of two adjacent rows of conductive line contacts of the second number of conductive line contacts and contacting one or more layers of the plurality of layers.

13. The method according to any one of claims 9 to 12, wherein each conductive wire comprises a metallic material.

14. The method according to any one of claims 9 to 12, wherein the dielectric material acts as a spacer.

15. A semiconductor memory device comprising: A vertically stacked memory cell array, comprising: A horizontal array of conductive wire contacts, wherein: The first row and the second row of the first number of vertical conductive wire contacts are arranged in the first horizontal direction, and the first row is spaced apart from the second row in the second horizontal direction; A first horizontal conductive line having one or more curved portions at the same level sequentially contacts the alternating conductive line contacts of the first row and the second row of the first number of vertical conductive line contacts. as well as A second horizontal conductive line having one or more curved portions at the same level above the first horizontal conductive line, each conductive line contacting the remaining conductive line contacts in the first and second rows of the first number of vertical conductive line contacts that were not contacted by the first horizontal conductive line.

16. The semiconductor memory device of claim 15, wherein the vertical direct contact contacted by the second horizontal conductive line is vertically longer than the vertical direct contact contacted by the first conductive line.

17. The semiconductor memory device of claim 15, further comprising a deposit of dielectric material adjacent to the first conductive line.

18. The semiconductor memory device according to any one of claims 15 to 17, wherein each conductive line contact is in contact with the substrate of the memory cell.

19. The semiconductor memory device according to any one of claims 15 to 17, wherein the vertical conductive line contacts of the first row of the first number of vertical conductive line contacts arranged in the first horizontal direction are non-uniformly spaced from each other.

20. The semiconductor memory device according to any one of claims 15 to 17, wherein the memory device is a three-dimensional 3D dynamic random access memory device.

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