Array substrate manufacturing method, array substrate and display panel

Abstract

The application discloses a preparation method of an array substrate, the array substrate and a display panel. The preparation method of the array substrate comprises the following steps: providing a substrate; forming a low-temperature polysilicon layer on the substrate, the low-temperature polysilicon layer having a source contact part and a drain contact part; forming a phosphorus ion heavily doped amorphous silicon layer on the low-temperature polysilicon layer in a phosphorus-containing gas atmosphere; performing a patterning treatment on the phosphorus ion heavily doped amorphous silicon layer to form a first ohmic contact part and a second ohmic contact part, the first ohmic contact part being connected with the source contact part, and the second ohmic contact part being connected with the drain contact part; forming a source electrode on the first ohmic contact part and a drain electrode on the second ohmic contact part. The application reduces the high process temperature caused by the phosphorus ion heavy doping in the array substrate, improves the applicability of the low-impedance metal in the array substrate, and further improves the performance of the display product.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a method for preparing an array substrate, the array substrate, and a display panel. Background Technology

[0002] Thin-film transistor liquid crystal displays (TFT-LCDs) have advantages such as low power consumption, high contrast, and space saving, making them the most mainstream display product on the market. Compared with traditional a-Si technology, low-temperature polycrystalline silicon (LTPS) technology has higher carrier mobility and is widely used in the fabrication of small-to-medium-sized, high-resolution TFT-LCDs and active-matrix organic light-emitting diode (AMOLED) display panels.

[0003] In the traditional LTPS (Low-Temperature Polymerization) technology for fabricating array substrates, the polysilicon layer in the TFT needs to be doped multiple times to ensure the electrical properties of the TFT. Doping methods include doping the entire channel with boron ions, forming heavily doped ohmic contact regions with phosphorus ions, and forming lightly doped regions with phosphorus ions, among others. In the method of forming heavily doped ohmic contact regions with phosphorus ions, on the one hand, the phosphorus ion doping process damages the structure of the polysilicon layer; on the other hand, since the doped phosphorus ions do not reach their most stable state, the heavily doped ohmic contact regions need to be activated at a high temperature approaching 600°C.

[0004] However, the aforementioned high-temperature processes limit the choice of materials for metal lines, such as gate lines, in the array substrate. For example, since low-resistivity metals such as aluminum or copper are not heat-resistant, their impedance increases significantly at temperatures above 400°C. Therefore, only heat-resistant metals such as molybdenum or titanium can be used for gate lines. However, using molybdenum or titanium as gate materials leads to problems such as low pixel charging rate and increased load, which greatly reduces the performance of display products. Therefore, how to reduce the high process temperature caused by heavy phosphorus ion doping in the array substrate and improve the applicability of low-resistivity metals in the array substrate has become an urgent technical problem to be solved. Summary of the Invention

[0005] This application provides a method for preparing an array substrate, an array substrate, and a display panel, in order to reduce the high process temperature caused by heavy phosphorus ion doping in the array substrate, improve the applicability of low-resistivity metals in the array substrate, and enhance the performance of display products.

[0006] This application provides a method for fabricating an array substrate, which includes the following steps:

[0007] Provide a base;

[0008] A low-temperature polycrystalline silicon layer is formed on the substrate, the low-temperature polycrystalline silicon layer having a source contact portion and a drain contact portion;

[0009] In a phosphorus-containing gas atmosphere, a phosphorus-doped amorphous silicon layer is formed on the low-temperature polycrystalline silicon layer.

[0010] The phosphorus-doped amorphous silicon layer is patterned to form a first ohmic contact and a second ohmic contact. The first ohmic contact is connected to the source contact, and the second ohmic contact is connected to the drain contact.

[0011] A source electrode is formed on the first ohmic contact, and a drain electrode is formed on the second ohmic contact.

[0012] Optionally, in some embodiments of this application, the phosphorus-containing gas is phosphorus trihydrogenate, and the step of forming a phosphorus-doped amorphous silicon layer on the low-temperature polycrystalline silicon layer includes: introducing silicon tetrahydrogenate, hydrogen gas and phosphorus trihydrogenate into the reaction chamber, wherein the silicon tetrahydrogenate, the hydrogen gas and the phosphorus trihydrogenate form a phosphorus-doped amorphous silicon layer.

[0013] Optionally, in some embodiments of this application, before the step of forming a phosphorus-doped amorphous silicon layer on the low-temperature polycrystalline silicon layer, the method further includes: forming a dielectric insulating layer on the low-temperature polycrystalline silicon layer, wherein a first via and a second via are formed in the dielectric insulating layer, the first via exposing the source contact portion, and the second via exposing the drain contact portion.

[0014] The step of patterning the phosphorus-doped amorphous silicon layer includes: etching the phosphorus-doped amorphous silicon layer to form a first ohmic contact and a second ohmic contact on the surface of the dielectric insulating layer away from the substrate, wherein the first ohmic contact extends into the first via and is connected to the exposed portion of the source contact, and the second ohmic contact extends into the second via and is connected to the exposed portion of the drain contact.

[0015] Optionally, in some embodiments of this application, the source electrode extends from the surface of the first ohmic contact away from the dielectric insulating layer into the first via, and the drain electrode extends from the surface of the second ohmic contact away from the dielectric insulating layer into the second via.

[0016] This application also provides an array substrate, which is prepared by the array substrate preparation method described in any of the foregoing embodiments.

[0017] Optionally, in some embodiments of this application, the array substrate further includes a gate located on the side of the low-temperature polysilicon layer near or away from the substrate, and the material of the gate includes copper and / or aluminum.

[0018] Optionally, in some embodiments of this application, the material of the source contact and the material of the drain contact are both phosphorus-doped amorphous silicon.

[0019] Optionally, in some embodiments of this application, the array substrate further includes a gate insulating layer and a gate. The gate insulating layer is located on the side of the low-temperature polysilicon layer away from the substrate. The gate is located between the gate insulating layer and the dielectric insulating layer. A third via and a fourth via are formed in the gate insulating layer. The third via communicates with the first via and exposes the source contact portion. The first ohmic contact portion extends sequentially into the first via and the third via. The fourth via communicates with the second via and exposes the drain contact portion. The second ohmic contact portion extends sequentially into the second via and the fourth via.

[0020] The source contact and the drain contact are both made of phosphorus-doped amorphous silicon.

[0021] Optionally, in some embodiments of this application, the array substrate further includes a gate insulating layer and a gate, wherein the gate insulating layer is located on the side of the low-temperature polysilicon layer close to the substrate, and the gate is located between the substrate and the gate insulating layer;

[0022] Wherein, the orthogonal projection of the gate onto the plane of the substrate covers the orthogonal projection of the low-temperature polycrystalline silicon layer onto the plane of the substrate, and the materials of the source contact and the drain contact are both amorphous silicon; or, the orthogonal projection of the gate onto the plane of the substrate lies within the orthogonal projection of the low-temperature polycrystalline silicon layer onto the plane of the substrate, and the materials of the source contact and the drain contact are both phosphorus-doped amorphous silicon.

[0023] This application also provides a display panel that includes an array substrate as described in any of the foregoing embodiments.

[0024] In the array substrate fabrication method provided in this application, after forming a low-temperature polycrystalline silicon layer, a phosphorus-doped amorphous silicon layer is formed in a phosphorus-containing gas atmosphere, and an ohmic contact connecting the low-temperature polycrystalline silicon layer to the source and drain electrodes is formed through a patterning process. Therefore, compared with the existing technology that uses an ion implanter for phosphorus-doping, since this application performs phosphorus-doping during the amorphous silicon layer film formation process, the phosphorus ions in this application can form a stable structure in the amorphous silicon layer. This eliminates the need for the high-temperature activation process in traditional phosphorus-doping methods, thereby reducing the fabrication temperature of the array substrate, improving the applicability of low-resistivity metals in the array substrate, and ultimately contributing to improved product performance. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. The accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic flowchart of the method for fabricating the array substrate provided in this application.

[0027] Figure 2 This is a schematic flowchart of the method for fabricating the array substrate provided in this application.

[0028] Figures 3A to 3H yes Figure 2 The diagram shows the structural results obtained sequentially from each step of the fabrication method of the array substrate.

[0029] Figure 4 This is a schematic flowchart of the method for fabricating an array substrate provided in the second embodiment of this application.

[0030] Figures 5A to 5F yes Figure 4 The diagram shows the structural results obtained sequentially from each step of the fabrication method of the array substrate.

[0031] Figure 6 This is a schematic flowchart of the method for fabricating an array substrate provided in the third embodiment of this application.

[0032] Figures 7A to 7G yes Figure 6 The diagram shows the structural results obtained sequentially from each step of the fabrication method of the array substrate.

[0033] Figure 8 This is a schematic diagram of the structure of the display panel provided in this application. Detailed Implementation

[0034] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0035] This application provides a method for fabricating an array substrate, the array substrate, and a display panel. These will be described in detail below.

[0036] Please refer to Figure 1 This application provides a method for fabricating an array substrate, which includes the following steps:

[0037] 101: Provides a base;

[0038] 102: A low-temperature polysilicon layer is formed on a substrate, the low-temperature polysilicon layer having a source contact and a drain contact;

[0039] 103: In a phosphorus-containing gas atmosphere, a phosphorus-doped amorphous silicon layer is formed on a low-temperature polycrystalline silicon layer;

[0040] 104: Patterning a phosphorus-doped amorphous silicon layer to form a first ohmic contact connected to the source contact and a second ohmic contact connected to the drain contact; and

[0041] 105: The source is formed on the first ohmic contact and the drain is formed on the second ohmic contact.

[0042] Therefore, in the array substrate fabrication method provided in this application, after forming a low-temperature polycrystalline silicon layer, a phosphorus-doped amorphous silicon layer is formed in a phosphorus-containing gas atmosphere, and an ohmic contact connecting the low-temperature polycrystalline silicon layer to the source and drain electrodes is formed through a patterning process. Therefore, compared to the existing technology that uses an ion implanter for phosphorus-doping, since phosphorus doping is performed during the amorphous silicon layer film formation process in this application, the phosphorus ions can form a stable structure in the amorphous silicon layer. This eliminates the need for the high-temperature activation process in traditional phosphorus-doping methods, thereby reducing the fabrication temperature of the array substrate, improving the applicability of low-resistivity metals in the array substrate, and ultimately contributing to improved product performance.

[0043] The fabrication method of the array substrate provided in this application will be described in detail below through specific embodiments. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0044] Please refer to Figure 2 , Figures 3A to 3H The first embodiment of this application provides a method for fabricating an array substrate 100 with a top-gate thin-film transistor, which includes the following steps:

[0045] 201: Provide substrate 10, such as Figure 3A As shown.

[0046] Specifically, the substrate 10 can be a rigid substrate, such as a glass substrate; or the substrate 10 can be a flexible substrate, such as a polyimide substrate. This application does not specifically limit the material of the substrate 10.

[0047] 202: A light-shielding portion 11, a buffer layer 12, and a low-temperature polycrystalline silicon layer 13 are sequentially formed on the substrate 10, such as... Figure 3B As shown.

[0048] First, a light-shielding portion 11 is formed on the substrate 10 sequentially using physical vapor deposition (PVD) and photolithography. The material of the light-shielding portion 11 may include one or more of molybdenum, copper, titanium, and aluminum. Second, a buffer layer 12 is formed on the light-shielding portion 11 using chemical vapor deposition (CVD). The material of the buffer layer 12 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride. Finally, an amorphous silicon layer is deposited on the buffer layer 12 using PVD, and a low-temperature polycrystalline silicon layer 13 is formed using a low-temperature crystallization process such as laser annealing or metal solid-state crystallization. The low-temperature polycrystalline silicon layer 13 includes a channel portion 131 and source contact portions 132 and drain contact portions 133 located on opposite sides of the channel portion 131.

[0049] 203: A gate insulating layer 14 and a gate 15 are sequentially formed on the low-temperature polysilicon layer 13, as follows: Figure 3C As shown.

[0050] First, a gate insulating layer 14 is formed on the low-temperature polysilicon layer 13 using a chemical vapor deposition process. The material of the gate insulating layer 14 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0051] Next, a gate 15 is formed on the gate insulating layer 14 using physical vapor deposition and photolithography processes. The orthogonal projection of the gate 15 onto the plane of the substrate 10 lies within the orthogonal projection of the channel portion 131 onto the plane of the substrate 10. The material of the gate 15 may include one or more metals, such as copper, molybdenum, titanium, and aluminum; alternatively, the material of the gate 15 may also include an alloy composed of at least two of the aforementioned metals. It should be noted that the gate 15 can be a single-layer, double-layer, or multi-layer structure. This embodiment only illustrates the case where the gate 15 is a single-layer structure and should not be construed as limiting the scope of this application.

[0052] 204: Using gate 15 as a mask, the source contact 132 and drain contact 133 are lightly doped with phosphorus ions, such as... Figure 3D As shown.

[0053] Specifically, after lightly doping the source contact 132 and drain contact 133 with phosphorus ions using an ion implanter, both the source contact 132 and drain contact 133 are made of lightly phosphorus-doped amorphous silicon. This arrangement avoids excessive carrier concentration in the source contact 132 and drain contact 133, which could damage the device and thus increase its stability.

[0054] It is understood that in this embodiment, phosphorus ion light doping is relative to phosphorus ion heavy doping, wherein the phosphorus ion doping amount in phosphorus ion light doping is less than the phosphorus ion doping amount in phosphorus ion heavy doping.

[0055] 205: A dielectric insulating layer 16 is formed on the gate 15, and the dielectric insulating layer 16 and the gate insulating layer 14 are patterned to form a first via 161 and a second via 162 in the dielectric insulating layer 16, and a third via 141 and a fourth via 142 in the gate insulating layer 14. The third via 141 connects to the first via 161 and exposes the source contact 132, and the fourth via 142 connects to the second via 162 and exposes the drain contact 133. Figure 3E As shown.

[0056] 206: In a phosphorus-containing gas atmosphere, a phosphorus-doped amorphous silicon layer 17 is formed on the dielectric insulating layer 16, such as... Figure 3F As shown.

[0057] In this embodiment, the phosphorus-containing gas is phosphorus trihydrogenase.

[0058] Specifically, step 206 includes: introducing silicon tetrahydrogenide, hydrogen, and phosphorus trihydrogenide into the reaction chamber using a physical vapor deposition process. First, silicon tetrahydrogenide and hydrogen react to generate amorphous silicon. Since the above reaction system is located in the atmosphere of phosphorus trihydrogenide, phosphorus ions provided by phosphorus trihydrogenide can be incorporated during the amorphous silicon film formation process. Then, the phosphorus-doped amorphous silicon gradually deposits onto the dielectric insulating layer 16, forming a phosphorus-doped amorphous silicon layer 17.

[0059] Specifically, the phosphorus-doped amorphous silicon layer 17 extends sequentially to cover the first via 161 and the third via 141 corresponding to the source contact portion 132, and contacts the exposed portion of the source contact portion 132; the phosphorus-doped amorphous silicon layer 17 extends sequentially to cover the second via 162 and the fourth via 142 corresponding to the drain contact portion 133, and contacts the exposed portion of the drain contact portion 133.

[0060] 207: The phosphorus-doped amorphous silicon layer 17 is patterned to form a first ohmic contact 171 connected to the source contact 132 and a second ohmic contact 172 connected to the drain contact 133, such as... Figure 3G As shown.

[0061] In this process, a phosphorus-doped amorphous silicon layer 17 is etched using photolithography to form patterned first ohmic contacts 171 and second ohmic contacts 172. The first ohmic contact 171 extends into the first via 161 and the third via 141, and connects to the exposed portion of the source contact 132. The second ohmic contact 172 extends into the second via 162 and the fourth via 142, and connects to the exposed portion of the drain contact 133. Since this etching process occurs after the formation of the dielectric insulating layer 16, the etching process does not damage the low-temperature polysilicon layer 13 due to the coverage of the dielectric insulating layer 16.

[0062] 208: A source electrode 181 is formed on the first ohmic contact 171, and a drain electrode 182 is formed on the second ohmic contact 172, as shown. Figure 3H As shown. In this embodiment, the low-temperature polysilicon layer 13, the gate 15, the source 181, and the drain 182 constitute a thin-film transistor.

[0063] Specifically, the source electrode 181 and the drain electrode 182 are formed sequentially using physical vapor deposition and photolithography. The source electrode 181 and the drain electrode 182 are made of the same material, which may include one or more of copper, molybdenum, titanium and aluminum.

[0064] In this embodiment, the source electrode 181 covers the first ohmic contact portion 171. Specifically, the source electrode 181 extends sequentially from the surface of the first ohmic contact portion 171 away from the dielectric insulating layer 16 into the first via 161 and the third via 141. The drain electrode 182 covers the second ohmic contact portion 172. Specifically, the drain electrode 182 extends sequentially from the surface of the second ohmic contact portion 172 away from the dielectric insulating layer 16 into the second via 162 and the fourth via 142.

[0065] Since the source 181 and the first ohmic contact 171, as well as the drain 182 and the second ohmic contact 172, are connected within a via in this embodiment, the source 181 and the first ohmic contact 171, as well as the drain 182 and the second ohmic contact 172, all have a large contact area. This improves the contact resistance between the source 181 and the first ohmic contact 171 and between the drain 182 and the second ohmic contact 172, thereby enhancing the conductivity of the thin-film transistor and improving the mobility of the thin-film transistor device.

[0066] Following step 208, the fabrication method of the array substrate 100 further includes forming a planarization layer 19, a common electrode 20, a passivation layer 21, and a pixel electrode 22 stacked on the source electrode 181 and the drain electrode 182. The pixel electrode 22 is connected to the drain electrode 182 via a via (not shown in the figure). It should be noted that the above structure and fabrication method are prior art and will not be described in detail here.

[0067] Compared to existing technologies that use ion implanters for heavy phosphorus doping, this embodiment performs heavy phosphorus doping during the amorphous silicon layer deposition process. Therefore, the phosphorus ions in this embodiment can form a stable structure within the amorphous silicon layer, eliminating the need for the high-temperature activation process required in traditional heavy phosphorus doping methods. This reduces the fabrication temperature of the array substrate 100; specifically, this embodiment can lower the fabrication temperature of the array substrate 100 to below 400°C. Consequently, the limitations on the high-temperature resistance of materials for metal lines such as the gate 15 are reduced. For example, this embodiment can use low-resistance metals such as copper or aluminum as the material for the gate 15, thereby improving pixel charge rate and reducing load. Therefore, this embodiment improves the applicability of low-resistance metals in the array substrate 100, thereby enhancing product performance.

[0068] Please refer to Figure 4 , Figures 5A to 5F The second embodiment of this application provides a method for fabricating an array substrate 100 with a bottom-gate thin-film transistor, which includes the following steps:

[0069] 301: Provides substrate 10, such as Figure 5A As shown.

[0070] Specifically, the substrate 10 can be a rigid substrate, such as a glass substrate; or the substrate 10 can be a flexible substrate, such as a polyimide substrate. This application does not specifically limit the material of the substrate 10.

[0071] 302: A gate 15, a gate insulating layer 14, and a low-temperature polysilicon layer 13 are sequentially formed on the substrate 10, such as... Figure 5B As shown.

[0072] First, a gate 15 is formed on the substrate 10 using physical vapor deposition and photolithography processes sequentially. The material of the gate 15 may include one or more metals, such as copper, molybdenum, titanium, and aluminum; alternatively, the material of the gate 15 may also include an alloy composed of at least two of the aforementioned metals. It should be noted that the gate 15 can be a single-layer, double-layer, or multi-layer structure. This embodiment only illustrates the case where the gate 15 is a single-layer structure and should not be construed as limiting the scope of this application.

[0073] Next, a gate insulating layer 14 is formed on the gate 15 using a chemical vapor deposition process. The material of the gate insulating layer 14 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0074] Next, an amorphous silicon layer is deposited on the gate insulating layer 14, and a low-temperature polycrystalline silicon layer 13 is formed using a low-temperature crystallization process such as laser annealing or metal solid-state crystallization. The orthogonal projection of the gate 15 onto the plane of the substrate 10 covers the orthogonal projection of the low-temperature polycrystalline silicon layer 13 onto the plane of the substrate 10.

[0075] In this embodiment, the low-temperature polysilicon layer 13 includes a channel portion 131 and source contact portion 132 and drain contact portion 133 located on opposite sides of the channel portion 131.

[0076] 303: A dielectric insulating layer 16 is formed on the low-temperature polysilicon layer 13, and the dielectric insulating layer 16 is patterned to form a first via 161 and a second via 162 in the dielectric insulating layer 16. The first via 161 exposes the source contact portion 132, and the second via 162 exposes the drain contact portion 133, as shown. Figure 5C As shown.

[0077] 304: In a phosphorus-containing gas atmosphere, a phosphorus-doped amorphous silicon layer 17 is formed on the dielectric insulating layer 16, such as... Figure 5D As shown.

[0078] In this embodiment, the phosphorus-containing gas is phosphorus trihydrogenase.

[0079] Specifically, step 304 includes: introducing silicon tetrahydrogen, hydrogen, and phosphorus trihydrogen into the reaction chamber using a physical vapor deposition process. First, silicon tetrahydrogen and hydrogen react to generate amorphous silicon. Since the above reaction system is located in the atmosphere of phosphorus trihydrogen, phosphorus ions provided by phosphorus trihydrogen can be incorporated during the amorphous silicon film formation process. Then, the phosphorus-doped amorphous silicon gradually deposits onto the dielectric insulating layer 16, forming a phosphorus-doped amorphous silicon layer 17.

[0080] Specifically, the phosphorus-doped amorphous silicon layer 17 extends to a portion corresponding to the source contact 132 and covers the first via 161, and contacts the exposed portion of the source contact 132; the phosphorus-doped amorphous silicon layer 17 extends to a portion corresponding to the drain contact 133 and covers the second via 162, and contacts the exposed portion of the drain contact 133.

[0081] 305: The phosphorus-doped amorphous silicon layer 17 is patterned to form a first ohmic contact 171 connected to the source contact 132 and a second ohmic contact 172 connected to the drain contact 133, such as... Figure 5E As shown.

[0082] In this process, a phosphorus-doped amorphous silicon layer 17 is etched using photolithography to form patterned first ohmic contacts 171 and second ohmic contacts 172. The first ohmic contact 171 extends into the first via 161 and connects to the exposed portion of the source contact 132. The second ohmic contact 172 extends into the second via 162 and connects to the exposed portion of the drain contact 133. Since the etching process occurs after the formation of the dielectric insulating layer 16, the etching process does not damage the low-temperature polysilicon layer 13 due to the coverage of the dielectric insulating layer 16.

[0083] 306: A source electrode 181 is formed on the first ohmic contact 171, and a drain electrode 182 is formed on the second ohmic contact 172, as shown below. Figure 5F As shown.

[0084] Specifically, the source electrode 181 and the drain electrode 182 are formed sequentially using physical vapor deposition and photolithography. The source electrode 181 and the drain electrode 182 are made of the same material, which may include one or more of copper, molybdenum, titanium and aluminum.

[0085] In this embodiment, the source electrode 181 covers the first ohmic contact 171. Specifically, the source electrode 181 extends from the surface of the first ohmic contact 171 away from the dielectric insulating layer 16 into the first via 161. The drain electrode 182 covers the second ohmic contact 172. Specifically, the drain electrode 182 extends from the surface of the second ohmic contact 172 away from the dielectric insulating layer 16 into the second via 162.

[0086] Since the source 181 and the first ohmic contact 171, as well as the drain 182 and the second ohmic contact 172, are connected within a via in this embodiment, the source 181 and the first ohmic contact 171, as well as the drain 182 and the second ohmic contact 172, all have a large contact area. This improves the contact resistance between the source 181 and the first ohmic contact 171 and between the drain 182 and the second ohmic contact 172, thereby enhancing the conductivity of the thin-film transistor and improving the mobility of the thin-film transistor device.

[0087] Following step 306, the fabrication method of the array substrate 100 further includes forming a planarization layer 19, a common electrode 20, a passivation layer 21, and a pixel electrode 22 stacked on the source electrode 181 and the drain electrode 182. The pixel electrode 22 is connected to the drain electrode 182 via a via (not shown in the figure). It should be noted that the above structure and fabrication method are prior art and will not be described in detail here.

[0088] Compared to the existing technology that uses an ion implanter for heavy phosphorus doping, this embodiment performs heavy phosphorus doping during the amorphous silicon layer deposition process. Therefore, the phosphorus ions in this embodiment can form a stable structure in the amorphous silicon layer, eliminating the need for the high-temperature activation process in traditional heavy phosphorus doping methods. This reduces the processing temperature of the array substrate 100; specifically, this embodiment can reduce the processing temperature of the array substrate 100 to below 400°C. Consequently, the limitations on the high-temperature resistance of materials for metal lines such as the gate 15 are reduced. For example, this embodiment can use low-resistance metals such as copper or aluminum as the material for the gate 15, thereby improving pixel charge rate and reducing load. Therefore, this embodiment improves the applicability of low-resistance metals in the array substrate 100, thereby enhancing product performance. Furthermore, since this embodiment eliminates the need for light phosphorus doping of the source contact 132 and drain contact 133, the process flow is simplified, and process costs are reduced.

[0089] Please refer to Figure 6 , Figures 7A to 7G The third embodiment of this application provides a method for fabricating an array substrate 100 with a bottom-gate thin-film transistor, which includes the following steps:

[0090] 401: Provide substrate 10, such as Figure 7A As shown.

[0091] Specifically, the substrate 10 can be a rigid substrate, such as a glass substrate; or the substrate 10 can be a flexible substrate, such as a polyimide substrate. This application does not specifically limit the material of the substrate 10.

[0092] 402: A gate 15, a gate insulating layer 14, and a low-temperature polysilicon layer 13 are sequentially formed on the substrate 10, such as... Figure 7B As shown.

[0093] First, a gate 15 is formed on the substrate 10 using physical vapor deposition and photolithography processes sequentially. The material of the gate 15 may include one or more metals, such as copper, molybdenum, titanium, and aluminum; alternatively, the material of the gate 15 may also include an alloy composed of at least two of the aforementioned metals. It should be noted that the gate 15 can be a single-layer, double-layer, or multi-layer structure. This embodiment only illustrates the case where the gate 15 is a single-layer structure and should not be construed as limiting this application.

[0094] Next, a gate insulating layer 14 is formed on the gate 15 using a chemical vapor deposition process. The material of the gate insulating layer 14 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0095] Next, an amorphous silicon layer is deposited on the gate insulating layer 14, and a low-temperature polycrystalline silicon layer 13 is formed using a low-temperature crystallization process such as laser annealing or metal solid-state crystallization. The low-temperature polycrystalline silicon layer 13 includes a channel portion 131 and source contact portions 132 and drain contact portions 133 located on opposite sides of the channel portion 131.

[0096] In this embodiment, the orthographic projection of the gate 15 onto the plane of the substrate 10 lies within the orthographic projection of the low-temperature polysilicon layer 13 onto the plane of the substrate 10. Furthermore, the orthographic projection of the gate 15 onto the plane of the substrate 10 may overlap with the orthographic projection of the channel portion 131 onto the plane of the substrate 10.

[0097] 403: Lightly dope the source contact 132 and drain contact 133 with phosphorus ions, such as... Figure 7C As shown.

[0098] Specifically, after lightly doping the source contact 132 and drain contact 133 with phosphorus ions using an ion implanter, both the source contact 132 and drain contact 133 are made of lightly phosphorus-doped amorphous silicon. This arrangement avoids excessive carrier concentration in the source contact 132 and drain contact 133, which could damage the device and thus increase its stability.

[0099] It is understood that in this embodiment, phosphorus ion light doping is relative to phosphorus ion heavy doping, wherein the phosphorus ion doping amount in phosphorus ion light doping is less than the phosphorus ion doping amount in phosphorus ion heavy doping.

[0100] 404: A dielectric insulating layer 16 is formed on the low-temperature polysilicon layer 13, and the dielectric insulating layer 16 is patterned to form a first via 161 and a second via 162 in the dielectric insulating layer 16. The first via 161 exposes the source contact portion 132, and the second via 162 exposes the drain contact portion 133, as shown. Figure 7D As shown.

[0101] 405: In a phosphorus-containing gas atmosphere, a phosphorus-doped amorphous silicon layer 17 is formed on the dielectric insulating layer 16, such as... Figure 7E As shown.

[0102] In this embodiment, the phosphorus-containing gas is phosphorus trihydrogenase.

[0103] Specifically, step 405 includes: introducing silicon tetrahydrogenide, hydrogen, and phosphorus trihydrogenide into the reaction chamber using a physical vapor deposition process. First, silicon tetrahydrogenide and hydrogen react to generate amorphous silicon. Since the above reaction system is located in the atmosphere of phosphorus trihydrogenide, phosphorus ions provided by phosphorus trihydrogenide can be incorporated during the amorphous silicon film formation process. Then, the phosphorus-doped amorphous silicon gradually deposits onto the dielectric insulating layer 16, forming a phosphorus-doped amorphous silicon layer 17.

[0104] Specifically, the phosphorus-doped amorphous silicon layer 17 extends to a portion corresponding to the source contact 132 and covers the first via 161, and contacts the exposed portion of the source contact 132; the phosphorus-doped amorphous silicon layer 17 extends to a portion corresponding to the drain contact 133 and covers the second via 162, and contacts the exposed portion of the drain contact 133.

[0105] 406: The phosphorus-doped amorphous silicon layer 17 is patterned to form a first ohmic contact 171 connected to the source contact 132 and a second ohmic contact 172 connected to the drain contact 133, such as... Figure 7F As shown.

[0106] In this process, a phosphorus-doped amorphous silicon layer 17 is etched using photolithography to form patterned first ohmic contacts 171 and second ohmic contacts 172. The first ohmic contact 171 extends into the first via 161 and connects to the exposed portion of the source contact 132. The second ohmic contact 172 extends into the second via 162 and connects to the exposed portion of the drain contact 133. Since the etching process occurs after the formation of the dielectric insulating layer 16, the etching process does not damage the low-temperature polysilicon layer 13 due to the coverage of the dielectric insulating layer 16.

[0107] 407: A source electrode 181 is formed on the first ohmic contact 171, and a drain electrode 182 is formed on the second ohmic contact 172, as shown. Figure 7G As shown.

[0108] Specifically, the source electrode 181 and the drain electrode 182 are formed sequentially using physical vapor deposition and photolithography. The source electrode 181 and the drain electrode 182 are made of the same material, which may include one or more of copper, molybdenum, titanium and aluminum.

[0109] In this embodiment, the source electrode 181 covers the first ohmic contact 171. Specifically, the source electrode 181 extends from the surface of the first ohmic contact 171 away from the dielectric insulating layer 16 into the first via 161. The drain electrode 182 covers the second ohmic contact 172. Specifically, the drain electrode 182 extends from the surface of the second ohmic contact 172 away from the dielectric insulating layer 16 into the second via 162.

[0110] Since the source 181 and the first ohmic contact 171, as well as the drain 182 and the second ohmic contact 172, are connected within a via in this embodiment, the source 181 and the first ohmic contact 171, as well as the drain 182 and the second ohmic contact 172, all have a large contact area. This improves the contact resistance between the source 181 and the first ohmic contact 171 and between the drain 182 and the second ohmic contact 172, thereby enhancing the conductivity of the thin-film transistor and improving the mobility of the thin-film transistor device.

[0111] Following step 407, the fabrication method of the array substrate 100 further includes forming a planarization layer 19, a common electrode 20, a passivation layer 21, and a pixel electrode 22 stacked on the source electrode 181 and the drain electrode 182. The pixel electrode 22 is connected to the drain electrode 182 via a via (not shown in the figure). It should be noted that the above structure and fabrication method are prior art and will not be described in detail here.

[0112] Compared to existing technologies that use ion implanters for heavy phosphorus doping, this embodiment performs heavy phosphorus doping during the amorphous silicon layer deposition process. Therefore, the phosphorus ions in this embodiment can form a stable structure within the amorphous silicon layer, eliminating the need for the high-temperature activation process required in traditional heavy phosphorus doping methods. This reduces the fabrication temperature of the array substrate 100; specifically, this embodiment can lower the fabrication temperature of the array substrate 100 to below 400°C. Consequently, the limitations on the high-temperature resistance of materials for metal lines such as the gate 15 are reduced. For example, this embodiment can use low-resistance metals such as copper or aluminum as the material for the gate 15, thereby improving pixel charge rate and reducing load. Therefore, this embodiment improves the applicability of low-resistance metals in the array substrate 100, thereby enhancing product performance.

[0113] This application also provides a display panel. The display panel can be a liquid crystal display panel, an organic light-emitting diode (OLED) display panel, a miniature OLED display panel, or a micro OLED display panel. This application only uses a liquid crystal display panel as an example for description, but is not limited thereto.

[0114] Please refer to Figure 8 The display panel 1000 includes an array substrate 100 and a color filter substrate 200 disposed opposite to each other, and a liquid crystal layer 300 disposed between the array substrate 100 and the color filter substrate 200. The array substrate 100 can be prepared by the method described in any of the foregoing embodiments, and the relevant preparation methods can be referred to the descriptions of the foregoing embodiments, and will not be repeated here. Furthermore, the related technologies of the color filter substrate 200 and the liquid crystal layer 300 are prior art and will not be described further here.

[0115] The above provides a detailed description of the preparation method of an array substrate, the array substrate, and the display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for fabricating an array substrate, characterized in that, Includes the following steps: Provide a base; A low-temperature polycrystalline silicon layer is formed on the substrate, the low-temperature polycrystalline silicon layer having a source contact portion and a drain contact portion; The source contact and the drain contact are lightly doped with phosphorus ions. In a phosphorus-containing gas atmosphere, a phosphorus-doped amorphous silicon layer is formed on the source and drain contacts after light phosphorus ion doping. The phosphorus-doped amorphous silicon layer is patterned to form a first ohmic contact and a second ohmic contact. The first ohmic contact is connected to the source contact after phosphorus ion doping, and the second ohmic contact is connected to the drain contact after phosphorus ion doping. as well as A source electrode is formed on the first ohmic contact, and a drain electrode is formed on the second ohmic contact.

2. The method for fabricating an array substrate according to claim 1, characterized in that, The phosphorus-containing gas is phosphorus trihydrogenate. The step of forming a phosphorus-doped amorphous silicon layer on the source contact and the drain contact after light phosphorus ion doping includes: introducing silicon tetrahydrogenate, hydrogen gas and phosphorus trihydrogenate into the reaction chamber, wherein the silicon tetrahydrogenate, the hydrogen gas and the phosphorus trihydrogenate form a phosphorus-doped amorphous silicon layer.

3. The method for fabricating an array substrate according to claim 1, characterized in that, Before the step of forming a phosphorus-doped amorphous silicon layer on the source contact and the drain contact after light phosphorus ion doping, the method further includes: forming a dielectric insulating layer on the low-temperature polycrystalline silicon layer, wherein a first via and a second via are formed in the dielectric insulating layer, the first via exposing the source contact and the second via exposing the drain contact. The step of patterning the phosphorus-doped amorphous silicon layer includes: etching the phosphorus-doped amorphous silicon layer to form a first ohmic contact and a second ohmic contact on the surface of the dielectric insulating layer away from the substrate, wherein the first ohmic contact extends into the first via and is connected to the exposed portion of the source contact, and the second ohmic contact extends into the second via and is connected to the exposed portion of the drain contact.

4. The method for fabricating an array substrate according to claim 3, characterized in that, The source electrode extends from the surface of the first ohmic contact away from the dielectric insulating layer into the first via, and the drain electrode extends from the surface of the second ohmic contact away from the dielectric insulating layer into the second via.

5. An array substrate, characterized in that, The array substrate is prepared by the method for preparing the array substrate according to any one of claims 1 to 4.

6. The array substrate according to claim 5, characterized in that, The array substrate further includes a gate located on the side of the low-temperature polysilicon layer near or away from the substrate, and the material of the gate includes copper and / or aluminum.

7. The array substrate according to claim 5, characterized in that, Both the source contact and the drain contact are made of phosphorus-doped amorphous silicon.

8. The array substrate according to claim 5, characterized in that, The array substrate is prepared by the method for preparing the array substrate according to claim 3; The array substrate further includes a gate insulating layer and a gate. The gate insulating layer is located on the side of the low-temperature polysilicon layer away from the substrate. The gate is located between the gate insulating layer and the dielectric insulating layer. A third via and a fourth via are formed in the gate insulating layer. The third via is connected to the first via and exposes the source contact portion. The first ohmic contact portion extends sequentially into the first via and the third via. The fourth via is connected to the second via and exposes the drain contact portion. The second ohmic contact portion extends sequentially into the second via and the fourth via. The source contact and the drain contact are both made of phosphorus-doped amorphous silicon.

9. The array substrate according to claim 5, characterized in that, The array substrate is prepared by the method for preparing the array substrate according to claim 3; the array substrate further includes a gate insulating layer and a gate, the gate insulating layer is located on the side of the low-temperature polysilicon layer close to the substrate, and the gate is located between the substrate and the gate insulating layer; Wherein, the orthogonal projection of the gate onto the plane of the substrate covers the orthogonal projection of the low-temperature polycrystalline silicon layer onto the plane of the substrate, and the materials of the source contact and the drain contact are both amorphous silicon; or, the orthogonal projection of the gate onto the plane of the substrate lies within the orthogonal projection of the low-temperature polycrystalline silicon layer onto the plane of the substrate, and the materials of the source contact and the drain contact are both phosphorus-doped amorphous silicon.

10. A display panel, characterized in that, Includes the array substrate as described in any one of claims 5 to 9.

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