Display panel and its manufacturing method

Abstract

The present application discloses a display panel and a manufacturing method thereof. The display panel includes an adjacent display area and a non-display area. The display panel includes a substrate, a transistor layer, and a light-emitting layer. The transistor layer is disposed on the substrate. The transistor layer includes a complementary part, transistors, and a wiring part located in the display area. The transistors and the wiring part are spaced apart. The orthographic projection of the transistors on the substrate is staggered from the orthographic projection of the complementary part and the wiring part on the substrate. Among them, the orthographic projection of the complementary part and the wiring part on the substrate is staggered, or the orthographic projection of the complementary part and the wiring part on the substrate overlaps. The light-emitting layer is disposed on the transistor layer and is located in the display area. By providing the complementary part, the step difference of the transistor layer in the display area can be reduced, thereby improving the flatness of the transistor layer, so that the film thickness of the formed light-emitting layer is uniform, and thus the display effect of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and particularly to a display panel and a method for manufacturing the same. Background Art

[0002] In a display device, a light-emitting layer is usually formed by inkjet printing on a pixel region. After the ink is printed onto the pixel region, it is fluid. One of the important factors affecting whether the ink can spread evenly and well is the flatness of the pixel region. If the flatness of the pixel region does not meet the requirements, it will cause uneven spreading of the ink, resulting in a poor light-emitting effect of the entire device.

[0003] Currently, after the transistors are fabricated, a non-flat surface with different heights is formed. Usually, a planarization layer is fabricated on the transistors to fill the non-uniform surface of the transistors. However, the planarization effect of using the planarization layer is limited and cannot meet the requirements of the flatness of the pixel region, thereby causing uneven spreading of the ink and resulting in a poor light-emitting effect of the entire device. Summary of the Invention

[0004] Embodiments of the present application provide a display panel and a method for manufacturing the same to solve the problem of low surface flatness of the transistor layer in the prior art.

[0005] The present application further provides a display panel. The display panel includes an adjacent display region and a non-display region, and includes:

[0006] A substrate;

[0007] A transistor layer, the transistor layer is disposed on the substrate, the transistor layer includes at least one complementary portion, at least one transistor, and at least one wiring portion. Each of the complementary portions, each of the transistors, and each of the wiring portions is located in the display region. Each of the transistors is disposed at an interval from one of the wiring portions. The orthographic projection of the transistor on the substrate, the orthographic projection of the wiring portion on the substrate, and the orthographic projection of the complementary portion on the substrate are staggered;

[0008] Wherein, the orthographic projection of the complementary portion on the substrate is staggered from the orthographic projection of the wiring portion on the substrate, or the orthographic projection of the complementary portion on the substrate overlaps with the orthographic projection of the wiring portion on the substrate; and

[0009] A light-emitting layer, the light-emitting layer is disposed on the transistor layer and is located in the display region.

[0010] Optionally, in some embodiments of the present application, the wiring portion includes at least two of a control wiring, a signal wiring, and an electrode wiring that are stacked, and the orthographic projection of the complementary portion on the substrate is staggered from the orthographic projection of the wiring portion on the substrate.

[0011] Optionally, in some embodiments of the present application, the transistor includes an active portion, the wiring portion includes a control wiring and a signal wiring, the active portion, the complementary portion, and the control wiring are disposed on the substrate in the same layer, the signal wiring is disposed at an interval from the complementary portion and the active portion, and the signal wiring is disposed corresponding to the control wiring.

[0012] Optionally, in some embodiments of the present application, the transistor includes a light-shielding portion, the wiring portion includes a signal wiring and a control wiring, the complementary portion, the light-shielding portion, and the signal wiring are disposed on the substrate in the same layer, the control wiring is disposed at an interval from the light-shielding portion, and the control wiring is located above the signal wiring.

[0013] Optionally, in some embodiments of the present application, the transistor layer further includes a buffer layer, the transistor further includes an insulating portion and a gate, the wiring portion further includes a dielectric portion, and the transistor layer further includes an interlayer dielectric layer;

[0014] The buffer layer covers the signal wiring, the complementary portion, and the light-shielding portion;

[0015] The active portion, the insulating portion, and the gate are sequentially stacked on the buffer layer and are disposed corresponding to the light-shielding portion;

[0016] The dielectric portion and the control wiring are sequentially stacked on the buffer layer and are disposed corresponding to the signal wiring;

[0017] The interlayer dielectric layer is disposed on the buffer layer, the active portion, the insulating portion, the gate, the dielectric portion, and the control wiring.

[0018] The transistor further includes source-drain electrodes, the wiring portion further includes electrode wirings, the transistor layer further includes a passivation layer and a planarization layer, the source-drain electrodes and the electrode wirings are in the same layer and are disposed at an interval on the interlayer dielectric layer, the source-drain electrodes are connected to and disposed corresponding to the active portion, the electrode wirings are disposed corresponding to the control wiring, and the passivation layer and the planarization layer are sequentially stacked on the interlayer dielectric layer, the source-drain electrodes, and the electrode wirings.

[0019] Optionally, in some embodiments of the present application, the sum of the thicknesses of the transistor, the buffer layer, the interlayer dielectric layer, the passivation layer, and the planarization layer and the sum of the thicknesses of the wiring portion, the buffer layer, the interlayer dielectric layer, the passivation layer, and the planarization layer are both less than the sum of the thicknesses of the buffer layer, the interlayer dielectric layer, the passivation layer, and the planarization layer;

[0020] The sum of the thicknesses of the transistor, the buffer layer, the interlayer dielectric layer, the passivation layer, and the planarization layer, and the sum of the thicknesses of the routing portion, the buffer layer, the interlayer dielectric layer, the passivation layer, and the planarization layer are equal to the sum of the thicknesses of the complementary portion, the buffer layer, the interlayer dielectric layer, the passivation layer, and the planarization layer.

[0021] Optionally, in some embodiments of the present application, the routing portion includes one of a control routing, a signal routing, and an electrode routing, and the orthographic projection of the complementary portion on the substrate overlaps with the orthographic projection of the routing portion on the substrate.

[0022] Optionally, in some embodiments of the present application, the transistor includes a light-shielding portion, the routing portion includes a signal routing, the complementary portion and the light-shielding portion are disposed on the substrate in the same layer, and the signal routing is disposed on a surface of the complementary portion away from the substrate.

[0023] Optionally, in some embodiments of the present application, the orthographic projection of the complementary portion on the substrate is offset from the orthographic projection of the routing portion on the substrate, and the thickness difference between the surface of the transistor layer having the complementary portion away from the substrate and the surface of the transistor layer having the transistor away from the substrate and the surface of the transistor layer having the routing portion away from the substrate is less than 400 nanometers.

[0024] Optionally, in some embodiments of the present application, the orthographic projection of the complementary portion on the substrate is offset from the orthographic projection of the routing portion on the substrate, and the surface of the transistor layer having the complementary portion away from the substrate is flush with the surface of the transistor layer having the transistor away from the substrate and the surface of the transistor layer having the routing portion away from the substrate.

[0025] Correspondingly, the present application further provides a method for manufacturing a display panel. The display panel includes an adjacent display area and a non-display area, and the display panel includes:

[0026] Providing a substrate;

[0027] Forming a transistor layer on the substrate. The transistor layer includes at least one complementary portion, at least one transistor, and at least one routing portion. Each complementary portion, each transistor, and each routing portion are located in the display area. Each transistor is spaced apart from a routing portion, and the orthographic projection of the transistor on the substrate is offset from the orthographic projection of the routing portion on the substrate and the orthographic projection of the complementary portion on the substrate;

[0028] Wherein, the positive projection of the complementary part on the substrate is offset from the positive projection of the wiring part on the substrate, or the positive projection of the complementary part on the substrate overlaps with the positive projection of the wiring part on the substrate; and

[0029] A light-emitting layer is formed on the transistor layer, and the light-emitting layer is located in the display area.

[0030] The present application discloses a display panel and a manufacturing method thereof. The display panel includes an adjacent display area and a non-display area. The display panel includes a substrate, a transistor layer, and a light-emitting layer. The transistor layer is disposed on the substrate. The transistor layer includes at least one complementary part, at least one transistor, and at least one wiring part. Each complementary part, each transistor, and each wiring part are located in the display area. The positive projection of the transistor on the substrate is offset from the positive projection of the wiring part on the substrate and the positive projection of the complementary part on the substrate; wherein, the positive projection of the complementary part on the substrate is offset from the positive projection of the wiring part on the substrate, or the positive projection of the complementary part on the substrate overlaps with the positive projection of the wiring part on the substrate; the light-emitting layer is disposed on the transistor layer and is located in the display area. By providing a complementary part in an area where no transistor is provided or in an area where no transistor and wiring part are provided, the step difference of the transistor layer in the display area can be reduced, thereby improving the flatness of the transistor layer, making the film thickness of the formed light-emitting layer uniform, and thus improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0032] Figure 1 FIG. 15 is a first schematic structural diagram of the display panel provided by the embodiment of the present application.

[0033] Figure 2 FIG. 19 is a conceptual structural diagram of the display panel provided by the embodiment of the present application with a complementary part provided.

[0034] Figure 3 FIG. 23 is a second schematic structural diagram of the display panel provided by the embodiment of the present application.

[0035] Figure 4 FIG. 27 is a third schematic structural diagram of the display panel provided by the embodiment of the present application.

[0036] Figure 5 FIG. 31 is a fourth schematic structural diagram of the display panel provided by the embodiment of the present application.

[0037] Figure 6 It is a schematic flow chart of the steps of the method for manufacturing a display panel provided by an embodiment of the present application.

[0038] Figure 7 It is a schematic flow chart of the steps of manufacturing a complementary part in the method for manufacturing a display panel provided by an embodiment of the present application.

[0039] Figures 8 - 17 It is a schematic structural diagram of the steps of the method for manufacturing a display panel provided by an embodiment of the present application.

[0040] Reference numerals:

[0041] Display panel 10; display area 11; non-display area 12; substrate 100; transistor layer 200; complementary part 210; transistor 220; light-shielding part 221; active part 222; insulating part 223; gate 224; source-drain electrode 225; wiring part 230; signal wiring 231; dielectric part 232; control wiring 233; electrode wiring 234; buffer layer 240; interlayer dielectric layer 250; passivation layer 260; planarization layer 270; anode 300; pixel definition layer 400; light-emitting layer 500. Detailed implementation manners

[0042] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application. In addition, it should be understood that the specific implementation manners described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the orientation words such as "upper" and "lower" usually refer to the upper and lower in the actual use or working state of the device, specifically the drawing direction in the accompanying drawings; and "inner" and "outer" refer to the outline of the device. In the present application, "reaction" can be a chemical reaction or a physical reaction.

[0043] The present application discloses a display panel and a method for manufacturing the same. The display panel includes an adjacent display area and a non-display area. The display panel includes a substrate, a transistor layer, and a light-emitting layer. The transistor layer is disposed on the substrate. The transistor layer includes at least one complementary part, at least one transistor, and at least one wiring part. Each complementary part, each transistor, and each wiring part are located in the display area. The orthographic projection of the transistor on the substrate is staggered from the orthographic projection of the wiring part on the substrate and the orthographic projection of the complementary part on the substrate; wherein, the orthographic projection of the complementary part on the substrate is staggered from the orthographic projection of the wiring part on the substrate, or the orthographic projection of the complementary part on the substrate overlaps with the orthographic projection of the wiring part on the substrate; the light-emitting layer is disposed on the transistor layer and is located in the display area.

[0044] In the present application, by providing a complementary portion in an area where no transistor is provided or in an area where no transistor and no wiring portion are provided, the step difference of the transistor layer in the display area can be reduced, thereby improving the flatness of the side of the transistor layer away from the substrate, so that when the light-emitting layer is formed by an inkjet printing method subsequently, the film thickness of the formed light-emitting layer is uniform, thereby improving the display effect of the display panel.

[0045] Please refer to Figure 1 , the present application provides a display panel 10. The display panel 10 includes an adjacent display area 11 and a non-display area 12. The display panel 10 includes a substrate 100, a transistor layer 200, an anode 300, a pixel definition layer 400, and a light-emitting layer 500.

[0046] The transistor layer 200 is disposed on the substrate 100. The transistor layer 200 includes at least one complementary portion 210, at least one transistor 220, and at least one wiring portion 230. Each complementary portion 210, each transistor 220, and each wiring portion 230 are located in the display area 11. Each transistor 220 is arranged at intervals with a wiring portion 230. The orthographic projection of the transistor 220 on the substrate 100 is staggered from the orthographic projection of the wiring portion 230 on the substrate 100 and the orthographic projection of the complementary portion 210 on the substrate 100; wherein, the orthographic projection of the complementary portion 210 on the substrate 100 is staggered from the orthographic projection of the wiring portion 230 on the substrate 100, or the orthographic projection of the complementary portion 210 on the substrate 100 overlaps with the orthographic projection of the wiring portion 230 on the substrate 100. Specifically, when the wiring portion 230 includes at least two of the control wiring 233, the signal wiring 231, and the electrode wiring 234, the orthographic projection of the complementary portion 210 on the substrate 100 is staggered from the orthographic projection of the wiring portion 230 on the substrate 100. The transistor layer 200 includes a buffer layer 240, an interlayer dielectric layer 250, a passivation layer 260, and a planarization layer 270. The transistor 220 is a top-gate transistor 220. The transistor 220 includes a light-shielding portion 221, an active portion 222, an insulating portion 223, a gate 224, and source / drain electrodes 225. The wiring portion 230 includes a signal wiring 231, a dielectric portion 232, a control wiring 233, and an electrode wiring 234. The complementary portion 210 is also disposed in the non-display area 12. The complementary portion 210, the light-shielding portion 221, and the signal wiring 231 are disposed on the substrate 100 in the same layer, that is, the transistor 220, the complementary portion 210, and the wiring portion 230 are disposed in the same layer. The buffer layer 240 covers the signal wiring 231 portion, the complementary portion 210, and the light-shielding portion 221. The active portion 222, the insulating portion 223, and the gate 224 are sequentially stacked on the buffer layer 240 and are correspondingly disposed with the light-shielding portion 221. The dielectric portion 232 and the control wiring 233 are sequentially stacked on the buffer layer 240 and are correspondingly disposed with the signal wiring 231. The interlayer dielectric layer 250 is disposed on the buffer layer 240, the active portion 222, the insulating portion 223, the gate 224, the dielectric portion 232, and the control wiring 233. The interlayer dielectric layer 250 is provided with through holes. The through holes are located in the display area 11 and the non-display area 12. The through holes penetrate the interlayer dielectric layer 250 to expose the active portion 222. The source / drain electrodes 225 and the electrode wiring 234 are in the same layer and are arranged at intervals on the interlayer dielectric layer 250, and the source / drain electrodes 225 extend into the through holes to be connected to the active portion 222. The source / drain electrodes 225 are correspondingly disposed with the active portion 222. The electrode wiring 234 is correspondingly disposed with the control wiring 233. The passivation layer 260 and the planarization layer 270 are sequentially stacked on the interlayer dielectric layer 250, the source / drain electrodes 225, and the electrode wiring 234. The passivation layer 260 is provided with connection holes. The connection holes penetrate the passivation layer 260 to expose the source / drain electrodes 225. The planarization layer 270 is provided with vias. The vias penetrate the planarization layer 270 to communicate with the connection holes.The connection holes and vias are located in the display area 11.

[0047] In one embodiment, the complementary part 210 is in contact with the transistor 220 and the wiring part 230. Specifically, the complementary part 210 is in contact with the light-shielding part 221 and the signal trace 231 and is disposed on the substrate 100 in the same layer. This further improves the flatness of the transistor 200, thereby further making the thickness of subsequent film layers uniform.

[0048] In another embodiment, there is a gap between the complementary part 210, the transistor 220, and the wiring part 230. Even though there is a gap between the complementary part 210, the transistor 220, and the wiring part 230, a part of the subsequent film layer will fill the gap between the complementary part 210, the transistor 220, and the wiring part 230, thereby achieving the purpose of reducing the step difference, thus improving the flatness of the transistor layer 200, and further making the thickness of subsequent film layers uniform.

[0049] In another embodiment, the transistor 220 can be a bottom-gate transistor 220. Specifically, the buffer layer 240, the light-shielding part 221, and the signal trace 231 are removed. The gate 224 is disposed at the position of the original light-shielding part 221. The insulating part 223 is disposed at the position of the original buffer layer 240. The control trace 233 is disposed at the position of the original signal trace 231, and the dielectric part 232 is removed. Other structures remain unchanged.

[0050] In one embodiment, the material of the complementary part 210 includes at least one of an organic photosensitive material and an inorganic material, such as an organic photoresist, a polyimide-based material, an acrylic-based material, silicon oxide, silicon nitride, and a silicon-based polymer.

[0051] In another embodiment, the dielectric part 232 may not be provided in the wiring part 230.

[0052] In the present application, when the dielectric part 232 is not provided in the wiring part 230, one manufacturing process can be saved, the manufacturing process of the display panel 10 is simplified, thereby shortening the production cycle. At the same time, the thickness of the transistor layer 200 provided with the wiring part 230 is further reduced, thereby further reducing the step difference between the surface of the transistor layer 200 provided with the wiring part 230 and other regions or reducing the area occupied by the maximum step difference, thereby further making the thickness of the subsequent formed light-emitting layer 500 uniform, and further avoiding the problem of unstable lighting of the display panel 10.

[0053] It should be noted that the step difference refers to the difference between the peak and valley of the film layer; the step difference can be the average step difference or a non-average step difference. By using the method provided in the present application, the step difference can be reduced, and thus the thickness of the formed light-emitting layer 500 can be made uniform.

[0054] It should be noted that the wiring portion 230 may also be provided with only any two of the control wiring 233, the signal wiring 231, and the electrode wiring 234.

[0055] It should be noted that the corresponding setting means that one film layer is directly above or directly below another film layer, and the same applies hereinafter.

[0056] In the prior art, in the transistor layer in the display area, transistors and wiring portions are usually provided. However, in some transistor layers, due to the presence of transistors and wiring portions, the surface of the corresponding part of the transistor layer is much higher than the surface of the adjacent part of the transistor layer that does not have transistors and wiring portions. That is, the surface step of the transistor layer is large, resulting in uneven film thickness when forming the light-emitting layer by inkjet printing later, and thus unstable lighting of the display panel, and poor display effect of the display panel. In this application, by providing the complementary portion 210 in the area of the transistor layer 200 where there are no transistors 220 and wiring portions 230, the complementary portion 210 forms thickness complementarity with the film layers in the transistor layer 200, thereby shortening the surface step of the transistor layer 200 in the display area 11 or reducing the area occupied by the maximum step, that is, improving the flatness of the surface of the transistor layer 200, so that the film thickness of the formed light-emitting layer 500 is uniform, and thus improving the display effect of the display panel 10.

[0057] It should be noted that the flatness may refer to the flatness of the average value, or may not be the flatness of the average value.

[0058] In one embodiment, the thickness d1 of the complementary portion 210 is greater than the thickness d2 of the light-shielding portion 221 and the thickness d3 of the signal wiring 231.

[0059] In this application, setting the thickness d1 of the complementary portion 210 to be greater than the thickness d2 of the light-shielding portion 221 and the thickness d3 of the signal wiring 231 can further reduce the problem of excessive surface step of the transistor layer 200 caused by the presence of transistors 220 and the wiring layer in the transistor layer 200. That is, it shortens the surface step of the transistor layer 200 in the display area 11, improves the flatness of the surface of the transistor layer 200, so that when the subsequent light-emitting layer 500 is inkjet printed, it spreads evenly on the transistor layer 200, so that the formed film layer has a uniform thickness, thereby improving the display effect of the display panel 10, and thus improving the efficiency, lifespan, and viewing angle of the display panel 10.

[0060] In one embodiment, the thickness difference between the surface of the transistor layer 200 provided with the complementary part 210 away from the substrate 100, the surface of the transistor layer 200 provided with the transistor 220 away from the substrate 100, and the surface of the transistor layer 200 provided with the wiring part 230 away from the substrate 100 is less than 400 nanometers. That is, in the display area 11, the maximum step difference between the surfaces of the transistor layer 200 close to the substrate 100 is less than 400 nanometers. Thus, the step difference on the surface of the transistor layer 200 in the display area 11 is further reduced, thereby improving the flatness of the surface of the transistor layer 200. Further, when the subsequent light-emitting layer 500 is ink-jet printed, it spreads evenly on the transistor layer 200, making the formed film layer thickness uniform. Thus, the display effect of the display panel 10 is further improved, and the efficiency, lifespan, and viewing angle of the display panel 10 are further improved.

[0061] In one embodiment, the thickness difference between the surface of the transistor layer 200 provided with the complementary part 210 away from the substrate 100, the surface of the transistor layer 200 provided with the transistor 220 away from the substrate 100, and the surface of the transistor layer 200 provided with the wiring part 230 away from the substrate 100 is 200 - 400 nanometers. Specifically, the thickness difference between the surface of the transistor layer 200 provided with the complementary part 210 away from the substrate 100, the surface of the transistor layer 200 provided with the transistor 220 away from the substrate 100, and the surface of the transistor layer 200 provided with the wiring part 230 away from the substrate 100 can be 200 nanometers, 250 nanometers, 300 nanometers, 450 nanometers, or 400 nanometers, etc.

[0062] In the prior art, after forming the transistors and the wiring part and before forming the light-emitting layer, only one flat layer is provided. Although it can reduce part of the step difference, the step difference of the transistor layer is still 600 nanometers and above. In this application, by providing the complementary part 210 in the area where the transistor 220 and the wiring part 230 are not provided, the step difference on the surface of the transistor layer 200 in the display area 11 can be reduced to less than 400 nanometers, thereby improving the flatness of the surface of the transistor layer 200, making the film thickness of the formed light-emitting layer 500 uniform, and thus improving the display effect of the display panel 10.

[0063] In one embodiment, the sum of the thicknesses of the transistor 220, the buffer layer 240, the interlayer dielectric layer 250, the passivation layer 260, and the planarization layer 270, and the sum of the thicknesses of the trace portion 230, the buffer layer 240, the interlayer dielectric layer 250, the passivation layer 260, and the planarization layer 270 are both less than the sum of the thicknesses of the buffer layer 240, the interlayer dielectric layer 250, the passivation layer 260, and the planarization layer 270. The sum of the thicknesses of the transistor 220, the buffer layer 240, the interlayer dielectric layer 250, the passivation layer 260, and the planarization layer 270 and the sum of the thicknesses of the trace portion 230, the buffer layer 240, the interlayer dielectric layer 250, the passivation layer 260, and the planarization layer 270 are equal to the sum of the thicknesses of the complementary portion 210, the buffer layer 240, the interlayer dielectric layer 250, the passivation layer 260, and the planarization layer 270. That is, the surface of the transistor layer 200 provided with the complementary portion 210 away from the substrate 100 is flush with the surface of the transistor layer 200 provided with the transistor 220 away from the substrate 100 and the surface of the transistor layer 200 provided with the trace portion 230 away from the substrate 100.

[0064] In the present application, by providing the complementary portion 210 in the area where the transistor 220 and the trace portion 230 are not provided, the surface of the transistor layer 200 provided with the complementary portion 210 away from the substrate 100 is flush with the surface of the transistor layer 200 provided with the transistor 220 away from the substrate 100 and the surface of the transistor layer 200 provided with the trace portion 230 away from the substrate 100. That is, the surface step difference of the transistor layer 200 in the display area 11 is reduced, the flatness of the surface of the transistor layer 200 is improved, so that when the subsequent light-emitting layer 500 is inkjet printed, it spreads evenly on the transistor layer 200, and the formed film layer has a uniform thickness, thereby improving the display effect of the display panel 10, and thus improving the efficiency, lifespan, and viewing angle of the display panel 10.

[0065] The anode 300 is disposed on the transistor layer 200. Specifically, the anode 300 is disposed on the planarization layer 270 and extends into the vias and connection holes to connect with the source-drain electrodes 225. The anode 300 is located in the display area 11 and the non-display area 12. Optionally, the anode 300 can be replaced with a cathode.

[0066] The pixel definition layer 400 is disposed on the planarization layer 270 and the anode 300. The pixel definition layer 400 is provided with openings. The openings penetrate through the pixel definition layer 400 to expose the planarization layer 270. The openings are located in the display area 11.

[0067] The light-emitting layer 500 is disposed on the transistor layer 200 and is located in the display area 11. Specifically, the light-emitting layer 500 is located in the openings and is connected to the anode 300.

[0068] Please refer to Figure 2, the process concept of setting the complementary part 210 in front of the transistor 220: If the thickness of the subsequent pattern to be made is very thick, then the thickness of the complementary part 210 is set to be thinner or not set. The area with a thinner complementary part 210 or the area where the complementary part 210 is set is used to place the subsequent very thick pattern. For example, if the subsequent patterns are the transistor 220 and the wiring part 230, then the complementary layer is not set in the areas corresponding to the transistor 220 and the wiring part 230; if the thickness of the subsequent pattern to be made is relatively thin, then the thickness of the complementary part 210 is set to be relatively thicker, such as the area of the transistor layer 200 where the transistor 220 and the wiring part 230 are set. That is, according to the thickness of the subsequent pattern in the transistor layer 200, the thicknesses t1, t2, and t3 of the complementary part 210 are set.

[0069] It should be noted that Figure 2 is only a simple schematic diagram and does not mean that it is symmetric with Figure 1 the structure.

[0070] Please refer to Figure 3 , it should be noted that the difference between the second structure and the first structure is:

[0071] The complementary part 210, the active part 222, and the dielectric part 232 are arranged on the buffer layer 240 in the same layer. The rest is the same as the first structure and will not be elaborated here.

[0072] In one embodiment, the thickness d1 of the complementary part 210 is greater than the thickness h1 of the active part 222.

[0073] In another embodiment, the complementary part 210 is provided on both the substrate 100 and the buffer layer 240.

[0074] Please refer to Figure 4 , it should be noted that the difference between the third structure and the second structure is:

[0075] The buffer layer 240, the light-shielding part 221, and the signal trace 231 are not provided in the display panel 10. The rest is the same as the second structure and will not be elaborated here.

[0076] Please refer to Figure 5 , it should be noted that the difference between the fourth structure and the first structure is:

[0077] When the wiring portion 230 includes one of the control wiring 233, the electrode wiring 234, and the signal wiring 231, the orthographic projection of the complementary portion 210 on the substrate 100 overlaps with the orthographic projection of the wiring portion 230 on the substrate 100. That is, the orthographic projection of the wiring portion 230 on the substrate 100 falls within the orthographic projection of the complementary portion 210 on the substrate 100. Specifically, only the signal wiring 231 is provided in the wiring portion 230. The signal wiring 231 is disposed above the complementary portion 210, and the control wiring 233, the electrode wiring 234, and the dielectric portion 232 are not provided. The rest is the same as the first structure and will not be described herein again.

[0078] In this application, when only one of the control wiring 233, the electrode wiring 234, and the signal wiring 231 is provided in the wiring portion 230, that is, only single-layer wiring is provided, and the complementary portion 210 is also provided in the area of the wiring portion 230, the difference between the thickness of the transistor layer 200 without the transistor 220, the thickness of the transistor layer 200 with the transistor 220, and the thickness of the transistor layer 200 with the wiring portion 230 can be reduced, thereby reducing the surface step of the transistor layer 200 in the display area 11, further improving the flatness of the surface of the transistor layer 200, further making the film thickness of the light-emitting layer 500 uniform, and further improving the display effect of the display panel 10.

[0079] In another embodiment, the wiring portion 230 may also be provided with only the control wiring 233 or the electrode wiring 234.

[0080] In one embodiment, the surface of the transistor layer 200 with the complementary portion 210 away from the substrate 100 and the surface of the transistor layer 200 with the wiring portion 230 away from the substrate 100 are flush with the surface of the transistor layer 200 with the transistor 220 away from the substrate 100.

[0081] In this application, by providing the complementary portion 210 in the area without the transistor 220, the surface of the transistor layer 200 with the complementary portion 210 away from the substrate 100 and the surface of the transistor layer 200 with the wiring portion 230 away from the substrate 100 are flush with the surface of the transistor layer 200 with the transistor 220 away from the substrate 100. That is, the surface step of the transistor layer 200 in the display area 11 is shortened, and the flatness of the surface of the transistor layer 200 is improved. Thus, when the subsequent light-emitting layer 500 is inkjet printed, it spreads evenly on the transistor layer 200, making the formed film layer thickness uniform, thereby improving the display effect of the display panel 10, and thus improving the efficiency, lifespan, and viewing angle of the display panel 10.

[0082] The present application provides a display panel 10. By providing a complementary portion 210 in an area where no transistor 220 is provided or in an area where no transistor 200 and wiring portion 230 are provided, the step difference of the transistor layer 200 in the display area 11 can be reduced or the area occupied by the maximum step difference can be decreased, thereby improving the flatness of the side of the transistor layer 200 away from the substrate 100. As a result, when the light-emitting layer 500 is formed by an inkjet printing method subsequently, the film thickness is uniform, thus improving the display effect of the display panel 10.

[0083] The present application further provides a method for manufacturing a display panel to manufacture the display panel provided by the present application. The display panel includes an adjacent display area and a non-display area, and the display panel includes:

[0084] B11. Provide a substrate.

[0085] B12. Form a transistor layer on the substrate. The transistor layer includes at least one complementary portion, at least one transistor, and at least one wiring portion. Each complementary portion, each transistor, and each wiring portion are located in the display area. Each of the transistors is arranged at an interval from one of the wiring portions.

[0086] The orthographic projection of the transistor on the substrate is staggered from the orthographic projection of the wiring portion on the substrate and the orthographic projection of the complementary portion on the substrate.

[0087] Wherein, the orthographic projection of the complementary portion on the substrate is staggered from the orthographic projection of the wiring portion on the substrate, or the orthographic projection of the complementary portion on the substrate overlaps with the orthographic projection of the wiring portion on the substrate.

[0088] B13. Form a light-emitting layer on the transistor layer. The light-emitting layer is located in the display area.

[0089] In the present application, by providing a complementary portion in an area where no transistor is provided or in an area where no transistor and wiring portion are provided, the step difference of the transistor layer in the display area can be reduced, thereby improving the flatness of the side of the transistor layer away from the substrate. As a result, when the light-emitting layer is formed by an inkjet printing method subsequently, the film thickness is uniform, thus improving the display effect of the display panel.

[0090] Please refer to Figures 6 - 17 The present application further provides a method for manufacturing a display panel 10 to manufacture the display panel 10 provided by the present application. The display panel 10 includes an adjacent display area 11 and a non-display area 12, and the display panel 10 includes: 7]

[0091] B11. Provide a substrate 100.

[0092] B12. A transistor layer is formed on a substrate. The transistor layer includes at least one complementary portion, at least one transistor, and at least one wiring portion. Each complementary portion, each transistor, and each wiring portion are located in a display area. Each of the transistors is arranged at an interval from one of the wiring portions. The orthographic projection of the transistor on the substrate is offset from the orthographic projection of the wiring portion on the substrate and the orthographic projection of the complementary portion on the substrate; wherein, the orthographic projection of the complementary portion on the substrate is offset from the orthographic projection of the wiring portion on the substrate, or the orthographic projection of the complementary portion on the substrate overlaps with the orthographic projection of the wiring portion on the substrate.

[0093] Please refer to Figure 7 and Figure 8 , specifically, the material for forming the complementary portion 210 is provided on the substrate 100. Through a halftone mask with different transmittances in the yellow light process, complementary portions 210 with different thicknesses are directly obtained. The complementary portions 210 are located in the display area 11 and the non-display area 12.

[0094] Please refer to Figure 9 , and then, a patterned process is adopted on the substrate 100 and the complementary portion 210 to form spaced-apart light-shielding portions 221 and control wirings 233. The light-shielding portions 221 and the control wirings 233 are located in the display area 11.

[0095] In an embodiment, the thickness d1 of the complementary portion 210 is greater than the thickness d2 of the light-shielding portion 221 and the thickness d3 of the signal wiring 231.

[0096] It should be noted that the patterned process includes exposure, development, etching, etc.

[0097] Please refer to Figure 10 , and then, a buffer layer 240 is formed on the light-shielding portion 221, the control wiring 233, and the complementary portion 210. The buffer layer 240 without the complementary portion 210 is recessed to form a groove under the buffer layer 240 of the control wiring 233 and the light-shielding portion 221 because the thickness of the complementary portion 210 is higher than the thickness of the light-shielding portion 221 and the control wiring 233.

[0098] Please refer to Figure 11 , and then, an active portion 222 is formed on the buffer layer 240. The active portion 222 is located above the light-shielding portion 221.

[0099] Please refer to Figure 12 , and then, an insulating portion 223 and a dielectric portion 232 are formed by one process. The insulating portion 223 is arranged corresponding to the active portion 222. The dielectric portion 232 is arranged corresponding to the complementary portion 210.

[0100] Please refer to Figure 13, then, a gate 224 and a control trace 233 are formed by one process. The insulating portion 223 is disposed corresponding to the gate 224. The dielectric portion 232 is disposed corresponding to the control trace 233.

[0101] Please refer to Figure 14 , then, a material of the interlayer dielectric layer 250 is disposed on the buffer layer 240, the active portion 222, the insulating portion 223, the gate 224, the dielectric portion 232, and the control trace 233, and is patterned to form the interlayer dielectric layer 250. The interlayer dielectric layer 250 is provided with through holes. The through holes are located in the display area 11 and the non-display area 12. The through holes penetrate the interlayer dielectric layer 250 to expose the active portion 222.

[0102] Please refer to Figure 15 , then, spaced-apart source / drain electrodes 225 and electrode traces 234 are formed by one process on the interlayer dielectric layer 250. The source / drain electrodes 225 extend into the through holes to connect with the active portion 222. The source / drain electrodes 225 are disposed corresponding to the active portion 222. The electrode traces 234 are disposed corresponding to the control traces 233.

[0103] Please refer to Figure 16 , then, a material of the passivation layer 260 is disposed on the interlayer dielectric layer 250, the source / drain electrodes 225, and the electrode traces 234, and is patterned to form the passivation layer 260. The passivation layer 260 is provided with connection holes. The connection holes penetrate the passivation layer 260 to expose the source / drain electrodes 225.

[0104] Please refer to Figure 17 , then, a material of the planarization layer 270 is disposed on the passivation layer 260, and is patterned to form the planarization layer 270. The planarization layer 270 is provided with vias. The vias penetrate the planarization layer 270 to communicate with the connection holes. The connection holes and the vias are located in the display area 11.

[0105] B13. Form a light-emitting layer on the transistor layer, and the light-emitting layer is located in the display area.

[0106] In one embodiment, before forming the light-emitting layer 500 on the transistor layer 200, it further includes:

[0107] Please continue to refer to Figure 17 , a material of the anode 300 is disposed on the planarization layer 270, and is patterned to form the anode 300. The anode 300 extends into the vias and the connection holes to connect with the source / drain electrodes 225. The anode 300 is located in the display area 11 and the non-display area 12.

[0108] Please continue to refer to Figure 17, then, the material of the pixel definition layer 400 is disposed on the anode 300 and patterned to form the pixel definition layer 400. The pixel definition layer 400 is provided with openings. The openings penetrate through the pixel definition layer 400 to expose the planar layer 270. The openings are located in the display area 11.

[0109] Finally, the material of the light-emitting layer 500 is printed into the openings by an inkjet printing method and dried to form the light-emitting layer 500.

[0110] The present application provides a display panel 10 and a manufacturing method thereof. By disposing the complementary part 210 in the area where the transistor 220 is not provided or in the area where the transistor 200 and the wiring part 230 are not provided, the step difference of the transistor layer 200 in the display area 11 can be reduced, thereby improving the flatness of the side of the transistor layer 200 away from the substrate 100. Thus, when the light-emitting layer 500 is formed by an inkjet printing method subsequently, the film thickness is uniform, thereby improving the display effect of the display panel 10.

[0111] The above has introduced in detail a display panel and a manufacturing method thereof provided by the embodiments of the present application. Specific examples are used herein to elaborate the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A display panel, characterized in that, The display panel includes an adjacent display area and a non-display area, including: a substrate; and a transistor layer disposed on the substrate. The transistor layer includes at least one complementary portion, at least one transistor, and at least one wiring portion. Each complementary portion, each transistor, and each wiring portion are located in the display area. Each transistor is disposed at an interval from a wiring portion. The orthographic projection of the transistor on the substrate is staggered from the orthographic projection of the wiring portion on the substrate and the orthographic projection of the complementary portion on the substrate; wherein the orthographic projection of the complementary portion on the substrate is staggered from the orthographic projection of the wiring portion on the substrate; and a light-emitting layer disposed on the transistor layer and located in the display area; the transistor includes a light-shielding portion. The wiring portion includes a signal wiring and a control wiring. The complementary portion, the light-shielding portion, and the signal wiring are disposed on the substrate in the same layer. The control wiring is disposed at an interval from the light-shielding portion, and the control wiring is located above the signal wiring; the transistor layer further includes a buffer layer. The transistor further includes an active portion, an insulating portion, and a gate. The wiring portion further includes a dielectric portion. The transistor layer further includes an interlayer dielectric layer; the buffer layer covers the signal wiring, the complementary portion, and the light-shielding portion; the active portion, the insulating portion, and the gate are sequentially stacked on the buffer layer and are disposed corresponding to the light-shielding portion; the dielectric portion and the control wiring are sequentially stacked on the buffer layer and are disposed corresponding to the signal wiring; the interlayer dielectric layer is disposed on the buffer layer, the active portion, the insulating portion, the gate, the dielectric portion, and the control wiring; the transistor further includes source-drain electrodes. The wiring portion further includes electrode wirings. The transistor layer further includes a passivation layer and a planarization layer. The source-drain electrodes and the electrode wirings are in the same layer and are disposed at an interval on the interlayer dielectric layer. The source-drain electrodes are connected to the active portion and are disposed corresponding to the active portion. The electrode wirings are disposed corresponding to the control wiring. The passivation layer and the planarization layer are sequentially stacked on the interlayer dielectric layer, the source-drain electrodes, and the electrode wirings; the sum of the thicknesses of the transistor, the buffer layer, the interlayer dielectric layer, the passivation layer, and the planarization layer and the sum of the thicknesses of the wiring portion, the buffer layer, the interlayer dielectric layer, the passivation layer, and the planarization layer are equal to the sum of the thicknesses of the complementary portion, the buffer layer, the interlayer dielectric layer, the passivation layer, and the planarization layer.

2. The display panel according to claim 1, wherein The thickness difference between the surface of the transistor layer provided with the complementary portion away from the substrate and the surface of the transistor layer provided with the transistor away from the substrate and the surface of the transistor layer provided with the wiring portion away from the substrate is less than 400 nanometers.

3. The display panel according to claim 1, wherein The surface of the transistor layer provided with the complementary portion away from the substrate is flush with the surface of the transistor layer provided with the transistor away from the substrate and the surface of the transistor layer provided with the wiring portion away from the substrate.

4. A method for preparing a display panel, characterized in that, The display panel includes a display area and a non-display area arranged adjacent to each other, and the display panel includes: providing a substrate; forming a transistor layer on the substrate, the transistor layer including at least one complementary part, at least one transistor, and at least one wiring part, each of the complementary parts, each of the transistors, and each of the wiring parts being located in the display area, each of the transistors being arranged at an interval from one of the wiring parts, and the orthographic projection of each of the transistors on the substrate being staggered from the orthographic projection of the wiring part on the substrate and the orthographic projection of the complementary part on the substrate; wherein, the orthographic projection of the complementary part on the substrate is staggered from the orthographic projection of the wiring part on the substrate; and forming a light-emitting layer on the transistor layer, the light-emitting layer being located in the display area; the transistor includes a light-shielding part, the wiring part includes a signal wiring and a control wiring, the complementary part, the light-shielding part, and the signal wiring are arranged on the substrate in the same layer, the control wiring is arranged at an interval from the light-shielding part, and the control wiring is located above the signal wiring; the transistor layer further includes a buffer layer, the transistor further includes an active part, an insulating part, and a gate, the wiring part further includes a dielectric part, and the transistor layer further includes an interlayer dielectric layer; the buffer layer covers the signal wiring, the complementary part, and the light-shielding part; the active part, the insulating part, and the gate are sequentially stacked on the buffer layer and are arranged corresponding to the light-shielding part; the dielectric part and the control wiring are sequentially stacked on the buffer layer and are arranged corresponding to the signal wiring; the interlayer dielectric layer is arranged on the buffer layer, the active part, the insulating part, the gate, the dielectric part, and the control wiring; the transistor further includes source and drain electrodes, the wiring part further includes an electrode wiring, the transistor layer further includes a passivation layer and a planarization layer, the source and drain electrodes are in the same layer as the electrode wiring and are arranged at an interval on the interlayer dielectric layer, and the source and drain electrodes are connected to and arranged corresponding to the active part, the electrode wiring is arranged corresponding to the control wiring, and the passivation layer and the planarization layer are sequentially stacked on the interlayer dielectric layer, the source and drain electrodes, and the electrode wiring; the sum of the thicknesses of the transistor, the buffer layer, the interlayer dielectric layer, the passivation layer, and the planarization layer and the sum of the thicknesses of the wiring part, the buffer layer, the interlayer dielectric layer, the passivation layer, and the planarization layer are equal to the sum of the thicknesses of the complementary part, the buffer layer, the interlayer dielectric layer, the passivation layer, and the planarization layer.

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