A high-linearity GaN HEMT device based on an asymmetric ohmic regrowth region and its preparation method

Abstract

The present invention discloses a high linearity GaN HEMT device based on an asymmetric ohmic regrowth region and a preparation method thereof. The device is prepared by using a high polarization strength and low square resistance heterojunction material; the ohmic regrowth region of the source is defined by photolithography; the nitride in the ohmic regrowth region of the source is etched under the mask of photoresist; the epitaxial n + GaN; photolithography defines the self-stop etching area; under the mask of photoresist, the n + GaN is self-terminated and etched; the device isolation area is self-terminated again to remove the surface of the area not protected by the photoresist. + When the operating voltage of the device prepared by the present invention increases, the source barrier height decreases and the barrier thickness decreases, causing hot electron transfer or tunneling between the source regrowth step (Ledge) and the 2DEG channel. This increases the source conduction path, weakens the increase in source access resistance caused by the increase in current, and improves the linearity of the GaN HEMT.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a high-linearity GaN HEMT device based on an asymmetric ohmic regrowth region and a preparation method thereof. Background Art

[0002] Group III nitride semiconductors form heterojunctions with semiconductors of varying bandgap widths. Their high two-dimensional electron gas (2DEG) density, wide bandgap, electron saturation drift velocity, and large critical breakdown electric field make them the preferred material for high-temperature, high-frequency, high-power, and radiation-resistant electronic devices. These devices primarily include high electron mobility transistors (HEMTs) and Schottky barrier diodes (SBDs), which are used in RF power amplifiers and power switch modules, respectively. GaN-based high-frequency (microwave and millimeter-wave) high-power HEMTs are commonly used in key applications such as satellites, radar, and base stations.

[0003] With the advancement of nitride material growth technology and device processing, the RF power characteristics of GaN-based HEMT devices continue to improve, specifically manifested in higher cutoff frequencies and operating frequencies, greater output power, and higher power-added efficiency. However, during signal transmission, due to the nonlinear amplification frequency distortion of semiconductor devices, the circuit will also produce nonlinear amplification, resulting in signal distortion. In particular, when the input signal is a sine wave with two frequencies close to each other, there will be intermodulation distortion, which will also affect the linearity of the circuit and limit the bandwidth of the power amplifier. Circuit design methods such as envelope negative feedback technology and polar loop negative feedback technology are usually used in the circuit to suppress distortion and improve linearity, but the design complexity and cost of the circuit will increase significantly.

[0004] Generally, OIP3 value and 1dB compression point (P 1dB ), transconductance (G m ) and its second-order derivative, third-order derivative, and frequency gain cutoff frequency (f T ) is used to indicate the linearity of the device. The factors that lead to nonlinearity at the device level are mainly the following: as the source-drain bias voltage of the device increases, the self-heating effect of the device intensifies, resulting in a decrease in the mobility of the GaN two-dimensional electron gas; as the source-drain conduction current of the device increases, a "source starvation" phenomenon occurs, causing the source access resistance (R s ) increases, resulting in a decrease in the intrinsic transconductance of the device; in addition, trap effects, capacitance modulation effects, etc. will also affect the linearity of the device.

[0005] For GaN-based HEMT device fabrication, methods for improving device linearity include: using a finFET structure to increase the device's gate control capability, resulting in better linearity than planar devices; using a gradient component barrier design to achieve a three-dimensional extended distribution of the 2DEG, improving device linearity; using a double-heterojunction barrier structure with a bimodal transconductance, which has the potential to achieve high transconductance linearity by optimizing the spacing between the device's two channels; and using transconductance compensation to form a composite structure device, which can achieve significant improvements in device linearity. Additionally, field plate design, fin-like multi-threshold coupling device structure design, and TRG gradient gate depth design can also optimize device linearity. However, there is currently no effective solution to the nonlinearity caused by the "source starvation" effect, which increases the source access resistance. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, the present invention provides a high-linearity GaN HEMT device based on an asymmetric ohmic regrowth region and a method for fabricating the same. The technical problems to be solved by the present invention are achieved through the following technical solutions:

[0007] A first aspect of an embodiment of the present invention provides a method for preparing a high-linearity GaN HEMT device based on an asymmetric ohmic regrowth region, comprising the following steps:

[0008] Step 1: sequentially growing a GaN buffer layer and a barrier layer on a substrate; the GaN buffer layer and the barrier layer forming a heterojunction structure;

[0009] Step 2: Photolithographically define an ohmic regrown region of the source, wherein the ohmic regrown region is located on one side of the barrier layer;

[0010] Step 3: using a dry etching method to etch the barrier layer in the ohmic regrown region of the source electrode to at least 20 nm below the boundary between the GaN buffer layer and the barrier layer, to form an etched groove;

[0011] Step 4: epitaxial growth of n on the product prepared in step 3 + GaN layer, doping concentration is 1e20cm -3 The order of magnitude is above that of n + forming a groove above the GaN layer;

[0012] Step 5: Photolithography defines a self-termination etching region, wherein the self-termination etching region is located at the n + The middle of the GaN layer;

[0013] Step 6: Use dry etching to expose the n-type self-termination etching area. + GaN layer removal, etching gas is SF6 / BCl3;

[0014] Step 7: Photolithography defines the isolation area in the n + A corresponding area to be etched on the GaN layer, wherein the area to be etched is located on the edge of the product prepared in step 6;

[0015] Step 8: Use dry etching to expose the n-type + The GaN layer is removed and the first n + GaN epitaxial layer and the second n + GaN epitaxial layer;

[0016] Step nine: using ion implantation equipment to implant B or Ar ions into the isolation region to form the isolation region and achieve device isolation;

[0017] Step 10: using electron beam evaporation equipment to form a + Electrode metal is deposited on the GaN epitaxial layer to form source and drain electrodes;

[0018] Step 11: depositing a passivation layer on the surface of the product prepared in step 10, and removing the passivation layer on the source electrode and the drain electrode by dry etching;

[0019] Step 12: Remove the passivation layer in the gate region by dry etching, where the gate region is located between the source and the drain; and deposit electrode metal in the gate region to form a gate, thereby completing the preparation of a high-linearity GaN HEMT device based on an asymmetric ohmic regrowth region.

[0020] In one embodiment of the present invention, the barrier layer is made of AlN, ScAlN, InAlN, InAlGaN or AlGaN; and the barrier layer has a thickness of 4 nm to 10 nm.

[0021] In one embodiment of the present invention, in step three, an ICP etching device is used, the etching gas is BCl3 / Cl2, the flow rate is 20 / 8 sccm, the chamber pressure is 5 mTorr, the upper electrode power is 51 W, and the lower electrode power is 14 W.

[0022] In one embodiment of the present invention, in step six, an ICP etching device is used, the etching gas flow rate is 10 / 30 sccm, the pressure is 5 mTorr, the ICP upper electrode power is 200 W, and the lower electrode power is 30 W.

[0023] In one embodiment of the present invention, in step eight, an ICP etching device is used, the etching gas is SF6 / BCl3, the flow rate is 10 / 30 sccm, the pressure is 5 mTorr, the upper electrode power is 200W, and the lower electrode power is 30W.

[0024] In one embodiment of the present invention, the material of the substrate is SiC or Si; the material of the passivation layer is SiN.

[0025] In one embodiment of the present invention, the source electrode and the drain electrode are Ti, Al, Ni and Au stacked in sequence from bottom to top;

[0026] The gate is Ni and Au stacked sequentially from bottom to top.

[0027] The second aspect of the embodiment of the present invention provides a high linearity GaN HEMT device based on an asymmetric ohmic re-growth region, which is prepared by the preparation method described in the first aspect of the embodiment of the present invention, comprising: a substrate, a GaN buffer layer, a barrier layer, a first n + GaN epitaxial layer and the second n + GaN epitaxial layer;

[0028] The substrate, the GaN buffer layer and the barrier layer are arranged in sequence from bottom to top, and the GaN buffer layer and the barrier layer form a heterojunction structure;

[0029] The first n + A portion of the GaN epitaxial layer extends to at least 20 nm below the interface between the GaN buffer layer and the barrier layer, and the remaining portion is disposed on the barrier layer to form a groove above the portion of the structure; the second n + The GaN epitaxial layer is disposed on the barrier layer and is adjacent to the first n + GaN epitaxial layer spacing setting;

[0030] The first n + GaN epitaxial layer and the second n + An isolation region is provided between the edge of the GaN epitaxial layer and the edge of the barrier layer;

[0031] The isolation region extends from the barrier layer into the GaN buffer layer;

[0032] The groove is provided with a source electrode, and the second n + A drain is provided on the GaN epitaxial layer; a gate is provided between the source and the drain;

[0033] The first n + GaN epitaxial layer, the second n + GaN epitaxial layer, the first n + GaN epitaxial layer and the second n + A passivation layer is provided between the GaN epitaxial layers and on the isolation region;

[0034] The source electrode, the drain electrode, and the gate electrode extend above the passivation layer.

[0035] Beneficial effects of the present invention:

[0036] When the operating voltage of the device of the present invention increases, the source barrier height decreases and the barrier thickness decreases, causing hot electron transfer or tunneling between the source regrowth step (Ledge) and the 2DEG channel, thereby increasing the source conductive path, reducing the increase in source access resistance due to increased current, and improving the linearity of the GaN HEMT.

[0037] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A schematic cross-sectional view of a high-linearity GaN HEMT device based on an asymmetric ohmic regrowth region provided by an embodiment of the present invention:

[0039] Figure 2a-2k A schematic structural diagram of a photoresist and a mask provided in an embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram of the operating state of a high-linearity GaN HEMT device based on an asymmetric ohmic regrowth region provided by an embodiment of the present invention.

[0041] Description of reference numerals:

[0042] 10-substrate; 20-GaN buffer layer; 30-barrier layer; 31-etched groove; 40-n + GaN layer; 41- groove; 42- self-stop etching area; 43- area to be etched; 50- isolation area; 60- first n + GaN epitaxial layer; 70-second n + GaN epitaxial layer; 80 - source; 90 - drain; 91 - gate; 92 - passivation layer. DETAILED DESCRIPTION

[0043] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0044] Example 1

[0045] See Figure 1 A first aspect of an embodiment of the present invention provides a method for preparing a high-linearity GaN HEMT device based on an asymmetric ohmic regrowth region, comprising the following steps:

[0046] Step 1: sequentially growing a GaN buffer layer 20 and a barrier layer 30 on the substrate 10; the GaN buffer layer 20 and the barrier layer 30 form a heterojunction structure.

[0047] Specifically, if Figure 2a As shown, a low-square-resistance heterojunction material is grown on a SiC or Si substrate 10 using MOCVD equipment. The low-square-resistance heterojunction structure comprises, from top to bottom, a high-polarization-strength and thin barrier layer 30 and a low-defect GaN buffer layer 20. The barrier layer 30 is made of materials such as AlN, ScAlN, InAlN, InAlGaN, or AlGaN with a high Al content, and has a thickness of 4nm-10nm. The GaN buffer layer 20 includes, from top to bottom, a UID-GaN layer and a high-resistance GaN layer doped with Fe or C. The sheet resistance of the low-square-resistance heterojunction structure is approximately 200Ω / sq (ohms per square).

[0048] Step 2: Photolithography defines the ohmic re-growth region of the source 80. The ohmic re-growth region is located on one side of the barrier layer 30. Figure 2b As shown, PR is photoresist.

[0049] Step 3: Use dry etching to etch the barrier layer 30 in the ohmic regrown region of the source 80 to a depth of at least 20 nm below the boundary between the GaN buffer layer 20 and the barrier layer 30 to form an etched groove 31 .

[0050] Specifically, if Figure 2c As shown, the barrier layer 30 nitride in the source 80 ohm regrown area is etched to at least 20 nm below the heterojunction interface (the junction of the GaN buffer layer 20 and the barrier layer 30) using an ICP etching device by dry etching. The etching gas is BCl3 / Cl2 with a flow rate of 20 / 8 sccm, a chamber pressure of 5 mTorr, an ICP top electrode power of 51 W, and a bottom electrode power of 14 W.

[0051] Step 4: Use MBE equipment to grow n epitaxially on the product prepared in step 3 + GaN layer 40, with a doping concentration of 1e20 cm -3 The order of magnitude is above n + A groove 41 is formed on the GaN layer 40. Figure 2d The epitaxial process uses a low temperature of 550°C to 650°C to avoid high temperature-induced barrier quality degradation. 600°C is preferred.

[0052] Step 5: Photolithography defines the self-termination etching region 42. The self-termination etching region 42 is located at n + The middle of the GaN layer 40, such as Figure 2e shown.

[0053] Step 6: Use dry etching to expose the n-type silicon nitride in the self-termination etching area 42. +The GaN layer 40 is removed, and the etching gas is SF6 / BCl3.

[0054] Specifically, if Figure 2f As shown, the exposed n-type silicon nitride layer in the self-termination etching region 42 is etched by dry etching using an ICP etching device. + The GaN layer 40 was removed using SF6 / BCl3 etching gases at a flow rate of 10 / 30 sccm, a pressure of 5 mTorr, an ICP top electrode power of 200 W, and a bottom electrode power of 30 W. The mixed gas used in the etching cannot etch Al-containing barrier materials, resulting in self-termination of the etching at the barrier layer 30.

[0055] Step 7: Photolithography defines the isolation region 50 at n + The corresponding area 43 to be etched on the GaN layer 40 is located on the edge of the product prepared in step 6. Figure 2g shown.

[0056] Step 8: Use dry etching to expose the n-type + The GaN layer 40 is removed and the first n + The GaN epitaxial layer 60 and the second n + GaN epitaxial layer 70 .

[0057] Specifically, if Figure 2h As shown, the exposed n-type silicon nitride layer in the isolation region 50 is etched by dry etching using an ICP etching device. + The GaN layer 40 is removed using SF6 / BCl3 etching gas with a flow rate of 10 / 30 sccm, a pressure of 5 mTorr, an ICP top electrode power of 200 W, and a bottom electrode power of 30 W. This step aims to prevent the device from having a large off-state leakage due to insufficient ion implantation isolation depth in step nine.

[0058] Step 9: Use ion implantation equipment to implant B or Ar ions into the isolation region 50 to form the isolation region 50 and achieve device isolation. Figure 2i shown.

[0059] Step 10: Using electron beam evaporation equipment, the groove 41 and the second n + Electrode metal is deposited on the GaN epitaxial layer 70 to form a source 80 and a drain 90, as shown in FIG. Figure 2j The source electrode 80 and the drain electrode 90 are both composed of four metal layers of Ti, Al, Ni and Au stacked in sequence from bottom to top.

[0060] Step 11: deposit a passivation layer 92 on the surface of the product prepared in step 10, and remove the passivation layer 92 on the source electrode 80 and the drain electrode 90 by dry etching.

[0061] Specifically, if Figure 2k As shown, a SiN passivation layer 92 is deposited using PECVD equipment; the SiN on the ohmic metal is removed by dry etching using an ICP etching equipment, the etching gas is CF4 / O2, the flow rate is 25 / 5sccm, the chamber pressure is 5mTorr, the ICP upper electrode power is 80W, and the lower electrode power is 10W.

[0062] Step 12: Use dry etching to remove the passivation layer 92 in the gate region, which is located between the source 80 and the drain 90; and deposit electrode metal in the gate region to form a gate 91. The high-linearity GaN HEMT device based on the asymmetric ohmic regrowth region is prepared.

[0063] Specifically, if Figure 1 As shown, the SiN passivation layer 92 in the gate area is removed by dry etching using an ICP etching device. The etching gas is CF4 / O2 with a flow rate of 25 / 5 sccm, a chamber pressure of 5 mTorr, an ICP upper electrode power of 80 W, and a lower electrode power of 10 W. Then, an electron beam evaporation device is used to deposit two layers of stacked metal in the gate area to form a gate 91. The structure of the gate 91 is a two-layer stacked metal of Ni and Au from bottom to top.

[0064] The gate 91 has a T-shaped structure. Electron beam evaporation is used to deposit a Ni / Au metal stack in the gate region to create a T-shaped gate electrode. The edge of the T-shaped gate 91 that contacts the passivation layer 92 is made of Ni, while the remaining upper layer is made of Au. The vertical section of the T-shaped gate passes through the passivation layer 92, while the horizontal section is located on the surface of the passivation layer 92.

[0065] In this embodiment, a high polarization strength and low square resistance heterojunction material is used to fabricate the device, and the ohmic regrowth region of the source 80 is defined by photolithography (note that the drain 90 is not subjected to photolithography of the regrowth region and is always protected by photoresist). However, unlike conventional GaN-based HEMT device fabrication, the device etched region 43 needs to be self-terminated to remove the surface n-type regions not protected by photoresist. + The GaN layer 40 prevents insufficient isolation depth during subsequent device ion implantation. A simple and easy-to-implement new ohmic regrowth method achieves low source-drain parasitic resistance while also creating differentiated source-drain current conduction capabilities through the asymmetric ohmic regrowth region, improving the linearity of GaN-based HEMT devices and meeting the requirements of 5G and future 6G applications.

[0066] Example 2

[0067] like Figure 1As shown, the second aspect of this embodiment provides a high linearity GaN HEMT device based on an asymmetric ohmic re-growth region, which is prepared by the preparation method in the first embodiment. The device includes: a substrate 10, a GaN buffer layer 20, a barrier layer 30, a first n + The GaN epitaxial layer 60 and the second n + GaN epitaxial layer 70. The substrate 10 is made of SiC or Si material.

[0068] The substrate 10, GaN buffer layer 20 and barrier layer 30 are arranged in sequence from bottom to top, and the GaN buffer layer 20 and barrier layer 30 form a heterojunction structure. The heterojunction structure is a low-square-resistance heterojunction structure, wherein the square resistance of the low-square-resistance heterojunction structure is about 200Ω / sq (ohms per square). The barrier layer 30 with high polarization strength and thin thickness is made of materials such as AlN, ScAlN, InAlN, InAlGaN or high-Al component AlGaN, and the thickness of the barrier layer 30 is 4nm-10nm. The low-defect GaN buffer layer 20 includes a UID-GaN layer and a Fe- or C-doped high-resistance GaN layer arranged in sequence from top to bottom.

[0069] First n + A portion of the GaN epitaxial layer 60 extends to at least 20 nm below the interface between the GaN buffer layer 20 and the barrier layer 30. + The remaining portion of the GaN epitaxial layer 60 is disposed on the barrier layer 30 to form a first n-type GaN epitaxial layer. + A groove 41 is formed on a portion of the GaN epitaxial layer 60; a second n + The GaN epitaxial layer 70 is disposed on the barrier layer 30 and is adjacent to the first n + The GaN epitaxial layers 60 are arranged at intervals.

[0070] First n + The GaN epitaxial layer 60 and the second n + An isolation region 50 is provided between the edge of the GaN epitaxial layer 70 and the edge of the barrier layer 30 . The isolation region 50 extends from the barrier layer 30 into the GaN buffer layer 20 .

[0071] The source electrode 80 is provided in the groove 41, and the second n + A drain electrode 90 is provided on the GaN epitaxial layer 70, and a gate electrode 91 is provided between the source electrode 80 and the drain electrode 90. Both the source electrode 80 and the drain electrode 90 are composed of four layers of metals Ti, Al, Ni and Au stacked in sequence from bottom to top. The gate electrode 91 is a two-layer stacked metal of Ni and Au from bottom to top. Among them, the gate electrode 91 is a T-type gate structure, the edge portion of the T-type gate electrode 91 in contact with the passivation layer 92 is metal Ni, and the remaining upper portion is metal Au. The vertical section of the T-type gate electrode 91 passes through the passivation layer 92, and the horizontal section is located on the surface of the passivation layer 92.

[0072] First n + GaN epitaxial layer 60, the second n + GaN epitaxial layer 70, the first n + GaN epitaxial layer 60 and the second n + A passivation layer 92 covers the GaN epitaxial layers 70 and the isolation region 50. The source 80, the drain 90 and the gate 91 extend above the passivation layer 92. The passivation layer 92 is made of SiN.

[0073] In this embodiment, the parasitic resistance of the device is reduced on the one hand by the asymmetric source regrowth region and the drain regrowth region; more importantly, on the other hand, the supply of source electrons is increased, and the source current conduction capability is greater than that of the drain, which alleviates the reduction in device linearity caused by the increase in source access resistance as the operating current increases.

[0074] In this embodiment, Figure 3 As shown, when the device is working normally, due to the lowering and thinning of the barrier between the source 80 step (Ledge) and the 2DEG channel, electrons can pass through the first n + The Ledge region of the GaN epitaxial layer 60 is transferred to the 2DEG channel, which increases the conductive path of the source region. The increase in source access resistance with increasing current is weakened, thereby increasing the device transconductance flatness and thus improving the device linearity.

[0075] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0076] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0077] In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "connect," "fixed," etc. should be understood broadly. For example, they may refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0078] In the present invention, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Furthermore, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0079] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0080] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A method for preparing a high-linearity GaN HEMT device based on an asymmetric ohmic regrowth region, characterized in that: The following steps are involved: Step 1: sequentially growing a GaN buffer layer (20) and a barrier layer (30) on a substrate (10); the GaN buffer layer (20) and the barrier layer (30) form a heterojunction structure; Step 2: photolithographically defining an ohmic regrown region of the source electrode, wherein the ohmic regrown region is located on one side of the barrier layer (30); Step 3: using a dry etching method to etch the barrier layer (30) in the ohmic regrown region of the source electrode until it is at least 20 nm below the junction of the GaN buffer layer (20) and the barrier layer (30), thereby forming an etching groove (31); Step 4: epitaxial growth of n on the product prepared in step 3 + GaN layer (40), doped at a concentration of 1e20 cm -3 The order of magnitude is above n on the etching groove (31). + A groove (41) is formed above the GaN layer (40); Step 5: Photolithographically define a self-termination etching region (42), wherein the self-termination etching region (42) is located at the n + a middle portion of the GaN layer (40); Step 6: Use dry etching to expose the n-type self-termination etching area (42). + The GaN layer (40) is removed, and the etching gas is SF6 / BCl3; Step 7: Photolithography defines the isolation region (50) on the n + A corresponding area (43) to be etched on the GaN layer (40), wherein the area (43) to be etched is located on the edge of the product prepared in step six; Step 8: Use dry etching to expose the n-type etched area (43). + The GaN layer (40) is removed and a first n + GaN epitaxial layer (60) and the second n + GaN epitaxial layer (70); Step nine: using ion implantation equipment to implant B or Ar ions into the isolation region (50) to form the isolation region (50) and achieve device isolation; Step 10: Using electron beam evaporation equipment, the groove (41) and the second n + Depositing electrode metal on the GaN epitaxial layer (70) to form a source electrode (80) and a drain electrode (90); Step 11: depositing a passivation layer (92) on the surface of the product prepared in step 10, and removing the passivation layer (92) on the source electrode (80) and the drain electrode (90) by dry etching; Step 12: using a dry etching method to remove the passivation layer (92) in the gate region, wherein the gate region is located between the source (80) and the drain (90); and depositing an electrode metal in the gate region to form a gate (91), thereby completing the preparation of a high-linearity GaN HEMT device based on an asymmetric ohmic regrowth region.

2. The method for preparing a high-linearity GaN HEMT device based on an asymmetric ohmic regrowth region according to claim 1, characterized in that: The material of the barrier layer (30) is AlN, ScAlN, InAlN, InAlGaN or AlGaN; the thickness of the barrier layer (30) is 4nm-10nm.

3. The method for preparing a high-linearity GaN HEMT device based on an asymmetric ohmic regrowth region according to claim 1, characterized in that: In the step 3, an ICP etching device is used, the etching gas is BCl3 / Cl2, the flow rate is 20 / 8 sccm, the chamber pressure is 5 mTorr, the upper electrode power is 51 W, and the lower electrode power is 14 W.

4. The method for preparing a high-linearity GaN HEMT device based on an asymmetric ohmic regrowth region according to claim 1, characterized in that: In the step six, an ICP etching device is used, the etching gas flow rate is 10 / 30 sccm, the pressure is 5 mTorr, the ICP upper electrode power is 200 W, and the lower electrode power is 30 W.

5. The method for preparing a high-linearity GaN HEMT device based on an asymmetric ohmic regrowth region according to claim 1, characterized in that: In the step eight, an ICP etching device is used, the etching gas is SF6 / BCl3, the flow rate is 10 / 30 sccm, the pressure is 5 mTorr, the upper electrode power is 200 W, and the lower electrode power is 30 W.

6. The method for preparing a high-linearity GaN HEMT device based on an asymmetric ohmic regrowth region according to claim 1, characterized in that: The material of the substrate (10) is SiC or Si; the material of the passivation layer (92) is SiN.

7. The method for preparing a high-linearity GaN HEMT device based on an asymmetric ohmic regrowth region according to claim 1, characterized in that: The source electrode (80) and the drain electrode (90) are both Ti, Al, Ni and Au stacked in sequence from bottom to top; The gate (91) is Ni and Au stacked in sequence from bottom to top.

8. A high linearity GaN HEMT device based on an asymmetric ohmic regrowth region, characterized in that: Prepared by the preparation method according to any one of claims 1 to 7, comprising: a substrate (10), a GaN buffer layer (20), a barrier layer (30), a first n + GaN epitaxial layer (60) and the second n + GaN epitaxial layer (70); The substrate (10), the GaN buffer layer (20), and the barrier layer (30) are arranged in sequence from bottom to top, and the GaN buffer layer (20) and the barrier layer (30) form a heterojunction structure; The first n + A portion of the GaN epitaxial layer (60) extends to at least 20 nm below the interface between the GaN buffer layer (20) and the barrier layer (30), and the remaining portion is disposed on the barrier layer (30) to form a groove (41) above the portion of the structure; the second n + The GaN epitaxial layer (70) is disposed on the barrier layer (30) and is connected to the first n + The GaN epitaxial layers (60) are arranged at intervals; The first n + GaN epitaxial layer (60) and the second n + An isolation region (50) is provided between the edge of the GaN epitaxial layer (70) and the edge of the barrier layer (30); The isolation region (50) extends from the barrier layer (30) into the GaN buffer layer (20); A source electrode (80) is provided in the groove (41), and the second n + A drain electrode (90) is provided on the GaN epitaxial layer (70); a gate electrode (91) is provided between the source electrode (80) and the drain electrode (90); The first n + GaN epitaxial layer (60), the second n + GaN epitaxial layer (70), the first n + GaN epitaxial layer (60) and the second n + A passivation layer (92) is covered between the GaN epitaxial layers (70) and on the isolation region (50); The source electrode (80), the drain electrode (90) and the gate electrode (91) extend above the passivation layer (92).

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