Double-gate structure gallium nitride high electron mobility transistor and manufacturing method thereof
By employing a dual-gate structure in GaN HEMT devices and etching a barrier layer below the sub-gate electrode to form a groove, a Schottky diode is formed to protect the main gate electrode. This solves the problems of unstable conduction capability in the third quadrant and gate reliability, achieving high reliability and high energy efficiency device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANJING UNIV
- Filing Date
- 2022-04-29
- Publication Date
- 2026-06-23
AI Technical Summary
Existing GaN HEMT devices have unstable conduction capability and high power consumption in the third quadrant. The gate is susceptible to energy shocks from parasitic capacitance and inductive coupling under circuit switching conditions, which can lead to device damage or unstable performance.
The device employs a dual-gate structure design. A groove structure is formed by etching a barrier layer under the sub-gate electrode. The sub-gate electrode and the two-dimensional electron gas form a Schottky diode. The sub-gate electrode protects the main gate electrode, thereby improving the device's third-quadrant conduction capability and gate reliability.
It improves the device's high reliability and energy efficiency, enhances the third quadrant conduction capability, and reduces the gate reliability risk, making it suitable for power electronics and radio frequency electronic devices.
Smart Images
Figure CN114843337B_ABST
Abstract
Description
Technical Field
[0001] This invention relates in particular to a dual-gate gallium nitride high electron mobility transistor and its fabrication method, belonging to the field of wide bandgap semiconductor transistor technology. Background Technology
[0002] Electrical energy is inextricably linked to the development of human society, and power electronic devices are the core components of energy conversion, capable of efficiently converting electrical energy in various forms and widely used in various power systems. With the continuous development of electronic technology, traditional Si-based devices, limited by the physical properties of their materials, are increasingly unable to meet the demands for power density, switching speed, and energy efficiency. Gallium nitride (GaN), with its large bandgap, high breakdown field strength, high saturated electron drift velocity, and high thermal conductivity, is a preferred material for fabricating next-generation power electronic devices. Based on the strong polarization characteristics of GaN, a high-concentration, high-mobility two-dimensional electron gas (2DEG) can be formed at the AlGaN / GaN heterojunction interface, making it a primary material system for fabricating high-performance power electronic devices, and it has already achieved large-scale commercialization. Due to the presence of 2DEG, conventional AlGaN / GaN HEMT devices are depletion-mode devices (also known as normally-on devices, meaning the device is in the on state at zero gate bias). In practical applications, a negative voltage source is required to turn off the device, which not only poses safety issues but also increases the complexity of the gate drive circuit design and raises the cost of the device. Correspondingly, enhancement-mode (also known as normally-off) GaN HEMT devices have become the main research direction, possessing broad application value and research significance.
[0003] Currently, the industry typically adopts two technical approaches: one is to use a p-type cap layer structure to deplete the 2DEG channel to achieve enhancement-mode operation, and the other is to use a low-voltage enhancement-mode Si MOSFET and a high-voltage depletion-mode GaN HEMT cascade structure (cascode) to achieve enhancement-mode operation.
[0004] However, both technical approaches face the problem of third-quadrant turn-on voltage drifting with changes in the GaN HEMT device threshold voltage and gate bias voltage, resulting in unstable third-quadrant conduction capability and high power consumption. Furthermore, due to the high voltage and high switching speed of GaN HEMT devices, the gate electrode is highly susceptible to impacts from parasitic capacitance and inductive coupling energy under circuit switching conditions, which can lead to gate oscillations or even direct device damage.
[0005] Therefore, whether in enhancement-mode GaN HEMT devices, depletion-mode GaN HEMT devices, or RF GaN HEMT devices with higher switching frequencies, it is necessary to develop a GaN HEMT device technology with excellent third-quadrant conduction capability and high gate reliability to achieve high reliability and high energy efficiency of the device. Summary of the Invention
[0006] The main objective of this invention is to provide a dual-gate gallium nitride high electron mobility transistor based on barrier layer etching technology and its fabrication method. By adopting a dual-gate structure with a main gate electrode and a sub-gate electrode, and by etching a barrier layer below the sub-gate electrode, the invention achieves superior third-quadrant conduction capability and improves gate reliability by protecting the main gate electrode with the sub-gate electrode, thereby overcoming the shortcomings of the prior art.
[0007] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:
[0008] This invention provides a dual-gate gallium nitride high electron mobility transistor based on barrier layer etching technology, including a heterostructure and a source electrode, a drain electrode, a main gate electrode, and a sub-gate electrode that cooperate with the heterostructure.
[0009] The heterostructure includes a channel layer and a barrier layer formed on the channel layer, and a two-dimensional electron gas is formed between the channel layer and the barrier layer.
[0010] The main gate electrode and the sub-gate electrode are respectively disposed in the main gate electrode region and the sub-gate electrode region of the barrier layer. The sub-gate electrode region of the barrier layer has a groove structure. The sub-gate electrode is partially disposed in the groove structure, and the sub-gate electrode and the two-dimensional electron gas form a Schottky diode.
[0011] This invention provides a method for fabricating the dual-gate gallium nitride high electron mobility transistor, comprising:
[0012] A heterostructure is provided, the heterostructure including a channel layer and a barrier layer formed on the channel layer, wherein a two-dimensional electron gas is formed between the channel layer and the barrier layer;
[0013] A source electrode is formed in the source electrode region on the surface of the barrier layer, and a drain electrode is formed in the drain electrode region on the surface of the barrier layer.
[0014] A main gate electrode is formed in the main gate region on the surface of the barrier layer; at least a portion of the barrier layer in the sub-gate electrode region on the surface of the barrier layer is removed to form a groove structure in the sub-gate region, and a sub-gate electrode is formed in the sub-gate electrode region, with a portion of the sub-gate electrode located within the groove structure; or, a sub-gate electrode is directly formed in the sub-gate electrode region on the surface of the barrier layer, and the sub-gate electrode and the two-dimensional electron gas form a Schottky diode.
[0015] Compared with the prior art, the present invention provides a dual-gate gallium nitride high electron mobility transistor based on barrier layer etching technology. By etching the barrier layer in the sub-gate electrode region to form a groove structure, a Schottky diode is formed at the 2DEG interface between the sub-gate electrode and the heterojunction. The sub-gate electrode protects the main gate electrode, thereby improving the device's third quadrant conduction capability and gate reliability. This enhances the device's high reliability and high energy efficiency, and it can be applied to power electronics and radio frequency electronic devices. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of a dual-gate GaN HEMT device based on barrier layer etching technology provided in Embodiment 1 of the present invention;
[0017] Figure 2 This is a top view of a dual-gate GaN HEMT device based on barrier layer etching technology provided in Embodiment 1 of the present invention;
[0018] Figure 3 This is a schematic diagram of the fabrication process of a dual-gate GaN HEMT device based on barrier layer etching technology provided in Embodiment 1 of the present invention;
[0019] Figure 4 This is a schematic diagram of a dual-gate GaN HEMT device based on barrier layer etching technology provided in Embodiment 2 of the present invention. Detailed Implementation
[0020] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate this technical solution, its implementation process, and its principles.
[0021] This invention provides a dual-gate gallium nitride high electron mobility transistor based on barrier layer etching technology, including a heterostructure and a source electrode, a drain electrode, a main gate electrode, and a sub-gate electrode that cooperate with the heterostructure.
[0022] The heterostructure includes a channel layer and a barrier layer formed on the channel layer, and a two-dimensional electron gas is formed between the channel layer and the barrier layer.
[0023] The main gate electrode and the sub-gate electrode are respectively disposed in the main gate electrode region and the sub-gate electrode region of the barrier layer. The sub-gate electrode region of the barrier layer has a groove structure. The sub-gate electrode is partially disposed in the groove structure, and the sub-gate electrode and the two-dimensional electron gas form a Schottky diode.
[0024] In a more specific embodiment, the groove structure includes one or more grooves recessed along the thickness direction of the barrier layer, the depth of the grooves being greater than or equal to 0 and less than or equal to the thickness of the heterojunction.
[0025] In a more specific implementation, the main gate electrode region is further provided with a main gate structure, and the main gate electrode is disposed on the main gate structure, wherein the main gate structure is an enhancement gate structure or a depletion gate structure.
[0026] In a more specific implementation, the main gate structure is any one of the following: Schottky gate structure, metal-insulator-semiconductor (MIS) gate structure, p-type gate cap structure, pn junction gate cap structure, groove gate structure, and fluorine ion implanted gate structure, but is not limited thereto.
[0027] In a more specific embodiment, the main gate electrode and the sub-gate electrode are disposed between the source electrode and the drain electrode, wherein the main gate electrode is located between the sub-gate electrode and the source electrode.
[0028] In a more specific implementation, the channel layer is made of GaN, and the barrier layer is made of one or more of AlGaN, InAlGaN, AlN, and InAlN.
[0029] In a more specific embodiment, the heterostructure further includes an insertion layer disposed between the channel layer and the barrier layer.
[0030] In a more specific implementation, the material of the insertion layer includes AlN, but is not limited to this.
[0031] In a more specific implementation, the thickness of the insertion layer is greater than 0 and less than or equal to 3 nm.
[0032] In a more specific implementation, a passivation layer is provided on the barrier layer in addition to the area covered by the source electrode, drain electrode, main gate electrode and sub-gate electrode.
[0033] In a more specific implementation, the material of the passivation layer includes any one or more combinations of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, silicon oxynitride, aluminum oxynitride, and polyimide, but is not limited thereto.
[0034] In a more specific embodiment, the heterostructure is disposed on a buffer layer, the buffer layer is disposed on a nucleation layer, and the nucleation layer is disposed on a substrate.
[0035] In a more specific implementation, the material of the buffer layer includes any one of AlGaN, GaN, and AlN, but is not limited thereto.
[0036] In a more specific embodiment, the substrate material includes Si, SiC, sapphire, GaN, AlN, or diamond.
[0037] This invention provides a method for fabricating the dual-gate gallium nitride high electron mobility transistor, comprising:
[0038] A heterostructure is provided, the heterostructure including a channel layer and a barrier layer formed on the channel layer, wherein a two-dimensional electron gas is formed between the channel layer and the barrier layer;
[0039] A source electrode is formed in the source electrode region on the surface of the barrier layer, and a drain electrode is formed in the drain electrode region on the surface of the barrier layer.
[0040] A main gate electrode is formed in the main gate region on the surface of the barrier layer; at least a portion of the barrier layer in the sub-gate electrode region on the surface of the barrier layer is removed to form a groove structure in the sub-gate region, and a sub-gate electrode is formed in the sub-gate electrode region, with a portion of the sub-gate electrode located within the groove structure; or, a sub-gate electrode is directly formed in the sub-gate electrode region on the surface of the barrier layer, and the sub-gate electrode and the two-dimensional electron gas form a Schottky diode.
[0041] In a more specific embodiment, the fabrication method includes: etching one or more selected regions within the sub-gate region to remove a portion of the barrier layer within the selected regions, thereby forming the groove structure; or etching one or more selected regions within the sub-gate region to remove all the barrier layers within the selected regions, thereby forming the groove structure; or etching one or more selected regions within the sub-gate region to remove all the barrier layers and a portion of the channel layer within the selected regions, thereby forming the groove structure; or etching one or more selected regions within the sub-gate region to remove all the barrier layers and all the channel layers within the selected regions, thereby forming the groove structure.
[0042] In a more specific embodiment, the fabrication method includes: forming a main gate structure in the main gate electrode region, and combining the main gate structure with the heterostructure to form an enhancement gate structure or a depletion gate structure, and then forming the main gate electrode on the main gate structure.
[0043] In a more specific implementation, the fabrication method includes: fabricating the main gate structure using any one of the following techniques: recessed gate technology, p-type gate cap layer technology, pn junction gate cap layer technology, and fluorine ion implantation technology.
[0044] The following will further explain the technical solution, its implementation process and principle in conjunction with the accompanying drawings and specific implementation examples. Unless otherwise specified, the semiconductor epitaxy, device isolation, photolithography, etching and annealing used in the embodiments of the present invention can all be implemented by processes known to those skilled in the art, and no specific limitations or explanations are made here.
[0045] The embodiments of this application are described in detail below. The described embodiments are exemplary and are only used to explain this application, and should not be construed as limiting this application.
[0046] In the description of this application, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.
[0047] In the description of this application, unless otherwise expressly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.
[0048] In the description of this application, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0049] Example 1
[0050] Please see Figure 1 and Figure 2A dual-gate GaN HEMT device based on barrier layer etching technology includes an epitaxial structure and a source electrode 9, a drain electrode 12, a main gate electrode 10, and a sub-gate electrode 11 that cooperate with the epitaxial structure. The epitaxial structure includes a GaN channel layer 4 and a barrier layer 6 stacked sequentially from bottom to top, forming a heterostructure. A two-dimensional electron gas is formed between the GaN channel layer 4 and the barrier layer 6. The source electrode 9, drain electrode 12, main gate electrode 10, and sub-gate electrode 11 are spaced apart on the barrier layer 6. The main gate electrode 10 and sub-gate electrode 11 are sequentially disposed on the source electrode. Between the 9 and the drain electrode 12, and in the region corresponding to the barrier layer 6 and the main gate electrode 10, a main gate structure 7 is also provided. The main gate electrode 10 is disposed on the main gate structure 7. The region of the barrier layer 6 covered by the sub-gate electrode 11 is also provided with a groove structure. The groove structure includes one or more grooves 13 formed by recessing along the thickness direction of the epitaxial structure. The depth of the groove 13 is less than the thickness of the barrier layer 6. The sub-gate electrode 11 is partially disposed in the groove 13, and the sub-gate electrode 11 and the two-dimensional electron gas form a Schottky diode.
[0051] In this embodiment, please refer again. Figure 2 The grooves 13 can be continuous or discontinuous, and multiple grooves 13 can be arranged at intervals. The orthographic projection shape of the grooves can be circular, square, or other shapes.
[0052] In this embodiment, the sub-gate electrode 11 and the source electrode 12 are electrically connected. The electrical connection can be a metal connection or a semiconductor connection on the device, or there can be no connection on the device but an electrical connection on the packaging substrate.
[0053] In this embodiment, the dual-gate GaN HEMT device is applicable to the fields of power electronic devices and radio frequency electronic devices. The power electronic devices include enhancement-mode and depletion-mode power electronic devices. The main gate structure can be any one of the following: Schottky gate structure, metal-insulator-semiconductor (MIS) gate structure, p-type gate cap structure, pn junction gate cap structure, groove gate structure, and fluorine ion implanted gate structure, but is not limited thereto.
[0054] In this embodiment, the epitaxial structure includes a substrate 1, a nucleation layer 2, a buffer layer 3, a GaN channel layer 4, and a barrier layer 6 stacked sequentially from bottom to top.
[0055] In this embodiment, the epitaxial structure includes a substrate 1, a nucleation layer 2, a buffer layer 3, a GaN channel layer 4, an insertion layer 5, and a barrier layer 6 stacked sequentially from bottom to top, wherein the GaN channel layer 4, the insertion layer 5, and the barrier layer 6 form the heterostructure.
[0056] In this embodiment, the substrate 1 is made of at least one of silicon, sapphire, silicon carbide, gallium nitride, aluminum nitride, and diamond; the nucleation layer 2 is made of AlN; the buffer layer 3 is made of GaN, preferably carbon-doped GaN; the insertion layer 5 is made of AlN; and the barrier layer 6 is made of AlGaN barrier layer, or more preferably Al 0.2 Ga 0.8 N-barrier layer.
[0057] In this embodiment, the thickness of the substrate 1 is 300-1000 μm, the thickness of the buffer layer is 0.5-10 μm, the thickness of the channel layer 4 is 100-1000 nm, the thickness of the insertion layer 5 is 3 nm, and the thickness of the barrier layer 6 is 5-30 nm.
[0058] In this embodiment, the main gate structure 7 can be a gate cap layer, the gate cap layer can be made of p-GaN, and the thickness of the main gate structure 7 is 100-300 nm. Preferably, the gate cap layer can be made of Mg-doped p-GaN, wherein the Mg doping concentration is 5 × 10⁻⁶. 19 cm -3 .
[0059] In this embodiment, a passivation layer 8 is also provided on the barrier layer 6. The passivation layer 8 is disposed in the area not covered by the source electrode 9, drain electrode 12, main gate electrode 10 and sub-gate electrode 11. The material of the passivation layer 8 includes any one or a combination of two or more of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, silicon oxynitride, aluminum oxynitride, and polyimide.
[0060] In this embodiment, please refer to Figure 3 A method for fabricating a dual-gate GaN HEMT device based on barrier layer etching technology may include the following steps:
[0061] 1) An AlN nucleation layer 2, a GaN buffer layer 3, a 300 nm thick GaN channel layer 4, a 3 nm thick AlN insertion layer 5, a 13 nm thick AlGaN barrier layer 6, and a 200 nm thick main gate structure 7 are sequentially deposited and grown on substrate 1 by means of metal-organic chemical vapor deposition.
[0062] 2) Active regions are defined by ion implantation to form electrical isolation between devices. The ion implantation adopts double nitrogen implantation planar isolation, and the implanted element is at least one of Ar, F, N and B, with implantation energies of 45keV and 135keV, respectively.
[0063] 3) Photolithography defines the window area outside the main gate electrode and the sub-gate electrode. The main gate structure 7 in all areas outside the main gate structure and the sub-gate electrode is removed by inductively coupled plasma etching. It should be noted that the main gate structure located in the sub-gate electrode area can also be removed and only the main gate structure located in the main gate electrode area can be retained.
[0064] 4) Photolithography defines the electrode contact areas of the source electrode 9 and the drain electrode 12. Ti / Al / Ni / Au metal stacks are deposited by electron beam evaporation or other methods. The thicknesses of each layer in the metal stack are 30nm for Ti, 150nm for Al, 40nm for Ni, and 100nm for Au. Then, the source electrode 9 and the drain electrode 12 are formed by a lift-off process. The entire wafer is then subjected to rapid thermal annealing to form ohmic contacts between the source electrode 9 and the drain electrode 12 and the barrier layer 6. The rapid thermal annealing is performed in a nitrogen atmosphere at a temperature of 500℃ to 950℃ for 0 to 500s. Preferably, the annealing temperature is 850℃ and the time is 30s.
[0065] 5) Photolithography defines the barrier layer etching region of the sub-gate electrode 11, and etching is performed on the surface of the barrier layer 6 by reactive ion etching and other methods. The etching depth is greater than 0 and less than the thickness of the barrier layer 6, thereby forming a groove structure.
[0066] 6) Photolithography defines the contact area between the main gate electrode 10 and the sub-gate electrode 11. Ni / Au metal stack is deposited by electron beam evaporation and other methods. The thickness of each layer of the metal stack is 30nm for Ni layer and 120nm for Au layer. The main gate electrode 10 and the sub-gate electrode 11 are formed by lift-off process.
[0067] 7) 300 nm SiN was deposited on the device surface using methods such as plasma-enhanced chemical vapor deposition. x Passivation layer 8 is used to define the electrode window regions of source electrode 9, main gate electrode 10, sub-gate electrode 11 and drain electrode 12. The passivation layer 8 is then removed by reactive ion etching or wet etching to obtain the final barrier layer etched structure dual-gate GaN HEMT device.
[0068] It should be noted that the preparation of the passivation layer 8 can be performed before or after the preparation of the metal electrode. The passivation layer preparation method includes any one or more combinations of in-situ growth, low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, and spin coating.
[0069] In this embodiment, the main gate structure 7 can be an enhancement gate structure or a depletion gate structure, also known as a normally-off gate structure or a normally-on gate structure. The implementation of the enhancement gate structure or the normally-off gate structure is selected from at least one of the following: recessed gate technology, p-type gate cap layer technology, pn junction gate cap layer technology, and fluorine ion implantation technology.
[0070] Example 2
[0071] Please see Figure 4 The structure and fabrication process of the dual-gate GaN HEMT device based on barrier layer etching technology in this embodiment are basically the same as those in Embodiment 1. The difference is that the groove located below the sub-gate electrode 11 extends from the surface of the barrier layer 6 along the thickness direction of the epitaxial structure into the channel layer 5. It should be noted that the groove can also extend from the surface of the barrier layer 6 along the thickness direction of the epitaxial structure into the entire channel layer 5, that is, the depth of the groove is equal to the thickness of the heterostructure.
[0072] Example 3
[0073] The structure and fabrication process of the dual-gate GaN HEMT device based on barrier layer etching technology in this embodiment are basically the same as those in Embodiment 1 or Embodiment 2, except that:
[0074] In this embodiment, a dual-gate GaN HEMT device has a dual-gate structure with a main source electrode, a main gate electrode, a main drain electrode, a secondary source electrode, a secondary gate electrode, and a secondary drain electrode formed on the barrier layer. The main drain electrode and the secondary source electrode are electrically connected via the two-dimensional electron gas. In the final fabricated device, it is optional whether or not the main drain electrode and the secondary source electrode have metal electrodes. In practical applications, the main drain electrode and the secondary source electrode can be omitted, or the metal electrodes can be omitted. The dual-gate GaN HEMT device etched by the barrier layer has an equivalent three-terminal device structure, with the three terminals being the main source electrode, the main gate electrode, and the secondary drain electrode.
[0075] This invention provides a dual-gate gallium nitride high electron mobility transistor based on barrier layer etching technology. By etching the barrier layer in the sub-gate electrode region to form a groove structure, a Schottky diode is formed between the sub-gate electrode and the heterojunction interface 2DEG. The sub-gate electrode protects the main gate electrode, thereby improving the device's third-quadrant conduction capability and gate reliability. This enhances the device's high reliability and high energy efficiency, and it can be applied to power electronics and radio frequency electronic devices.
[0076] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.
Claims
1. A dual-gate gallium nitride high electron mobility transistor based on barrier layer etching technology, characterized in that, include: Heterogeneous structure and source electrode, drain electrode, main gate electrode and sub-gate electrode that cooperate with said heterogeneous structure; The heterostructure includes a channel layer and a barrier layer formed on the channel layer, and a two-dimensional electron gas is formed between the channel layer and the barrier layer. The main gate electrode and the sub-gate electrode are spaced apart between the source electrode and the drain electrode. The main gate electrode is located between the sub-gate electrode and the source electrode. The main gate electrode and the sub-gate electrode are respectively disposed in the main gate electrode region and the sub-gate electrode region of the barrier layer. The sub-gate electrode region of the barrier layer has a groove structure. The sub-gate electrode is partially disposed in the groove structure. The sub-gate electrode and the two-dimensional electron gas form a Schottky diode. The sub-gate electrode is electrically connected to the source electrode. The groove structure includes one or more grooves recessed along the thickness direction of the barrier layer. The depth of the groove is greater than or equal to 0 and less than or equal to the thickness of the heterostructure. Furthermore, the main gate electrode region is also provided with a main gate structure, and the main gate electrode is disposed on the main gate structure, wherein the main gate structure is an enhancement gate structure or a depletion gate structure.
2. The dual-gate gallium nitride high electron mobility transistor according to claim 1, characterized in that: The main gate structure is any one of the following: Schottky gate structure, metal-insulator-semiconductor (MIS) gate structure, p-type gate cap structure, pn junction gate cap structure, groove gate structure, and fluorine ion implanted gate structure.
3. The dual-gate gallium nitride high electron mobility transistor according to claim 1, characterized in that: The channel layer is made of GaN, and the barrier layer is made of one or more of AlGaN, InAlGaN, AlN, and InAlN.
4. The dual-gate gallium nitride high electron mobility transistor according to claim 1, characterized in that: The heterostructure further includes an insertion layer disposed between the channel layer and the barrier layer.
5. The dual-gate gallium nitride high electron mobility transistor according to claim 4, characterized in that: The material of the insertion layer includes AlN.
6. The dual-gate gallium nitride high electron mobility transistor according to claim 4, characterized in that: The thickness of the insertion layer is greater than 0 and less than or equal to 3 nm.
7. The dual-gate gallium nitride high electron mobility transistor according to claim 1, characterized in that: In addition to the areas covered by the source electrode, drain electrode, main gate electrode, and sub-gate electrode, a passivation layer is also provided on the barrier layer.
8. The dual-gate gallium nitride high electron mobility transistor according to claim 7, characterized in that: The passivation layer is made of any one or a combination of two or more of the following materials: silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, silicon oxynitride, aluminum oxynitride, and polyimide.
9. The dual-gate gallium nitride high electron mobility transistor according to claim 1, characterized in that: The heterostructure is disposed on a buffer layer, the buffer layer is disposed on a nucleation layer, and the nucleation layer is disposed on a substrate.
10. The dual-gate gallium nitride high electron mobility transistor according to claim 9, characterized in that: The material of the buffer layer includes any one or more of AlGaN, GaN, and AlN to form a composite structure layer.
11. The dual-gate gallium nitride high electron mobility transistor according to claim 9, characterized in that: The substrate material includes Si, SiC, sapphire, GaN, AlN, or diamond.
12. The method for fabricating a dual-gate gallium nitride high electron mobility transistor as described in any one of claims 1-11, characterized in that, include: A heterostructure is provided, the heterostructure including a channel layer and a barrier layer formed on the channel layer, wherein a two-dimensional electron gas is formed between the channel layer and the barrier layer; A source electrode is formed in the source electrode region on the surface of the barrier layer, and a drain electrode is formed in the drain electrode region on the surface of the barrier layer. A main gate structure is formed in the main gate region on the surface of the barrier layer, and the main gate structure is combined with the heterostructure to form an enhancement gate structure or a depletion gate structure. Then, the main gate electrode is formed on the main gate structure. At least a portion of the barrier layer in the sub-gate electrode region on the surface of the barrier layer is removed to form a groove structure in the sub-gate electrode region. A sub-gate electrode is formed in the sub-gate electrode region, and a portion of the sub-gate electrode is located within the groove structure. Alternatively, the sub-gate electrode is formed directly in the sub-gate electrode region on the surface of the barrier layer. The sub-gate electrode and the two-dimensional electron gas form a Schottky diode.
13. The manufacturing method according to claim 12, characterized in that, include: One or more selected regions within the sub-gate electrode region are etched to remove a portion of the barrier layer within the selected regions, thereby forming the groove structure. Alternatively, one or more selected regions within the sub-gate electrode region can be etched to remove all the barrier layer within the selected regions, thereby forming the groove structure. Alternatively, one or more selected regions within the sub-gate electrode region can be etched to remove all the barrier layer and part of the channel layer within the selected regions, thereby forming the groove structure. Alternatively, one or more selected regions within the sub-gate electrode region may be etched to remove all barrier layers and all channel layers within the selected regions, thereby forming the groove structure.
14. The manufacturing method according to claim 12, characterized in that, include: The main gate structure is fabricated using any one of the following methods: concave gate technology, p-type gate cap layer technology, pn junction gate cap layer technology, and fluorine ion implantation technology.