An asymmetric trench gate IGBT device and a method of manufacturing the same

Abstract

The present application relates to an asymmetric trench gate IGBT device, which forms a certain potential barrier by making a Schottky contact above a non-conductive side P well region (i.e. a first P well region), so as to prevent holes from directly escaping from the grounded P well region, and to improve the hole concentration, thereby significantly reducing the forward conduction voltage drop of the device, reducing the on-state loss, and significantly enhancing the conduction capacity of the device, while the breakdown voltage is not degraded by the gate oxide electric field. The present application also relates to a preparation method of the asymmetric trench gate IGBT device, and the preparation process is simple.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to an asymmetric trench gate IGBT device and a preparation method thereof. BACKGROUND

[0002] Insulated Gate Bipolar Transistor (IGBT) is the latest power electronic device, which marks the technical frontier of power semiconductor. IGBT is initially realized by introducing PN junction in power MOSFET substrate. The existence of PN junction on the substrate introduces the effect of conductance modulation when turned on, so that IGBT not only has the advantages of high input impedance, small driving power, high switching frequency and large breakdown voltage of power MOSFET, but also has the advantages of large on-state current and small on-state voltage drop of bipolar transistor, and is widely used in strong electric control fields such as ship drive, rail transit, smart grid, AC frequency conversion, aerospace, wind power, new energy, motor drive and automobile.

[0003] With the application of power devices more and more widely, the parameters of the device itself are also more and more important. Throughout the development history of IGBT, the research team mainly focuses on improving the breakdown voltage and reducing the on-state voltage drop. In order to reduce the on-state voltage drop and improve the conduction capability, researchers have developed trench gate IGBT. Trench gate IGBT eliminates the JFET region, has high channel density, obvious carrier storage effect, and has a bidirectional conductance modulation effect similar to PiN diode, thereby reducing the on-state voltage drop and improving the conduction capability of the device. However, although the on-state voltage drop of the existing trench gate IGBT is reduced, the breakdown voltage and the gate oxide electric field are degraded.

[0004] Therefore, it is necessary to develop an improved trench gate IGBT which has significantly reduced on-state voltage drop without degradation of breakdown voltage and gate oxide electric field. SUMMARY

[0005] The purpose of the present application is to overcome the shortcomings of the prior art and provide an asymmetric trench gate IGBT device. The device forms a certain potential barrier by making a Schottky contact above the non-conductive side P well region (i.e. the first P well region), thereby preventing holes from directly escaping from the ground P well region, improving the hole concentration, significantly reducing the forward on-state voltage drop of the device, reducing the on-state loss, and significantly enhancing the conduction capability of the device, while the breakdown voltage and the gate oxide electric field are not degraded.

[0006] Another purpose of the present application is to provide a preparation method of the above-mentioned asymmetric trench gate IGBT device.

[0007] In order to achieve the above purposes, the present application provides the following technical solutions.

[0008] An asymmetric trench gate IGBT device, comprising:

[0009] a collector electrode;

[0010] a P-type collector layer disposed on an upper surface of the collector electrode;

[0011] an N-type drift layer disposed on an upper surface of the P-type collector layer, a surface layer of an upper surface of the N-type drift layer being provided with a first P-well region and a second P-well region separated from each other, a surface layer of an upper surface of the second P-well region being provided with a P-type heavily doped contact region and an N-type heavily doped source region, the P-type heavily doped contact region and the N-type heavily doped source region being in contact with each other;

[0012] a trench gate cell comprising a gate electrode, a gate dielectric layer covering a sidewall and a lower surface of the gate electrode, and an interlayer dielectric layer covering an upper surface of the gate electrode, the trench gate cell being disposed between and in contact with the first P-well region and the second P-well region, the trench gate cell being in contact with the N-type heavily doped source region;

[0013] an emitter electrode covering an upper surface of the P-type heavily doped contact region and the N-type heavily doped source region, and covering a part of an upper surface of the interlayer dielectric layer; and

[0014] a metal layer covering an upper surface of the first P-well region, and covering a part of an upper surface of the interlayer dielectric layer, wherein the metal layer forms a Schottky contact with the first P-well region.

[0015] A method for manufacturing the asymmetric trench gate IGBT device described above, comprising:

[0016] forming a P-type collector layer on an upper surface of an N-type substrate;

[0017] forming an N-type drift layer on an upper surface of the P-type collector layer;

[0018] forming an initial P-well region on a surface layer of an upper surface of the N-type drift layer by ion implantation;

[0019] forming an N-type heavily doped source region and a P-type heavily doped contact region in contact with each other on a surface layer of an upper surface of the initial P-well region;

[0020] etching the initial P-well region to form a trench, the trench dividing the initial P-well region into a first P-well region and a second P-well region, and a sidewall of the N-type heavily doped source region being part of a sidewall of the trench;

[0021] forming a gate dielectric layer on the sidewall of the trench, refilling the trench to form a gate electrode, and forming an interlayer dielectric layer on an upper surface of the gate electrode, thereby obtaining a trench gate cell;

[0022] forming an emitter covering the upper surface of the N-type heavily doped source region and the P-type heavily doped contact region, and covering part of the upper surface of the interlayer dielectric layer;

[0023] forming a metal layer covering the upper surface of the first P-well region, and covering part of the upper surface of the interlayer dielectric layer, after annealing, the metal layer forms a Schottky contact with the first P-well region; and

[0024] forming a collector on the lower surface of the P-type collector layer after removing the N-type substrate, and then laser annealing.

[0025] Compared with the prior art, the present application has the following beneficial effects:

[0026] 1. The present application provides an asymmetric trench gate IGBT device, which forms a certain potential barrier by making a Schottky contact above the non-conductive side P-well region (i.e. the first P-well region), thereby preventing holes from directly escaping from the grounded P-well region, increasing the hole concentration, significantly reducing the forward conduction voltage drop of the device, reducing the on-state loss, and significantly enhancing the conduction capacity of the device, while the breakdown voltage and the gate oxide field do not degrade.

[0027] 2. The preparation process of the asymmetric trench gate IGBT device of the present application is simple. BRIEF DESCRIPTION OF DRAWINGS

[0028] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a description of preferred embodiments, and are not meant to limit the present application. Moreover, the same reference numerals are used throughout the various drawings to designate the same or similar parts. In the drawings:

[0029] Figure 1 Figure 1 is a structural schematic diagram of the asymmetric trench gate IGBT device of the present application.

[0030] Figures 2-13 Figure 2 is a schematic diagram of the structure obtained in each step of the preparation method provided in Example 1 of the present application.

[0031] Figure 14 Figure 3 is a structural schematic diagram of the asymmetric trench gate IGBT device prepared in Comparative Example 1 of the present application.

[0032] Figure 15 Figure 4 is a hole concentration distribution diagram of the asymmetric trench gate IGBT device of Example 1 and Comparative Example 1 of the present application.

[0033] Figure 16 Figure 5 is a forward conduction characteristic curve simulation diagram of the asymmetric trench gate IGBT device of Example 1 and Comparative Example 1 of the present application.

[0034] Reference Signs List

[0035] 100 is a collector, 200 is a P-type collector layer, 300 is an N-type drift layer, 301 is an initial P-well region, 301a is a first P-well region, 301b is a second P-well region, 302 is a P-type heavily doped contact region, 303 is an N-type heavily doped source region, 304 is an initial N-type current spreading region, 304a is an N-type current spreading region, 305 is a step structure, 305a is a first side surface, 305b is a first upper surface, 305c is a second side surface, 305d is a second upper surface, 306 is a trench, 400 is a trench gate unit, 401 is a gate dielectric layer, 402 is a gate electrode, 403 is an interlayer dielectric layer, 500 is an emitter, 600 is a metal layer, 700 is an N-type substrate, and 800 is a bump structure. DETAILED DESCRIPTION

[0036] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that the description is merely exemplary and is not intended to limit the scope of the present disclosure. Also, in the following description, the description of well-known structures and techniques have been omitted to avoid obscuring the concept of the present disclosure.

[0037] In the drawings, various structural diagrams according to embodiments of the present disclosure are illustrated. These diagrams are not drawn to scale in which certain details are exaggerated for clarity of presentation and can omit certain details. The shapes of various regions, layers, and the relative sizes and positional relationships between them shown in the drawings are merely exemplary, and in actuality, they can be deviated due to manufacturing process or technical limitations, and a person skilled in the art can additionally design regions / layers having different shapes, sizes, and relative positions according to actual needs.

[0038] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element can be directly on the other layer / element, or an intervening layer / element can be present therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, it can be "under" the other layer / element when the orientation is reversed.

[0039] Since the existing trench gate IGBT cannot reduce the on-state voltage drop without degradation of the breakdown voltage and the gate oxide electric field, the present disclosure provides an improved asymmetric trench gate IGBT device.

[0040] Figure 1 A structural diagram of the asymmetric trench gate IGBT device of the present disclosure is given. Specifically, as shown in FIG. 1, the asymmetric trench gate IGBT device of the present disclosure includes a collector 100, a P-type collector layer 200, an N-type drift layer 300, an initial P-well region 301, a first P-well region 301a, a second P-well region 301b, a P-type heavily doped contact region 302, an N-type heavily doped source region 303, an initial N-type current spreading region 304, an N-type current spreading region 304a, a step structure 305, a first side surface 305a, a first upper surface 305b, a second side surface 305c, a second upper surface 305d, a trench 306, a trench gate unit 400, a gate dielectric layer 401, a gate electrode 402, an interlayer dielectric layer 403, an emitter 500, a metal layer 600, an N-type substrate 700, and a bump structure 800. Figure 1As shown, the asymmetric trench gate IGBT device of the present application comprises: a collector 100; a P-type collector layer 200 disposed on the upper surface of the collector 100; a N-type drift layer 300 disposed on the upper surface of the P-type collector layer 200, the upper surface of the N-type drift layer 300 is provided with a first P-well region 301a and a second P-well region 301b separated from each other, the upper surface of the second P-well region 301b is provided with a P-type heavily doped contact region 302 and a N-type heavily doped source region 303, the P-type heavily doped contact region 302 and the N-type heavily doped source region 303 are in contact with each other; a trench gate unit 400, the trench gate unit 400 comprises: a gate 402; a gate dielectric layer 401 covering the sidewall and the lower surface of the gate 402; and an interlayer dielectric layer 403 covering the upper surface of the gate 402; the trench gate unit 400 is disposed between and in contact with the first P-well region 301a and the second P-well region 302b, and the trench gate unit 400 is in contact with the N-type heavily doped source region 303; an emitter 500, the emitter 500 covers the upper surface of the P-type heavily doped contact region 302 and the N-type heavily doped source region 303, and covers part of the upper surface of the interlayer dielectric layer 304; and a metal layer 600, the metal layer 600 covers the upper surface of the first P-well region 301a, and covers part of the upper surface of the interlayer dielectric layer 304, wherein the metal layer 600 forms a Schottky contact with the first P-well region 301a.

[0041] The asymmetric trench gate IGBT device of the present application forms a certain potential barrier by making a Schottky contact above the non-conductive side P-well region (i.e. the first P-well region 301a), thereby preventing holes from escaping directly from the P-well region grounded, improving the hole concentration, thereby significantly reducing the forward on-state voltage drop of the device, reducing the on-state loss, and significantly enhancing the conduction capability of the device, while the breakdown voltage does not degrade with the gate oxide field.

[0042] Preferably, the collector 100 is a metal material, such as a metal or a metal alloy. Preferably, the thickness of the collector 100 can be 1-2 μm. In an embodiment of the present application, the collector 100 is a titanium-aluminum alloy. Of course, according to actual needs, the collector 100 can be any desired metal capable of forming an ohmic contact with the P-type collector layer 200.

[0043] Preferably, the P-type collector layer 200 is a P-type heavily doped layer, and the doping ions are preferably Al ions. Preferably, the P-type collector layer 200 is a P-type heavily doped SiC layer, which is preferably formed by epitaxy through chemical vapor deposition. Preferably, the doping concentration of the P-type collector layer 200 can be 1 x 1018-5 x 1019cm-3, preferably 1 x 1019-2 x 1019cm-3. 19 -5 x 1019cm-3, preferably 1 x 1019-2 x 1019cm-3. 19 cm -3 , preferably 1 x 1019-2 x 1019cm-3. 19 -5 x 1019cm-3, preferably 1 x 1019-2 x 1019cm-3. 19 cm -3; the thickness can be 0.3-5 μm, preferably 0.5-0.1 μm.

[0044] Preferably, the N-type drift layer 300 is an N-type lightly doped layer, and the doping ions are preferably N ions. Preferably, the N-type drift layer 300 is an N-type lightly doped SiC layer, which is preferably formed by epitaxy by chemical vapor deposition. Preferably, the doping concentration of the N-type drift layer 300 can be 2 x 1014- 1 x 1016cm"3, preferably 8 x 1014- 1 x 1015cm"3. The doping concentration of the N-type drift layer 300 can be determined by the voltage withstanding level. 14 -1 x 1016cm"3 15 cm"3 -3 , for example 8 x 1014- 1 x 1015cm"3 14 -1 x 1016cm"3 15 cm"3 -3 . The doping concentration of the N-type drift layer 300 can be determined by the voltage withstanding level.

[0045] Preferably, the N-type drift layer 300 is provided with an N-type current spreading region 304a, which is arranged at the lower surface of the first P-well region 301a and the second P-well region 301b. The doping concentration of the N-type current spreading region 304a can be 6 x 1014- 1.7 x 1016cm"3, preferably 8 x 1014- 1.5 x 1016cm"3. By making an N-type region with high doping concentration on the surface of the drift region, the N-type current spreading region lowers the resistance of the drift region when electrons flow from the channel into the drift region; and hinders the escape of holes from the drift region through the P-well when holes escape from the drift region through the P-well, thus enhancing the effect of conductance modulation, and therefore the current capacity of the device can be greatly improved. 15 -1.7 x 1016cm"3 16 cm"3 -3 , preferably 8 x 1014- 1.5 x 1016cm"3 15 -1.7 x 1016cm"3 16 cm"3 -3 . By making an N-type region with high doping concentration on the surface of the drift region, the N-type current spreading region lowers the resistance of the drift region when electrons flow from the channel into the drift region; and hinders the escape of holes from the drift region through the P-well when holes escape from the drift region through the P-well, thus enhancing the effect of conductance modulation, and therefore the current capacity of the device can be greatly improved.

[0046] Preferably, the upper surface of the N-type current spreading region 304a is provided with a stepped structure 305, which comprises a first side surface 305a, a first upper surface 305b, a second side surface 305c and a second upper surface 305d, the trench gate unit 400 covers the first upper surface 305b and the second side surface 305c, and the second upper surface 305d is in contact with the second P-well region 301b. Preferably, the first side surface 305a is arranged at a position below the center of the trench gate unit 400. If the first side surface 305a is close to the right sidewall of the trench gate unit 400, the JFET region below the channel will hinder the passage of electrons, resulting in poor on-state performance of the device; if the first side surface 305a is close to the left sidewall of the trench gate unit 400, the gate dielectric layer 401 cannot be sufficiently protected. Preferably, when the first side surface 305a is arranged at a position below the center of the trench gate unit 400, the maximum width of the stepped structure 305 is less than or equal to 1.6 μm, and preferably 1.4-1.6 μm. By controlling the spacing between the well regions, the electric field lines are cut off by the depletion region, and the bottom corner of the trench is sufficiently protected. The narrower the spacing, the better the protection effect, but the greater the hindrance to electrons relative to the JFET region. The position in the center has less impact on the passage of electrons flowing down the channel than the complete wrapping of the trench, and the conduction effect is better.

[0047] In this document, the "maximum width" refers to the width value at the widest point, and conversely, the "minimum width" refers to the width value at the narrowest point. The "maximum depth" refers to the depth value at the deepest point, and conversely, the "minimum depth" refers to the depth value at the shallowest point.

[0048] Preferably, the first P-well region 301a and the second P-well region 301b have the same doping concentration, which can be 1×10 17 -5×10 17 cm -3 , and preferably 4×10 17 -5×10 17 cm -3 ; and the doping ions are preferably Al ions.

[0049] Preferably, the first P-well region 301a has a maximum depth of 3-5 μm and a maximum width of 2-5 μm. Such arrangement can completely wrap the bottom corner of one side of the trench, achieving sufficient protection.

[0050] Preferably, the first P-well region 301a and the second P-well region 301b have the same maximum depth.

[0051] Preferably, the P-type heavily doped contact region 302 has Al ions as the doping ions, and the doping concentration can be 1×10 19 -2×10 20 cm -3, for example, 1 x 1018 20 cm -3 The width of the P-type heavily doped contact region 302 can be 0.5-1 μm, for example, 1 μm; and the depth can be 0.2-0.5 μm, for example, 0.5 μm.

[0052] Preferably, the doping ions of the N-type heavily doped source region 303 are N ions, and the doping concentration can be 5 x 1018 19 - 1 x 1019 20 cm -3 , for example, 1 x 1018 20 cm -3 The width of the N-type heavily doped source region 303 can be 2-3 μm, for example, 2.5 μm; and the depth can be 0.2-0.5 μm, for example, 0.5 μm.

[0053] Preferably, the gate dielectric layer 401 is silicon oxide. Preferably, the thickness of the gate dielectric layer 401 is 50-60 nm. If the thickness of the gate dielectric layer 401 is too thin, it is easy to be broken down; if the thickness of the gate dielectric layer 401 is too thick, it will result in a large threshold voltage of the device. The first P-well region 301a and the second P-well region 301b located on both sides of the trench gate unit can protect the electric field intensity of the gate dielectric layer 401 to be below 3 MV / cm.

[0054] Preferably, the gate electrode 402 is polysilicon.

[0055] Preferably, the interlayer dielectric layer 403 is silicon oxide. Preferably, the upper surface of the interlayer dielectric layer 403 is higher than the upper surfaces of the first P-well region 301a and the second P-well region 301b. Preferably, the lower surface of the interlayer dielectric layer 403 is flush with or lower than the lower surfaces of the first P-well region 301a and the second P-well region 301b, as shown in Fig. 4. Figure 1

[0056] Preferably, the emitter 500 is a metallic material, for example, a metal or a metal alloy. Preferably, the thickness of the emitter 500 can be 4-6 μm. In one embodiment of the present application, the emitter 500 is a nickel-titanium-aluminum alloy. Of course, the emitter 500 can be any desired metal that can form an ohmic contact with the N-type heavily doped source region 303 according to actual needs.

[0057] ​Preferably, the thickness of the metal layer 600 can be 4-6 μm. In one embodiment of the present application, the metal layer 600 is nickel. Of course, the metal layer 600 can be any desired metal capable of forming a Schottky contact with the first P-well region 301a, according to actual needs. Preferably, the barrier height of the Schottky contact is 1.4-1.8 eV. The higher the barrier height, the smaller the forward conduction voltage drop, the smaller the total loss, but the higher the off-state loss. The barrier height is determined by the difference between the work function of the metal and the electron affinity of the semiconductor, and the electron affinity of silicon carbide material is 3.7 eV, while the work function of the metal is generally less than 5.65 eV, and the work function of nickel is 5.15 eV. Therefore, by setting the barrier height to 1.4-1.8 eV, a compromise between the forward conduction voltage drop and the off-state loss can be achieved.

[0058] The present application also provides a method for manufacturing an asymmetric trench gate IGBT device, comprising the following steps.

[0059] First, a P-type collector layer is formed on the upper surface of an N-type substrate.

[0060] Preferably, the N-type substrate is an N-type 4H-SiC substrate, and the doping concentration thereof can be 5 x 1015-1 x 1018cm-3. 16 17 cm -3 .

[0061] Preferably, the P-type collector layer can be formed by chemical vapor deposition (CVD). In some specific embodiments, the P-type collector layer is epitaxially formed on the C face of the N-type 4H-SiC substrate by CVD.

[0062] Then, an N-type drift layer is formed on the upper surface of the P-type collector layer.

[0063] Preferably, the N-type drift layer can be formed by chemical vapor deposition (CVD). The thickness of the N-type drift layer can be 90-100 μm, preferably 93-96 μm.

[0064] Subsequently, an initial P-well region is formed on the surface layer of the upper surface of the N-type drift layer by ion implantation.

[0065] Preferably, the initial P-well region can be formed by multiple ion implantations, and the shape of the initial P-well region can be controlled by adjusting the ion implantation conditions, including the dosage and the range. The maximum depth of the initial P-well region is 3-5 μm.

[0066] ​Preferably, after forming the N-type drift layer, an initial N-type current spreading region is formed on the surface layer of the upper surface of the N-type drift layer by ion implantation, and then the initial P-well region is formed on the middle-upper part of the initial N-type current spreading region by ion implantation, and the remaining part of the initial N-type current spreading region is formed into an N-type current spreading region. The thickness of the initial N-type current spreading region can be 4-6 μm, preferably 4.5-5.5 μm. In some embodiments, the initial P-well region is formed by multiple ion implantations, and the shape of the initial P-well region is controlled by adjusting the ion implantation conditions, so that the upper surface of the N-type current spreading region has a mesa structure.

[0067] In the present application, the masks used for ion implantation are all silicon dioxide.

[0068] Next, an N-type heavily doped source region and a P-type heavily doped contact region are formed on the shallow surface layer of the upper surface of the initial P-well region and are in contact with each other.

[0069] Preferably, the formation methods of the N-type heavily doped source region and the P-type heavily doped contact region are both ion implantation.

[0070] Then, the initial P-well region is etched to form a trench, which divides the initial P-well region into a first P-well region and a second P-well region, and the sidewall of the N-type heavily doped source region is part of the sidewall of the trench. The height of the trench is 2-4 μm, preferably 2.5-3.5 μm. In some embodiments, the upper surface of the N-type current spreading region has a mesa structure, and the initial P-well region and the mesa structure are etched to form a trench, and the remaining part of the mesa structure is formed into a stepped structure, which includes a first side surface, a first upper surface, a second side surface and a second upper surface, wherein the first side surface is located at the central position below the trench.

[0071] Preferably, the etching is reactive ion etching.

[0072] After that, a gate dielectric layer is formed on the sidewall of the trench, the trench is filled to form a gate, and an interlayer dielectric layer is formed on the upper surface of the gate, thereby obtaining a trench gate unit.

[0073] Preferably, the gate dielectric layer can be formed by thermal oxidation method.

[0074] Preferably, the gate is polysilicon, and polysilicon can be deposited on the gate dielectric layer by chemical vapor deposition method (such as low pressure chemical vapor deposition method) to fill the trench, thereby forming a gate.

[0075] In some embodiments, the interlayer dielectric layer (i.e. silicon oxide) can be formed by oxidizing the gate (i.e. polysilicon), and the lower surface of the resulting interlayer dielectric layer is lower than the lower surfaces of the first and second P-well regions. In other embodiments, the interlayer dielectric layer (i.e. silicon oxide) can be formed by direct deposition on the upper surface of the gate by chemical vapor deposition, and the lower surface of the resulting interlayer dielectric layer is flush with the lower surfaces of the first and second P-well regions.

[0076] Next, an emitter is formed to cover the upper surfaces of the N-type heavily doped source region and the P-type heavily doped contact region, and to cover part of the upper surface of the interlayer dielectric layer.

[0077] Preferably, after the emitter is formed, annealing is performed, for example, high-temperature annealing, and the annealing temperature can be 1600-1700 °C.

[0078] In the present application, the emitter can be made by evaporation, sputtering, etc. The present application does not limit the method of forming the emitter, and any method conventionally used in the art can be used to form the emitter of the present application.

[0079] Then, a metal layer is formed to cover the upper surface of the first P-well region, and to cover part of the upper surface of the interlayer dielectric layer, and after annealing, the metal layer forms a Schottky contact with the first P-well region.

[0080] Preferably, the annealing is high-temperature annealing, and the annealing temperature can be 1600-1700 °C.

[0081] In the present application, the metal layer can be made by evaporation, sputtering, etc. The present application does not limit the method of forming the metal layer, and any method conventionally used in the art can be used to form the metal layer of the present application.

[0082] Finally, after the N-type substrate is removed, a collector is formed on the lower surface of the P-type collector layer, and then laser annealing is performed.

[0083] Preferably, the N-type substrate can be removed by grinding.

[0084] The present application does not limit the specific parameters of laser annealing, which can be selected according to actual needs. The temperature of laser annealing is generally greater than 800 °C. High-temperature annealing is selected because it can make the back surface of the device reach a high temperature of more than 800 °C in a very short time, while the front surface of the device is less than 100 °C, thereby avoiding damage to the already completed contact on the front surface when making the back surface ohmic contact.

[0085] In the present application, the collector can be made by evaporation, sputtering, etc. The present application does not limit the method of forming the collector, and any method conventionally used in the art can be used to form the collector of the present application.

[0086] The present invention will be further described below with reference to specific embodiments and accompanying drawings.

[0087] Example 1

[0088] First, at a doping concentration of 1×10 17 cm -3 A P-type collector layer 200 was epitaxially grown on the C-plane of an N-type 4H-SiC substrate 700 using CVD; the doping concentration of the P-type collector layer 200 was 1×10⁻⁶. 19 cm -3 The thickness is 0.5μm.

[0089] Then, an N-type drift layer 300 is epitaxially grown on the upper surface of the P-type current collector layer 200 using CVD; the doping concentration of the N-type drift layer 300 is 1×10⁻⁶. 15 cm -3 The thickness is 94.5 μm, and the resulting structure is as follows: Figure 2 As shown.

[0090] Subsequently, N ions were implanted into the surface of the N-type drift layer 300 to form the initial N-type current extension region 304, with a doping concentration of 1.5 × 10⁻⁶. 16 cm -3 The depth is 5μm, and the resulting structure is as follows: Figure 3 As shown.

[0091] Next, Al ions are implanted into the upper middle part of the initial N-type current extension region 304 to form the initial P-well region 301, with a doping concentration of 4 × 10⁻⁶. 17 cm -3 The maximum depth is 4 μm. The remaining portion of the initial N-type current extension region 304 is formed as N-type current extension region 304a. During ion implantation, the shape of the initial P-well region 301 is controlled by adjusting the ion implantation conditions (including dose and range), so that the upper surface of the N-type current extension region 304a has a boss structure 800, the width of which is 1.6 μm and the height of which is 2 μm. The resulting structure is as follows. Figure 4 As shown.

[0092] Then, by implanting Al ions into the shallow layer of the upper surface of the initial P-well region 301, a heavily doped P-type contact region 302 is formed with a doping concentration of 1×10⁻⁶. 20 cm -3 The p-type heavily doped contact region 302 has a width of 1 μm and a depth of 0.5 μm, and the resulting structure is as follows: Figure 5 As shown. Subsequently, by implanting N ions into the shallow layer of the upper surface of the initial P-well region 301, an N-type heavily doped source region 303 is formed with a doping concentration of 1 × 10⁻⁶. 20 cm -3; the width of the N-type heavily doped source region 303 is 2.5 μm, and the depth is 0.5 μm, wherein the P-type heavily doped contact region 302 and the N-type heavily doped source region 303 are in contact with each other, and the resulting structure is as shown in Fig. 3. Figure 6

[0093] After that, the initial P-well region 301 and the mesa structure 800 are etched by reactive ion etching to form a trench 306 with a depth of 3 μm and a width of 1 μm, which divides the initial P-well region 301 into a first P-well region 301a and a second P-well region 301b, and the sidewall of the N-type heavily doped source region 303 is part of the sidewall of the trench 306. The remaining mesa structure 800 is partially formed into a stepped structure 305, which includes a first side surface 305a, a first upper surface 305b, a second side surface 305c, and a second upper surface 305d. Among them, the first side surface 305a is located at the central position below the trench 306. The resulting structure is as shown in Fig. 4. Figure 7

[0094] Next, a 50 nm thick gate dielectric layer 401 is formed on the sidewall of the trench 306 by thermal oxidation method, and the resulting structure is as shown in Fig. 5. Then, polycrystalline silicon is deposited on the gate dielectric layer 401 by low-pressure chemical vapor deposition method to fill the trench 306, thereby forming a gate electrode 402, and the resulting structure is as shown in Fig. 6. After that, an interlayer dielectric layer 403 is formed by oxidizing the polycrystalline silicon, thereby obtaining a trench gate unit 400, and the resulting structure is as shown in Fig. 7. Figure 8 Figure 9 Figure 10

[0095] Then, an emitter 500 with a thickness of 5 μm is formed by sputtering, which covers the upper surfaces of the N-type heavily doped source region 303 and the P-type heavily doped contact region 302, and covers part of the upper surface of the interlayer dielectric layer 403, wherein the emitter 500 is a nickel-titanium-aluminum alloy. After high-temperature annealing, an ohmic contact is formed. The resulting structure is as shown in Fig. 8. Figure 11

[0096] After that, a metal layer 600 with a thickness of 5 μm is formed by sputtering, which covers the upper surface of the first P-well region 301a and covers part of the upper surface of the interlayer dielectric layer 403, wherein the metal layer 600 is nickel. After high-temperature annealing, the metal layer 600 forms a Schottky contact with the first P-well region 301a, and the barrier height of the Schottky contact is 1.4 eV. The resulting structure is as shown in Fig. 9. Figure 12

[0097] Next, the N-type 4H-SiC substrate 700 is ground away, and the resulting structure is as shown in Fig. 10. Figure 13 ​​​​​​​As shown in the figure. Then, a collector electrode 100 with a thickness of 1.5 μm is formed on the lower surface of the P-type collector layer 200 by sputtering, wherein the collector electrode 100 is made of titanium-aluminum alloy. Finally, laser annealing is performed. The structural schematic diagram of the resulting asymmetric trench gate IGBT device is shown in the figure. Figure 1 As shown.

[0098] Comparative Example 1

[0099] An asymmetric trench gate IGBT device was fabricated according to the method of Example 1, except that the metal layer 600 was made of nickel-titanium-aluminum alloy. After high-temperature annealing, the metal layer 600 formed an ohmic contact with the first P-well region 301a. A schematic diagram of the asymmetric trench gate IGBT device fabricated in Comparative Example 1 is shown below. Figure 14 As shown.

[0100] Under the same electrode bias conditions, the longitudinal distribution of hole concentration in the asymmetric trench gate IGBT devices of Example 1 and Comparative Example 1 was simulated using Sentaurus simulation software. The simulation results are as follows: Figure 15 As shown. From Figure 15 As can be seen, the asymmetric trench gate IGBT device of Example 1 has a Schottky barrier, and the hole concentration in its drift region is greater than that in the drift region of Comparative Example 1, which enhances the conductivity modulation effect of the device.

[0101] The forward conduction characteristics of the asymmetric trench gate IGBT devices of Example 1 and Comparative Example 1 were simulated using Sentaurus simulation software. The simulation curves are shown below. Figure 16 As shown, under the same current standard, the forward voltage drop of the asymmetric trench gate IGBT device with Schottky barrier in Example 1 is smaller than that of the asymmetric trench gate IGBT device without Schottky barrier in Comparative Example 1, which reduces the conduction loss of the device and significantly enhances the conductivity of the device.

[0102] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An asymmetric trench gate IGBT device, characterized by, Comprise: a collector electrode; a P-type collector layer disposed on an upper surface of the collector electrode; an N-type drift layer disposed on an upper surface of the P-type collector layer, a surface layer of an upper surface of the N-type drift layer being provided with a first P-well region and a second P-well region separated from each other, a surface layer of an upper surface of the second P-well region being provided with a P-type heavily doped contact region and an N-type heavily doped source region, the P-type heavily doped contact region and the N-type heavily doped source region being in contact with each other; a trench gate cell comprising a gate electrode, a gate dielectric layer covering a sidewall and a lower surface of the gate electrode, and an interlayer dielectric layer covering an upper surface of the gate electrode, the trench gate cell being disposed between and in contact with the first P-well region and the second P-well region, the trench gate cell being in contact with the N-type heavily doped source region; an emitter covering an upper surface of the P-type heavily doped contact region and the N-type heavily doped source region, and covering a part of an upper surface of the interlayer dielectric layer; and a metal layer covering an upper surface of the first P-well region, and covering a part of an upper surface of the interlayer dielectric layer, wherein the metal layer forms a Schottky contact with the first P-well region; the N-type drift layer is provided with an N-type current spreading region disposed on a lower surface of the first P-well region and the second P-well region; an upper surface of the N-type current spreading region is provided with a stepped structure comprising a first side, a first upper surface, a second side, and a second upper surface, the trench gate cell covering the first upper surface and the second side, the second upper surface being in contact with the second P-well region, the first side being disposed at a central position below the trench gate cell, a maximum width of the stepped structure being less than or equal to 1.6 μm.

2. The asymmetric trench gate IGBT device of claim 1, wherein, a barrier height of the Schottky contact is 1.4-1.8 eV.

3. The asymmetric trench gate IGBT device of claim 1, wherein, a maximum width of the stepped structure is 1.4-1.6 μm.

4. The asymmetric trench gate IGBT device according to claim 1 or 2, characterized by, a maximum depth of the first P-well region is 3-5 μm, and a maximum width is 2-5 μm.

5. The asymmetric trench gate IGBT device according to claim 1 or 2, characterized by, a thickness of the gate dielectric layer is 50-60 nm.

6. The asymmetric trench gate IGBT device according to claim 1 or 2, comprising: The P-type collector layer has a doping concentration of 1 x 10 19 -5 x 10 19 cm -3 -3 The N-type drift layer has a doping concentration of 2 x 1015cm-3 14 -1 x 1016cm-3 15 cm -3 -3 The N-type current spreading region has a doping concentration of 6 x 1018cm-3 15 -1.7 x 1018cm-3 16 cm -3 .

7. The method of producing an asymmetric trench gate IGBT device according to claim 1 or 2, characterized by, forming a P-type collector layer on an upper surface of an N-type substrate; forming an N-type drift layer on an upper surface of the P-type collector layer; forming an initial P-well region on a surface layer of an upper surface of the N-type drift layer by ion implantation; forming an N-type heavily doped source region and a P-type heavily doped contact region in contact with each other on a surface layer of an upper surface of the initial P-well region; etching the initial P-well region to form a trench, the trench dividing the initial P-well region into a first P-well region and a second P-well region, and a sidewall of the N-type heavily doped source region being part of a sidewall of the trench; forming a gate dielectric layer on a sidewall of the trench, refilling the trench to form a gate electrode, and forming an interlayer dielectric layer on an upper surface of the gate electrode, thereby obtaining a trench gate cell; forming an emitter covering an upper surface of the N-type heavily doped source region and the P-type heavily doped contact region, and covering a part of an upper surface of the interlayer dielectric layer; and forming a metal layer covering an upper surface of the first P-well region, and covering a part of an upper surface of the interlayer dielectric layer, wherein the metal layer forms a Schottky contact with the first P-well region. forming a metal layer to cover the upper surface of the first P-well region and to cover part of the upper surface of the interlayer dielectric layer, after annealing, the metal layer forms Schottky contact with the first P-well region; and after removing the N-type substrate, a collector is formed on the lower surface of the P-type collector layer, and then laser annealing is performed again.

8. The preparation method according to claim 7, characterized in that, After forming the N-type drift layer, an initial N-type current spreading region is formed on the surface layer of the upper surface of the N-type drift layer by ion implantation, and then the initial P-well region is formed on the middle upper part of the initial N-type current spreading region by ion implantation, and the remaining part of the initial N-type current spreading region is formed as an N-type current spreading region.

9. The preparation method according to claim 8, characterized in that, The shape of the initial P-well region is controlled by adjusting the ion implantation conditions, so that the upper surface of the N-type current spreading region has a boss structure; etching the initial P-well region and the boss structure to form a trench, and the remaining boss structure part is formed as a stepped structure, which includes a first side surface, a first upper surface, a second side surface and a second upper surface, wherein the first side surface is located at the middle position below the trench.

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