Thin film transistor, preparation method thereof, and display panel

Abstract

An embodiment of the present application provides a thin film transistor, a preparation method thereof, and a display panel. The thin film transistor includes a gate insulating layer, an active structure, a doping structure, and a source-drain structure which are stacked. The active structure includes a source-drain region and a channel region, and the doping structure covers the source-drain region. By covering the source-drain region of the active structure with the doping structure, the present application can effectively avoid the water ripple defect, is beneficial to improving the brightness uniformity of the display panel, and is beneficial to improving the yield and quality of the display panel. Moreover, using this thin film transistor can improve the quality of large-size high-end display products, and there is no need to add an additional mask plate, which can be directly completed on the basis of the existing production line, reducing the production cost and having wide popularization value.

Description

Technical Field

[0001] The present application relates to the field of display technologies. Specifically, the present application relates to a thin-film transistor, a method for manufacturing the same, and a display panel. Background Art

[0002] Currently, display panel manufacturers improve the production capacity of display panels and reduce the manufacturing cost of display panels by reducing the number of photolithography processes. That is, a semi-transmissive mask plate is used for four photolithography processes to manufacture thin-film transistors in a display panel. The diffraction of ultraviolet light by the semi-transmissive film or graphic slit on the mask plate is used to reduce the local ultraviolet light transmittance, so that the source-drain pattern and the silicon island pattern are formed through one photolithography process.

[0003] However, for thin-film transistors manufactured by using four photolithography processes, water ripple defects are likely to occur, affecting the display brightness of the display panel. Summary of the Invention

[0004] In view of the shortcomings of the existing methods, the present application provides a thin-film transistor, a method for manufacturing the same, and a display panel, so as to solve the technical problem of water ripple defects caused by existing thin-film transistors.

[0005] In a first aspect, an embodiment of the present application provides a thin-film transistor, including a gate insulating layer, an active structure, a doping structure, and a source-drain structure that are stacked. The active structure includes a source-drain region and a channel region, and the doping structure covers the source-drain region.

[0006] In a second aspect, an embodiment of the present application provides a display panel, including the thin-film transistor of the first aspect.

[0007] In a third aspect, an embodiment of the present application provides a method for manufacturing the thin-film transistor of the first aspect, including:

[0008] An initial active layer, an initial doping layer, and an initial source-drain layer are sequentially formed on one side of the gate insulating layer. The initial active layer and the initial doping layer form an initial non-metal layer. A first photoresist structure is formed on a side of the initial source-drain layer away from the gate insulating layer;

[0009] Based on the first photoresist structure, the initial source-drain layer and the initial non-metal layer are wet-etched to form an intermediate source-drain structure and an intermediate non-metal structure, such that the intermediate source-drain structure just covers a side of the intermediate non-metal structure close to the intermediate source-drain structure;

[0010] The first photoresist structure is patterned to form a second photoresist structure;

[0011] Based on the second photoresist structure, etch the intermediate source-drain structure and the intermediate non-metal structure to form a stacked active structure, doping structure, and source-drain structure, such that the doping structure covers the source-drain region, and the active structure includes the source-drain region and the channel region;

[0012] Strip the second photoresist structure.

[0013] Optionally, based on the first photoresist structure, wet-etch the initial source-drain layer and the initial non-metal layer to form an intermediate source-drain structure and an intermediate non-metal structure, such that the intermediate source-drain structure just covers one side of the intermediate non-metal structure close to the intermediate source-drain structure, including:

[0014] Using the first photoresist structure as a mask, etch the initial source-drain layer with a first etchant to obtain a preliminary intermediate source-drain structure;

[0015] Etch the preliminary intermediate source-drain structure and the initial non-metal layer with the first etchant to obtain the intermediate source-drain structure and the intermediate non-metal structure, and the orthographic projection of the side of the intermediate non-metal structure close to the intermediate source-drain structure on the gate insulating layer coincides with the orthographic projection of the intermediate source-drain structure on the gate insulating layer.

[0016] Optionally, etch the preliminary intermediate source-drain structure and the initial non-metal layer with the first etchant to obtain the intermediate source-drain structure and the intermediate non-metal structure, and the orthographic projection of the side of the intermediate non-metal structure close to the intermediate source-drain structure on the gate insulating layer coincides with the orthographic projection of the intermediate source-drain structure on the gate insulating layer, including:

[0017] Etch the preliminary intermediate source-drain structure, the initial doping layer, and the initial active layer with the first etchant to obtain the intermediate source-drain structure, intermediate doping structure, and intermediate active structure, such that the intermediate doping structure covers the intermediate active structure.

[0018] Optionally, prepare a first photoresist structure on the side of the initial source-drain layer away from the gate insulating layer, including: prepare a third photoresist structure on the side of the initial source-drain layer away from the gate insulating layer, and the size of the third photoresist structure in a first direction is greater than the size of the first photoresist, and the first direction is parallel to the gate insulating layer;

[0019] And, based on the first photoresist structure, wet etching is performed on the initial source-drain layer and the initial non-metal layer to form an intermediate source-drain structure and an intermediate non-metal structure, such that the intermediate source-drain structure just covers one side of the intermediate non-metal structure close to the intermediate source-drain structure, including:

[0020] Using the third photoresist structure as a mask, etching the initial source-drain layer with a first etching solution to obtain a preliminary intermediate source-drain structure;

[0021] Etching the preliminary intermediate source-drain structure and the initial non-metal layer with the first etching solution to obtain the intermediate source-drain structure and the intermediate non-metal structure.

[0022] Optionally, the first etching solution includes fluoride ions.

[0023] Optionally, based on the first photoresist structure, wet etching is performed on the initial source-drain layer and the initial non-metal layer to form an intermediate source-drain structure and an intermediate non-metal structure, such that the intermediate source-drain structure just covers one side of the intermediate non-metal structure close to the intermediate source-drain structure, including:

[0024] Using the first photoresist structure as a mask, etching the initial source-drain layer with a first etching solution to form the intermediate source-drain structure;

[0025] Using the intermediate source-drain structure as a mask, etching the initial non-metal layer with a second etching solution to form the intermediate non-metal structure.

[0026] Optionally, the preparation method includes at least one of the following:

[0027] The mass percentage concentration of fluoride ions in the first etching solution is not less than 0.3% and not more than 1%; the mass percentage concentration of fluoride ions in the second etching solution is not less than 1% and not more than 2%;

[0028] The mass percentage concentration of hydrogen peroxide in the first etching solution is not less than 15% and not more than 25%, and the mass percentage concentration of hydrogen peroxide in the second etching solution is not less than 3% and not more than 10%.

[0029] Optionally, patterning the first photoresist structure to form a second photoresist structure, including:

[0030] Performing ashing treatment on the first photoresist structure to expose the intermediate source-drain structure above the channel region, thereby forming the second photoresist structure.

[0031] The beneficial technical effects brought by the technical solution provided by the embodiments of the present application include:

[0032] By covering the source and drain regions of the active structure with a doped structure, since the doped structure is insensitive to light and the doped structure itself is a conductor, when the PWM (Pulse Width Modulation) backlight is turned on, the overlapping capacitance between the source-drain structure and the gate (not shown) of the thin-film transistor will not change, which can effectively avoid the problem of water ripples, is beneficial to improving the brightness uniformity of the display panel, and is beneficial to improving the yield and quality of the display panel.

[0033] In addition, using this thin-film transistor can improve the quality of large-size high-end display products, and there is no need to add an additional mask plate. It can be directly completed on the basis of the existing production line, reducing production costs and having wide popularization value.

[0034] The additional aspects and advantages of this application will be partially given in the following description, which will become obvious from the following description, or will be understood through the practice of this application. Description of the Drawings

[0035] The above-mentioned and / or additional aspects and advantages of this application will become obvious and easy to understand from the following description of the embodiments in conjunction with the drawings, where:

[0036] Figure 1 It is a schematic diagram of the film layer structure of a thin-film transistor provided by the prior art;

[0037] Figure 2 It is a schematic diagram of the film layer structure of an intermediate source-drain structure formed after wet etching of the initial source-drain layer in a method for manufacturing a thin-film transistor provided by the prior art;

[0038] Figure 3 It is a schematic diagram of the film layer structure of an intermediate doped structure and an intermediate active structure formed after dry etching of the initial doped layer and the initial active layer in a method for manufacturing a thin-film transistor provided by the prior art;

[0039] Figure 4 It is a schematic diagram of the film layer structure of a second photoresist structure formed after ashing the first photoresist structure in a method for manufacturing a thin-film transistor provided by the prior art;

[0040] Figure 5 It is a schematic diagram of the film layer structure of a source-drain structure formed after wet etching of the intermediate source-drain structure in a method for manufacturing a thin-film transistor provided by the prior art;

[0041] Figure 6 It is a schematic diagram of the film layer structure of a doped structure and an active structure formed after dry etching of the intermediate doped structure and the intermediate active structure in a method for manufacturing a thin-film transistor provided by the prior art;

[0042] Figure 7 Schematic diagram of a thin film transistor film layer structure provided by an embodiment of the present application;

[0043] Figure 8 Schematic flow chart of a preparation method of a thin film transistor provided by an embodiment of the present application;

[0044] Figure 9 Schematic diagram of a film layer structure after preparing a first photoresist structure on a side of an initial source-drain layer away from a gate insulating layer in a preparation method of a thin film transistor film layer provided by an embodiment of the present application;

[0045] Figure 10 Schematic diagram of a film layer structure after etching an initial source-drain layer with a first etching solution by using the first photoresist structure as a mask to obtain a preliminary intermediate source-drain structure in a preparation method of a thin film transistor film layer provided by an embodiment of the present application;

[0046] Figure 11 Schematic diagram of a film layer structure after etching a preliminary intermediate source-drain structure and an initial non-metal layer with a first etching solution to obtain an intermediate source-drain structure and an intermediate non-metal structure in a preparation method of a thin film transistor film layer provided by an embodiment of the present application;

[0047] Figure 12 Schematic diagram of a film layer structure after preparing a third photoresist structure on a side of an initial source-drain layer away from a gate insulating layer in a preparation method of a thin film transistor film layer provided by an embodiment of the present application;

[0048] Figure 13 Schematic diagram of a film layer structure after etching an initial source-drain layer with a first etching solution by using the third photoresist structure as a mask to obtain a preliminary intermediate source-drain structure in a preparation method of a thin film transistor film layer provided by an embodiment of the present application;

[0049] Figure 14 Schematic diagram of a film layer structure after etching a preliminary intermediate source-drain structure and an initial non-metal layer with a first etching solution to obtain an intermediate source-drain structure and an intermediate non-metal structure in a preparation method of a thin film transistor film layer provided by an embodiment of the present application;

[0050] Figure 15 Schematic diagram of a film layer structure after etching an initial source-drain layer with a first etching solution by using the first photoresist structure as a mask to form an intermediate source-drain structure in a preparation method of a thin film transistor film layer provided by an embodiment of the present application;

[0051] Figure 16Schematic diagram of a film layer structure of a method for preparing a thin film transistor film layer provided in an embodiment of the present application, in which an intermediate source-drain structure is used as a mask, and an initial non-metal layer is etched with a second etching solution to form an intermediate non-metal structure film layer structure;

[0052] Figure 17 Schematic diagram of a film layer structure of a method for preparing a thin film transistor film layer provided in an embodiment of the present application, in which a first photoresist structure is patterned to form a second photoresist structure film layer structure;

[0053] Figure 18 Schematic diagram of a film layer structure of a method for preparing a thin film transistor film layer provided in an embodiment of the present application, in which, based on the second photoresist structure, an intermediate source-drain structure is etched to form a source-drain structure film layer structure;

[0054] Figure 19 Schematic diagram of a film layer structure of a method for preparing a thin film transistor film layer provided in an embodiment of the present application, in which, based on the second photoresist structure, an intermediate non-metal structure is etched to form an active structure and a doped structure film layer structure.

[0055] Description of reference numerals:

[0056] 1 - Thin film transistor; 11 - Gate insulating layer; 12 - Active structure; 121 - Source-drain region; 122 - Channel region; 123 - Ramp region; 13 - Doped structure; 14 - Source-drain structure; 15 - Non-metal structure;

[0057] 21 - Initial active layer; 22 - Initial doped layer; 23 - Initial source-drain layer; 24 - Initial non-metal layer; 25 - Intermediate source-drain structure; 251 - Preliminary intermediate source-drain structure; 26 - Intermediate non-metal structure; 261 - Intermediate doped structure; 262 - Intermediate active structure;

[0058] 31 - First photoresist structure; 32 - Second photoresist structure; 33 - Third photoresist structure;

[0059] 4 - Thin film transistor; 41 - Gate insulating layer; 42 - Active structure; 43 - Doped structure; 44 - Source-drain structure; 45 - Initial active layer; 451 - Intermediate active layer; 46 - Intermediate source-drain structure; 47 - Initial doped layer; 471 - Intermediate doped structure;

[0060] 51 - First photoresist structure; 52 - Second photoresist structure. Detailed implementation manners

[0061] The embodiments of the present application will be described below with reference to the drawings in the present application. It should be understood that the embodiments described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application, and do not constitute limitations on the technical solutions of the embodiments of the present application.

[0062] Those skilled in the art can understand that, unless specifically stated otherwise, the singular forms "a", "an", "the" and "said" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of this application means the presence of the described features, integers, steps, operations, elements and / or components, but does not exclude the presence of other features, information, data, steps, operations, elements, components and / or their combinations supported by the art. The term "and / or" used herein means at least one of the items defined by the term, for example, "A and / or B" can be implemented as "A", or implemented as "B", or implemented as "A and B".

[0063] To make the objectives, technical solutions and advantages of this application clearer, the following will further describe the embodiments of this application in detail with reference to the accompanying drawings.

[0064] The R & D idea of this application includes: the current four - lithography process for preparing thin - film transistors includes: the first lithography forms the gate metal pattern, the second lithography forms the source - drain pattern and the silicon island pattern, where the silicon island includes a gate insulating layer, an active structure and a doping structure, the third lithography forms a via on the passivation layer, and the fourth lithography forms the pixel electrode pattern, so that the pixel electrode is connected to the source - drain through the via.

[0065] The backlight of the display panel is PWM (Pulse Width Modulation) backlight, which is modulated through a series of pulse widths to equivalently obtain the required pattern, and is more economical and has stronger anti - interference ability than ordinary backlight. However, when the thin - film transistor prepared by the four - lithography process is in the PWM backlight mode, there will be a problem of poor water ripple.

[0066] The applicant found that during the second lithography process, a semiconductor tail (the outermost part of the active structure) is formed outside the source - drain structure (which belongs to the metal line). When the PWM backlight corresponding to the position of the semiconductor tail is turned on, the semiconductor tail conducts electricity due to the photoelectric effect, resulting in an increase in the signal delay time and a decrease in the charging rate in the display panel. As a result, the light transmittance of the semiconductor tail region is different from that of the region where the backlight is not turned on, and then there is a brightness difference in the display panel, manifested as poor water ripple, which affects the yield and quality of the display panel.

[0067] Figure 1 FIG. is a schematic diagram of the film layer structure of a thin - film transistor provided by the prior art. The thin - film transistor 4 is prepared by a four - lithography process using HTM (Half - tone Mask) technology, and includes a gate insulating layer 41, an active structure 42, a doping structure 43 and a source - drain structure 44 arranged in layers. The specific preparation process of the thin - film transistor 4 is as follows:

[0068] Reference Figure 2 , after HTM exposure, the initial source-drain layer is wet-etched to form a schematic diagram of the film structure of the intermediate source-drain structure 46.

[0069] Reference Figure 3 , after dry-etching the initial doped layer 47 and the initial active layer 45, a schematic diagram of the film structure of the intermediate doped structure 471 and the intermediate active structure 451 is formed. Figure 3 In [reference], T1 comes from the CD Bias (critical dimension deviation) caused by wet-etching the initial source-drain layer. Specifically, in the direction parallel to the gate insulating layer 41, the distance between the edge of the intermediate source-drain structure 46 and the edge of the first photoresist 51.

[0070] Reference Figure 4 , after ashing the first photoresist structure 51, a schematic diagram of the film structure of the second photoresist structure 52 is formed. Through the ashing process, the first photoresist structure in the exposed area is ashed away, exposing the channel of the thin-film transistor. The edge of the second photoresist structure 52 is shortened by a distance of T2 relative to the edge of the intermediate source-drain structure 46.

[0071] Reference Figure 5 , after wet-etching the intermediate source-drain structure 46, a schematic diagram of the film structure of the source-drain structure 44 is formed. The edge of the source-drain structure 44 is further shortened on the basis of the distance of T2, and the shortened distance is T3.

[0072] Reference Figure 6 , after dry-etching the intermediate doped structure 471 and the intermediate active structure 451, a schematic diagram of the film structure of the doped structure 43 and the active structure 42 is formed. When etching away the intermediate doped structure 471 in the channel, the intermediate doped structure 471 not covered by the second photoresist structure 52 will also be etched away, exposing the active structure 42. The exposed area of the active structure 42 is the T4 area. From the above process, it can be seen that T4≈T1+T2.

[0073] If the second photoresist structure 52 is peeled off by wet-etching to form the thin-film transistor 4, Figure 6 in [reference], T4 is the exposed semiconductor tail or the semiconductor residual width. If the second photoresist structure 52 is peeled off by dry-etching, due to over-etching, the doped structure 43 in the Figure 6 T5 area will be etched away, and the final semiconductor tail will be T4+T5. T5 is the distance between the edge of the source-drain structure 44 and the edge of the doped structure 43.

[0074] For large-size high-end display panels, to ensure the charging rate, the source-drain metal thickness is generally relatively thick (>5000 Å), so the CD Bias is very large (bilateral Bias > 1.5 μm). That is to say, the semiconductor tailing mainly comes from the CD Bias caused by etching the initial source-drain layer to form the intermediate source-drain structure 46. When the active structure is prepared with amorphous silicon, this semiconductor tailing is the amorphous silicon tailing (a-Si Tail).

[0075] The thin-film transistor, its manufacturing method, and the display panel provided by this application aim to solve the above technical problems in the prior art.

[0076] The technical solution of this application and how this technical solution solves the above technical problems will be described in detail below with specific embodiments. It should be noted that the following embodiments can refer to, draw on, or combine with each other. For the same terms, similar features, and similar implementation steps in different embodiments, they will not be described repeatedly.

[0077] An embodiment of this application provides a thin-film transistor 1. The structural schematic diagram of the thin-film transistor 1 is as Figure 7 shown, including a gate insulating layer 11, an active structure 12, a doping structure 13, and a source-drain structure 14 that are stacked. The active structure 12 includes a source-drain region 121 and a channel region 122. The doping structure 13 covers the source-drain region 121.

[0078] In this embodiment, by covering the source-drain region 121 of the active structure 12 with the doping structure 13, since the doping structure 13 is insensitive to light and the doping structure 13 itself is a conductor, when the PWM backlight is turned on, the light transmittance through the doping structure 13 is the same as that of the area where the backlight is not turned on. The overlapping capacitance between the source-drain structure and the gate of the thin-film transistor will not change, effectively avoiding water ripple defects, being beneficial to improving the brightness uniformity of the display panel, and being beneficial to improving the yield and quality of the display panel.

[0079] Moreover, using the thin-film transistor 1 can improve the quality of large-size high-end display products, and there is no need to add an additional mask plate, which can be directly completed on the basis of the existing production line, reducing the production cost.

[0080] Optionally, the doping structure 13 includes N-type heavily doped amorphous silicon or P-type heavily doped amorphous silicon.

[0081] In this embodiment, if the material of the doping structure 13 is N-type amorphous silicon (N+a-Si), N-type heavy doping can be used; if the material of the doping structure 13 is P-type amorphous silicon (P+a-Si), P-type heavy doping can be used.

[0082] Based on the same inventive concept, an embodiment of the present application provides a display panel, including the thin-film transistor 1 provided in the above embodiment.

[0083] In this embodiment, since the display panel includes the thin-film transistor 1 provided in the above embodiment, the beneficial effects of the display panel also include the beneficial effects of the thin-film transistor 1, which will not be elaborated here.

[0084] Based on the same inventive concept, an embodiment of the present application provides a method for manufacturing a thin-film transistor 1. The schematic flow diagram of this method is as Figure 8 shown, including the following steps S1 - S5:

[0085] S1: Sequentially prepare an initial active layer 21, an initial doping layer 22, and an initial source-drain layer 23 on one side of the gate insulating layer 11. The initial active layer 21 and the initial doping layer 22 form an initial non-metal layer 24. Prepare a first photoresist structure 31 on the side of the initial source-drain layer 23 away from the gate insulating layer 11.

[0086] Optionally, as Figure 9 shown is the schematic diagram of the film layer structure obtained after step S1.

[0087] In this embodiment, a photoresist is coated on the side of the initial source-drain layer 23 away from the gate insulating layer 11. After exposure through an HTM Mask, a first photoresist structure 31 is formed, and a part of the initial source-drain layer 23 is exposed at the edge of the first photoresist structure 31.

[0088] S2: Based on the first photoresist structure 31, wet-etch the initial source-drain layer 23 and the initial non-metal layer 24 to form an intermediate source-drain structure 25 and an intermediate non-metal structure 26, such that the intermediate source-drain structure 25 just covers the side of the intermediate non-metal structure 26 close to the intermediate source-drain structure 25.

[0089] In this embodiment, after wet-etching the initial source-drain layer 23 to form the intermediate source-drain structure 25, by increasing the etching time, continue to wet-etch the initial non-metal layer 24. Utilize the isotropic characteristic of chemical etching to etch away all the initial non-metal layer 24 not covered by the intermediate source-drain structure 25. That is, when etching the initial non-metal layer 24, the edge of the intermediate source-drain structure 25 is used as the etching edge, rather than the edge of the first photoresist structure 31. Thus, the semiconductor tail generated during the etching of the initial non-metal layer in the prior art is eliminated, which is beneficial to eliminating the water ripple defect caused by the semiconductor tail. Under PWM backlight, the display brightness of the display panel is uniform, and the yield of the display panel is improved.

[0090] Moreover, by using the thin film transistor 1, the quality of large-size high-end display products can be improved, and there is no need to add an additional mask plate, which can be directly completed on the basis of the existing production line, reducing production costs. At the same time, since the wet etching process is used for the initial non-metal layer 24 instead of the existing dry etching process for the initial non-metal layer 24, the integrity of the glass substrate can be protected, and the interlayer short-circuit defect caused by glass breakdown or electrostatic breakdown of the glass substrate due to being in the plasma environment for a long time during the dry etching process can be avoided.

[0091] There are multiple ways to implement step S2. Several feasible ways are specifically introduced below.

[0092] One feasible way is as follows:

[0093] First step: Using the first photoresist structure 31 as a mask, the initial source-drain layer 23 is etched with the first etching solution to obtain a preliminary intermediate source-drain structure 251.

[0094] Optionally, as Figure 10 shown is the film layer structure schematic diagram of the preliminary intermediate source-drain structure 251 obtained after the first step.

[0095] Second step: The preliminary intermediate source-drain structure 251 and the initial non-metal layer 24 are etched with the first etching solution to obtain an intermediate source-drain structure 25 and an intermediate non-metal structure 26. The positive projection of the side of the intermediate non-metal structure 26 close to the intermediate source-drain structure 25 on the gate insulating layer 11 coincides with the positive projection of the intermediate source-drain structure 25 on the gate insulating layer 11.

[0096] Optionally, as Figure 11 shown is the film layer structure schematic diagram of the intermediate source-drain structure 25 and the intermediate non-metal structure 26 obtained after the second step.

[0097] In this embodiment, the initial source-drain layer 23 and the initial non-metal layer 24 are etched with the same first etching solution, and the etching circuit is simple, which is beneficial to reducing process steps and shortening production time. At the same time, the designed line width of the preliminary intermediate source-drain structure 251 obtained in the first step is greater than the designed line width of the intermediate source-drain structure 25, so as to compensate for the further etching of the line width of the preliminary intermediate source-drain structure 251 when the initial non-metal layer 24 is etched with the first etching solution subsequently, and thus it is beneficial to ensure the requirement for the line width of the source-drain structure 14.

[0098] Optionally, etching the preliminary intermediate source-drain structure 251 and the initial non-metal layer 24 with the first etching solution includes etching the preliminary intermediate source-drain structure 251, the initial doping layer 22, and the initial active layer 21 with the first etching solution to obtain an intermediate source-drain structure 25, an intermediate doping structure 261, and an intermediate active structure 262, such that the intermediate doping structure 261 covers the intermediate active structure 262.

[0099] In this embodiment, the intermediate non-metal structure 26 includes an intermediate doping structure 261 and an intermediate active structure 262. By covering the intermediate active structure 262 with the intermediate doping structure 261, that is, the orthographic projection of the intermediate doping structure 261 on the gate insulating layer 11 coincides with the orthographic projection of the side of the intermediate active structure 262 close to the intermediate doping structure 261 on the gate insulating layer 11, it is beneficial to eliminate the water ripple defect caused by semiconductor trailing, and the display brightness of the display panel containing the thin film transistor 1 is good.

[0100] Optionally, the first etching solution includes fluoride ions.

[0101] In this embodiment, the etching solution containing fluoride ions has a strong etching ability for the initial non-metal layer 24. The mass percentage concentration of fluoride ions is not less than 0.3% and not greater than 1%, which can protect the glass substrate from damage by fluoride ions and ensure the etching rate of the initial non-metal layer 24, improving work efficiency.

[0102] Another achievable way is as follows:

[0103] First step: Using the third photoresist structure 33 as a mask, etching the initial source-drain layer 23 with the first etching solution to obtain a preliminary intermediate source-drain structure 251. The third photoresist structure 33 is prepared on the side of the initial source-drain layer 23 away from the gate insulating layer 11. Along the first direction, the size of the third photoresist structure 33 is larger than the size of the first photoresist structure 31, and the first direction is parallel to the gate insulating layer 11.

[0104] Optionally, FIG. 12 is a schematic diagram of the film layer structure of the third photoresist structure 33 prepared on the side of the initial source-drain layer 23 away from the gate insulating layer 11. Figure 13 FIG. 20 is a schematic diagram of the film layer structure of the preliminary intermediate source-drain structure 251 obtained after the first step.

[0105] In this embodiment, the third photoresist structure 33 is used as a mask to replace the first photoresist structure 31. Along the first direction, the size of the third photoresist structure 33 is larger than that of the first photoresist structure 31. A larger-sized third photoresist structure 33 can be obtained by reducing the exposure amount. Then, relative to the first photoresist structure 31, the distance from the edge of the third photoresist structure 33 to the edge of the initial source-drain layer 23 is reduced, which is beneficial to making the line width of the preliminary intermediate source-drain structure 251 larger than that of the intermediate source-drain structure 25, so as to compensate for the further etching of the line width of the preliminary intermediate source-drain structure 251 when the initial non-metal layer 24 is etched with the first etching solution subsequently, and further beneficial to ensuring the requirement for the line width of the source-drain structure 14.

[0106] Step 2: Use the first etching solution to etch the preliminary intermediate source-drain structure 251 and the initial non-metal layer 24 to obtain the intermediate source-drain structure 25 and the intermediate non-metal structure 26.

[0107] Optionally, the orthographic projection of the side of the intermediate non-metal structure 26 close to the intermediate source-drain structure 25 on the gate insulating layer 11 coincides with the orthographic projection of the intermediate source-drain structure 25 on the gate insulating layer 11. Figure 14 FIG. is a schematic diagram of the film layer structure of the intermediate source-drain structure 25 and the intermediate non-metal structure 26 obtained after the second step is completed.

[0108] In this embodiment, the first etching solution is used to continue etching the initial non-metal layer 24. The etching process is simple, which is beneficial to reducing the process steps and shortening the production time.

[0109] Optionally, using the first etching solution to etch the preliminary intermediate source-drain structure 251 and the initial non-metal layer 24 includes using the first etching solution to etch the preliminary intermediate source-drain structure 251, the initial doping layer 22, and the initial active layer 21 to obtain the intermediate source-drain structure 25, the intermediate doping structure 261, and the intermediate active structure 262, such that the intermediate doping structure 261 covers the intermediate active structure 262.

[0110] Another achievable way is as follows:

[0111] Step 1: Using the first photoresist structure 31 as a mask, use the first etching solution to etch the initial source-drain layer 23 to form the intermediate source-drain structure 25.

[0112] Optionally, Figure 15 FIG. is a schematic diagram of the film layer structure of the intermediate source-drain structure 25 obtained after the first step is completed.

[0113] Step 2: Using the intermediate source-drain structure 25 as a mask, use the second etching solution to etch the initial non-metal layer 24 to form the intermediate non-metal structure 26.

[0114] Optionally, Figure 16 It is a schematic diagram of the film structure of the intermediate non-metal structure 26 obtained after the second step.

[0115] In this embodiment, the initial source-drain layer 23 is etched with the first etching solution, and the initial non-metal layer 24 is etched with the second etching solution. Then, while etching the initial non-metal layer 24, the intermediate source-drain structure 25 is not further etched, ensuring the line width of the intermediate source-drain structure 25.

[0116] Optionally, the mass percentage concentration of fluoride ions in the first etching solution is not less than 0.3% and not more than 1%; the mass percentage concentration of fluoride ions in the second etching solution is not less than 1% and not more than 2%.

[0117] In this embodiment, the mass percentage concentration of fluoride ions in the first etching solution is less than that in the second etching solution, avoiding the etching of the intermediate source-drain structure 25 and facilitating the protection of the line width of the intermediate source-drain structure 25. The mass percentage concentration of fluoride ions in the second etching solution is not less than 1% and not more than 2%. Within this concentration range, on the one hand, it is conducive to protecting the intermediate source-drain structure 25 from being etched, on the other hand, it is conducive to protecting the glass substrate from being damaged by high-concentration fluoride ions, and on the third hand, it can increase the etching rate of the initial non-metal layer 24 and improve production efficiency.

[0118] Optionally, the mass percentage concentration of hydrogen peroxide in the first etching solution is not less than 15% and not more than 25%, and the mass percentage concentration of hydrogen peroxide in the second etching solution is not less than 3% and not more than 10%.

[0119] In this embodiment, the mass percentage concentration of hydrogen peroxide in the second etching solution is less than that in the first etching solution, which is conducive to the mass percentage concentration of fluoride ions in the second etching solution being greater than that in the first etching solution and conducive to protecting the line width of the intermediate source-drain structure 25.

[0120] Optionally, both the first etching solution and the second etching solution can include a copper ion etching solution, or other etching solutions can be selected according to the actual situation.

[0121] Optionally, the thickness of the initial active layer 21 is not greater than 1000 angstroms.

[0122] In this embodiment, when wet etching the initial active layer 21, the chemical solution used will cause a certain degree of damage to the glass substrate. To protect the glass substrate, the etching time of the initial active layer 21 needs to be shortened, so the thickness of the initial active layer 21 is controlled to be no more than 1000 angstroms. Compared with the existing active layer with a thickness of 1300 angstroms - 2000 angstroms, the thickness of the initial active layer 21 in this application is reduced, which is also beneficial for cost saving, shortening the etching time, and improving production efficiency.

[0123] S3: Pattern the first photoresist structure 31 to form a second photoresist structure 32.

[0124] Optionally, as Figure 17 shown is a schematic diagram of the film layer structure of the second photoresist structure 32 formed after step S3 is completed.

[0125] Optionally, in step S3, it includes ashing the first photoresist structure 31 to expose the intermediate source-drain structure 25 above the channel region 122, and forming the second photoresist structure 32.

[0126] Optionally, the orthographic projection of the second photoresist structure 32 on the gate insulating layer 11 exceeds the designed distance of the orthographic projection of the intermediate source-drain structure 25 on the gate insulating layer 11.

[0127] In this embodiment, the orthographic projection of the second photoresist structure 32 on the gate insulating layer 11 exceeds the designed distance of the orthographic projection of the intermediate source-drain structure 25 on the gate insulating layer 11, which is beneficial for protecting the edge of the intermediate non-metal structure 26 from being etched away during dry etching of the intermediate non-metal structure 26, thereby eliminating semiconductor tailing, avoiding the occurrence of water ripple defects, and improving the yield of the display panel.

[0128] Optionally, the orthographic projection of the edge of the second photoresist structure 32 on the gate insulating layer 11 does not exceed the orthographic projection of the side of the intermediate active structure 262 far from the second photoresist structure 22 on the gate insulating layer 11, so as to protect the edge of the intermediate doping structure 261 from being etched away during dry etching of the intermediate doping structure 261, thereby eliminating semiconductor tailing, and the edge of the second photoresist structure 32 is between the orthographic projection of the upper surface of the intermediate active structure 262 on the gate insulating layer 11 and the orthographic projection of the lower surface on the gate insulating layer 11, which is beneficial for saving photoresist and reducing costs.

[0129] S4: Based on the second photoresist structure 32, etch the intermediate source-drain structure 25 and the intermediate non-metal structure 26 to form a stacked active structure 12, doping structure 13, and source-drain structure 14, such that the doping structure 13 covers the source-drain region 121, and the active structure 12 includes the source-drain region 121 and the channel region 122.

[0130] Optionally, based on the second photoresist structure 32, the intermediate source-drain structure 25 and the intermediate non-metal structure 26 are etched, including:

[0131] The first step: Based on the second photoresist structure 32, the intermediate source-drain structure 25 is etched with a third etching solution to form the source-drain structure 14.

[0132] Optionally, as Figure 18 shown is the schematic diagram of the film layer structure of the source-drain structure 14 after the first step is completed.

[0133] In this embodiment, the third etching solution includes fluoride ions, and the mass percentage concentration of the fluoride ions is not greater than 0.1, so only the intermediate source-drain structure 25 is etched, and the intermediate non-metal structure 26 is not etched.

[0134] The second step; the intermediate non-metal structure 26 is dry-etched to obtain the non-metal structure 15, that is, the intermediate doped structure 261 and the intermediate active structure 262 are dry-etched to form the doped structure 13 and the active structure 12, and the doped structure 13 covers the source-drain region 121 of the active structure 12.

[0135] Optionally, as Figure 19 shown is the schematic diagram of the film layer structure of the doped structure 13 and the active structure 12 after the second step is completed.

[0136] In this embodiment, when the intermediate doped structure 261 is dry-etched, since the positive projection of the edge of the second photoresist structure 32 on the gate insulating layer 11 exceeds the positive projection of the edge of the intermediate doped structure 261 on the gate insulating layer 11 to protect the edge of the intermediate doped structure 261 from being etched, only the intermediate doped structure 261 exposed on the channel region 122 is etched, which is beneficial to eliminating semiconductor tailing and can improve the yield and quality of the display panel.

[0137] Optionally, the active structure 12 further includes a taper region 123, and the taper region 123 is located at one end of the source-drain region 121 away from the channel region 122.

[0138] S5: Strip the second photoresist structure 32.

[0139] In this embodiment, the second photoresist structure 32 is wet-stripped, so that during the stripping process, it is beneficial to protect the doped structure 13 from being damaged.

[0140] Applying the embodiments of the present application can at least achieve the following beneficial effects:

[0141] 1. In the embodiments of the present application, the source-drain regions of the active structure are covered by a doping structure. Since the doping structure 13 is insensitive to light and the doping structure itself is a conductor, when the PWM backlight is turned on, the light transmittance through the doping structure is the same as that of the area where the backlight is not turned on, which can effectively avoid the defect of water ripples, is beneficial to improving the brightness uniformity of the display panel, and is beneficial to improving the yield and quality of the display panel.

[0142] 2. Using the thin-film transistor 1 in the embodiments of the present application can improve the quality of large-size high-end display products, and there is no need to add an additional mask plate, which can be directly completed on the basis of the existing production line, reducing the production cost.

[0143] 3. In the embodiments of the present application, the isotropic characteristic of chemical etching is utilized to etch away all the initial non-metal layers not covered by the intermediate source-drain structure. That is, the etching of the initial non-metal layer is based on the edge of the intermediate source-drain structure as the etching edge, rather than the edge of the first photoresist structure as the etching edge, thereby eliminating the semiconductor tail generated during the etching of the initial non-metal layer in the prior art, and thus being beneficial to eliminating the water ripple defect caused by the semiconductor tail. Under the PWM backlight, the display brightness of the display panel is uniform, improving the yield of the display panel.

[0144] Those skilled in the art of the present technology can understand that the various operations, methods, steps, measures, and solutions in the processes discussed in the present application can be alternated, changed, combined, or deleted. Further, the other steps, measures, and solutions in the various operations, methods, and processes discussed in the present application can also be alternated, changed, rearranged, decomposed, combined, or deleted. Further, those in the prior art having the steps, measures, and solutions in the various operations, methods, and processes disclosed in the present application can also be alternated, changed, rearranged, decomposed, combined, or deleted.

[0145] In the description of the present application, the directions or positional relationships indicated by the words "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are the exemplary directions or positional relationships based on the drawings, which are for the convenience of describing or simplifying the embodiments of the present application, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation to the present application.

[0146] The terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, unless otherwise specified, the meaning of "plurality" is two or more.

[0147] In the description of the present application, it should be noted that, unless otherwise clearly specified and defined, the terms "installation", "connection", and "coupling" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a direct connection, or an indirect connection through an intermediate medium, and it may be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0148] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any one or more embodiments or examples in a suitable manner.

[0149] It should be understood that although the steps in the flowchart of the accompanying drawings are shown sequentially as indicated by the arrows, the execution order of these steps is not limited to the order indicated by the arrows. Unless otherwise clearly stated in this document, in some implementation scenarios of the embodiments of the present application, the steps in each process can be executed in other orders according to requirements. Moreover, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on the actual implementation scenario. Some or all of these sub-steps or stages can be executed at the same time, or at different times. In the scenario where the execution times are different, the execution order of these sub-steps or stages can be flexibly configured according to requirements, and the embodiments of the present application do not limit this.

[0150] The above are only some implementation manners of the present application. It should be pointed out that for those of ordinary skill in the art, without departing from the technical concept of the solution of the present application, other similar implementation means based on the technical idea of the present application also belong to the protection scope of the embodiments of the present application.

Claims

1. A method for manufacturing a thin film transistor, characterized in that, The thin film transistor includes a gate insulating layer, an active structure, a doping structure, and a source-drain structure which are stacked. The active structure includes a source-drain region and a channel region. The doping structure covers the source-drain region. The manufacturing method includes: Sequentially preparing an initial active layer, an initial doping layer, and an initial source-drain layer on one side of the gate insulating layer. The initial active layer and the initial doping layer form an initial non-metal layer. A first photoresist structure is prepared on the side of the initial source-drain layer away from the gate insulating layer. Based on the first photoresist structure, the initial source-drain layer and the initial non-metal layer are wet etched to form an intermediate source-drain structure and an intermediate non-metal structure, such that the intermediate source-drain structure just covers the side of the intermediate non-metal structure close to the intermediate source-drain structure. The first photoresist structure is patterned to form a second photoresist structure. Based on the second photoresist structure, the intermediate source-drain structure and the intermediate non-metal structure are etched to form a stacked active structure, doping structure, and source-drain structure, such that the doping structure covers the source-drain region, and the active structure includes the source-drain region and the channel region. The second photoresist structure is stripped.

2. The manufacturing method according to claim 1, characterized in that, Based on the first photoresist structure, the initial source-drain layer and the initial non-metal layer are wet etched to form an intermediate source-drain structure and an intermediate non-metal structure, such that the intermediate source-drain structure just covers the side of the intermediate non-metal structure close to the intermediate source-drain structure, including: Using a first etching solution to etch the initial source-drain layer with the first photoresist structure as a mask to obtain a preliminary intermediate source-drain structure. Using the first etching solution to etch the preliminary intermediate source-drain structure and the initial non-metal layer to obtain the intermediate source-drain structure and the intermediate non-metal structure. The orthographic projection of the side of the intermediate non-metal structure close to the intermediate source-drain structure on the gate insulating layer coincides with the orthographic projection of the intermediate source-drain structure on the gate insulating layer.

3. The manufacturing method according to claim 2, characterized in that, Using the first etching solution to etch the preliminary intermediate source-drain structure and the initial non-metal layer to obtain the intermediate source-drain structure and the intermediate non-metal structure. The orthographic projection of the side of the intermediate non-metal structure close to the intermediate source-drain structure on the gate insulating layer coincides with the orthographic projection of the intermediate source-drain structure on the gate insulating layer, including: Using the first etching solution to etch the preliminary intermediate source-drain structure, the initial doping layer, and the initial active layer to obtain the intermediate source-drain structure, an intermediate doping structure, and an intermediate active structure, such that the intermediate doping structure covers the intermediate active structure.

4. The manufacturing method according to claim 1, characterized in that, Preparing a first photoresist structure on the side of the initial source-drain layer away from the gate insulating layer includes: preparing a third photoresist structure on the side of the initial source-drain layer away from the gate insulating layer. The size of the third photoresist structure in a first direction is larger than the size of the first photoresist. The first direction is parallel to the gate insulating layer. And, based on the first photoresist structure, wet etching is performed on the initial source-drain layer and the initial non-metal layer to form an intermediate source-drain structure and an intermediate non-metal structure, such that the intermediate source-drain structure just covers one side of the intermediate non-metal structure close to the intermediate source-drain structure, including: Using the third photoresist structure as a mask, etching the initial source-drain layer with a first etching solution to obtain a preliminary intermediate source-drain structure; Etching the preliminary intermediate source-drain structure and the initial non-metal layer with the first etching solution to obtain the intermediate source-drain structure and the intermediate non-metal structure.

5. The manufacturing method according to claim 2 or 3, characterized in that, The first etching solution includes fluoride ions.

6. The manufacturing method according to claim 1, characterized in that, Based on the first photoresist structure, wet etching is performed on the initial source-drain layer and the initial non-metal layer to form an intermediate source-drain structure and an intermediate non-metal structure, such that the intermediate source-drain structure just covers one side of the intermediate non-metal structure close to the intermediate source-drain structure, including: Using the first photoresist structure as a mask, etching the initial source-drain layer with a first etching solution to form the intermediate source-drain structure; Using the intermediate source-drain structure as a mask, etching the initial non-metal layer with a second etching solution to form the intermediate non-metal structure.

7. The manufacturing method according to claim 6, characterized in that, Including at least one of the following: The mass percentage concentration of fluoride ions in the first etching solution is not less than 0.3% and not more than 1%; the mass percentage concentration of fluoride ions in the second etching solution is not less than 1% and not more than 2%; The mass percentage concentration of hydrogen peroxide in the first etching solution is not less than 15% and not more than 25%, and the mass percentage concentration of hydrogen peroxide in the second etching solution is not less than 3% and not more than 10%.

8. The manufacturing method according to claim 1, characterized in that, Patterning the first photoresist structure to form a second photoresist structure, including: Performing ashing treatment on the first photoresist structure to expose the intermediate source-drain structure above the channel region, forming the second photoresist structure.

9. A thin film transistor, characterized in that, Obtained by using the preparation method according to any one of claims 1-8.

10. A display panel, characterized in that, Including the thin film transistor according to claim 9.

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