LED chip and manufacturing method thereof

Abstract

The application provides an LED chip and a manufacturing method thereof. The manufacturing method of the LED chip provided by the application has the following advantages. Firstly, the blocking layer is subjected to patterning treatment in a photolithography and etching manner, so that a current blocking layer and an N region mask are formed simultaneously in one photolithography process. Secondly, a P region mask, an N region mask and a cutting path pattern are etched simultaneously by dry etching, so that an N type region mesa and the cutting path are formed in one etching process. The process is simplified, the yield is improved, and the etching surfaces are all inclined surfaces, which is beneficial to depositing an insulating protective layer in a PV process. The inclined surface of the epitaxial structure and the cutting path are exposed without additional photolithography, and finally are protected by the insulating protective layer in the PV process, so that the luminous brightness and reliability of the LED chip are improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor device manufacturing, and more particularly to an LED chip and a manufacturing method thereof. BACKGROUND

[0002] In the preparation process of the current flip LED chip, the commonly used process is composed of four photoetchings or five photoetchings. The four photoetchings include a Mesa process (a step, which refers to a process of manufacturing an N-type layer exposed area on the surface of an epitaxial wafer by dry etching), an ITO process (which refers to a transparent conductive film layer pattern manufacturing process), a Pad process (which refers to a photoetching pattern manufacturing process of an electrode), and a PV process (which refers to a photoetching pattern manufacturing process of a passivation layer). The five photoetchings include the Mesa process, a CB process (a current blocking layer manufacturing process), the ITO process, the Pad process, and the PV process. The CB process is added to the five photoetchings, which is a current blocking layer for manufacturing a P-type electrode, and the purpose is to prevent the current injected from the P-type electrode of the flip LED chip from being concentrated on the directly below of the P-type electrode to cause current congestion effect. Based on this, the five photoetchings are generally used for manufacturing large-size high-power LED chips, and the four photoetchings are generally used for manufacturing small-size low-power chips. The LED manufactured by using these methods has the characteristics of high efficiency and low cost.

[0003] However, since the flip LED chip does not need to do the DE process (which refers to a cutting path photoetching pattern manufacturing process) in the preparation process, the epitaxial structure thereof is exposed outside through cutting and cleavage in the final product, which will cause problems to the reliability of the LED chip, and if the DE process is additionally added, the preparation of the LED chip will increase the cost and the process complexity. SUMMARY

[0004] Therefore, the present application provides an LED chip and a manufacturing method thereof to solve the problems in the prior art that the epitaxial structure of the flip LED chip is exposed outside through cutting and cleavage in the final product due to the fact that the flip LED chip does not need to do the DE process in the preparation process, which will cause problems to the reliability of the LED chip, and if the DE process is additionally added, the preparation of the LED chip will increase the cost and the process complexity.

[0005] To achieve the above object, the technical scheme adopted by the present application is as follows:

[0006] A manufacturing method of an LED chip, comprising:

[0007] Step S1, providing a substrate;

[0008] Step S2, laminating an epitaxial structure on the substrate, the epitaxial structure comprising, in sequence from the substrate, a laminated N-type semiconductor layer, an active region and a P-type semiconductor layer;

[0009] Step S3, depositing an integral layer barrier layer on the epitaxial structure;

[0010] Step S4, patterning the barrier layer by lithography and etching to form a current barrier layer and an N-region mask; the current barrier layer comprises a first opening, and the first opening exposes the P-type semiconductor layer;

[0011] Step S5, forming a P-region mask by mask lithography, the P-region mask covering the current barrier layer, part of the N-region mask and part of the P-type semiconductor layer, and defining a cutting path pattern on the upper surface edge of the P-type semiconductor layer, the overlapping part of the P-region mask and the N-region mask being an overlapping region;

[0012] Step S6, etching the P-region mask, the N-region mask and the cutting path pattern simultaneously to form an N-type region mesa and a cutting path, and the etching surfaces are all inclined surfaces;

[0013] The step S6 specifically comprises the following processes:

[0014] By dry etching, etching along the exposed N-region mask to expose part of the N-type semiconductor layer to form the N-type region mesa; at the same time, etching along the cutting path to expose the substrate to form the cutting path, the cutting path surrounding the epitaxial structure; and at the same time, etching part of the P-region mask along the P-region mask;

[0015] By wet etching, laterally etching the N-region mask in the overlapping region;

[0016] By removing the residual P-region mask with a glue removal liquid;

[0017] Step S7, depositing a transparent conductive layer on the upper surface of the P-type semiconductor layer and the surface of the current barrier layer, the transparent conductive layer comprising a second opening, and the second opening exposing the first opening and part of the current barrier layer, the first opening and the second opening forming a P-type electrode step;

[0018] Step S8, depositing an N-type electrode on the N-type region mesa; and depositing a P-type electrode on the P-type electrode step, the P-type electrode connecting the P-type semiconductor layer, the current barrier layer and the transparent conductive layer;

[0019] Step S9, depositing an integral surface insulating protective layer, and exposing the N-type electrode and the P-type electrode by lithography and etching, the insulating protective layer covering the transparent conductive layer, the exposed surface of the epitaxial structure and the cutting path.

[0020] Preferably, the inclined surface comprises a first inclined surface, a second inclined surface and a third inclined surface, the first inclined surface is the inclined surface from the upper surface of the epitaxial structure to the cutting groove, the included angle between the first inclined surface and the cutting groove is a first angle; the second inclined surface is the inclined surface from the upper surface of the epitaxial structure to the N-type region mesa, the included angle between the second inclined surface and the N-type region mesa is a second angle; the third inclined surface is the inclined surface from the N-type region mesa to the cutting groove, the included angle between the third inclined surface and the cutting groove is a third angle.

[0021] Preferably, the first angle ranges from 120 degrees to 150 degrees, including the end point value; the second angle ranges from 135 degrees to 140 degrees, including the end point value; the third angle ranges from 100 degrees to 150 degrees, including the end point value.

[0022] Preferably, in the dry etching of the step S6, the etching rate of the epitaxial structure is S1, the etching rate of the N region mask is S2, and the etching rate of the P region mask is S3, wherein S1=S3>S2.

[0023] Preferably, in the dry etching of the step S6, the etching selectivity ratio of the epitaxial structure to the N region mask ranges from 4:1 to 8:1, and the etching selectivity ratio of the epitaxial structure to the P region mask is 1:1.

[0024] Preferably, the insulating protective layer comprises an adhesion layer, a dense layer and a hydrophobic layer stacked in order from bottom to top.

[0025] Preferably, the adhesion layer comprises one or any combination of nitride and oxide; the dense layer comprises oxide; and the hydrophobic layer comprises one or any combination of hydrophobic group organic material, alkane compound and organosilicon compound.

[0026] Preferably, the adhesion layer comprises one or any combination of silicon nitride and zirconium oxide; the dense layer comprises one or any combination of aluminum oxide and hafnium oxide; and the hydrophobic layer comprises one or any combination of trifluoromethyl, methyl, phenyl, polyethylene, polypropylene and polysiloxane.

[0027] Preferably, the refractive index of the adhesion layer > the refractive index of the dense layer > the refractive index of the hydrophobic layer.

[0028] Preferably, the refractive index of the adhesion layer is greater than 2.0; the refractive index of the dense layer is between 1.6 and 2.0; and the refractive index of the hydrophobic layer is less than 1.6.

[0029] An LED chip, comprising:

[0030] The LED chip is manufactured by the manufacturing method of the LED chip.

[0031] The technical scheme achieves the following effects:

[0032] 1. The manufacturing method of the LED chip, by means of photolithography and etching, the blocking layer is patterned, realizing one photolithography process to form the current blocking layer and the N region mask, the current blocking layer can improve the current crowding caused by the vertical injection of the current at the P electrode, improve the current diffusion, reduce the light absorption of the P electrode, improve the quantum efficiency, and further improve the luminous brightness of the LED chip, the N region mask is used to delay the etching of the epitaxial structure in the MESA etching; by dry etching, the P region mask, the N region mask and the cutting path pattern are etched at the same time, realizing the formation of the N type region mesa and the cutting path in one etching process, simplifying the process, improving the yield, and the etching surface is all inclined surface, which is beneficial to depositing the insulating protective layer in the PV process, the inclined surface of the epitaxial structure and the cutting path are exposed without additional photolithography, and finally protected by the insulating protective layer in the PV process, thereby improving the reliability of the LED chip.

[0033] 2. Further, the etching rate of the epitaxial structure is S1, the etching rate of the N region mask is S2, and the etching rate of the P region mask is S3, wherein S1=S3>S2, that is, the etching rate of the epitaxial structure is the same as that of the P region mask under the same etching condition, and the etching rate of the epitaxial structure and the P region mask is faster than that of the N region mask, in the dry etching process, the P region mask, the N region mask and the cutting path pattern (i.e. the epitaxial structure in the cutting path pattern area) are etched at the same time, after the N region mask is etched, the epitaxial structure in the P region mask, the N region mask area and the epitaxial structure in the cutting path pattern area are etched at the same time, and the etching depth of the cutting path is greater than that of the N type region mesa, realizing the formation of two different etching depths in one etching process.

[0034] 3. Further, the insulating protective layer is provided to improve the reverse pressure reliability of the LED chip, the insulating protective layer comprises an adhesion layer, a dense layer and a hydrophobic layer stacked from bottom to top, the adhesion layer can firmly adhere to the epitaxial structure, the dense layer can effectively prevent external moisture from penetrating, and the hydrophobic layer can avoid the attachment of moisture on the surface of the insulating protective layer.

[0035] 4. Further, the refractive index of the adhesion layer is greater than that of the dense layer, and the refractive index of the dense layer is greater than that of the hydrophobic layer, along the light emitting direction, the refractive index of each layer of the insulating protective layer decreases from bottom to top, which is beneficial to the light emission of the LED chip.

[0036] 5. The LED chip provided by the present invention is manufactured by using the aforementioned LED chip manufacturing method, which can effectively improve the luminous brightness and reliability of the LED chip. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0038] Figure 1 A flowchart illustrating a method for manufacturing an LED chip according to an embodiment of the present invention;

[0039] Figures 2.1 to 2.14 for Figure 1 The process cross-sectional diagrams and corresponding top views for each step of the manufacturing method shown are provided.

[0040] Figure 3 A schematic diagram of an LED chip structure provided in an embodiment of the present invention;

[0041] Explanation of symbols in the diagram:

[0042] 1. Substrate; 2. Epitaxial structure; 21. N-type semiconductor layer; 22. Active region; 23. P-type semiconductor layer; 3. Barrier layer; 31. Current barrier layer; 32. N-region mask; 4. P-region mask; 5. Transparent conductive layer; 6. N-type electrode; 7. P-type electrode; 8. Insulating protective layer; 81. Adhesion layer; 82. Dense layer; 83. Hydrophobic layer; K1. First opening; K2. Second opening; A. Cutting pattern; A1. Cutting track; B. Overlapping region; C. N-type mesa; θ1. First angle; θ2. Second angle; θ3. Third angle. Detailed Implementation

[0043] To make the content of this invention clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0044] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0045] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0046] This embodiment provides a method for manufacturing an LED chip, such as... Figure 1 As shown, it includes the following steps:

[0047] Step S1, as follows Figure 2.1 As shown, a substrate 1 is provided;

[0048] In this embodiment, there is no restriction on the specific type of substrate. Optionally, the substrate can be a semiconductor substrate such as a sapphire substrate, a silicon substrate, or a silicon carbide substrate. The specific material of the substrate can be selected and used according to the requirements.

[0049] Step S2, as follows Figure 2.2 As shown, an epitaxial structure 2 is stacked on a substrate 1. The epitaxial structure 2 includes, in sequence, a stacked N-type semiconductor layer 21, an active region 22, and a P-type semiconductor layer 23 along the direction away from the substrate 1.

[0050] In this embodiment, the specific materials of the N-type semiconductor layer and the P-type semiconductor layer are not limited. Optionally, the N-type semiconductor layer is an N-type GaN layer and the P-type semiconductor layer is a P-type GaN layer.

[0051] In this embodiment, the specific number of layers and structure of the epitaxial structure are not limited. The epitaxial structure includes at least an N-type semiconductor layer, an active region, and a P-type semiconductor layer. In other embodiments, in order to improve lattice matching, the epitaxial structure of the LED chip may also include a superlattice structure, etc.

[0052] Step S3, as follows Figure 2.3 As shown, a full-length barrier layer 3 is deposited on the epitaxial structure 2;

[0053] In this embodiment, the specific material of the barrier layer is not limited. Optionally, the barrier layer can be silicon dioxide or silicon nitride.

[0054] Step S4, as follows Figures 2.4 to 2.5 As shown, the barrier layer 3 is patterned by photolithography and etching to form a current blocking layer 31 and an N-region mask 32; the current blocking layer 31 includes a first opening K1, and the first opening K1 exposes the P-type semiconductor layer 23.

[0055] It should be noted that in this embodiment, the barrier layer is patterned by photolithography and etching, so that the current barrier layer and the N-region mask can be formed simultaneously in one photolithography process. The current barrier layer can improve the current congestion caused by the vertical injection of current at the P-type electrode, improve current diffusion, reduce the light absorption of the P-type electrode, improve quantum efficiency, and thus improve the luminous brightness of the LED chip. The N-region mask is used to delay the etching of the epitaxial structure in MESA etching.

[0056] In this embodiment, the specific shape of the current blocking layer is not limited. Optionally, the shape of the current blocking layer can be annular or other geometric shapes including the first opening.

[0057] In this embodiment, the specific shape of the N-region mask is not limited. Optionally, the shape of the N-region mask can be fan-shaped.

[0058] Step S5, as follows Figures 2.6 to 2.7 As shown, a P-region mask 4 is formed by photolithography. The P-region mask 4 covers a current blocking layer 31, a portion of an N-region mask 32, and a portion of a P-type semiconductor layer 23. A dicing pattern A is defined on the edge of the upper surface of the P-type semiconductor layer 23. The overlapping portion of the P-region mask 4 and the N-region mask 32 is the overlapping region B.

[0059] It should be noted that the overlapping area set in this embodiment can avoid gaps between the P-area mask and the N-area mask, which would cause the gap area to be etched during subsequent etching, thus destroying the integrity of the N-area mask pattern.

[0060] In this embodiment, optionally, the width of the overlapping region B in the vertical direction ranges from 3um to 8um, excluding the endpoint values.

[0061] Step S6: Simultaneously etch the P-area mask 4, the N-area mask 32, and the etch pattern A to form the N-type area mesa C and the etch pattern A1, and the etched surfaces are all inclined surfaces.

[0062] Step S6 specifically includes the following procedures:

[0063] like Figure 2.8 As shown, by dry etching, a portion of the N-type semiconductor layer 21 is exposed by etching along the exposed N-region mask 32 to form the N-type mesa C; at the same time, the substrate 1 is exposed by etching along the dicing pattern A to form the dicing A1, which surrounds the epitaxial structure 2; at the same time, a portion of the P-region mask 4 is etched away along the P-region mask 4.

[0064] like Figure 2.9 As shown, the N-region mask 32 of the overlapping region B is etched away laterally by wet etching.

[0065] like Figure 2.10 As shown, the residual P-area mask 4 is removed by adhesive remover;

[0066] It should be noted that in the embodiment, the P region mask, the N region mask and the cutting path pattern are etched at the same time by dry etching, so that the N type region mesa and the cutting path are formed in one etching process, the process is simplified, the yield is improved, and the etching surfaces are all inclined surfaces, which is beneficial to depositing an insulating protective layer in the PV process. The inclined surface of the epitaxial structure and the cutting path are exposed without additional photolithography, and finally are protected by the insulating protective layer in the PV process, so that the reliability of the LED chip is improved.

[0067] In the embodiment, the P region mask is photoresist.

[0068] Preferably, in the dry etching of step S6, the etching rate of the epitaxial structure 2 is S1, the etching rate of the N region mask 32 is S2, and the etching rate of the P region mask 4 is S3, wherein S1=S3>S2.

[0069] That is, under the same etching conditions, the etching rate of the epitaxial structure is the same as that of the P region mask, and the etching rate of the epitaxial structure and the P region mask is faster than that of the N region mask. In the dry etching process, the P region mask, the N region mask and the cutting path pattern (i.e. the epitaxial structure in the cutting path pattern region) are etched at the same time. After the N region mask is etched, the epitaxial structure in the P region mask and the N region mask region and the epitaxial structure in the cutting path pattern region are etched at the same time, so that the etching depth of the cutting path is greater than that of the N type region mesa, and two different etching depths are formed in one etching process.

[0070] Preferably, in the dry etching of step S6, the etching selectivity ratio of the epitaxial structure 2 and the N region mask 32 is 4:1-8:1, and the etching selectivity ratio of the epitaxial structure 2 and the P region mask 4 is 1:1.

[0071] In the embodiment, the specific material of the etching gas in step S6 is not limited, and the etching gas in step S6 includes a mixed gas of Cl2, Ar and BCl3, wherein the flow rate of Cl2 is 195 sccm, the flow rate of Ar is 30 sccm, and the flow rate of BCl3 is 5 sccm.

[0072] In the embodiment, the etching depth of the upper surface of the epitaxial structure 2 to the N type region mesa C is 0.8-1.6 μm, and the end point value is not included.

[0073] In the embodiment, the etching depth of the upper surface of the epitaxial structure 2 to the cutting path A1 is 3-8 μm, and the end point value is not included.

[0074] It should be noted that in the embodiment, the thickness of the P region mask is greater than the etching depth of the cutting path, so as to avoid damaging the current blocking layer when the P region mask, the N region mask and the cutting path pattern are etched at the same time in step S6.

[0075] Preferably, the inclined surface includes a first inclined surface, a second inclined surface, and a third inclined surface. The first inclined surface is the inclined surface from the upper surface of the extension structure 2 to the cutting channel A1, and the angle between the first inclined surface and the cutting channel A1 is a first angle θ1. The second inclined surface is the inclined surface from the upper surface of the extension structure 2 to the N-type region platform C, and the angle between the second inclined surface and the N-type region platform C is a second angle θ2. The third inclined surface is the inclined surface from the N-type region platform C to the cutting channel A1, and the angle between the third inclined surface and the cutting channel A1 is a third angle θ3.

[0076] Preferably, the first angle θ1 ranges from 120 degrees to 150 degrees, including the endpoint values; the second angle θ2 ranges from 135 degrees to 140 degrees, including the endpoint values; and the third angle θ3 ranges from 100 degrees to 150 degrees, including the endpoint values.

[0077] Step S7, as follows Figure 2.11 As shown, a transparent conductive layer 5 is deposited on the upper surface of the P-type semiconductor layer 23 and the surface of the current blocking layer 31. The transparent conductive layer 5 includes a second opening K2, and the second opening K2 exposes the first opening K1 and part of the current blocking layer 31. The first opening K1 and the second opening K2 form a P-type electrode step.

[0078] In this embodiment, the transparent conductive layer is a material with high transparency, high conductivity and low contact resistance. This embodiment does not limit the specific material of the transparent conductive layer. Optional materials for the transparent conductive layer include NiAu (nickel-gold) alloy, indium tin oxide (ITO), indium zinc oxide, etc.

[0079] Step S8, as follows Figure 2.12 As shown, an N-type electrode 6 is deposited on the N-type mesa C; a P-type electrode 7 is deposited on the P-type electrode step, and the P-type electrode 7 connects the P-type semiconductor layer 23, the current blocking layer 31 and the transparent conductive layer 5.

[0080] In this embodiment, the N-type electrode and the P-type electrode can be made of the same material or different materials. To enable the N-type and P-type electrodes to be fabricated in the same step, simplifying the LED chip manufacturing process and reducing costs, in this embodiment, optionally, the N-type and P-type electrodes are made of the same material. This embodiment does not limit the specific materials of the N-type and P-type electrodes; optionally, the N-type and P-type electrodes are made of high-conductivity materials, such as one or more of the following metals: Cr, Ni, Al, Ti, Pt, Au, etc.

[0081] Step S9, as follows Figure 2.13 As shown, an insulating protective layer 8 is deposited on the entire surface, and N-type electrode 6 and P-type electrode 7 are exposed by photolithography and etching. The insulating protective layer 8 covers the transparent conductive layer 5, the exposed surface of the epitaxial structure 2 and the cleavage A1.

[0082] It should be noted that the present embodiment improves the reverse pressure reliability of the LED chip by arranging the insulating protective layer.

[0083] Preferably, as shown in the figure, the insulating protective layer 8 comprises an adhesion layer 81, a dense layer 82 and a hydrophobic layer 83 stacked in order from bottom to top. The adhesion layer can firmly adhere to the epitaxial structure, the dense layer can effectively prevent external water vapor from penetrating, and the hydrophobic layer can avoid water vapor from adhering to the surface of the insulating protective layer. Figure 2.14 Preferably, the adhesion layer 81 comprises one or any combination of nitride and oxide; the dense layer 82 comprises oxide; and the hydrophobic layer 83 comprises one or any combination of hydrophobic group organic material, alkane compound and organosilicon compound.

[0084] Preferably, the adhesion layer 81 comprises one or any combination of silicon nitride and zirconium oxide; the dense layer 82 comprises one or any combination of aluminum oxide and hafnium oxide; and the hydrophobic layer 83 comprises one or any combination of trifluoromethyl, methyl, phenyl, polyethylene, polypropylene and polysiloxane.

[0085] Preferably, the refractive index of the adhesion layer 81 > the refractive index of the dense layer 82 > the refractive index of the hydrophobic layer 83. In the light emitting direction, the refractive index of each layer of the insulating protective layer decreases in order from bottom to top, which is beneficial to the light emission of the LED chip.

[0086] Preferably, the refractive index of the adhesion layer 81 is greater than 2.0; the refractive index of the dense layer 82 is between 1.6 and 2.0; and the refractive index of the hydrophobic layer 83 is less than 1.6.

[0087] In the present embodiment, the thickness of the adhesion layer 81 is in the range of 200 angstroms to 800 angstroms, the thickness of the dense layer 82 is in the range of 1000 angstroms to 1500 angstroms, and the thickness of the hydrophobic layer 83 is in the range of 200 angstroms to 800 angstroms.

[0088] The present embodiment provides an LED chip made by the above manufacturing method, as shown in the figure, the LED chip comprises:

[0089] Figure 3 a substrate 1;

[0090] a substrate 1;

[0091] In the present embodiment, the specific type of the substrate is not limited, and the substrate can be a semiconductor substrate such as a sapphire substrate, a silicon substrate or a silicon carbide substrate. The specific material of the substrate can be selected according to the needs, and the present embodiment does not limit this.

[0092] ​An epitaxial structure 2 is arranged on the surface of the substrate 1, and the epitaxial structure 2 comprises, from bottom to top, an N-type semiconductor layer 21, an active region 22 and a P-type semiconductor layer 23 stacked on the substrate 1 in sequence, and the epitaxial structure 2 has an inclined surface;

[0093] In the embodiment, the specific materials of the N-type semiconductor layer and the P-type semiconductor layer are not limited, and the N-type semiconductor layer can be an N-type GaN layer and the P-type semiconductor layer can be a P-type GaN layer.

[0094] In the embodiment, the specific number of layers and structure of the epitaxial structure are not limited, and the epitaxial structure at least comprises the N-type semiconductor layer, the active region and the P-type semiconductor layer, and in other embodiments, in order to improve lattice matching, the epitaxial structure of the LED chip can further comprise a superlattice structure and the like.

[0095] An upper surface of the P-type semiconductor layer 23 is provided with a groove extending towards the substrate 1 and exposing the substrate 1, forming a cutting path A1, and the cutting path A1 surrounds the epitaxial structure 2;

[0096] An upper surface of the P-type semiconductor layer 23 is provided with a groove extending towards the N-type semiconductor layer 21 and exposing the N-type semiconductor layer 21, forming an N-type region mesa C, and the N-type region mesa C is provided with an N-type electrode 6;

[0097] Reference Figure 2.11 As shown in the figure, a current blocking layer 31 is arranged on a side surface of the P-type semiconductor layer 23 away from the active region 22, the current blocking layer 31 comprises a first opening K1, and the first opening K1 exposes the P-type semiconductor layer 23;

[0098] In the embodiment, the specific shape of the current blocking layer is not limited, and the shape of the current blocking layer can be annular or other geometric shapes comprising the first opening.

[0099] In the embodiment, the specific material of the current blocking layer is not limited, and the current blocking layer can be silicon dioxide or silicon nitride.

[0100] It should be noted that, by arranging the current blocking layer, the current crowding caused by the vertical injection of current at the P-type electrode can be improved, the current diffusion is improved, the light absorption of the P-type electrode is reduced, the quantum efficiency is improved, and the luminous brightness of the LED chip is improved.

[0101] Reference Figure 2.11 As shown in the figure, a transparent conductive layer 5 is arranged on the upper surface of the P-type semiconductor layer 23 and the surface of the current blocking layer 31, the transparent conductive layer 5 comprises a second opening K2, and the second opening K2 exposes the first opening K1 and part of the current blocking layer 31, and the first opening K1 and the second opening K2 form a P-type electrode step;

[0102] The transparent conductive layer in the embodiment is a material with high transparency, high conductivity and low contact resistance. In the embodiment, the specific material of the transparent conductive layer is not limited. Optionally, the material of the transparent conductive layer is NiAu (nickel gold) alloy, indium tin oxide (ITO), indium zinc oxide or the like.

[0103] The P-type electrode 7 is arranged at the P-type electrode step, and the P-type electrode 7 is connected with the P-type semiconductor layer 23, the current blocking layer 31 and the transparent conductive layer 5.

[0104] In the embodiment, the material of the N-type electrode and the material of the P-type electrode can be the same or different. In order to make the N-type electrode and the P-type electrode be formed by the same step, simplify the process steps of the LED chip and reduce the manufacturing cost, in the embodiment, the material of the N-type electrode and the material of the P-type electrode are the same. In the embodiment, the specific material of the N-type electrode and the P-type electrode is not limited. Optionally, the N-type electrode and the P-type electrode are high conductivity materials, such as one or more of Cr, Ni, Al, Ti, Pt, Au and the like.

[0105] The insulating protective layer 8 covers the transparent conductive layer 5, the exposed surface of the epitaxial structure 2 and the cutting path A1.

[0106] It should be noted that the insulating protective layer is arranged to improve the reverse pressure reliability of the LED chip.

[0107] Preferably, as shown in Figure 2.14 Preferably, the insulating protective layer 8 includes an adhesion layer 81, a dense layer 82 and a hydrophobic layer 83 stacked in order from bottom to top. The adhesion layer can firmly adhere to the epitaxial structure, the dense layer can effectively prevent external water vapor from penetrating, and the hydrophobic layer can avoid water vapor from adhering to the surface of the insulating protective layer.

[0108] Preferably, the adhesion layer 81 includes one or any combination of nitride and oxide; the dense layer 82 includes oxide; and the hydrophobic layer 83 includes one or any combination of hydrophobic group organic material, alkane compound and organosilicon compound.

[0109] Preferably, the adhesion layer 81 includes one or any combination of silicon nitride and zirconium oxide; the dense layer 82 includes one or any combination of aluminum oxide and hafnium oxide; and the hydrophobic layer 83 includes one or any combination of trifluoromethyl, methyl, phenyl, polyethylene, polypropylene and polysiloxane.

[0110] Preferably, the refractive index of the adhesion layer 81 > the refractive index of the dense layer 82 > the refractive index of the hydrophobic layer 83. In the light emitting direction, the refractive index of each layer of the insulating protective layer decreases in order from bottom to top, which is beneficial to the light emission of the LED chip.

[0111] Preferably, the refractive index of the adhesion layer 81 is greater than 2.0; the refractive index of the dense layer 82 is between 1.6 and 2.0; and the refractive index of the hydrophobic layer 83 is less than 1.6.

[0112] In this embodiment, the thickness of the adhesion layer 81 is between 200 angstroms and 800 angstroms, the thickness of the dense layer 82 is between 1000 angstroms and 1500 angstroms, and the thickness of the hydrophobic layer 83 is between 200 angstroms and 800 angstroms.

[0113] Preferably, the inclined surface comprises a first inclined surface, a second inclined surface, and a third inclined surface, the first inclined surface is the inclined surface from the upper surface of the epitaxial structure 2 to the cutting groove A1, the included angle between the first inclined surface and the cutting groove A1 is the first angle θ1; the second inclined surface is the inclined surface from the upper surface of the epitaxial structure 2 to the N-type region mesa C, the included angle between the second inclined surface and the N-type region mesa C is the second angle θ2; the third inclined surface is the inclined surface from the N-type region mesa C to the cutting groove A1, the included angle between the third inclined surface and the cutting groove A1 is the third angle θ3.

[0114] Preferably, the first angle θ1 is in the range of 120 degrees to 150 degrees, inclusive; the second angle θ2 is in the range of 135 degrees to 140 degrees, inclusive; and the third angle θ3 is in the range of 100 degrees to 150 degrees, inclusive.

[0115] In this embodiment, the depth from the upper surface of the epitaxial structure 2 to the N-type region mesa C is 0.8 μm to 1.6 μm, not including the end point value.

[0116] In this embodiment, the depth from the upper surface of the epitaxial structure 2 to the cutting groove A1 is 3 μm to 8 μm, not including the end point value.

[0117] In summary, the above technical solutions achieve the following effects:

[0118] 1. The LED chip manufacturing method provided in the embodiment, by means of photolithography and etching, the blocking layer is processed in a pattern, realizing a photolithography process to form the current blocking layer and the N region mask at the same time, the current blocking layer can improve the current crowding caused by the vertical injection of the current at the P electrode, improve the current diffusion, reduce the light absorption of the P electrode, improve the quantum efficiency, and further improve the luminous brightness of the LED chip, the N region mask is used to delay the etching of the epitaxial structure in the MESA etching; the P region mask, the N region mask and the cutting path pattern are etched at the same time by dry etching, realizing the formation of the N type region mesa and the cutting path in one etching process, simplifying the process, improving the yield, and the etching surface is all inclined surface, which is beneficial to the deposition of the insulating protective layer in the PV process, the inclined surface of the epitaxial structure and the cutting path are exposed without additional photolithography, and finally protected by the insulating protective layer in the PV process, thereby improving the reliability of the LED chip.

[0119] 2. Further, the etching rate of the epitaxial structure is S1, the etching rate of the N region mask is S2, and the etching rate of the P region mask is S3, wherein S1=S3>S2, that is, the etching rates of the epitaxial structure and the P region mask are the same under the same etching conditions, and the etching rates of the epitaxial structure and the P region mask are faster than the etching rate of the N region mask, in the dry etching process, the P region mask, the N region mask and the cutting path pattern (i.e. the epitaxial structure in the cutting path pattern area) are etched at the same time, after the N region mask is etched, the epitaxial structure in the P region mask, the N region mask area and the epitaxial structure in the cutting path pattern area are etched at the same time, and then the etching depth of the cutting path is greater than the etching depth of the N type region mesa, realizing the formation of two different etching depths in one etching process.

[0120] 3. Further, the insulating protective layer is provided to improve the reverse pressure reliability of the LED chip, the insulating protective layer comprises an adhesion layer, a dense layer and a hydrophobic layer stacked in order from bottom to top, the adhesion layer can firmly adhere to the epitaxial structure, the dense layer can effectively prevent external moisture from penetrating, and the hydrophobic layer can avoid the attachment of water vapor on the surface of the insulating protective layer.

[0121] 4. Further, the refractive index of the adhesion layer is greater than the refractive index of the dense layer, and the refractive index of the dense layer is greater than the refractive index of the hydrophobic layer, along the light emitting direction, the refractive index of each layer of the insulating protective layer decreases in order from bottom to top, which is beneficial to the light emission of the LED chip.

[0122] 5. The LED chip provided in the embodiment is manufactured by using the LED chip manufacturing method described above, which can effectively improve the luminous brightness and reliability of the LED chip.

[0123] Those skilled in the art will understand that the terms "transverse", "longitudinal", "upper", "lower" and the like designate orientation or positional relationships in the disclosure as shown in the drawings with reference to which the application will be described and illustrated, and that such terms are used only on the basis of the drawings for convenience and simplification of description and do not indicate or imply that the referred device or element must be in a particular orientation, constructed and operated in a particular orientation, and therefore should not be construed as limiting the application.

[0124] It should be noted that each of the embodiments in the present specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be mutually referred to.

[0125] The above description of disclosed embodiments enables a person skilled in the art to implement or use the application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the application. Therefore, the application will not be limited to these embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method of fabricating an LED chip, the method comprising: The application relates to a method for manufacturing a semiconductor laser diode, which comprises the following steps: ​ S1, providing a substrate; S2, depositing an epitaxial structure on the substrate, the epitaxial structure comprising, in sequence from the substrate, a N-type semiconductor layer, an active region and a P-type semiconductor layer; S3, depositing an integral blocking layer on the epitaxial structure; S4, performing a photolithography and etching process on the blocking layer to form a current blocking layer and a N-region mask, the current blocking layer comprising a first opening, and the first opening exposing the P-type semiconductor layer; S5, forming a P-region mask by mask photolithography, the P-region mask covering the current blocking layer, part of the N-region mask and part of the P-type semiconductor layer, and defining a cutting path pattern on the upper surface edge of the P-type semiconductor layer, and the overlapping part of the P-region mask and the N-region mask being an overlapping region; S6, simultaneously etching the P-region mask, the N-region mask and the cutting path pattern to form a N-type region mesa and a cutting path, and the etching surfaces being inclined surfaces; S7, depositing a transparent conductive layer on the upper surface of the P-type semiconductor layer and the surface of the current blocking layer, the transparent conductive layer comprising a second opening, and the second opening exposing the first opening and part of the current blocking layer, and the first opening and the second opening forming a P-type electrode step; S8, depositing a N-type electrode on the N-type region mesa; S9, depositing an integral insulating protective layer, and exposing the N-type electrode and the P-type electrode by photolithography and etching, the insulating protective layer covering the transparent conductive layer, the exposed surface of the epitaxial structure and the cutting path. The inclined surfaces comprise a first inclined surface, a second inclined surface and a third inclined surface, the first inclined surface being the inclined surface from the upper surface of the epitaxial structure to the cutting path, the included angle between the first inclined surface and the cutting path being a first angle; the second inclined surface being the inclined surface from the upper surface of the epitaxial structure to the N-type region mesa, the included angle between the second inclined surface and the N-type region mesa being a second angle; and the third inclined surface being the inclined surface from the N-type region mesa to the cutting path, the included angle between the third inclined surface and the cutting path being a third angle. The first angle ranges from 120 degrees to 150 degrees, including the end point value; the second angle ranges from 135 degrees to 140 degrees, including the end point value; and the third angle ranges from 100 degrees to 150 degrees, including the end point value. ​ ​ ​ 2. The method of claim 1, wherein: ​ 3. The method of claim 2, wherein: ​ 4. The method of claim 1, wherein: In the dry etching of the step S6, the etching rate of the epitaxial structure is S1, the etching rate of the N region mask is S2, and the etching rate of the P region mask is S3, wherein S1=S3>S2.

5. The method of claim 1, wherein: In the dry etching of the step S6, the etching selectivity ratio of the epitaxial structure to the N region mask ranges from 4:1 to 8:1, and the etching selectivity ratio of the epitaxial structure to the P region mask is 1:

1.

6. The method of claim 1, wherein: The insulating protective layer comprises, from bottom to top, an adhesion layer, a dense layer and a hydrophobic layer.

7. The method of claim 6, wherein: The adhesion layer comprises one or any combination of nitride, oxide; the dense layer comprises oxide; and the hydrophobic layer comprises one or any combination of hydrophobic group organic material, alkane compound, organosilicon compound.

8. The method of claim 7, wherein: The adhesion layer comprises one or any combination of silicon nitride, zirconium oxide; the dense layer comprises one or any combination of aluminum oxide, hafnium oxide; and the hydrophobic layer comprises one or any combination of trifluoromethyl, methyl, phenyl, polyethylene, polypropylene, polysiloxane.

9. The method of claim 6, wherein: The refractive index of the adhesion layer > the refractive index of the dense layer > the refractive index of the hydrophobic layer.

10. The method of claim 9, wherein: The refractive index of the adhesion layer is greater than 2.0; the refractive index of the dense layer is between 1.6 and 2.0; and the refractive index of the hydrophobic layer is less than 1.6.

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