A duty cycle adjustable adaptive resonant driving circuit

Abstract

The application discloses a kind of duty cycle adjustable adaptive resonant driving circuit, for driving switch tube in switching converter, including power part and adaptive control circuit two parts.By controlling the switching timing of switch tube in power part, zero voltage switching of all switch tubes in driving circuit can be realized, and the energy in the input capacitor of the driven power switch tube is fed back to the driving source, effectively reducing the driving loss.Adaptive control circuit adjusts the turn-on time of switch tube in driving circuit by detecting the midpoint voltage of two driving bridge arms, which can ensure soft switching of all switch tubes in driving circuit at any duty cycle.The control method proposed by the application is simple and practical, and can well solve the shortcoming that traditional resonant driving circuit cannot adjust duty cycle.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of control of power electronic converters, and particularly to a duty cycle adjustable adaptive resonant driving circuit. BACKGROUND

[0002] The passive devices such as transformers, inductors and filter capacitors in the internal switching converter of a switching power supply account for more than 70% of the volume of the switching power supply, greatly limiting the improvement of the power density. Raising the switching frequency of the switching converter to the MHz level can greatly reduce the volume of the transformers, inductors and filter capacitors therein, thereby greatly improving the power density of the switching power supply. However, raising the switching frequency brings many challenges. On the one hand, raising the switching frequency will cause the switching loss to rise sharply, reducing the overall conversion efficiency of the converter. In view of this problem, domestic and foreign scholars have carried out in-depth research and proposed a variety of switching converters suitable for MHz switching frequency level, such as LLC resonant converter, four-tube soft-switching Buck-Boost converter, multi-phase coupled inductor Buck converter, etc., so that very high conversion efficiency can still be achieved in MHz level application occasions.

[0003] In order to drive the switching tube in the switching converter, a totem pole or an integrated commercial driving chip needs to be used to power amplify the driving control signal. The existing commercial driving chip integrates additional circuits while realizing the driving capability, can realize protection or logic control functions, and realizes miniaturization at the same time. Essentially, the core of most commercial driving chips is also a totem pole. The most basic totem pole circuit is composed of a bridge arm circuit. When the driving signal is high, the upper tube is turned on, the power supply charges the gate capacitance of the switching tube through the driving current-limiting resistor, and the switching tube is turned on; when the driving signal is low, the lower tube is turned on, and the gate capacitance of the switching tube is discharged through the driving resistor, and its energy is consumed in the driving circuit. It can be found that in the switching process, the driving loss is mainly the energy stored in the gate parasitic capacitance of the power switch, which generally changes little with the power of the power stage, and linearly increases with the increase of the switching frequency, which is a constant inherent loss, so it has a great influence on the light load efficiency of the switching converter. In particular, the package of the existing commercial driving chip is usually small, and the large heat dissipation will cause difficulty in heat dissipation. This is also a big challenge for the high frequency of the switching converter. Therefore, it is necessary to study the method of reducing the driving loss.

[0004] In order to reduce the drive loss, the drive circuit can also adopt a soft switching control strategy to reduce the drive loss. In this regard, the Vicor company of the United States proposes a simple and feasible resonant drive suitable for a resonant converter, which includes two bridge arms, and for the sake of distinction, the two bridge arms are referred to as a first bridge arm and a second bridge arm. Among them, two upper tubes are P-channel MOSFETs, and two lower tubes are N-channel MOSFETs; the gate level of the first bridge arm lower tube is connected with the midpoint of the second bridge arm, and the gate level of the second bridge arm lower tube is connected with the midpoint of the first bridge arm, forming a drive interlock; the gate level of the two upper tube PMOS is the input of the two-way drive control signal; the midpoints of the two bridge arms are connected to the two ends of the primary winding of the drive transformer, which is used for exciting the transformer, and the secondary winding of the transformer can directly drive the switch tube. It is worth noting that the midpoints of the first bridge arm and the second bridge arm can also directly drive the power switch tube which is common with the power supply of the drive circuit. In the drive circuit, soft switching of all drive switch tubes can be realized, and at the same time, the recycling of the gate drive charge of the power switch tube is realized, thereby reducing the drive loss. In this scheme, the output drive duty cycle is slightly less than 0.5. In order to adjust the dead time, the rising speed of the rising edge of the drive can be adjusted by adjusting the excitation inductance of the drive transformer. However, it is not convenient to adjust the excitation inductance. In particular, for the DCX-LLC resonant converter, the drive method has the following two shortcomings, one is that the DCX-LLC resonant converter generally adopts a soft start method with adjustable width, and since the drive duty cycle is not adjustable, the drive method limits the soft start strategy of the DCX-LLX; two is that in order to optimize the light load efficiency, it is generally necessary to adjust the switch tube duty cycle, and obviously the fixed duty cycle also limits the optimization of the power circuit. In order to solve the above-mentioned shortcomings while ensuring small drive loss, it is necessary to study a duty cycle adjustable resonant drive method. SUMMARY

[0005] The present application aims to provide a duty cycle adjustable adaptive resonant drive circuit, which can realize soft switching of the drive circuit and adjustable duty cycle.

[0006] The technical solution for achieving the purpose of the present application is as follows: a duty cycle adjustable adaptive resonant drive circuit for driving a switch tube in a switching converter, comprising a power part and an adaptive control circuit, by controlling the switching time sequence of the switch tube in the power part, realizing zero voltage switching of all switch tubes in the drive circuit, and feeding back the energy in the input capacitor of the driven power switch tube to the drive source; the adaptive control circuit detects the midpoint voltage of the two drive bridge arms, and adaptively adjusts the turn-on time of the switch tube in the drive circuit to realize soft switching of all switch tubes in the drive circuit at any duty cycle.

[0007] Further, the power part comprises: a drive power supply V D, first auxiliary resonance capacitor C a1 , second auxiliary resonance capacitor C a2 and driving transformer T1; the positive pole of the driving power supply V D is connected with the D end of the first switch tube Q1 and the third switch tube Q3, the negative pole of the driving power supply V D is connected with the S end of the second switch tube Q2 and the fourth switch tube Q4, the one end of the first auxiliary capacitor C a1 , the one end of the second auxiliary capacitor C a2 ; the S end of the first switch tube Q1 is connected with the D end of the second switch tube Q2, the other end of the first auxiliary capacitor C a1 and the one end of the driving transformer T1; the S end of the third switch tube Q3 is connected with the D end of the fourth switch tube Q4, the other end of the second auxiliary capacitor C a2 and the other end of the driving transformer T1.

[0008] Further, the duty cycle pulse width of the driving signal v gs1 of the first switch tube Q1 and the driving signal v gs3 of the third switch tube Q3 is same, and the phase difference is 180°.

[0009] Further, the duty cycle pulse width of the driving signal v gs2 of the second switch tube Q2 and the driving signal v gs4 of the fourth switch tube Q4 is same, and the phase difference is 180°.

[0010] Further, the duty cycle center of the driving signal v gs1 of the first switch tube Q1 and the driving signal v gs2 of the second switch tube Q2 is aligned.

[0011] Further, the turn-on time of the first switch tube Q1 is when the first bridge arm midpoint voltage v A rises to the driving power voltage time, the turn-on time of the third switch tube Q3 is when the second bridge arm midpoint voltage v B rises to the driving power voltage time, the turn-on time of the second switch tube Q2 is when the first bridge arm midpoint voltage v A drops to 0 time, and the turn-on time of the fourth switch tube Q4 is when the second bridge arm midpoint voltage v B drops to 0 time.

[0012] Further, the adaptive control circuit comprises a PWM generating unit, a frequency division circuit, a hysteresis comparison unit 1, a logic operation unit 1, an RS flip-flop 1, a driving unit 1, a logic operation unit 2, a minimum duty cycle limiting unit 1, an RS flip-flop 2, a driving unit 2, a hysteresis comparison unit 2, a minimum duty cycle limiting unit 2, a logic operation unit 3, an RS flip-flop 3, a driving unit 3, a logic operation unit 4, an RS flip-flop 4, and a driving unit 4.

[0013] The PWM generating unit is configured to generate a required duty cycle according to an input control signal v m and output the required duty cycle to subsequent logic units for generating driving signals v gs1 ~v gs4 .

[0014] The frequency division circuit is configured to divide the output signal Q D of the PWM generating unit by two to generate two control signals v Q1 and v Q2 with halved frequency and 180° phase difference.

[0015] The hysteresis comparison unit 1 is configured to determine a soft switching state according to the first bridge arm midpoint voltage v A and generate a logic level v cA .

[0016] The hysteresis comparison unit 2 is configured to determine a soft switching state according to the second bridge arm midpoint voltage v B and generate a logic level v cB .

[0017] The logic operation unit 1 is connected to the output v cA of the hysteresis comparison unit 1 and the output v Q1 of the frequency division circuit, and is configured to extract a rising edge of the logic level v cA .

[0018] The RS flip-flop 1 is connected to the output v c1 of the logic operation unit 1 and the output v Q1 of the frequency division circuit, and is configured to control the turn-on and turn-off time of the second switch Q2, thereby generating a driving control signal of the second switch Q2.

[0019] The logic operation unit 2 is connected to the output v cA of the hysteresis comparison unit 1 and the output v Q1 of the frequency division circuit, and is configured to extract a falling edge of the logic level v cA .

[0020] The minimum duty cycle limiting unit 1 is configured to extract the output vQ1 the falling edge signal of the output v

[0021] The RS flip-flop 2 is connected with the output v c2 of the minimum duty cycle limiting unit 1 and the output v c3 of the frequency dividing circuit, for controlling the turn-on time and turn-off time of the first switch tube Q1, thereby generating the driving control signal of the first switch tube Q1.

[0022] The minimum duty cycle limiting unit 2 is used for extracting the falling edge signal of the output v Q2 of the frequency dividing circuit and generating a narrow pulse signal according to the delay of the duty cycle requirement.

[0023] The logic operation unit 3 is connected with the output v cB of the hysteresis comparison unit 2 and the output v Q2 of the frequency dividing circuit, for extracting the rising edge of the logic level v cB .

[0024] The RS flip-flop 3 is connected with the output v c5 of the logic operation unit 3 and the output v c4 of the minimum duty cycle limiting unit 2, for controlling the turn-on time and turn-off time of the third switch tube Q3, thereby generating the driving control signal of the third switch tube Q3.

[0025] The logic operation unit 4 is connected with the output v cB of the hysteresis comparison unit 2 and the output v Q2 of the frequency dividing circuit, for extracting the rising edge of the logic level v cB .

[0026] The RS flip-flop 4 is connected with the output v c6 of the logic operation unit 4 and the output v Q2 of the frequency dividing circuit, thereby generating the driving control signal of the third switch tube Q3.

[0027] The driving units 1-4 are respectively connected with the RS flip-flops 1-4, for power amplifying the driving control signals of the first switch tube Q1-fourth switch tube Q4, thereby generating the driving signals v gs1 -v gs4 , for driving the switch tubes.

[0028] Further, the SET port and RESET port of the RS flip-flop 1 are respectively connected with the output v c1 of the logic operation unit 1 and the output v Q1 of the frequency dividing circuit; the SET port and RESET port of the RS flip-flop 2 are respectively connected with the output v of the logic operation unit 2 and the output v of the frequency dividing circuit.c2 and the output v of the minimum duty cycle limiting unit 1 c3 ; the SET port and the RESET port of the RS flip-flop 3 are connected with the output v of the logic operation unit 3 respectively c5 and the output v of the minimum duty cycle limiting unit 2 c4 ; the SET port and the RESET port of the RS flip-flop 4 are connected with the output v of the logic operation unit 4 respectively c6 and the output v of the frequency dividing circuit Q2 .

[0029] Compared with the prior art, the present application has the following advantages:

[0030] 1. Soft switching of all switch tubes in the driving circuit can be realized.

[0031] 2. Compared with the traditional resonant driving, the duty cycle can be freely adjusted.

[0032] 3. Soft switching of all switch tubes can be realized adaptively under different duty cycles.

[0033] The present application will be described in further detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is the main power topology diagram of the duty cycle adjustable adaptive resonant driving of the present application.

[0035] Figure 2 is the adaptive control block diagram of the duty cycle adjustable adaptive resonant driving of the present application.

[0036] Figure 3 is the main working waveform diagram of the proposed duty cycle adjustable adaptive resonant driving.

[0037] Figure 4 is the relationship diagram of the output driving and the driving signal of the proposed duty cycle adjustable adaptive resonant driving circuit.

[0038] Figure 5 is the amplified waveform diagram at time 1. Figure 4

[0039] Figure 6 is the amplified waveform diagram at time 2. Figure 4

[0040] Figure 7 is the amplified waveform diagram at time 3. Figure 4

[0041] is the waveform diagram of the first bridge arm switch tube GS and DS at time 1. Figure 8

[0042] Figure 9 ​​​is the first bridge arm switch tube GS and DS waveform chart at time 2.

[0043] Figure 10 is the first bridge arm switch tube GS and DS waveform chart at time 3. DETAILED DESCRIPTION

[0044] The application will be further described in conjunction with the accompanying drawings and by way of examples, the following examples are an explanation of the application and the application is not limited to the following examples.

[0045] The application provides a duty cycle adjustable adaptive resonance driving circuit for driving power switch tubes in a switching converter, including a power part and an adaptive control circuit part. By controlling the switching timing of the switch tubes in the power part, zero voltage switching of all switch tubes in the driving circuit is realized, and the energy in the input capacitor of the driven power switch tube is fed back to the driving source; the adaptive control circuit adjusts the turn-on time of the switch tubes in the driving circuit by detecting the midpoint voltage of the two driving bridge arms, so as to realize soft switching of all switch tubes in the driving circuit at any duty cycle.

[0046] As shown in Figure 1 , it is the main circuit part of the duty cycle adjustable adaptive resonance driving circuit, which contains: a driving power supply V D , first to fourth switch tubes Q1-Q4, first and second auxiliary resonance capacitors C a1 -C a2 and a driving transformer T1; the positive electrode of the driving power supply V D is connected with the D end of the first and third switch tubes Q1 and Q3, the negative electrode of the driving power supply V D is connected with the S end of the second and fourth switch tubes Q2 and Q4, one end of the first auxiliary capacitor C a1 and one end of the second auxiliary capacitor C a2 ; the S end of the first switch tube Q1 is connected with the D end of the second switch tube Q2, the other end of the first auxiliary capacitor C a1 and one end of the driving transformer T1; the S end of the third switch tube Q3 is connected with the D end of the fourth switch tube Q4, the other end of the second auxiliary capacitor C a2 and the other end of the driving transformer T1.

[0047] It should be noted that the auxiliary capacitors C a1 and C a2 can be added as needed, in addition, a main switch tube gate capacitance C gs can also be used as an auxiliary capacitor.

[0048] Further, in one of the embodiments, the driving signal v gs1and the drive signal v of the third switch Q3 gs3 The duty cycle pulse widths are the same, but the phase difference is 180°; the drive signal v of the second switch Q2 gs2 and the drive signal v of the fourth switch Q4 gs4 The drive signals have the same duty cycle and pulse width, but are 180° out of phase; the drive signal v of the first switch Q1 gs1 The drive signal v of the second switch Q2 gs2 The duty cycle is center aligned.

[0049] Furthermore, in one embodiment, the turn-on time of the first switch Q1 is the midpoint voltage v of the first bridge arm. A When the voltage rises to the drive supply voltage, the turn-on time of the third switch Q3 is the midpoint voltage v of the second bridge arm. B When the voltage rises to the drive supply voltage, the turn-on time of the second switch Q2 is the midpoint voltage v of the first bridge arm. A When the voltage drops to 0, the turn-on time of the fourth switch Q4 is the midpoint voltage v of the second bridge arm. B It drops to 0.

[0050] It should be noted that only two drive windings are shown here. Optionally, for a specific switching topology, additional windings can be added to drive switching transistors that have the same drive control signal as the excitation signal.

[0051] like Figure 2 The adaptive control circuit shown includes a PWM generation unit, a frequency divider circuit, a hysteresis comparison unit 1, a logic operation unit 1, an RS flip-flop 1, a drive unit 1, a logic operation unit 2, a minimum duty cycle limiting unit 1, an RS flip-flop 2, a drive unit 2, a hysteresis comparison unit 2, a minimum duty cycle limiting unit 2, a logic operation unit 3, an RS flip-flop 3, a drive unit 3, a logic operation unit 4, an RS flip-flop 4, and a drive unit 4.

[0052] The PWM generation unit is used to generate the PWM signal based on the input control signal v. m The required duty cycle is generated and output to subsequent logic units to generate the drive signals v for the first switch Q1 to the fourth switch Q4. gs1 ~v gs4 ;

[0053] The frequency divider circuit is used to divide the output signal Q of the PWM generation unit. D The frequency is divided by two to generate two control signals v with half the frequency and 180° out of phase. Q1 and v Q2 ;

[0054] The hysteresis comparator 1 is used to determine the voltage v at the midpoint of the first bridge arm.A determining soft switching state, generating logic level v cA ;

[0055] the hysteresis comparison unit 2 is used for determining soft switching state according to the second bridge arm midpoint voltage v B determining soft switching state, generating logic level v cB ;

[0056] the logic operation unit 1 is connected with the output v cA of the hysteresis comparison unit 1 and the output v Q1 of the frequency division circuit, used for extracting the rising edge of the logic level v cA and generating the narrow pulse width v c1 , outputting to the RS flip-flop 1;

[0057] the RS flip-flop 1 is connected with the output v c1 of the logic operation unit 1 and the output v Q1 of the frequency division circuit, used for controlling the turn-on and turn-off time of the first switch tube Q1 and generating the driving control signal of the first switch tube Q1;

[0058] the logic operation unit 2 is connected with the output v cA of the hysteresis comparison unit 1 and the output v Q1 of the frequency division circuit, used for extracting the falling edge of the logic level v cA and generating the narrow pulse width signal v c2 , outputting to the RS flip-flop 2;

[0059] the minimum duty cycle limiting unit 1 is used for extracting the falling edge signal of the output v Q1 of the frequency division circuit and generating the narrow pulse signal according to the delay set by the duty cycle requirement, generating the narrow pulse signal v c3 , outputting to the RS flip-flop 2;

[0060] the RS flip-flop 2 is connected with the output v c2 of the logic operation unit 2 and the output v c3 of the minimum duty cycle limiting unit 1, used for controlling the turn-on time and turn-off time of the second switch tube Q2, thereby generating the driving control signal of the second switch tube Q2;

[0061] the minimum duty cycle limiting unit 2 is used for extracting the falling edge signal of the output v Q2 of the frequency division circuit and generating the narrow pulse signal according to the delay set by the duty cycle requirement, generating the narrow pulse signal v c4 , outputting to the RS flip-flop 3;

[0062] the logic operation unit 3 is connected with the output v cB of the hysteresis comparison unit 2 and the output vQ2 the rising edge of the logic level v cB , and generates a narrow pulse signal v c5 , which is output to the RS flip-flop 3.

[0063] The RS flip-flop 3 is connected with the output v c5 of the logic operation unit 3 and the output v c4 of the minimum duty cycle limiting unit 2, and is used to control the turn-on time and turn-off time of the third switch tube Q3, thereby generating the driving control signal of the third switch tube Q3.

[0064] The logic operation unit 4 is connected with the output v cB of the hysteresis comparison unit 2 and the output v Q2 of the frequency division circuit, and is used to extract the rising edge of the logic level v cB , and generates a narrow pulse signal v c6 , which is output to the RS flip-flop 4.

[0065] The RS flip-flop 4 is connected with the output v c6 of the logic operation unit 4 and the output v Q2 of the frequency division circuit, thereby generating the driving control signal of the third switch tube Q3.

[0066] The driving units 1-4 are respectively connected with the RS flip-flops 1-4, and are used to power amplify the driving control signals of the first switch tube Q1-fourth switch tube Q4, thereby generating driving signals v gs1 -v gs4 , and driving the switch tubes.

[0067] As shown in Figure 3 , a working waveform diagram of the duty cycle adjustable adaptive resonant driving circuit is given, wherein V gs1 -V gs4 are the driving waveforms of the switch tubes in the driving circuit, v A -v B are the midpoint voltages of the first bridge arm and the second bridge arm, respectively. v cA and v cA are the output signals of the hysteresis comparison units 1-2, v QD is the driving signal of the PWM generating unit, v Q1 and v Q2 are the output signals of the frequency division circuit, v c1 -v c6 are the input signals of the RS flip-flops 1-4, respectively.

[0068] The functions of the duty cycle adjustable adaptive resonant driving circuit will be described below in combination with Figure 3 .

[0069] 1) The PWM generation unit controls the signal v based on the duty cycle. m Generates a signal v at twice the switching frequency QD v QD The control signal v, output by the frequency divider circuit, has a frequency equal to the switching frequency and a phase difference of 180°. Q1 and v Q2 v Q1 Used to control the generation of drive signals for switching transistors Q1 and Q3, v Q2 It is used to control the generation of drive signals for switching transistors Q2 and Q4, thereby achieving a 180° phase difference between switching transistors Q1 and Q3, and between switching transistors Q2 and Q4.

[0070] 2) The output signal v of the frequency divider circuit Q1 The input is sent to the RESET pin of RS flip-flop 1, v Q1 When set high, the output of RS flip-flop 1 is reset, that is, the second switch Q2 is turned off; when the voltage at the midpoint of the first bridge arm is v A Below the benchmark value V L At that time, the output of hysteresis comparator 1 is v cA Set it low, and its relationship with v Q1 The logic operation unit 1 performs logic operations to extract v. cA At the falling edge time, a narrow pulse v is generated. c1 v c1 The input is sent to the SET pin of RS flip-flop 1, v c1 If set high, the output of RS flip-flop 1 will be set high, that is, the switch Q2 will be turned on.

[0071] When the voltage at the midpoint of the first bridge arm is v A Higher than the benchmark value V H At that time, the output of hysteresis comparator 1 is v cA Set high, which is related to v Q1 The logic operation unit 2 performs logic operations to extract v. cA The rising edge generates a narrow pulse v. c2 v c2 The input is sent to the SET pin of RS flip-flop 1, v c2 When set high, the output of RS flip-flop 2 is set high, meaning the first switch Q1 is turned on; the minimum duty cycle limiting unit 1 is used to extract the output v of the divide-by-two circuit. Q1 The falling edge, after a minimum duty cycle delay, generates a narrow pulse v. c3 v c3 The input is sent to the RESET pin of RS flip-flop 2, v c3 When the jump occurs, the output of RS flip-flop 2 is set low, meaning the first switch Q1 is turned off.

[0072] 3) Minimum duty cycle limiting unit 2 is used to extract the output v of the frequency divider circuit.Q2 The falling edge, after a minimum duty cycle delay, generates a narrow pulse v. c4 v c4 The input is sent to the RESET pin of RS flip-flop 3, v c4 When the voltage jumps, the output of RS flip-flop 3 is set low, meaning the third switch Q3 is turned off; when the voltage at the midpoint of the second bridge arm v... B Higher than the benchmark value V H At that time, the output of hysteresis comparator 2 is v cB Set high, which is related to v Q2 The logic operation unit 3 performs logic operations to extract v. cB At the rising edge time, and generate a narrow pulse width v c5 v c5 When the input is sent to the SET pin of RS flip-flop 3, V5 jumps high, the output of RS flip-flop 3 is set high, that is, the third switch Q3 is turned on.

[0073] 4) When the voltage at the midpoint of the second bridge arm is v B Below the benchmark value V L At that time, the output of hysteresis comparator 2 is v cB Set it low, and its relationship with v Q2 The logic operation unit 4 performs logic operations to extract v. cB The falling edge generates a narrow pulse width v c6 v c6 The input is sent to the SET pin of RS flip-flop 4, v c6 When set high, the output of RS flip-flop 4 is set high, meaning the fourth switch Q4 is turned on. At this time, switch Q4 is performing soft switching. Q2 The input is sent to the RESET pin of RS flip-flop 4, v Q2 If set high, the output of RS flip-flop 4 is reset, that is, the fourth switch Q4 is turned off.

[0074] Furthermore, it should be noted that in order to achieve zero-voltage turn-on of the soft switches Q1 to Q4, the upper threshold reference value V of hysteresis comparator 1 and hysteresis comparator 2 is... H It should be slightly lower than the power supply voltage V of the drive circuit. D Lower threshold reference value V L It should be slightly higher than 0. Under the premise of satisfying the above conditions, before the switching transistors Q1 to Q4 are turned on, the voltage across the switching transistors is approximately 0, which can just achieve zero-voltage turn-on of the switching transistors. Note that by adding hysteresis comparators 1 to 2, soft switching of the switching transistors can be guaranteed under any duty cycle condition, realizing its adaptive control. On the other hand, due to the clamping effect of the resonant capacitor, the switching transistors Q1 to Q4 can achieve zero-voltage turn-off. It can be found that by using the proposed circuit, the energy in the gate junction capacitance of the driving switching transistors can be recovered, and zero-voltage switching of all switching transistors in the driving circuit can be achieved, which can effectively reduce driving losses.

[0075] Optionally, the driving adaptive circuit can also be realized by a digital controller, which has the same implementation idea as the above-mentioned analog implementation method.

[0076] An application example of the present application is given below.

[0077] The main circuit diagram of the application example is shown in Figure 1 The specific prototype parameters are as follows:

[0078] • Driving power supply voltage: V D = 12V;

[0079] • Switching frequency: f s = 1MHz;

[0080] • Transformer ratio: 1:1;

[0081] • Transformer excitation inductance: L m = 1.5μH;

[0082] • C a1 = C a1 = C gs = 5nF;

[0083] • Minimum on-time of Q1 and Q3: 50ns;

[0084] Figure 4 The working waveform of the duty cycle adjustable adaptive resonance driving width modulation is given, and the waveforms from top to bottom are duty cycle control signal v m , and power switch tube driving signal v gs . Figures 5 to 7 The detailed expansion waveforms at three time points are given respectively. As can be seen from the figure, the amplitude of the duty cycle control signal directly determines the duty cycle of the switch tube driving signal, and the duty cycle of the switch tube driving signal gradually increases with the increase of the control signal v m , which shows that the circuit can effectively adjust the duty cycle according to the amplitude of the control signal.

[0085] Figures 8 to 10 The working waveforms of the upper tube and the lower tube on the first bridge arm at the above-mentioned three time points are given respectively, and the waveforms from top to bottom are upper tube driving waveform v gs1 , upper tube DS waveform v ds1 , lower tube driving waveform v gs2 , and lower tube DS waveform v ds2 . At time 1, it corresponds to Figure 8Due to the minimum duty cycle limit of the upper tube, when the first switch tube Q1 is turned on, the voltage across the two ends of the switch tube is not 0, so the switch tube is hard turned on, and before the switch tube is turned off, the voltage across the two ends of the DS is dropped to 0 in advance, so it is zero voltage turn-off; for the switch tube, at the turn-on and turn-off time, the voltage across the two ends of the DS is 0, realizing the zero voltage turn-on and turn-off of the switch tube. At time 2 and time 3, respectively corresponding Figure 8 and Figure 9 When the switch tubes Q1 and Q2 are turned on and turned off, the voltage across the two ends of the switch tube DS is 0, realizing the zero voltage switching of the switch tube. From the above working waveform, it can be found that when the duty cycle is greater than the minimum duty cycle limit of the upper tube, soft switching of all switch tubes can be realized, which verifies that the adaptive algorithm proposed in the application is feasible and effective.

[0086] The technical solutions of the application are not limited to the above embodiments, and any technical solution obtained by equivalent replacement falls within the scope of the application. Optionally, the driving adaptive circuit can also be realized by a digital controller, and the implementation idea is the same as the above-mentioned analog implementation method.

Claims

1. A duty cycle adjustable adaptive resonant drive circuit for driving a switching transistor in a switching converter, characterized in that, It consists of two parts: a power section and an adaptive control circuit. By controlling the switching timing of the switching transistors in the power section, it achieves zero-voltage switching of all switching transistors in the drive circuit and feeds back the energy from the input capacitor of the driven power switching transistor to the drive source. The adaptive control circuit detects the midpoint voltage of the two drive bridge arms and adaptively adjusts the turn-on time of the switching transistors in the drive circuit to achieve soft switching of all the switching transistors in the drive circuit under any duty cycle. The power section includes: a drive power supply V D First switching transistor Q1 to fourth switching transistor Q4, first auxiliary resonant capacitor C a1 ~Second auxiliary resonant capacitor C a2 The drive transformer T1, wherein the first switch Q1 and the second switch Q2 form the first bridge arm, and the third switch Q3 and the fourth switch Q4 form the second bridge arm; the drive power supply V D The positive terminal is connected to the drain terminals of the first switch Q1 and the third switch Q3, driving the power supply V. D The negative terminal is connected to the source terminal of the second switch Q2 and the fourth switch Q4, and the first auxiliary capacitor C. a1 One end, the second auxiliary capacitor C a2 One end is connected; the source terminal of the first switching transistor Q1 is connected to the drain terminal of the second switching transistor Q2, and the first auxiliary capacitor C. a1 The other end is connected to one end of the drive transformer T1; the S terminal of the third switch Q3 is connected to the D terminal of the fourth switch Q4 and the second auxiliary capacitor C. a2 The other end is connected to the other end of the drive transformer T1; The turn-on time of the first switch Q1 is the voltage v at the midpoint of the first bridge arm. A When the voltage rises to the drive supply voltage, the turn-on time of the third switch Q3 is the midpoint voltage v of the second bridge arm. B When the voltage rises to the drive supply voltage, the turn-on time of the second switch Q2 is the midpoint voltage v of the first bridge arm. A When the voltage drops to 0, the turn-on time of the fourth switch Q4 is the midpoint voltage v of the second bridge arm. B Descending to 0; The adaptive control circuit includes a PWM generation unit, a frequency divider circuit, a hysteresis comparison unit 1, a logic operation unit 1, an RS flip-flop 1, a drive unit 1, a logic operation unit 2, a minimum duty cycle limiting unit 1, an RS flip-flop 2, a drive unit 2, a hysteresis comparison unit 2, a minimum duty cycle limiting unit 2, a logic operation unit 3, an RS flip-flop 3, a drive unit 3, a logic operation unit 4, an RS flip-flop 4, and a drive unit 4.

2. The duty cycle adjustable adaptive resonant drive circuit according to claim 1, characterized in that, The drive signal v of the first switch Q1 gs1 and the drive signal v of the third switch Q3 gs3 They have the same duty cycle and pulse width, but are 180° out of phase.

3. The duty cycle adjustable adaptive resonant drive circuit according to claim 1, characterized in that, The drive signal v of the second switch Q2 gs2 and the drive signal v of the fourth switch Q4 gs4 The drive signals have the same duty cycle and pulse width, but are 180° out of phase.

4. The duty cycle adjustable adaptive resonant drive circuit according to claim 1, characterized in that, The drive signal v of the first switch Q1 gs1 The drive signal v of the second switch Q2 gs2 The duty cycle is center aligned.

5. The duty cycle adjustable adaptive resonant drive circuit according to claim 1, characterized in that, The PWM generation unit is used to generate the PWM signal based on the input control signal v. m The required duty cycle is generated and output to subsequent logic units to generate the drive signals v for the first switch Q1 to the fourth switch Q4. gs1 ~ v gs4 ; The frequency divider circuit is used to divide the output signal Q of the PWM generation unit. D The frequency is divided by two to generate two control signals v with half the frequency and 180° out of phase. Q1 and v Q2 ; The hysteresis comparator 1 is used to determine the voltage v at the midpoint of the first bridge arm. A Determine the soft switch state and generate a logic level v. cA ; The hysteresis comparator 2 is used to determine the voltage v at the midpoint of the second bridge arm. B Determine the soft switch state and generate a logic level v. cB ; The logic operation unit 1, and the output v of the hysteresis comparison unit 1 cA The output v of the frequency divider circuit Q1 Connected, used to extract logic level v cA The rising edge; The RS flip-flop 1, and the output v of the logic operation unit 1 c1 The output v of the frequency divider circuit Q1 Connected, it is used to control the turn-on and turn-off times of the first switch Q2, thereby generating the drive control signal for the second switch Q2; The logic operation unit 2, and the output v of the hysteresis comparison unit 1 cA The output v of the frequency divider circuit Q1 Connected, used to extract logic level v cA The falling edge; The minimum duty cycle limiting unit 1 is used to extract the output v of the frequency divider circuit. Q1 The falling edge signal is used to generate a narrow pulse signal by setting a delay according to the duty cycle requirement; The RS flip-flop 2, and the output v of the logic operation unit 2 c2 and the output v of minimum duty cycle limiting unit 1 c3 Connected to control the turn-on and turn-off times of the second switch Q1, thereby generating a drive control signal for the first switch Q1; The minimum duty cycle limiting unit 2 is used to extract the output v of the frequency divider circuit. Q2 The falling edge signal is used to generate a narrow pulse signal by setting a delay according to the duty cycle requirement; The logic operation unit 3, and the output v of the hysteresis comparison unit 2 cB The output v of the frequency divider circuit Q2 Connected, used to extract logic level v cB The rising edge; The RS flip-flop 3, and the output v of the logic operation unit 3 c5 and the output v of minimum duty cycle limiting unit 2 c4 Connected to control the turn-on and turn-off times of the third switch Q3, thereby generating a drive control signal for the third switch Q3; The logic operation unit 4, and the output v of the hysteresis comparison unit 2 cB The output v of the frequency divider circuit Q2 Connected, used to extract logic level v cB The rising edge; The RS flip-flop 4, and the output v of the logic operation unit 4 c6 The output v of the frequency divider circuit Q2 They are connected together, thereby generating the drive control signal for the third switch Q3; The drive units 1 to 4 are respectively connected to RS flip-flops 1 to 4, and are used to amplify the power of the drive control signals of the first switch Q1 to the fourth switch Q4 to generate a drive signal v. gs1 ~v gs4 This drives the switching transistor.

6. The duty cycle adjustable adaptive resonant drive circuit according to claim 5, characterized in that, The SET and RESET ports of the RS flip-flop 1 are respectively connected to the outputs v of the logic operation unit 1. c1 The output v of the frequency divider circuit Q1 The SET and RESET ports of the RS flip-flop 2 are respectively connected to the output v of the logic operation unit 2. c2 and the output v of minimum duty cycle limiting unit 1 c3 The SET and RESET ports of the RS flip-flop 3 are respectively connected to the output v of the logic operation unit 3. c5 and the output v of minimum duty cycle limiting unit 2 c4 The SET and RESET ports of the RS flip-flop 4 are respectively connected to the output v of the logic operation unit 4. c6 The output v of the frequency divider circuit Q2 .

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