Configurable termination circuitry

Abstract

Resistances of configurable termination circuitry located at an interface between a memory component and a processing device are adjusted. The configurable termination circuitry includes a plurality of transistors, a plurality of switches coupled to the plurality of transistors, and a plurality of resistors coupled to the plurality of switches. The resistances of the configurable termination circuitry are adjusted based on a mode of the configurable termination circuitry.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to configurable termination circuitry systems. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Attached Figure Description

[0003] This disclosure will be more fully understood from the accompanying drawings, which are given below and describe various embodiments of the present disclosure. However, the drawings should not be construed as limiting the disclosure to the specific embodiments, but are merely for illustration and understanding.

[0004] Figure 1 An example computing system including a memory subsystem is shown according to some embodiments of the present disclosure.

[0005] Figure 2 Examples of configurable termination circuitry systems according to some embodiments of the present disclosure are shown.

[0006] Figure 3 Another example of a configurable termination circuitry system according to some embodiments of the present disclosure is shown.

[0007] Figure 4 Another example of a configurable termination circuitry system according to some embodiments of the present disclosure is shown.

[0008] Figure 5 Another example of a configurable termination circuitry system according to some embodiments of the present disclosure is shown.

[0009] Figure 6 This is a flowchart of an example method for operating a configurable termination circuitry system according to some embodiments of the present disclosure.

[0010] Figure 7 This is a block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0011] This disclosure relates to configurable termination circuitry systems in memory subsystems. The memory subsystem may be a storage device, a memory module, or a hybrid of both. The following is combined with… Figure 1Examples of storage devices and memory modules are described. Generally, a host system may utilize a memory subsystem comprising one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request retrieval of data from the memory subsystem.

[0012] When a signal, such as a video or control signal, travels along a conductor in a transmission line, such as a bus, the signal can be reflected within the bus. Signal reflection can occur due to various factors, such as discontinuities in the conductor. For example, if the conductor is simply cut, then when the signal reaches the end of the conductor in the line, the signal can reach that end and be reflected directly back. This reflection can cause various problems, such as signal degradation and / or returning additional (e.g., erroneous) signals.

[0013] In a conventional memory subsystem, termination circuitry configured for transmit or receive modes can be added to one or both ends of the transmission line to prevent signal reflection from the ends. However, configuring transmit mode termination circuitry on a separate circuit, in addition to receive mode termination circuitry, can degrade the performance of the memory subsystem. For example, having separate circuitry for both transmit and receive mode termination circuitry increases the area of ​​the termination circuitry, leaving little space for adding other components to the memory subsystem. Furthermore, separate circuitry can increase parasitic capacitance within the memory subsystem.

[0014] This disclosure addresses the aforementioned and other drawbacks by forming a configurable termination circuitry system within the memory subsystem. The configurable termination circuitry system combines receive-mode and transmit-mode terminations into a single circuit. Combining transmit-mode and receive-mode terminations into a single circuit provides several benefits to the memory subsystem, such as occupying less space within the memory device and reducing parasitic capacitance within the memory subsystem.

[0015] One advantage of combining receive and transmit mode circuitry is that it occupies less space within the memory subsystem compared to having two separate circuits for receive and transmit mode termination. Forming a termination circuitry system that occupies less space in the memory subsystem frees up more space to incorporate additional components. For example, the extra space created by combining receive and transmit mode termination circuitry can provide more space for adding processors, controllers, and various other memory device components. Adding additional memory subsystem components can provide the memory subsystem with benefits including, but not limited to, increased functionality and improved performance.

[0016] Another benefit of combining receive and transmit mode termination circuitry is that it reduces parasitic capacitance within the memory subsystem. As used herein, "parasitic capacitance" refers to capacitance that exists between parts of an electronic component or circuit due to their proximity. Parasitic capacitance occurs because the two parts have different potentials and generate an electric field, causing them to store charge. Parasitic capacitance can cause a variety of negative effects within the memory subsystem, including, but not limited to, reduced signal bandwidth and increased noise injected into other signals or power supplies and ground.

[0017] Figure 1 An example computing system 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0018] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0019] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing power.

[0020] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is shown. As used herein, the terms “coupled to” or “coupled with” can refer to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intermediate components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0021] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses, for example, memory subsystem 110 to write data to and read data from memory subsystem 110.

[0022] Host system 120 may be coupled to memory subsystem 110 via an interface (e.g., physical host interface) 121. Examples of interface 121 may include, but are not limited to, Serial Advanced Technology Attachment (SATA) interface, Peripheral Component Interconnect High Speed ​​(PCIe) interface, Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interface (e.g., DIMM socket interface supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Dual Data Rate (DDR), Low Power Dual Data Rate (LPDDR), Universal Serial Bus (USB), or any other interface. Interface 121 can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via PCIe interface, host system 120 may further utilize NVM High Speed ​​(NVMe) interface to access memory components (e.g., memory device 130). Interface 121 provides a means for transmitting control, address, data and other signals between memory subsystem 110 and host system 120. Figure 1 Memory subsystem 110 is shown as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple independent communication connections, and / or combinations of communication connections.

[0023] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0024] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0025] Each memory device 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), stores one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC), store multiple bits per cell. In some embodiments, each memory device 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0026] While non-volatile memory components, such as 3D cross-point non-volatile memory cell arrays and NAND-type memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory or storage device, such as read-only memory (ROM), phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0027] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading, writing, or erasing data and other such operations performed at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0028] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing operations controlling the memory subsystem 110, including various processes, operations, logical flows, and routines for handling communication between the memory subsystem 110 and the host system 120.

[0029] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 has been shown to include a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0030] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to enable desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with memory device 130. The memory subsystem controller 115 may further include a host interface (undescribed) circuitry for communicating with the host system 120 via a physical host interface (undescribed). The host interface circuitry can translate commands received from the host system into command instructions to access memory devices 130 and / or 140, and translate responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0031] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., a row decoder and a column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access memory devices 130 and / or 140.

[0032] In some embodiments, memory device 130 includes a local media controller 135 that operates together with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0033] The memory subsystem 110 includes a termination circuitry system 113, which can be configured to operate in different modes, such as a transmit mode and / or a receive mode. The termination circuitry system 113 may be located at an interface 121 between the memory subsystem controller 115 and the memory device 130, and can be used to prevent reflections of signals transmitted between the controller 115 and the memory device 130 by reducing signals arriving at or from the memory device 130 at the interface.

[0034] For example, one end of the bus may be connected to the memory subsystem controller 115, and the other end of the bus may be connected to the memory device 130 to couple the memory subsystem controller 115 to the memory device 130. In some embodiments, the bus may be one or more connectors coupled via one or more wires as described above.

[0035] Termination circuitry 113 may be located at interface 121. In some embodiments, such as Figure 1 As shown, interface 121 with termination circuitry 113 may be located on memory subsystem controller 115. In other embodiments (not depicted), interface 121 with termination circuitry 113 may be located on memory device 130. In some embodiments (e.g., embodiments where interface 121 is located on controller 115), termination circuitry 113 may be coupled to the output of an input / output (I / O) bus at interface 121, and in some embodiments (e.g., embodiments where interface 121 is located on memory device 130), termination circuitry 113 may be coupled to the input of an I / O bus at interface 121. As used herein, the term "input / output bus" may refer to a communication system that allows different components of the memory subsystem to communicate with each other.

[0036] Based on the mode of the configurable termination circuitry system, termination circuitry system 113 can reduce signals arriving at or from memory device 130 at interface 121, where the termination circuitry system is located. In some embodiments, a processing device (e.g., processor 117) can adjust the resistance of configurable termination circuitry system 113 based on the mode of the configurable termination circuitry system (e.g., based on whether the termination circuitry system is configured to operate in transmit or receive mode). For example, configurable termination circuitry system 113 may include a plurality of transistors, a plurality of switches coupled to the plurality of transistors, and a plurality of resistors coupled to the plurality of switches, and the processing device can adjust the resistance of configurable termination circuitry system by turning on or off one or more of the plurality of switches. Examples of termination circuitry systems, different modes in which termination circuitry systems can be configured, and adjustments to the resistance of termination circuitry systems will be further described herein.

[0037] In some embodiments, the interface 121 having the termination circuitry 113 may be located on both the memory subsystem controller 115 and the memory device 130. For example, if the memory subsystem controller 115 is coupled to the memory device 130 via a bidirectional bus, then having the termination circuitry 113 at both ends of the bus allows the termination circuitry 113 to reduce (e.g., terminate) signals traveling in both directions of the bidirectional bus.

[0038] The configurable termination circuitry system 113 can be backward compatible. As used herein, the term "backward compatible" means that the electrical component meets all requirements of the current standard for the electrical component, as well as the requirements of previous standards for the electrical component. Therefore, the termination circuitry system 113 can be coupled to electrical components that conform to both current and previous standards.

[0039] Figure 2 Examples of configurable termination circuitry system 213 according to some embodiments of the present disclosure are shown. Termination circuitry system 213 may include logic circuitry systems 201-1, 201-2 (individually or collectively referred to as logic circuitry system 201), transistors 203-1, 203-2, 203-3, 203-4 (individually or collectively referred to as transistor 203) coupled to logic circuitry system 201, switches 205-1, 205-2, 205-3, 205-4 (individually or collectively referred to as switch 205) coupled to transistor 203, resistors 207-1, 207-2 (individually or collectively referred to as resistor 207) coupled to switch 205, and input / output (IO) pads 209. Additionally, switches 205-3 and 205-4, and transistors 203-3 and 203-4 may be coupled to ground. Additionally, switches 205-1 and 205-2, as well as transistors 203-1 and 203-2, can be coupled to the source.

[0040] exist Figure 2 In the example shown, termination circuitry system 213 can be configured to be in a transmission mode. As used herein, the term "transmission mode" can refer to a configuration of the termination circuitry system in which the termination circuitry system is configured to drive signals onto a transmission medium. As used herein, the term "transmission medium" can refer to an object used to transmit signals from one memory device component to a different memory device component. For example, the transmission medium can be coupled to an interface (e.g., Figure 1 One or more wires of interface 121 shown. Figure 2 In the example shown, the termination circuit system 213 can be configured to be in transmission mode by turning on all switches 205.

[0041] Termination circuitry 213 can receive one or more signals from a controller (e.g., memory subsystem controller 115) or other electrical components via logic circuitry 201. One or more signals can travel through termination circuitry 213 to I / O pads 209. As used herein, the term "input / output pad" can refer to an intermediate structure that connects internal signals from memory device components to a transmission medium. Because switches 205-2 and 205-4 are on, one or more signals can travel through termination resistor 207-1, and because switches 205-1 and 205-3 are on, one or more signals can also travel through termination resistor 207-2. In transmission mode, resistor 207 provides a source termination for the transmission medium and sets the amplitude of the signal transmitted into the transmission medium. As used herein, the term "source termination" can refer to a resistor placed in series with a driver, where the source resistance is equal to the impedance of the transmission medium.

[0042] Figure 3 Another example of a configurable termination circuitry system 313 according to some embodiments of the present disclosure is shown. The termination circuitry system 313 may include logic circuitry systems 301-1, 301-2 (individually or collectively referred to as logic circuitry system 301), transistors 303-1, 303-2, 303-3, 303-4 (individually or collectively referred to as transistor 303) coupled to logic circuitry system 301, switches 305-1, 305-2, 305-3, 305-4 (individually or collectively referred to as switch 305) coupled to transistor 303, resistors 307-1, 307-2 (individually or collectively referred to as resistor 307) coupled to switch 305, IO pads 309 coupled to resistor 307, and receiver circuitry system 311. Furthermore, switches 305-3 and 305-4, transistors 303-3 and 303-4, and logic circuit system 301-2 can be coupled to ground. Additionally, switches 305-1 and 305-2, and transistors 303-1 and 303-2 can be coupled to the source.

[0043] exist Figure 3 In the example shown, the termination circuitry system 313 can be configured to be in receive mode. As used herein, the term "receive mode" can refer to a configuration of the termination circuitry system in which it is configured to terminate one or more signals from leaving the transmission medium. When in receive mode, the termination circuitry system 313 can be configured with a variety of sub-modes, including but not limited to center tap termination, ground termination, and power supply termination. As used herein, the term "sub-mode" can refer to a mode in which the termination circuitry system can be configured when it is configured to be in a specified mode.

[0044] exist Figure 3In the example shown, the termination circuit system 313 can be configured for center tap termination. In some embodiments, in the center tap circuit system, one or more switches 305 can be turned on and one or more switches 305 can be turned off. For example, such as Figure 3 As shown, switches 305-1 and 305-4 can be disconnected, and switches 305-2 and 305-3 can be connected to configure the termination circuit system 313 for center tap termination.

[0045] Termination circuitry system 313 can receive one or more signals from different memory device components. For example, if termination circuitry system 313 is located in a memory device (e.g., Figure 1 On the memory device 130 shown herein, the termination circuitry 313 can receive one or more signals from a controller (e.g., memory subsystem controller 115). The termination circuitry 313 can receive one or more signals via I / O pads 309. Once one or more signals are received from I / O pads 309, the one or more signals can travel to the receiver circuitry 311. As used herein, the term "receiver circuitry" can refer to the circuitry that captures signals from the transmission medium. In a receive mode configuration, the termination resistor 307 can provide impedance to minimize reflections of incident signals from the transmission medium. As used herein, the term "incident signal" can refer to a signal that travels from the source pole through the transmission medium to the load. A signal may become an incident signal when it reaches a discontinuity or another transmission medium with different propagation characteristics, which affect how the signal travels through the transmission medium.

[0046] Termination circuitry 313 can receive one or more signals via I / O pad 309. One or more signals can travel to receiver circuitry 311. At least one of the signals can be reflected back towards other components of termination circuitry 313. The reflected signal can travel through termination resistor 307. As described above, switches 305-1 and 305-4 can be open, and switches 305-2 and 305-3 can be closed. Therefore, the incident signal can travel through termination resistor 307-1 to the source and / or through termination resistor 307-2 to ground. This reduces the current of the reflected signal and minimizes the adverse effects of the reflected signal on the memory device.

[0047] Manipulating the input current using the termination circuitry system 313 as described herein can reduce reflections in the transmission medium by matching or modifying the impedance of the IO pad 309. For example, a termination resistor 307 can restrict the flow of one or more signals. By restricting the flow of one or more signals, the termination resistor 307 reduces signal reflections within the transmission medium, which can improve the performance of the memory subsystem.

[0048] As described above, one or more signals can travel through receiver circuitry 311. Once one or more signals have traveled through receiver circuitry 311, they can then travel to the memory subsystem component. In some embodiments, the signal may be an instruction sent from a controller to the memory device. For example, the signal may be from a controller (e.g., Figure 1 The memory subsystem controller 115 shown in the figure sends data to the memory device (e.g., ...). Figure 1 (Memory device 130 shown in the figure). If the termination circuitry 313 is located on the interface of the memory device (e.g., interface 121-2), then the signal can travel through the termination circuitry 313 and through the receiver circuitry 311 to reach the memory device.

[0049] Figure 4 Another example of a configurable termination circuitry system according to some embodiments of the present disclosure is shown. Termination circuitry system 413 may include logic circuitry systems 401-1, 401-2 (individually or collectively referred to as logic circuitry 401), transistors 403-1, 403-2, 403-3, 403-4 (individually or collectively referred to as transistor 403) coupled to logic circuitry system 401, switches 405-1, 405-2, 405-3, 405-4 (individually or collectively referred to as switch 405) coupled to transistor 403, resistors 407-1, 407-2 (individually or collectively referred to as resistor 407) coupled to switch 405, I / O pad 409, and receiver circuitry system 411. Additionally, switches 405-3 and 405-4 and transistors 403-3 and 403-4 may be coupled to ground. Additionally, switches 405-1 and 405-2, as well as transistors 403-1 and 403-2, can be coupled to the source.

[0050] exist Figure 4 In the example shown, the termination circuitry system 413 can be configured to be in receive mode. When in receive mode, the termination circuitry system 413 can be configured to be in various sub-modes. Figure 4 In the example shown, termination circuit system 413 is similar to termination circuit system 313; however, termination circuit system 413 may be configured for grounding termination.

[0051] Termination circuitry system 413 can be configured for grounding termination because the circuit can be configured to terminate the incident signal to ground. For example... Figure 4 As shown, to configure the termination circuit system 413 for grounding termination, switches 405-1 and 405-2 can be disconnected, and switches 405-3 and 405-4 can be turned on. Furthermore, the two turned-on switches 405-3 and 405-4 can be coupled to (e.g., to) ground.

[0052] Termination circuitry 413 can receive one or more signals via I / O pad 409. One or more signals can travel to receiver circuitry 411. At least one of the signals can be reflected back towards other components of termination circuitry 413. The reflected signal can travel through termination resistor 407. As described above, switches 405-1 and 405-2 can be open, and switches 405-3 and 405-4 can be closed. Therefore, the incident signal can travel through termination resistor 407 to ground. This reduces the current of the reflected signal and reduces the adverse effects of the reflected signal on the memory device.

[0053] Figure 5 Another example of a termination circuit system according to some embodiments of the present disclosure is shown. Termination circuit system 513 may include logic circuit systems 501-1, 501-2 (individually or collectively referred to as logic circuit 501), transistors 503-1, 503-2, 503-3, 503-4 (individually or collectively referred to as transistor 503) coupled to logic circuit system 501, switches 505-1, 505-2, 505-3, 505-4 (individually or collectively referred to as switch 505) coupled to transistor 503, resistors 507-1, 507-2 (individually or collectively referred to as resistor 507) coupled to switch 505, IO pad 509, and receiver circuit system 511. Furthermore, switches 505-3 and 505-4 and transistors 503-3 and 503-4 may be coupled to ground. Additionally, switches 505-1 and 505-2, as well as transistors 503-1 and 503-2, can be coupled to the source.

[0054] exist Figure 5 In the example shown, the termination circuitry system 513 can be configured to be in receive mode. When in receive mode, the termination circuitry system 513 can be configured to be in various sub-modes. Figure 5 In the example shown, termination circuit system 513 may be similar to termination circuit system 313; however, termination circuit system 513 may be configured for power supply termination.

[0055] The termination circuit system 513 can be configured for power supply termination because the circuit system can be configured to terminate the power supply of the incident signal. For example... Figure 5 As shown, to configure the termination circuit system 513 for power supply termination, switches 505-1 and 505-2 can be turned on, and switches 505-3 and 505-4 can be turned off. Furthermore, the turned-on switches 505-1 and 505-2 can be coupled to (e.g., to) a power supply.

[0056] Termination circuitry 513 can receive one or more signals via I / O pad 509. One or more signals can travel to receiver circuitry 511. One or more of the signals can be reflected back towards other components of termination circuitry 513. The reflected signal can travel through termination resistor 507. As described above, switches 505-1 and 505-2 can be turned on, and switches 505-3 and 505-4 can be turned off. Therefore, the incident signal can travel through termination resistor 507 to the power supply. This reduces the current of the reflected signal and reduces the adverse effects of the reflected signal on the memory device.

[0057] Figure 6 This is a flowchart of an example method 612 of an operationally configurable termination circuitry system according to several embodiments of the present disclosure. Method 612 may be performed by processing logic that may include hardware (e.g., processing means, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on a processing means) or a combination thereof. In some embodiments, method 612 is performed by… Figure 1 Configurable termination circuitry system 113 Figure 2 Configurable termination circuitry system 213 Figure 3 Configurable termination circuitry system 313 and / or Figure 4 The configurable termination circuitry system 413 performs the operation. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all operations are required in every embodiment. Other process flows are possible.

[0058] At block 614, method 612 includes adjusting the resistance of a configurable termination circuit system located at the interface between the memory component and the processing device by selecting a mode of the configurable termination circuit system and turning a plurality of switches of the configurable termination circuit system on or off based on the selected mode of the configurable termination circuit system. As described above, the termination circuit system (e.g., Figure 1 The termination circuit system 113 shown can be configured to operate in multiple modes. For example, the termination circuit system can be configured to a receive mode or a transmit mode. If the termination circuit system is configured to receive mode, then the termination circuit system can be configured to operate in multiple sub-modes. In some embodiments, these sub-modes may include, but are not limited to, center termination, ground termination, and power supply termination.

[0059] Furthermore, as mentioned above, the termination circuit system may include one or more switches and termination resistors. The configuration mode of the configurable termination circuit system can be determined in part by the configuration of the switches. For example, if all switches of the configurable termination circuit are on, then the configurable termination circuit can be in transmit mode. If multiple switches are on and multiple switches are off, then the configurable termination circuit system can be in receive mode.

[0060] Furthermore, as stated above, the sub-mode of the configurable termination circuitry system can be determined in part based on which of the switches is on and which is off. For example, if two of the on switches are coupled to ground, the sub-mode of the configurable termination circuitry system can be ground termination mode. If two of the on switches are coupled to a power supply, the mode of the configurable termination circuitry system can be power supply termination mode. Additionally, if one of the switches coupled to ground is on, and simultaneously one of the switches coupled to a power supply is on, the mode of the configurable termination circuitry system can be center termination mode.

[0061] At block 616, method 612 includes guiding current received by the configurable termination circuitry system via an adjusted resistor based on the configurable termination circuitry system. Switch configuration guides signal flow through the termination circuitry system, as described above. For example, as Figure 5 As shown, switch 505-1 can guide a signal through termination resistor 507-2, and switch 505-2 can guide a signal through termination resistor 507-1. In some embodiments, the termination circuitry can reduce the interface between the memory component and the processing device (e.g., by guiding a signal (e.g., current)). Figure 1 The diagram shows multiple output signals of the IO bus at interface 121.

[0062] Turning a particular switch on or off can also adjust the resistance of the terminating circuit system. For example, if a switch coupled to a resistor is turned on, it makes the circuit complete and allows current to flow through the resistor. Alternatively, if a switch coupled to a resistor is turned off, it causes the circuit to become incomplete and prevents current from flowing through the resistor. The resistance of the terminating circuit system can be determined by the total resistance of the resistors coupled to the terminating circuit system. Terminating resistors can be configured in parallel (e.g., ...). Figure 2 The terminating resistor 207 shown is configured to be enabled or disabled to achieve a configurable resistance value.

[0063] Figure 7An example machine illustrating computer system 700 is shown, capable of executing a set of instructions within the computer system to cause the machine to perform any or more of the methods discussed herein. In some embodiments, computer system 700 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of the configurable termination circuitry system 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment within the capacity of a server or client machine in a client-server network environment.

[0064] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, while a single machine is shown, it should also be understood that the term "machine" includes any collection of machines that individually or collectively execute (one or more) sets of instructions to perform any one or more of the methods discussed herein.

[0065] The example computer system 700 includes a processing device 702 that communicates with each other via a bus 730, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718.

[0066] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets or combinations of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 702 is configured to execute instructions 726 to perform the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 for communication on network 720.

[0067] Data storage system 718 may include machine-readable storage medium 724 (also referred to as computer-readable medium) on which one or more instruction sets 726 or software embodying any one or more of the methods or functions described herein are stored. The instructions 726 may also reside wholly or at least partially within main memory 704 and / or processing device 702 during execution by computer system 700, the main memory 704 and the processing device 702 also constituting the machine-readable storage medium. Machine-readable storage medium 724, data storage system 718, and / or main memory 704 may correspond to... Figure 1 The memory subsystem 110.

[0068] In one embodiment, instruction 726 includes instructions for implementing a configurable termination circuitry system (e.g., Figure 1 The configurable termination circuitry system 113) contains instructions for its functionality. While the machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine to cause a machine to perform any one or more of the methods disclosed herein. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0069] This disclosure includes apparatus, methods, and systems that support configurable termination circuitry systems. Several embodiments include configurations of the configurable termination circuitry systems.

[0070] Although specific embodiments have been shown and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover modifications or variations of several embodiments of this disclosure. It should be understood that the above description is illustrative rather than restrictive. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art upon review of the above description. The scope of several embodiments of this disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of several embodiments of this disclosure should be determined by reference to the full scope of the appended claims together with the equivalents claimed by such claims.

[0071] In the foregoing detailed embodiments, some features are grouped together in a single embodiment for the purpose of simplification. This approach of the present disclosure should not be construed as reflecting an intention that the disclosed embodiments must use more features than those expressly stated in each claim. In fact, as reflected in the appended claims, the subject matter of the invention lies in fewer than all features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed embodiments, wherein each claim is, in itself, a separate embodiment.

Claims

1. A memory system comprising: a memory component; and a processing device operatively coupled to the memory component to adjust a resistance of a configurable termination circuitry at an interface between the memory component and the processing device, wherein the configurable termination circuitry includes: a plurality of transistors; a plurality of switches coupled to the plurality of transistors; and a plurality of resistors coupled to the plurality of switches; and wherein the processing device adjusts the resistance of the configurable termination circuitry based on a mode of the configurable termination circuitry by turning on two of the plurality of switches and turning off two of the plurality of switches.

2. The memory system of claim 1, wherein the configurable termination circuitry is coupled to an output of an input / output (IO) bus at the interface between the memory component and the processing device.

3. The memory system of claim 1, wherein the configurable termination circuitry is coupled to an input of an input / output (IO) bus at the interface between the memory component and the processing device.

4. The memory system of any one of claims 1-3, wherein the configurable termination circuitry is backward compatible.

5. The memory system of claim 1, wherein the memory component comprises the interface.

6. The memory system of claim 1, wherein the processing device comprises the interface.

7. A memory system comprising: a memory component; and a configurable termination circuitry including: a plurality of transistors; a plurality of switches coupled to the plurality of transistors; a plurality of selectable resistors coupled to the plurality of switches; and wherein the configurable termination circuitry reduces a plurality of signals to or from the memory component based on a mode of the configurable termination circuitry by turning on two of the plurality of switches and turning off two of the plurality of switches.

8. The memory system of claim 7, wherein the mode of the configurable termination circuitry is a receive mode configured for a center-tap termination.

9. The memory system of claim 7, wherein the mode of the configurable termination circuitry is a receive mode configured for a ground termination.

10. The memory system of claim 7, wherein the mode of the configurable termination circuitry is a receive mode configured for a supply termination.

11. The memory system of claim 7, wherein the mode of the configurable termination circuitry is a transmit mode.

12. The memory system of any one of claims 7-11, wherein the configurable termination circuitry is configurable for a receive mode and a transmit mode.

13. A method of operating a configurable termination circuitry comprising: adjusting a resistance of a configurable termination circuitry at an interface between a memory component and a processing device by: selecting a mode of the configurable termination circuitry; and adjusting the resistance of the configurable termination circuitry based on the mode of the configurable termination circuitry by turning on two of a plurality of switches and turning off two of the plurality of switches. ​ turning on or off a plurality of switches of the configurable termination circuitry based on a selected mode of the configurable termination circuitry by turning on two of the plurality of switches and turning off two of the plurality of switches; and directing current received by the configurable termination circuitry based on an adjusted resistance of the configurable termination circuitry.

14. The method of claim 13, wherein the two of the plurality of switches that are turned on are coupled to ground.

15. The method of claim 13, wherein the two of the plurality of switches that are turned on are coupled to a source.

16. The method of claim 13, wherein one of the plurality of switches that is turned on and one of the plurality of switches that is turned off are coupled to ground.

17. The method of any one of claims 13-16, further comprising reducing a plurality of output signals of an input / output bus at the interface between the memory component and the processing device by directing the current.

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