Memory device

Abstract

The present disclosure relates to a memory device. A memory device having improved operating speed can include a memory block including memory cells, a peripheral circuit configured to perform a program operation to increase each of threshold voltages of the memory cells, and a control logic configured to control the peripheral circuit to perform the program operation. The program operation can include a plurality of program loops, each of the plurality of program loops can include a program voltage application operation and a verify operation, and when a verify pass for a next highest program state among a plurality of program states during the verify operation included in an arbitrary one of the plurality of program loops, the control logic can control the peripheral circuit to perform a verify for a highest program state during the verify operation included in a next program loop of the arbitrary one of the plurality of program loops.

Description

TECHNICAL FIELD

[0001] The disclosure relates to an electronic device, and more particularly, to a memory device and a method of operating the same. BACKGROUND

[0002] A storage device is a device that stores data under the control of a host device such as a computer or a smart phone. The storage device can include a memory device that stores data and a memory controller that controls the memory device. The memory device can be classified into a volatile memory device and a non-volatile memory device.

[0003] The volatile memory device can be a device that stores data only when power is supplied and loses the stored data when power is turned off. The volatile memory device can include a static random access memory (SRAM) and a dynamic random access memory (DRAM), etc.

[0004] The non-volatile memory device is a device that does not lose data even when power is turned off. The non-volatile memory device includes a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), and a flash memory, etc. SUMMARY

[0005] Embodiments of the disclosure provide a memory device having improved reliability and operating speed and a method of operating the same.

[0006] A memory device according to one embodiment of the disclosure can include a memory block including memory cells, a peripheral circuit configured to perform a program operation that increases a threshold voltage of the memory cells such that the threshold voltage of the memory cells is included in a threshold voltage distribution corresponding to a target program state among a plurality of program states determined according to data to be stored in the memory cells, and a control logic configured to control the peripheral circuit to perform the program operation. The program operation can include a plurality of program loops, the plurality of program loops can include a program voltage application operation and a verify operation, and when a verify for a next highest program state among the plurality of program states is determined to pass during the verify included in an arbitrary one of the plurality of program loops, the control logic can control the peripheral circuit to perform a verify for a highest program state during the verify included in a next program loop of the arbitrary one of the plurality of program loops.

[0007] A memory device according to one embodiment of the present disclosure can include a memory block including memory cells, a peripheral circuit configured to perform a program operation to increase a threshold voltage of the memory cells such that the threshold voltage of the memory cells is included in a threshold voltage distribution corresponding to a target program state among a plurality of program states determined according to data to be stored in the memory cells, and control logic configured to control the peripheral circuit to, during the program operation, apply a program control voltage to a bit line of the memory cell targeting a highest program state among the plurality of program states while applying a program voltage corresponding to a next highest program state among the plurality of program states to a word line to which the memory cells are commonly connected.

[0008] A memory device according to one embodiment of the present disclosure can include a memory block including memory cells, a peripheral circuit configured to perform a program operation to increase a threshold voltage of the memory cells such that the threshold voltage of the memory cells is included in a threshold voltage distribution corresponding to a target program state among a plurality of program states determined according to data to be stored in the memory cells, and control logic configured to control the peripheral circuit to, during the program operation, apply a program control voltage to a bit line of the memory cell targeting a highest program state among the plurality of program states while applying a program voltage corresponding to a next highest program state among the plurality of program states to a word line to which the memory cells are commonly connected.

[0009] A method of operating a memory device having a word line coupled to memory cells coupled to respective bit lines, the method comprising: during a current program cycle, applying a control voltage to a bit line coupled to a first cell while applying a program voltage corresponding to a second state to the word line; and when one or more second cells verify for the second state during the current program cycle, starting to verify the first cell for a first state during a subsequent program cycle. The first and second states are two states in order of highest to which the memory cells are to be programmed. The first cell is among the memory cells to be programmed to the first state. The second cell is among the memory cells to be programmed to the second state.

[0010] According to the present technology, a memory device with improved reliability and operation speed can be provided. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 FIG. 1 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0012] Figure 2 FIG. 2 is a diagram illustrating a memory device of FIG. 1. Figure 1

[0013] Figure 3 FIG. 3 is a diagram illustrating a configuration of any one of the memory blocks of FIG. 2. Figure 2

[0014] Figure 4 FIG. 4 is a diagram illustrating a plurality of program loops included in a program operation and a program voltage application operation and a verify operation included in each of the program loops.

[0015] Figure 5A FIG. 5 is a diagram illustrating a threshold voltage distribution of a single-layer cell. Figure 5B

[0016] Figure 6A FIG. 6 is a diagram illustrating a threshold voltage distribution of a multi-layer cell. Figure 6B

[0017] Figure 7A FIG. 7 is a diagram illustrating a threshold voltage distribution of a triple-layer cell. Figure 7B

[0018] Figure 8A FIG. 8 is a diagram illustrating a threshold voltage distribution of a quadruple-layer cell. Figure 8B

[0019] Figure 9A FIG. 9 is a graph illustrating a program state verified in a plurality of program loops according to a comparative embodiment of the present disclosure.

[0020] Figure 9B FIG. 10 is a graph illustrating a program state verified in a plurality of program loops according to an embodiment of the present disclosure.

[0021] Figure 10 FIG. 11 is a diagram illustrating a program operation corresponding to FIG. 10. Figure 9A

[0022] FIG. 12 is a diagram illustrating a program operation corresponding to FIG. 10. Figure 11 Figure 9B FIG. 13 is a diagram illustrating a case where a threshold voltage distribution corresponding to a highest program state is widened according to an embodiment of the present disclosure.

[0023] Figure 12A Figure 12B FIG. 14 is a diagram illustrating a case where a threshold voltage distribution corresponding to a highest program state is widened according to an embodiment of the present disclosure.

[0024] Figure 13A FIG. 15 is a diagram illustrating a case where a threshold voltage distribution corresponding to a highest program state is widened according to an embodiment of the present disclosure. Figure 13B ​​​​​​​​is a graph illustrating an improved threshold voltage distribution according to one embodiment of the present disclosure.

[0025] Figure 14 is a block diagram illustrating a method of performing a program operation according to one embodiment of the present disclosure.

[0026] Figure 15 is a flowchart illustrating a method of operating a memory device according to one embodiment of the present disclosure.

[0027] Figure 16 is a block diagram illustrating a memory card system to which a memory device according to one embodiment of the present disclosure is applied.

[0028] Figure 17 is a block diagram illustrating a solid state drive (SSD) system to which a memory device according to one embodiment of the present disclosure is applied.

[0029] Figure 18 is a block diagram illustrating a user system to which a memory device according to one embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0030] The description of the structure or function of the embodiments according to the concept disclosed in the present application is only for describing the embodiments. The embodiments can be implemented in various forms, and should not be interpreted as being limited to the embodiments described in the present application.

[0031] Figure 1 is a graph illustrating a memory device according to one embodiment of the present disclosure.

[0032] Referring to Figure 1 , the memory device 50 can include a memory device 100 and a memory controller 200 controlling an operation of the memory device. The memory device 50 can be a device storing data under the control of a host 300 such as a cellular phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game player, a television, a tablet PC, or a car infotainment system.

[0033] The storage device 50 can be manufactured as one of various types of storage devices according to a host interface that is a communication method of communication with the host 300. For example, the storage device 50 can be configured as any one of various types of storage devices such as an SSD, a multimedia card (in the form of an MMC, an eMMC, an RS-MMC, and a micro-MMC), a secure digital card (in the form of an SD, a mini-SD, and a micro-SD), a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a personal computer memory card international association (PCMCIA) card-type storage device, a peripheral component interconnect (PCI) card-type storage device, a PCI Express card-type storage device, a compact flash (CF) card, a smart media card, and a memory stick.

[0034] The storage device 50 can be manufactured as any one of various types of packages. For example, the storage device 50 can be manufactured as any one of various types of package types such as a package on package (POP), a system in package (SIP), a system on chip (SOC), a multi-chip package (MCP), a chip on board (COB), a wafer level package (WFP), and a wafer level stack package (WSP).

[0035] The memory device 100 can store data. The memory device 100 operates under the control of the memory controller 200. The memory device 100 can include a memory cell array including a plurality of memory cells that store data.

[0036] The memory cell can be configured as a single layer cell (SLC) that stores one bit of data, a multi layer cell (MLC) that stores two bits of data, a triple layer cell (TLC) that stores three bits of data, or a quad layer cell (QLC) that is capable of storing four bits of data

[0037] The memory cell array can include a plurality of memory blocks. The memory block can include a plurality of memory cells. One memory block can include a plurality of pages. In one embodiment, the page can be a unit for storing data in or reading data stored in the memory device 100. The memory block can be a unit for erasing data.

[0038] In one embodiment, the memory device 100 can be, for example, a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate 4 (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, a low power DDR (LPDDR), a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), or a spin transfer torque random access memory (STT-RAM), etc. In the present specification, it is assumed that the memory device 100 is a NAND flash memory.

[0039] The memory device 100 is configured to receive a command CMD and an address ADDR from the memory controller 200, and access a region selected by the address ADDR in a memory cell array. The memory device 100 can perform an operation indicated by the command CMD on the region selected by the address. For example, the memory device 100 can perform a program operation, a read operation, and an erase operation. During the program operation, the memory device 100 can store data in the region selected by the address ADDR. During the read operation, the memory device 100 can read data from the region selected by the address ADDR. During the erase operation, the memory device 100 can erase data stored in the region selected by the address ADDR.

[0040] In one embodiment, the memory device 100 can include a plurality of planes. A plane can be a unit capable of independently performing an operation. For example, the memory device 100 can include two, four, or eight planes. The plurality of planes can simultaneously and independently perform each of a program operation, a read operation, or an erase operation.

[0041] The memory controller 200 can control the overall operation of the storage 50.

[0042] When the storage 50 is powered, the memory controller 200 can execute firmware (FW). When the memory device 100 is a flash memory device, the firmware (FW) can include a host interface layer (HIL) that controls communication with the host 300. The memory controller can include a flash translation layer (FTL) that controls communication between the host 300 and the memory device 100, and a flash interface layer (FIL) that controls communication with the memory device 100.

[0043] The memory controller 200 can receive write data and a logical block address (LBA) from the host 300, and can convert the LBA into a physical block address (PBA) indicating an address of a memory cell included in the memory device 100 to store the data. In one embodiment, the LBA and a "logical address" or "logical's address" can be used as the same meaning. In one embodiment, the PBA and a "physical address" can be used as the same meaning.

[0044] The memory controller 200 can control the memory device 100 to perform a program operation, a read operation, or an erase operation, etc. according to a request of the host 300. During the program operation, the memory controller 200 can provide a program command, a PBA, and data to the memory device 100. During the read operation, the memory controller 200 can provide a read command and a PBA to the memory device 100. During the erase operation, the memory controller 200 can provide an erase command and a PBA to the memory device 100.

[0045] In one embodiment, the memory controller 200 can independently generate a command, an address, and data regardless of a request from the host 300, and transmit the command, the address, and the data to the memory device 100. For example, the memory controller 200 can provide a command, an address, and data to the memory device 100 for performing a read operation and a program operation accompanied when performing wear leveling, read recycling, and garbage collection, etc.

[0046] In one embodiment, the memory controller 200 can control two or more memory devices 100. In this case, the memory controller 200 can control the memory devices 100 according to an interleaving method to improve operation performance. The interleaving method can be a method of controlling operations of at least two memory devices 100 to overlap each other. Alternatively, the interleaving method can be a method in which two or more memory devices 100 operate in parallel.

[0047] The buffer memory can temporarily store data provided from the host 300, i.e., data to be stored in the memory device 100, or can temporarily store data read from the memory device 100. In one embodiment, the buffer memory can be a volatile memory device. For example, the buffer memory can be, for example, a dynamic random access memory (DRAM) or a static random access memory (SRAM).

[0048] The host 300 can communicate with the memory device 50 using at least one of various communication methods such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High Speed Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multi-Media Card (MMC), Embedded MMC (eMMC), Dual In-Line Memory Module (DIMM), Registered DIMM (RDIMM), and Load Reduced DIMM (LRDIMM).

[0049] Figure 2 is a diagram illustrating Figure 1 a memory device.

[0050] Referring to Figure 2 , the memory device 100 includes a memory cell array 110, an address decoder 120, a read / write circuit 130, control logic 140, a voltage generator 150, and a current sensing circuit 160. The address decoder 120, the read / write circuit 130, the voltage generator 150, and the current sensing circuit 160 define a peripheral circuit controlled by the control logic 140.

[0051] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to the address decoder 120 through word lines WL. The plurality of memory blocks BLK1 to BLKz are connected to the read / write circuit 130 through bit lines BL1 to BLm. The plurality of memory blocks BLK1 to BLKz include a plurality of memory cells. In one embodiment, the plurality of memory cells are non-volatile memory cells, and can be configured by non-volatile memory cells having a vertical channel structure. The memory cell array 110 can be configured as a two-dimensional structure of memory cells. According to one embodiment, the memory cell array 110 can be configured as a three-dimensional structure of memory cells. Meanwhile, each of the plurality of memory cells included in the memory cell array can store at least one bit of data. In one embodiment, each of the plurality of memory cells included in the memory cell array 110 can be an SLC storing one bit of data. In another embodiment, each of the plurality of memory cells included in the memory cell array 110 can be an MLC storing two bits of data. In still another embodiment, each of the plurality of memory cells included in the memory cell array 110 can be a TLC storing three bits of data. In yet another embodiment, each of the plurality of memory cells included in the memory cell array 110 can be a QLC storing four bits of data. According to one embodiment, the memory cell array 110 can include a plurality of memory cells each storing five or more bits of data.

[0052] The address decoder 120 is connected to the memory cell array 110 through the word lines WL. The address decoder 120 is configured to operate in response to control of the control logic 140. The address decoder 120 receives an address through an input / output buffer inside the memory device 100.

[0053] The address decoder 120 is configured to decode a block address among the received address. The address decoder 120 selects at least one memory block according to the decoded block address. Further, at the time of a read voltage application operation during a read operation, the address decoder 120 applies a read voltage Vread generated in the voltage generator 150 to a selected word line of the selected memory block, and applies a pass voltage Vpass to the remaining unselected word lines. Further, during a program verify operation, the address decoder 120 applies a verify voltage generated in the voltage generator 150 to a selected word line of the selected memory block, and applies a pass voltage Vpass to the remaining unselected word lines.

[0054] The address decoder 120 can be configured to decode a column address among the received address. The address decoder 120 transmits the decoded column address to the read / write circuit 130.

[0055] Read and program operations of the memory device 100 are performed in units of pages. Addresses received at the time of requesting read and program operations include a block address, a row address, and a column address. The address decoder 120 selects one memory block and one word line according to the block address and the row address. The column address is decoded by the address decoder 120 and is provided to the read / write circuit 130. In this specification, a memory cell connected to one word line can be referred to as a "physical page".

[0056] The read / write circuit 130 includes a plurality of page buffers PB1 to PBm. The read / write circuit 130 can operate as a "read circuit" during a read operation of the memory cell array 110 and can operate as a "write circuit" during a write operation of the memory cell array 110. The plurality of page buffers PB1 to PBm are connected to the memory cell array 110 through bit lines BL1 to BLm. During a read operation and a program verify operation, in order to sense a threshold voltage of a memory cell, the plurality of page buffers PB1 to PBm sense a change in an amount of current flowing according to a program state of a corresponding memory cell through a sense node while continuously providing a sense current to a bit line connected to the memory cell, and latch the sensed change as sense data. The read / write circuit 130 operates in response to a page buffer control signal output from the control logic 140. In one embodiment, a write operation of the write circuit can be used in the same meaning as a program operation of a selected memory cell.

[0057] During a read operation, the read / write circuit 130 senses data of a memory cell, temporarily stores the read data, and outputs the data DATA to an input / output buffer (not shown) of the memory device 100. In one embodiment, the read / write circuit 130 can include a column selection circuit or the like in addition to a page buffer (or a page register). The read / write circuit 130 can be a page buffer according to one embodiment of the disclosure.

[0058] The control logic 140 is connected to the address decoder 120, the read / write circuit 130, the voltage generator 150, and the current sense circuit 160. The control logic 140 receives a command CMD and a control signal CTRL through an input / output buffer of the memory device 100. The control logic 140 is configured to control overall operations of the memory device 100 in response to the control signal CTRL. Further, the control logic 140 outputs a control signal for adjusting a sense node pre-charge potential level of the plurality of page buffers PB1 to PBm. The control logic 140 can control the read / write circuit 130 to perform a read operation of the memory cell array 110.

[0059] The control logic 140 can determine whether the verify operation of a certain target program state is pass or fail in response to the pass signal PASS or the fail signal FAIL received from the current sensing circuit 160.

[0060] The voltage generator 150 generates a read voltage Vread and a pass voltage Vpass during a read operation in response to a control signal output from the control logic 140. To generate a plurality of voltages having various voltage levels, the voltage generator 150 can include a plurality of pumping capacitors that receive an internal power supply voltage, and generate a plurality of voltages by selectively activating the plurality of pumping capacitors in response to the control of the control logic 140.

[0061] The current sensing circuit 160 can generate a reference current and a reference voltage during a verify operation in response to an enable bit VRY_BIT<#> received from the control logic 140. By comparing the generated reference voltage with a sense voltage VPB received from a page buffer PB1 to PBm included in the read-write circuit 130, or comparing the generated reference current with a sense current received from the page buffer PB1 to PBm included in the read-write circuit 130, the pass signal PASS or the fail signal FAIL can be output.

[0062] The address decoder 120, the read-write circuit 130, the voltage generator 150, and the current sensing circuit 160 can function as a "peripheral circuit" that performs a read operation, a write operation, and an erase operation on the memory cell array 110. The peripheral circuit performs the read operation, the write operation, and the erase operation on the memory cell array 110 based on the control of the control logic 140.

[0063] Figure 3 is a diagram illustrating a configuration of any one of Figure 2 storage blocks BLK1 to BLKz.

[0064] The storage block BLKz is Figure 2 any one of the storage blocks BLK1 to BLKz of

[0065] Referring to Figure 3 , a plurality of word lines arranged in parallel to each other can be connected between a first selection line and a second selection line. In the present embodiment, the first selection line can be a source selection line SSL, and the second selection line can be a drain selection line DSL. More specifically, the storage block BLKz can include a plurality of strings ST connected between bit lines BL1 to BLm and a source line SL. The bit lines BL1 to BLm can be connected to respective strings ST, and the source line SL can be commonly connected to the respective strings ST. Since the respective strings ST can be configured to be identical to each other, as an example, the string ST connected to the first bit line BL1 is specifically described.

[0066] A string ST can include a source select transistor SST connected in series between a source line SL and a first bit line BL1, a plurality of memory cells MC1 to MC16, and a drain select transistor DST. One string ST can include at least one of the source select transistor SST and the drain select transistor DST, and can include more memory cells than the number shown in the figure.

[0067] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. The memory cells MC1 to MC16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different strings ST can be connected to a source select line SSL, the gates of the drain select transistors DST can be connected to a drain select line DSL, and the gates of the memory cells MC1 to MC16 can be connected to a plurality of word lines WL1 to WL16, respectively. A group of memory cells included in different strings ST that are connected to the same word line can define one page PG. Accordingly, the memory block BLKz can include the number of pages PG of the word lines WL1 to WL16.

[0068] One memory cell SLC can store one bit of data. In this embodiment, one physical page PG can store one logical page (LPG) data. One logical page (LPG) data can include the same number of data bits as the number of cells included in one physical page PG.

[0069] One memory cell can store two or more bits of data. In this embodiment, one physical page PG can store two or more logical pages (LPG) data.

[0070] Figure 4 is a diagram illustrating a plurality of program loops included in a program operation and a program voltage application operation and a verify operation included in one or more program loops.

[0071] Referring to Figure 4 , a program operation can include a plurality of program loops. As Figure 4 indicated, a program operation can be started by performing a first program loop 1 st PGM Loop. When the program operation of the selected memory cell is not completed even though the first program loop 1 st PGM Loop is performed, a second program loop 2 nd PGM Loop can be performed. When the program operation of the selected memory cell is not completed even though the second program loop 2 nd PGM Loop is performed, a third program loop 3 rdPGMLoop. In this implementation, the program loop can be repeatedly performed until the program operation is completed.

[0072] When the program operation is not completed even if the program loop is repeated up to a predetermined maximum number of program loops, it can be determined that the program operation fails.

[0073] Figure 5A and Figure 5B are graphs showing threshold voltage distributions of SLCs.

[0074] Referring to Figure 5A and Figure 5B , the horizontal axis represents threshold voltages of memory cells, and the vertical axis represents numbers of memory cells.

[0075] A memory device can perform a program operation in units of word lines. A plurality of memory cells connected to one word line can constitute one physical page. A physical page can be a unit of a program operation or a read operation.

[0076] A memory device can perform a program operation to store data in memory cells connected to a selected word line among a plurality of word lines.

[0077] Before performing the program operation, selected memory cells, which are memory cells connected to the selected word line, can have a threshold voltage distribution corresponding to any one of an erased state E as shown in Figure 5A .

[0078] When a memory cell stores data corresponding to one bit, the memory cell can be programmed to have a threshold voltage corresponding to any one of the erased state E or a first program state PI.

[0079] The erased state E can correspond to data "1", and the first program state PI can correspond to data "0". However, the data corresponding to the first program state PI is exemplary, and the erased state E can correspond to data "0", and the first program state PI can correspond to data "1".

[0080] When the program operation ends, the selected memory cells can have a threshold voltage corresponding to any one of the erased state E or the first program state PI as shown in Figure 5B . The memory device can read data stored in the selected memory cells by performing a read operation using a first read voltage Rl between the erased state E and the first program state PI.

[0081] Figure 6A and Figure 6B are graphs showing threshold voltage distributions of MLCs.

[0082] Referring to Figure 6A and Figure 6BFIG. 1A is a graph illustrating a threshold voltage distribution of a TLC.

[0083] Before the programming operation is performed, the selected memory cells, as memory cells connected to the selected word line, can have a threshold voltage distribution corresponding to the erase state E as illustrated in Figure 6A FIG. 2A.

[0084] When the memory cells store data corresponding to two bits, the memory cells can be programmed to have a threshold voltage corresponding to any one of the erase state E, the first programmed state PI, the second programmed state P2, and the third programmed state P3.

[0085] The erase state E can correspond to data "11", the first programmed state PI can correspond to data "10", the second programmed state P2 can correspond to data "00", and the third programmed state P3 can correspond to data "01". However, the data corresponding to each programmed state is exemplary and can be modified.

[0086] When the programming operation ends, the selected memory cells can have a threshold voltage corresponding to any one of the erase state E, the first programmed state PI, the second programmed state P2, and the third programmed state P3 as illustrated in Figure 6B FIG. 2B.

[0087] The first read voltage Rl can be a read voltage that distinguishes the erase state E and the first programmed state PI, the second read voltage R2 can be a read voltage that distinguishes the first programmed state PI and the second programmed state P2, and the third read voltage R3 can be a read voltage that distinguishes the second programmed state P2 and the third programmed state P3.

[0088] Figure 7A and Figure 7B are graphs illustrating threshold voltage distributions of a TLC.

[0089] Referring to Figure 7A and Figure 7B , the horizontal axis indicates a threshold voltage of a memory cell, and the vertical axis indicates a number of memory cells.

[0090] Before the programming operation is performed, the selected memory cells, as memory cells connected to the selected word line, can have a threshold voltage distribution corresponding to the erase state E as illustrated in Figure 7A FIG. 3A.

[0091] When the memory cell stores three bits of data, the memory cell can be programmed to have a threshold voltage corresponding to any one of an erased state E, a first programmed state PI, a second programmed state P2, a third programmed state P3, a fourth programmed state P4, a fifth programmed state P5, a sixth programmed state P6, and a seventh programmed state P7.

[0092] The erased state E can correspond to data ‘111’, the first programmed state PI can correspond to data ‘110’, the second programmed state P2 can correspond to data ‘101’, the third programmed state P3 can correspond to data ‘100’, the fourth programmed state P4 can correspond to data ‘011’, the fifth programmed state P5 can correspond to data ‘010’, the sixth programmed state P6 can correspond to data ‘001’, and the seventh programmed state P7 can correspond to data ‘000’. However, the data corresponding to each programmed state is exemplary and can be modified.

[0093] When the programming operation ends, the selected memory cell can have a threshold voltage corresponding to any one of the erased state E, the first programmed state PI, the second programmed state P2, the third programmed state P3, the fourth programmed state P4, the fifth programmed state P5, the sixth programmed state P6, and the seventh programmed state P7 as shown in FIG. 1. Figure 7B The memory device can read the data stored in the selected memory cell by performing a read operation using the first to seventh read voltages R1-R7.

[0094] The first read voltage R1 can be a read voltage that distinguishes the erased state E and the first programmed state PI, the second read voltage R2 can be a read voltage that distinguishes the first programmed state PI and the second programmed state P2, the third read voltage R3 can be a read voltage that distinguishes the second programmed state P2 and the third programmed state P3, the fourth read voltage R4 can be a read voltage that distinguishes the third programmed state P3 and the fourth programmed state P4, the fifth read voltage R5 can be a read voltage that distinguishes the fourth programmed state P4 and the fifth programmed state P5, the sixth read voltage R6 can be a read voltage that distinguishes the fifth programmed state P5 and the sixth programmed state P6, and the seventh read voltage R7 can be a read voltage that distinguishes the sixth programmed state P6 and the seventh programmed state P7.

[0095] Figure 8A and Figure 8B are graphs showing threshold voltage distributions of QLCs.

[0096] Referring to Figure 8A and Figure 8B , the horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells.

[0097] Before the programming operation is performed, the selected memory cell, as a memory cell connected to the selected word line, can have a threshold voltage distribution corresponding to an erase state E as shown in Figure 8A

[0098] When the memory cell stores data corresponding to four bits, the memory cell can be programmed to have a threshold voltage corresponding to any one of the erase state E and the first through fifteenth program states Pl to P15.

[0099] The erase state E can correspond to data ‘1111’, the first program state Pl can correspond to data ‘1110’, the second program state P2 can correspond to data ‘1101’, the third program state P3 can correspond to data ‘1100’, the fourth program state P4 can correspond to data ‘1011’, the fifth program state P5 can correspond to data ‘1010’, the sixth program state P6 can correspond to data ‘1001’, the seventh program state P7 can correspond to data ‘1000’. In addition, the eighth program state P8 can correspond to data “0111”, the ninth program state P9 can correspond to data “0110”, the tenth program state P10 can correspond to data “0101”, the eleventh program state Pl l can correspond to data “0100”, the twelfth program state P12 can correspond to data “0011”, the thirteenth program state P13 can correspond to data “0010”, the fourteenth program state P14 can correspond to data “0001”, and the fifteenth program state P15 can correspond to data “0000”. However, the data corresponding to each program state is exemplary and can be modified.

[0100] When the programming operation ends, the selected memory cell can have a threshold voltage corresponding to any one of the erase state E and the first through fifteenth program states Pl to P15 as shown in Figure 8B

[0101] ​​The first read voltage R1 can be a read voltage that distinguishes the erased state E and the first programmed state P1, the second read voltage R2 can be a read voltage that distinguishes the first programmed state P1 and the second programmed state P2, the third read voltage R3 can be a read voltage that distinguishes the second programmed state P2 and the third programmed state P3, the fourth read voltage R4 can be a read voltage that distinguishes the third programmed state P3 and the fourth programmed state P4, the fifth read voltage R5 can be a read voltage that distinguishes the fourth programmed state P4 and the fifth programmed state P5, the sixth read voltage R6 can be a read voltage that distinguishes the fifth programmed state P5 and the sixth programmed state P6, the seventh read voltage R7 can be a read voltage that distinguishes the sixth programmed state P6 and the seventh programmed state P7, the eighth read voltage R8 can be a read voltage that distinguishes the seventh programmed state P7 and the eighth programmed state P8, the ninth read voltage R9 can be a read voltage that distinguishes the eighth programmed state P8 and the ninth programmed state P9, the tenth read voltage R10 can be a read voltage that distinguishes the ninth programmed state P9 and the tenth programmed state P10, the eleventh read voltage R11 can be a read voltage that distinguishes the tenth programmed state P10 and the eleventh programmed state P11, the twelfth read voltage R12 can be a read voltage that distinguishes the eleventh programmed state P11 and the twelfth programmed state P12, the thirteenth read voltage R13 can be a read voltage that distinguishes the twelfth programmed state P12 and the thirteenth programmed state P13, the fourteenth read voltage R14 can be a read voltage that distinguishes the thirteenth programmed state P13 and the fourteenth programmed state P14, and the fifteenth read voltage R15 can be a read voltage that distinguishes the fourteenth programmed state P14 and the fifteenth programmed state P15.

[0102] In Figure 9A , Figure 9B and the subsequent drawings, it is assumed that each of the plurality of memory cells is TLC which stores 3-bit data. However, the scope of the present disclosure is not limited thereto, and each of the plurality of memory cells can be MLC which stores 2-bit data or QLC which stores 4-bit data.

[0103] Figure 9A is a graph showing programmed states verified in a plurality of program cycles according to a comparative embodiment of the present disclosure. Figure 9B is a graph showing programmed states verified in a plurality of program cycles according to one embodiment of the present disclosure.

[0104] In Figure 9A and Figure 9B , the columns in the graph represent program cycles, and the rows in the graph represent programmed states for which a verify operation is performed in each program cycle. In Figure 9A and Figure 9BIn an embodiment, it is assumed that the programming cycles are the first programming cycle through the twenty-first programming cycle, and that the memory cells for which the program operation is performed are programmed as TLC.

[0105] Figure 9A and Figure 9B The fourteenth programming cycle through the twenty-first programming cycle of the plurality of programming cycles and the program state for which the verify operation is performed in each cycle are shown.

[0106] In Figure 9A and Figure 9B In the graph shown in

[0107] In Figure 9B In

[0108] In Figure 14 In the embodiment shown in

[0109] In Figure 9B In Figure 9A Figure 9B In

[0110] In Figure 10 In the embodiment of the comparative example of the present disclosure, the amount of time required for verification for both the second highest program state PV6 and the highest program state PV7 is required in the sixteenth programming cycle through the nineteenth programming cycle. On the other hand, in the embodiment of the present disclosure, the amount of time required for verification for the second highest program state PV6 is required in the sixteenth programming cycle through the nineteenth programming cycle, and the amount of time required for verification for the highest program state PV7 is required in the twentieth programming cycle. Figure 9A ​In the sixteenth programming cycle to the nineteenth programming cycle, only the amount of time for verification for the next highest programming state PV6 is needed, and the verification operation for the highest programming state PV7 is not performed, so the overall programming time can be saved.

[0111] Figure 9A is a diagram illustrating a programming operation corresponding to Figure 11

[0112] The programming operation of the memory device can include a plurality of programming cycles PL1 to PLn. That is, the memory device 100 can perform a plurality of programming cycles PL1 to PLn to program the selected memory cells to have a threshold voltage distribution corresponding to any one of a plurality of programming states.

[0113] The plurality of programming cycles PL1 to PLn can include a program voltage application operation of applying a program voltage and a verification operation of determining whether the memory cells are programmed by applying a verify voltage.

[0114] For example, when the third programming cycle PL3 is performed, after the third program voltage Vp3 is applied, the first verify voltage V1 to the third verify voltage V3 are sequentially applied to verify the programming states of the plurality of memory cells. The memory cells whose target programming state is the first programming state can be verified by the first verify voltage V1, the memory cells whose target programming state is the second programming state can be verified by the second verify voltage V2, and the memory cells whose target programming state is the third programming state can be verified by the third verify voltage V3.

[0115] The memory cells verified through the verify voltages V1 to V3 can be determined to have the target programming state, and thereafter, the programming of these memory cells can be inhibited in the fourth programming cycle PL4. In the fourth programming cycle PL4, a fourth program voltage Vp4 higher than the third program voltage Vp3 by a unit voltage is applied to program the remaining memory cells except for the memory cells whose programming is inhibited. Thereafter, the verification operation can be performed identically to the verification operation of the third programming cycle PL3. For example, the verification pass can be reading the memory cells as off-cells through the corresponding verify voltage.

[0116] During the verification operation, the verify voltage can be applied to a selected word line which is a word line to which the selected memory cell is connected. The page buffer can determine whether the verification of the memory cell passes based on a voltage or a current flowing through a bit line respectively connected to each selected memory cell.

[0117] When described as corresponding to Figure 9B ​PL(n-4) can correspond to the sixteenth program loop, and the (n-4)th program voltage can correspond to Vp16. The memory cells whose target program state is the second highest program state can be verified by the sixth verify voltage V6. The memory cells whose target program state is the highest program state can be verified by the seventh verify voltage V7. The verification by the sixth verify voltage V6 and the verification by the seventh verify voltage V7 can be performed from the sixteenth program loop to PL(n-1) corresponding to the nineteenth program loop.

[0118] Figure 11 is a graph illustrating a program operation corresponding to Figure 11 .

[0119] In this embodiment, the highest program state can be a program state corresponding to a highest threshold voltage distribution among the plurality of program states, and the second highest program state can be a program state adjacent to the program state corresponding to the highest threshold voltage distribution among the plurality of program states.

[0120] In Figure 10 , since "n" corresponds to 21, "n-1" can correspond to 20, "n-2" can correspond to 19, "n-3" can correspond to 18, and "n-4" can correspond to 17. In Figure 12A , although the sixteenth program loop or lower program loops are not illustrated, the verify operation can be performed once in each program loop from the seventeenth program loop to the twenty-first program loop.

[0121] Specifically, the program voltage Vp19 can be applied in the nineteenth program loop corresponding to PL(n-2), and the memory cells whose target program state is the second highest program state can be verified by the sixth verify voltage V6. When verified in the nineteenth program loop, the memory cells whose target program state is the highest program state can be verified by the seventh verify voltage V7 from the twentieth program loop corresponding to PL(n-1).

[0122] According to one embodiment of the disclosure, after the verification for the second highest program state is passed in the program loop, the verification operation for the highest program state can be performed. In this embodiment, compared to the comparative embodiment of Figure 12B , since the verification operation for the highest program state can be omitted, the overall program time can be reduced.

[0123] Figure 12A and Figure 12B is a graph illustrating a case where the threshold voltage distribution corresponding to the highest program state is widened according to one embodiment of the disclosure.

[0124] Figure 12Aand Figure 12A The horizontal axis represents threshold voltages of memory cells, and the vertical axis represents the number of memory cells. Figure 9B A threshold voltage of a memory cell which targets a highest programming state as a target programming state when verification for a sub-highest programming state passes is illustrated according to one embodiment of the present disclosure. Figure 12B A threshold voltage of a memory cell which targets a highest programming state as a target programming state when verification for a sub-highest programming state passes can be illustrated. Figure 12B A threshold voltage of a memory cell which targets a highest programming state as a target programming state when a nineteenth programming loop is performed is illustrated. Figure 9B A threshold voltage of a memory cell which targets a highest programming state as a target programming state when a last programming loop is performed is illustrated according to one embodiment. Figure 13A A threshold voltage of a memory cell which targets a highest programming state as a target programming state when verification for a sub-highest programming state passes can be illustrated. Figure 13B A threshold voltage of a memory cell which targets a highest programming state as a target programming state when a twenty-first programming loop is performed is illustrated.

[0125] A threshold voltage distribution of a memory cell which targets a highest programming state as a target programming state when a programming operation is performed until a nineteenth programming loop can be "A". However, since a programming voltage is applied until verification for a sub-highest programming state passes, a threshold voltage distribution of the memory cell can be "B" which is shifted to the right. Here, "X" can represent a change width of a threshold voltage distribution of the memory cell. When a threshold voltage of the memory cell corresponds to "B", a threshold voltage distribution of the memory cell according to a subsequent programming operation "D" can be wider than a normal threshold voltage distribution "C". Here, "Y" can represent an increase width of a threshold voltage distribution of a memory cell which completes programming. When a threshold voltage distribution of the memory cell is widened, reliability of a memory device can decrease, and thus, in one embodiment, a width of a threshold voltage distribution of the memory cell is maintained. Referring to Figure 13A and Figure 13B A method of maintaining a width of a threshold voltage distribution of a memory cell by adjusting a programming speed of the memory cell is described in detail.

[0126] Figure 13A and Figure 13B are graphs illustrating an improved threshold voltage distribution according to one embodiment of the present disclosure.

[0127] Figure 13A and Figure 13A The horizontal axis represents threshold voltages of memory cells, and the vertical axis represents the number of memory cells. Figure 9B A threshold voltage of a memory cell which targets a highest programming state as a target programming state while a programming control voltage is applied to a bit line of the memory cell according to one embodiment of the present disclosure is illustrated. Figure 13B A threshold voltage of a memory cell which targets a highest programming state as a target programming state when verification for a sub-highest programming state passes can be illustrated. Figure 13B A threshold voltage of a memory cell which targets a highest programming state as a target programming state when a nineteenth programming loop is performed is illustrated.Figure 9B A threshold voltage of a memory cell corresponding to the highest program state is shown as the program cycle progresses up to the last program cycle according to one embodiment of the present disclosure. Figure 9B A threshold voltage of a memory cell corresponding to the highest program state is shown as the program cycle progresses up to the last program cycle according to one embodiment of the present disclosure. Figure 12A A threshold voltage of a memory cell corresponding to the highest program state is shown as the program cycle progresses up to the last program cycle according to one embodiment of the present disclosure.

[0128] Specifically, in Figure 12B , when a program voltage is applied from the fourteenth program cycle to the nineteenth program cycle, a program control voltage can be applied to a bit line of a memory cell targeting the highest program state as a target program state. When the program control voltage is applied to the bit line, a program speed of the corresponding memory cell can be reduced. In comparison with Figure 12A and Figure 13A , a threshold voltage distribution of the memory cell targeting the highest program state as the target program state can be shifted to the left. Figure 12A "A" of Figure 13A corresponds to Figure 13A "B" of Figure 12A corresponds to Figure 13B "E" of Here, "Z" can denote a variation width of a threshold voltage distribution of a memory cell. When Figure 9A "Z" of is wider than

[0129] "X", a width of the threshold voltage distribution of the memory cell can be maintained. Figure 9B When a threshold voltage of a memory cell targeting the highest program state as a target program state is adjusted by controlling a program speed, even when the last program cycle progresses, a width of the threshold voltage distribution of the memory cell targeting the highest program state as the target program state can be maintained as shown in

[0130] "F". Accordingly, reliability and an operating speed of a memory device can be improved. Figure 9A Figure 9B According to one embodiment of the present disclosure, whether a program control voltage is to be applied can be determined according to a program voltage applied to a word line connected with a memory cell. When the program voltage exceeds a predetermined value in the thirteenth program cycle Figure 9A and Figure 9B , the program control voltage can be applied in the fourteenth program cycle of Figure 14 and Figure 9B . When the program voltage is less than the predetermined value up to the eighteenth program cycle of

[0131] According to one embodiment of the disclosure, a magnitude of a program control voltage can vary according to a position of a word line connected to a memory cell. The magnitude of the program control voltage to be applied to a bit line coupled to the memory cell can be increased or decreased according to the position of the word line coupled to the memory cell.

[0132] Figure 15 is a block diagram illustrating a method of performing a program operation according to one embodiment of the disclosure.

[0133] According to the embodiment, the control logic 140 can transmit a control signal to the read-write circuit 130 and the current sensing circuit 160. The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to the read-write circuit 130 through bit lines BL1 to BLm. The plurality of memory blocks BLK1 to BLKz include a plurality of memory cells.

[0134] The read-write circuit 130 includes a plurality of page buffers PB1 to PBm. The plurality of page buffers PB1 to PBm are connected to the memory cell array 110 through the bit lines BL1 to BLm. The plurality of page buffers PB1 to PBm transmit sensing data SDT to the current sensing circuit 160, the sensing data SDT being obtained by sensing a change in an amount of current flowing according to a program state of a corresponding memory cell.

[0135] The current sensing circuit 160 can perform a current sensing operation by receiving the sensing data SDT from the read-write circuit 130. The current sensing operation can be an operation of determining whether the memory cell is programmed to a target state, and can include an individual current sensing operation and an overall current sensing operation.

[0136] The current sensing circuit 160 can generate a reference current and a reference voltage in response to a preset pass bit, and generate a verify current and a verify voltage according to the sensing data SDT. The current sensing circuit 160 can compare the reference voltage with the verify voltage, and transmit a pass signal PS or a fail signal FS to the control logic 140.

[0137] In one embodiment of the disclosure, when the number of memory cells in which a verify operation fails among memory cells to be programmed to a target program state is less than or equal to a set number, the current sensing circuit 160 can determine that the verify operation for the selected program state passes, and output a pass signal PS. When the number of memory cells in which the verify operation fails exceeds the set number, the current sensing circuit 160 can determine that the verify operation for the specific program state fails, and output a fail signal FS.

[0138] The control logic 140 can include a word line voltage controller 141, a bit line current sensing controller 143, a program state verifier 145, a program voltage information storage 147, and a program control voltage information storage 149.

[0139] The word line voltage controller 141 can control the peripheral circuit to apply a verify voltage to a word line to which the memory cells are commonly connected during a verify operation included in the program cycle. The word line voltage controller 141 can control to apply a verify voltage corresponding to any one of the plurality of program states to the word line to which the memory cells are commonly connected.

[0140] The bit line current sensing controller 143 can control the current sensing circuit 160 to sense a bit line current according to a threshold voltage of the memory cell while applying a verify voltage to a word line of the memory cell. The bit line current sensing controller 143 can transmit information about a preset allowed bit so that the current sensing circuit 160 generates a reference current and a reference voltage.

[0141] The program state verifier 145 can determine whether the verification for a specific program state passes based on a result of sensing the bit line current. The program state verifier 145 can calculate a ratio of the memory cells among the memory cells determined to be programmed to a specific program state based on a sum of the bit line currents, and when the calculated ratio exceeds a predetermined value, control the current sensing circuit 160 to determine that the verification for the specific program state passes.

[0142] The program voltage information storage 147 can include information about a relationship between a program cycle and a program voltage. Referring back to Figure 16 , information indicating that a program voltage corresponding to the sixth program state PV6 is applied from the fourteenth program cycle to the nineteenth program cycle can be stored in the program voltage information storage 147. Information indicating that a program voltage corresponding to the seventh program state PV7 is applied in the twentieth program cycle and the twenty-first program cycle can be stored in the program voltage information storage 147.

[0143] The program voltage information storage 147 can include information about a relationship between a voltage magnitude and a program voltage. Since a range of a specific program voltage magnitude is determined in advance, a program voltage can be determined according to an applied voltage magnitude.

[0144] The program control voltage information storage section 149 can include information on the magnitude of the program control voltage corresponding to each of the plurality of word lines included in the memory block. Since the program speed of the memory cell programmed with the highest program state as the target program state is controlled differently depending on the position of the word line coupled to the memory cell, a different program control voltage can be applied for each word line. The program control voltage according to one embodiment of the present disclosure can be 0.5 V

[0145] The program control voltage information storage section 149 can include information on the magnitude of the program control voltage to be applied to the bit line coupled to the memory cell in the program cycle and the program voltage applied to the coupled word line of the memory cell. When the magnitude of the program voltage applied to the word line of the memory cell is less than a predetermined value, the program speed of the memory cell does not need to be controlled, and thus the program control voltage can not be applied to the bit line of the memory cell.

[0146] Figure 16 is a flowchart illustrating a method of operating a memory device according to one embodiment of the present disclosure.

[0147] According to one embodiment of the present disclosure, a memory device can apply a program control voltage to a bit line of a memory cell programmed with a highest program state among a plurality of program states as a target program state while applying a program voltage corresponding to a next highest program state among the plurality of program states to a word line coupled to the memory cell, and perform a verify operation for the highest program state among the plurality of program states after a verify for the next highest program state among the plurality of program states is passed.

[0148] Here, the highest program state can be a program state corresponding to a highest threshold voltage distribution among the plurality of program states, and the next highest program state can be a program state adjacent to the highest program state.

[0149] Here, the program voltage corresponding to the next highest program state can be a program voltage applied to a word line of a memory cell during a program voltage application operation of a predetermined program cycle among a plurality of program cycles. Here, the program voltage corresponding to the next highest program state can be a voltage of a predetermined magnitude of a memory cell included in a memory block. Here, the program voltage corresponding to the next highest program state can be a program voltage that allows a threshold voltage of a memory cell to be included in a threshold voltage distribution corresponding to a program state adjacent to a program state corresponding to a highest threshold voltage distribution among the plurality of program states.

[0150] In step S1501, the memory device can apply a program voltage corresponding to a next highest program state among the plurality of program states to a word line of the memory cell. The control logic can apply a program control voltage to a bit line of the memory cell targeting a highest program state among the plurality of program states while applying the program voltage to the word line commonly connected to the memory cell. The control logic can apply the program control voltage of different sizes according to a location of the word line of the memory cell.

[0151] According to another embodiment of the disclosure, the control logic included in the memory device performing a program operation of storing data in the memory cell targeting any one of the first program state to the Nth program state can apply a program control voltage to a bit line of the memory cell targeting the Nth program state while applying a program voltage corresponding to the (N-1)th program state to a word line commonly connected to the memory cell during the program operation.

[0152] In step S1503, the control logic can determine whether verification for a next highest program state among the plurality of program states passes. The bit line current sensing controller can control the current sensing circuit 160 receiving sensing data from the read / write circuit connected to the memory cell included in the memory cell array through the bit line. The control logic can receive a verification result for the next highest program state. The program state verifier can control the peripheral circuit to determine whether verification for a specific program state passes based on a result of sensing the bit line current.

[0153] When the verification result is a failure, in step S1505, the control logic can increase a program voltage applied to a word line of the memory cell by a unit voltage. The word line voltage controller can control the peripheral circuit to apply an increased program voltage corresponding to a specific program state to a word line commonly connected to the memory cell. The control logic can repeatedly control steps S1501 to S1505 by increasing the program voltage.

[0154] When the verification result is a pass, in step S1507, the memory device can apply a program voltage corresponding to a highest program state among the plurality of program states to a word line of the memory cell. When the program voltage is applied, a threshold voltage of the memory cell can increase and can be included in a threshold voltage distribution corresponding to a target program state.

[0155] In step S1509, the control logic can determine whether verification for a highest program state among the plurality of program states passes. Similar to step S1503, a verification result can be received from the current sensing circuit.

[0156] When the verification result is fail, in step S1511, the control logic 140 can increase the program voltage applied to the word line of the memory cell by a unit voltage. Step S1511 can correspond to step S1505.

[0157] When the verification result is pass, the verification up to the highest program state can be completed, and the program process can be ended.

[0158] According to another embodiment of the present disclosure, when the verification for the (N-1)th program state passes during the verification operation included in the nth program cycle among the plurality of program cycles (S1503), the control logic included in the memory device that performs the program operation of storing data in the memory cells each targeting any one of the first program state to the Nth program state can perform the verification for the Nth program state during the verification operation included in the (n+1)th program cycle among the plurality of program cycles (S1509).

[0159] Figure 1 is a block diagram illustrating a memory card system to which a memory device according to an embodiment of the present disclosure is applied.

[0160] Referring to Figure 17 , the memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

[0161] The memory controller 2100 is connected to the memory device 2200. The memory controller 2100 is configured to access the memory device 2200. For example, the memory controller 2100 can be configured to control a read operation, a program operation, an erase operation, and a background operation of the memory device 2200. The memory controller 2100 is configured to provide an interface between the memory device 2200 and a host. The memory controller 2100 is configured to drive an instruction or a firmware for controlling the memory device 2200. The memory controller 2100 can be implemented identically to the memory controller 200 described with reference to Figure 17 .

[0162] For example, the memory controller 2100 can include components such as a random access memory (RAM), a processor, a host interface, a memory interface, and an error corrector.

[0163] The memory controller 2100 can communicate with an external device through the connector 2300. The memory controller 2100 can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the memory controller 2100 is configured to communicate with an external device through at least one of various communication standards such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 2300 can be defined through at least one of the various communication standards described above.

[0164] For example, the memory device 2200 can be configured of various nonvolatile memory elements such as Electrically Erasable Programmable ROM (EEPROM), NAND flash memory, NOR flash memory, Phase-Change RAM (PRAM), Resistive RAM (ReRAM), Ferroelectric RAM (FRAM), and Spin Transfer Torque Magnetic RAM (STT-MRAM).

[0165] In one embodiment, the memory controller 2100 and the memory device 2200 can be integrated into one semiconductor device to configure a memory card. For example, the memory controller 2100 and the memory device 2200 can be integrated into one semiconductor device to configure a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a CompactFlash (CF) card, a Smart Media card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro, or eMMC), an SD card (SD, miniSD, microSD, or SDHC), and Universal Flash Storage (UFS).

[0166] Figure 1 is a block diagram illustrating a solid state drive (SSD) system to which a storage device according to one embodiment of the disclosure is applied.

[0167] Referring to Figure 18 The SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals with the host 3100 through a signal connector 3001 and receives power through a power connector 3002. The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 through 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0168] According to one embodiment of the disclosure, the SSD controller 3210 can perform the functions of the memory controller 200 described with reference to Figure 18

[0169] The SSD controller 3210 can control the plurality of flash memories 3221 through 322n in response to a signal received from the host 3100. For example, the signal can be a signal based on an interface between the host 3100 and the SSD 3200. For example, the signal can be a signal defined by at least one of interfaces such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a PCI Express (PCI-E), an advanced technology attachment (ATA), a serial ATA, a parallel ATA, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), FireWire, universal flash storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0170] The auxiliary power supply 3230 is connected to the host 3100 through the power connector 3002. The auxiliary power supply 3230 can receive power from the host 3100 and can be charged. The auxiliary power supply 3230 can supply power of the SSD 3200 when the power supply from the host 3100 is not smooth. For example, the auxiliary power supply 3230 can be located in the SSD 3200, or can be located outside the SSD 3200. For example, the auxiliary power supply 3230 can be located on a main board and can supply auxiliary power to the SSD 3200.

[0171] The buffer memory 3240 serves as a buffer memory of the SSD 3200. For example, the buffer memory 3240 can temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 through 322n, or can temporarily store metadata (for example, a mapping table) of the flash memories 3221 through 322n. The buffer memory 3240 can include a volatile memory (for example, DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM), or a non-volatile memory (for example, FRAM, ReRAM, STT-MRAM, and PRAM).

[0172] Figure 1 FIG. 4 is a block diagram illustrating a user system to which a storage device according to one embodiment of the disclosure is applied.

[0173] Referring to Figure 1 , the user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0174] ​The application processor 4100 can drive components included in the user system 4000, such as an operating system (OS) and a user program, etc. The application processor 4100 can include a controller, an interface, and a graphic engine, etc. that control components included in the user system 4000. The application processor 4100 can be set as a system on chip (SoC).

[0175] The memory module 4200 can be used as a main memory, an operation memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 can include a volatile random access memory (e.g., DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM), or a non-volatile random access memory (e.g., PRAM, ReRAM, MRAM, and FRAM). The application processor 4100 and the memory module 4200 can be packaged based on a package on package (POP), and set as one semiconductor package.

[0176] The network module 4300 can communicate with an external device. For example, the network module 4300 can support wireless communication such as code division multiple access (CDMA), global system for mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution, Wimax, WLAN, UWB, Bluetooth, and Wi-Fi. The network module 4300 can be included in the application processor 4100.

[0177] The storage module 4400 can store data. For example, the storage module 4400 can store data received from the application processor 4100. Alternatively, the storage module 4400 can transmit data stored in the storage module 4400 to the application processor 4100. The storage module 4400 can be implemented with a non-volatile memory element such as phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash, NOR flash, and three-dimensional NAND flash. The storage module 4400 can be set as a removable storage device (a removable drive) such as a memory card, and can be set as an external drive of the user system 4000.

[0178] For example, the storage module 4400 can include a plurality of non-volatile memory devices, and the plurality of non-volatile memory devices can operate identically to the memory device 100 described with reference to ​ The storage module 4400 can operate identically to the storage device 50 described with reference to ​ The storage module 4400 can operate identically to the storage device 50 described with reference to

[0179] The user interface 4500 can include an interface for inputting data or instructions to the application processor 4100 or for outputting data to an external device. For example, the user interface 4500 can include a user input interface such as a keypad, a key pad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, and a piezoelectric element. The user interface 4500 can include a user output interface such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor.

[0180] CROSS-REFERENCE TO RELATED APPLICATIONS

[0181] This application claims priority to Korean Patent Application No. 10-2021-0016989, filed on February 5, 2021, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: a memory block including memory cells; a peripheral circuit performing a program operation that increases threshold voltages of the memory cells so that the threshold voltages of the memory cells are included in a threshold voltage distribution corresponding to a target program state among a plurality of program states, the target program state being determined according to data to be stored in the memory cells; and control logic that controls the peripheral circuit to perform the program operation, wherein the program operation includes a plurality of program loops, wherein each of the plurality of program loops includes a program voltage application operation and a verify operation, and wherein, when a verify for a next highest program state among the plurality of program states is determined to pass during a verify operation included in an arbitrary one of the plurality of program loops, the control logic controls the peripheral circuit to perform a verify for a highest program state during a verify operation included in a next program loop of the arbitrary one of the plurality of program loops.

2. The memory device of claim 1, wherein, the next highest program state is an adjacent program state to the highest program state.

3. The memory device of claim 1, wherein, the highest program state is a highest program state among the plurality of program states.

4. The memory device of claim 1, wherein, the control logic includes: a word line voltage controller that controls the peripheral circuit to apply, during the verify operation included in the arbitrary one of the plurality of program loops, a verify voltage corresponding to the next highest program state to a word line to which the memory cells are commonly connected; a bit line current sensing controller that controls the peripheral circuit to sense each of bit line currents according to the threshold voltages of the memory cells while the verify voltage corresponding to the next highest program state is applied; and a program state verifier that determines whether the verify for the next highest program state passes based on a result of the sensing of the bit line currents during the verify operation included in the arbitrary one of the plurality of program loops.

5. The memory device according to claim 4, wherein the program state verifier further calculates a ratio of the memory cells determined to be programmed to the next highest program state based on a sum of the bit line currents, and wherein, when the calculated ratio exceeds a predetermined value, the program state verifier determines that the verify for the next highest program state passes.

6. The memory device of claim 1, wherein, the control logic controls the peripheral circuit to further apply, during the program operation, a program control voltage to bit lines of the memory cells targeting the highest program state while applying a program voltage corresponding to the next highest program state to the word line to which the memory cells are commonly connected.

7. The memory device of claim 6, wherein, the control logic controls the peripheral circuit to vary a magnitude of the program control voltage according to a position of the word line.

8. The memory device of claim 6, wherein, the control logic controls the peripheral circuit to apply the program control voltage when a magnitude of the program voltage applied to the word line exceeds a predetermined value.

9. A memory device, the memory device comprising: a memory block including memory cells; a peripheral circuit that performs a program operation that increases a threshold voltage of the memory cell so that the threshold voltage of the memory cell is included in a threshold voltage distribution corresponding to a target program state among a plurality of program states, the target program state being determined in accordance with data to be stored in the memory cell; and control logic that controls the peripheral circuit to apply, during the program operation, a program control voltage to a bit line of a memory cell that targets a highest program state among the plurality of program states while applying, to a word line to which the memory cell is commonly connected, a program voltage corresponding to a next highest program state among the plurality of program states.

10. The memory device according to claim 9, wherein, the program operation includes a plurality of program loops, and wherein each of the plurality of program loops includes a program voltage application operation and a verify operation.

11. The memory device of claim 10, wherein, the control logic controls the peripheral circuit to apply, during the program voltage application operation of a predetermined program loop among the plurality of program loops, the program voltage corresponding to the next highest program state.

12. The memory device of claim 11, wherein, the control logic includes a program voltage information storage section that includes information about a relationship between a program loop and a program voltage.

13. The memory device of claim 10, wherein, the program voltage corresponding to the next highest program state has a predetermined size in accordance with the memory cell included in the memory block.

14. The memory device of claim 13, wherein, the control logic includes a program voltage information storage section that includes information about a relationship between a voltage size and a program voltage.

15. The memory device of claim 10, wherein, the control logic controls the peripheral circuit to apply, during the program voltage application operation, the program voltage corresponding to the next highest program state so that the memory cell is programmed to a program state adjacent to the highest program state.

16. The memory device of claim 9, wherein, the control logic controls the peripheral circuit to change a size of the program control voltage in accordance with a position of the word line.

17. The memory device of claim 16, wherein, the control logic includes a program control voltage information storage section that includes information about a size of the program control voltage for each of a plurality of word lines included in the memory block.

18. The memory device of claim 9, wherein, the control logic controls the peripheral circuit to apply the program control voltage when a size of the program voltage applied to the word line exceeds a predetermined value.

19. The memory device of claim 10, wherein, the control logic controls the peripheral circuit to further perform a verification for the highest program state during a verify operation included in a next program loop of an arbitrary one of the plurality of program loops when a verification for the next highest program state passes during the verify operation included in the arbitrary one of the plurality of program loops.

20. A memory device that performs a program operation that stores data in a memory cell that targets any one of a first program state to an Nth program state, the memory device comprising: a memory block that includes the memory cell; a peripheral circuit that performs the program operation including a plurality of program loops, each of the plurality of program loops including a program voltage application operation and a verify operation; and control logic that controls the peripheral circuit to perform the program operation, wherein the control logic further: performs a verify for an Nth program state during a verify operation included in an (n+1)th program loop of the plurality of program loops when a verify for an (N-1)th program state passes during the verify operation included in an nth program loop of the plurality of program loops, and applies a program control voltage to bit lines of memory cells targeted for the Nth program state while applying a program voltage corresponding to the (N-1)th program state to a word line to which the memory cells are commonly connected during a program voltage application operation included in the nth program loop.

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