Device and method for protecting wafer from etching damage

Abstract

The present invention relates to the field of semiconductor processing technology, and in particular to a device and method for protecting wafers from etching damage. The device for protecting wafers from etching damage of the present invention comprises a shielding ring and a ceramic ring. The wedge surface design on the upper surface of the shielding ring reduces the influence of reflected power and etching uniformity. Holes are provided on the side of the shielding ring to prevent deformation, cracking or wrinkling of the photoresist on the surface of the wafer due to untimely heat dissipation. By adapting the height of the ceramic ring and the wafer, a gap of a reasonable width is provided between the shielding ring and the wafer to ensure a better protective effect. A groove is provided on the ceramic ring, and the shielding ring is limited by the groove to prevent the shielding ring from moving on the ceramic ring and affecting the protective effect. The method for protecting wafers from etching damage of the present invention only enters and exits the reaction chamber together with the wafer during wafer processing, greatly reducing the influence of the material and structure of the protective device placed in the chamber for a long time on the equipment and process.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor processing technology, and in particular to a device and method for protecting wafers from etching damage. Background Art

[0002] As attached Figure 1 As shown, an inductively coupled deep silicon etching system employs the Bosch process principle, using C4F8 as a passivating polymer generator and SF6 as an etchant. During the passivation process, C4F8 gas is introduced into the reaction chamber. The polymer produced by plasma ionization is deposited on the surface of the silicon wafer to be etched. This process is highly isotropic, resulting in a uniform polymer protective film covering the wafer surface and deep structural trenches. During the subsequent etching process, the gas in the reaction chamber is converted to SF6 and ionized, making it reactive. After plasma is generated at the top, the ions are guided by the lower electrode, causing them to move in a directional manner. A magnetic field is applied around the device to constrain the movement of charged ions and free radicals, ensuring excellent directionality and uniformity, enabling anisotropic etching. By alternating between deposition protection and etching, high-aspect-ratio deep silicon etching is achieved.

[0003] Film transfer and processing workflow: as attached Figure 1 As shown, the wafer 109 is first placed on the wafer carrier of the robot 101. When the vacuum degree of the loadlock chamber 102 (pre-vacuum chamber) matches that of the process chamber 106, the isolation valve 103 is opened, and the robot 101 transfers the wafer 109 on the wafer carrier to the top of the ejector pin 111. The ejector pin 111 rises and lifts the wafer 109 from the wafer carrier. At this time, the wafer 109 is higher than the wafer carrier. The robot 101 returns to the loadlock chamber 102, closes the isolation valve 103, and the ejector pin 111 descends to the ESC110 (Electrostatic Chuck, electrostatic suction cup), place the wafer 109 on ESC110, ESC110 is loaded with DC ±6kV voltage to adsorb the wafer 109, and after the process gas is introduced and stabilized, the RF source 104 is turned on for RF ignition and helium is introduced. The generated plasma is bombarded vertically downward on the wafer 109 in the figure under the action of bias RF 115 and inductive coupling coil 107 (a ceramic cavity 108 is provided around the inductive coupling coil 107 for protection) to etch. The thickness of wafer 109 is about 250 to 400 microns. In the process of etching through holes, if the through hole size of wafer 109 is large, it is necessary to place a film on the back of wafer 109 and place it on ESC110. In this way, it can be ensured that the back of wafer 109 is cooled by He during the process to maintain a certain pressure range to meet the cooling requirements of wafer 109.

[0004] Problems existing in the prior art process: During the etching process, plasma bombards directly downward onto the wafer 109 in the figure. During the deep silicon through-hole etching process, the edge portion of the circumference of the wafer 109, 30 microns in the direction of the center of the circle, is bombarded by plasma to form numerous notches or holes. The edge portion is exactly the portion that is clamped by the tweezers. Since the notches or holes are extremely easy to break when clamped by the tweezers, the entire wafer 109 is scrapped. In addition, in the subsequent processing, defects in the edge portion of the wafer 109 cause processing cracks or poor processing effects, increasing the scrap rate and reducing the yield rate. Existing deep silicon etching equipment mostly uses an electrostatic chuck adsorption method. During the through-hole etching process using the electrostatic chuck adsorption method, due to the lack of circumferential edge protection of the wafer 109, the plasma bombardment of the wafer 109 during the etching process causes damage to the edge, forming numerous notches or holes, which affects subsequent process processing.

[0005] Based on this, it is necessary to develop and design a device to protect wafers from etching damage. Summary of the Invention

[0006] The embodiments of the present invention provide a device and method for protecting wafers from etching damage, which is used to solve the problem in the prior art that plasma directly bombards the wafer downward during the etching process, forming numerous gaps or holes on the edge of the wafer in the direction from the circumference to the center of the circle due to plasma bombardment.

[0007] In a first aspect, an embodiment of the present invention provides a device for protecting a wafer from etching damage, comprising:

[0008] Shielding ring and ceramic ring;

[0009] The inner diameter of the shielding ring is smaller than the diameter of the wafer, the upper part of the inner diameter of the shielding ring is a wedge surface, and the side surface of the shielding ring is provided with a hole;

[0010] The inner ring of the ceramic ring is adapted to the outer ring of the shielding ring. When the wafer is bombarded, the shielding ring is arranged above the ceramic ring. A gap is provided between the shielding ring and the wafer, and the upper surface of the ceramic ring is lower than the lower surface of the wafer.

[0011] In one possible implementation, a groove is provided on the upper surface of the ceramic ring, and the groove has the same shape as the outer ring of the shielding ring. When the wafer is bombarded, the ceramic ring supports the shielding ring through the groove.

[0012] In one possible implementation, the device further includes a wafer carrier ring, wherein the wafer carrier ring is in an open ring shape as a whole, and the inner ring of the wafer carrier ring is smaller than the outer ring of the wafer and the outer ring of the shielding ring;

[0013] When the wafer is fed into a device for bombarding wafers, the wafer is arranged on the inner ring of the wafer carrier ring, and the shielding ring is arranged above the wafer.

[0014] In one possible implementation, the wafer carrier ring is provided with fingers, and when the wafer is fed into the device for bombarding the wafer, the wafer is supported by the fingers.

[0015] In one possible implementation, a hole is provided on the upper surface of the wafer carrier ring, and the wafer carrier ring is connected to a device for transferring wafers through the hole.

[0016] In one possible implementation, the wafer carrier ring is provided with a first groove for supporting the wafer and a second groove for supporting the shielding ring; the first groove and the second groove form a stepped shape.

[0017] In a second aspect, an embodiment of the present invention provides a method for protecting wafers from etching damage, which is applied to a wafer etching device, wherein the wafer etching device is provided with the device for protecting wafers from etching damage as described in the first aspect, and the method comprises:

[0018] Outputting an incoming instruction, wherein the incoming instruction is used to instruct a conveying device to convey a shielding ring and a wafer into the etching chamber, wherein the shielding ring is located above the wafer;

[0019] Outputting a lifting instruction, wherein the lifting instruction is used to instruct the wafer to be lifted and the conveying device to exit the etching chamber;

[0020] Outputting an etching instruction, wherein the etching instruction is used to instruct the wafer to drop and place it on the ESC of the etching equipment to etch the wafer, wherein the ceramic ring is located below the wafer, the upper surface of the ceramic ring is lower than the upper surface of the ESC, and the shielding ring is supported by a groove of the ceramic ring;

[0021] Outputting an outgoing instruction, wherein the outgoing instruction is used to instruct to lift the wafer and transfer the shielding ring and the wafer out of the etching chamber through the conveying device.

[0022] In one possible implementation, the conveying device is equipped with the wafer carrier ring, and the opening direction of the wafer carrier ring is the same as the feeding direction of the conveying device; the ceramic ring is arranged in the etching chamber.

[0023] In a third aspect, an embodiment of the present invention provides a terminal comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and when the processor executes the computer program, it implements the steps of the method described in the second aspect or any possible implementation of the second aspect.

[0024] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the steps of the method described in the second aspect or any possible implementation of the second aspect.

[0025] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0026] The embodiment of the present invention discloses a device for protecting wafers from etching damage. In the embodiment of the device for protecting wafers from etching damage, a shielding ring and a ceramic ring are included. The wedge surface design on the upper surface of the shielding ring reduces the influence of reflected power and etching uniformity. Holes are provided on the side of the shielding ring, through which the heat generated on the upper surface of the wafer during the etching process can be discharged, thereby avoiding deformation, cracking or wrinkling of the photoresist on the surface of the wafer due to untimely heat dissipation. By adapting the height of the ceramic ring to the wafer, a gap of a reasonable width is provided between the shielding ring and the wafer to ensure a better protection effect.

[0027] A groove is provided on the ceramic ring, and the shielding ring is limited by the groove to prevent the shielding ring from moving on the ceramic ring and affecting the protection effect.

[0028] The shielding ring and wafer are transferred into or out of the process chamber through the open carrier ring. The carrier ring is provided with inserting fingers and grooves for supporting the wafer and the shielding ring respectively, so that they are more stable when transferred into or out of the process chamber.

[0029] An embodiment of the present invention also provides a method for protecting wafers from etching damage. In this method, the shielding ring only enters and exits the reaction chamber with the wafer during wafer processing, greatly reducing the impact of the material and structure of the protective device placed in the chamber for a long time on the equipment and process. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0031] Figure 1 This is a schematic diagram of the inductively coupled deep silicon etching system in the prior art;

[0032] Figure 2 is a three-dimensional diagram of a shielding ring provided in an embodiment of the present invention;

[0033] Figure 3is a three-dimensional diagram of a ceramic ring provided in an embodiment of the present invention;

[0034] Figure 4 is a stereoscopic view of a slide ring provided in an embodiment of the present invention;

[0035] Figure 5 This is a schematic diagram of placing a carrier ring, a wafer, and a shielding ring into a loadlock chamber according to an embodiment of the present invention;

[0036] Figure 6 This is a schematic diagram showing a wafer and a shielding ring being lifted by ejector pins according to an embodiment of the present invention;

[0037] Figure 7 This is a schematic diagram of the wafer and the shielding ring in the process chamber after the ejector pins are lowered according to an embodiment of the present invention;

[0038] Figure 8 This is a schematic diagram showing the wafer and shielding ring being retrieved into the loadlock chamber after the ejector pins are lowered according to an embodiment of the present invention;

[0039] Figure 9 This is a flow chart of a method for protecting wafers from etching damage provided by an embodiment of the present invention;

[0040] Figure 10 This is a functional block diagram of a terminal provided by an embodiment of the present invention.

[0041] In the picture:

[0042] 101 Robotic Arm;

[0043] 102 Loadlock cavity;

[0044] 103 Isolation valve;

[0045] 104 RF source;

[0046] 105 lower electrode base;

[0047] 106 process chamber;

[0048] 107 Inductively coupled coil;

[0049] 108 Ceramic cavity;

[0050] 109 wafers;

[0051] 110 ESC;

[0052] 111 thimble;

[0053] 112 ceramic ring;

[0054] 114 cylinders;

[0055] 115 Bias RF;

[0056] 116 shielding ring;

[0057] 117 slide ring;

[0058] 201 wedge surface;

[0059] 202 finger insertion;

[0060] 203 first slot;

[0061] 204 Second slot. DETAILED DESCRIPTION

[0062] In the following description, specific details such as particular system structures and techniques are provided for purposes of illustration, not limitation, to facilitate a thorough understanding of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced in alternative embodiments without these specific details. In other instances, detailed descriptions of well-known systems, devices, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

[0063] In order to make the objectives, technical solutions and advantages of the present invention more clear, the following will be described through specific implementation methods in conjunction with the accompanying drawings.

[0064] The following is a detailed description of an embodiment of the present invention. This example is implemented based on the technical solution of the present invention, and provides a detailed implementation method and specific operation process, but the protection scope of the present invention is not limited to the following embodiment.

[0065] Figure 2 A three-dimensional diagram of a shielding ring 116 provided in an embodiment of the present invention;

[0066] Figure 3 A three-dimensional diagram of a ceramic ring 112 provided in an embodiment of the present invention.

[0067] A device for protecting wafers from etching damage includes: a shielding ring 116 and a ceramic ring 112;

[0068] The inner diameter of the shielding ring 116 is smaller than the diameter of the wafer 109 , the upper portion of the inner diameter of the shielding ring 116 is a wedge surface 201 , and a hole is provided on the side of the shielding ring 116 ;

[0069] The inner ring of the ceramic ring 112 is adapted to the outer ring of the shielding ring 116. When the wafer 109 is bombarded, the shielding ring 116 is arranged above the ceramic ring 112. A gap is provided between the shielding ring 116 and the wafer 109. The upper surface of the ceramic ring 112 is lower than the lower surface of the wafer 109.

[0070] In some embodiments, a groove is provided on the upper surface of the ceramic ring 112 , and the groove has the same shape as the outer ring of the shielding ring 116 . When the wafer 109 is bombarded, the ceramic ring 112 supports the shielding ring 116 through the groove.

[0071] Exemplarily, shield ring 116 is a device used to protect the edge of the top surface of wafer 109. When plasma bombards the top surface of wafer 109 from above, shield ring 116 serves to isolate the top surface of wafer 109 from the plasma bombardment. In one application scenario, based on the degree of damage to the edge of wafer 109 from plasma bombardment, a 1.5mm width of shield ring 116 can be sufficient to shield wafer 109. To reduce the impact of reflected power and etching uniformity, the shielding portion is designed with an upper wedge surface 201 structure and a lower flat structure.

[0072] The plasma bombardment etching process generates a large amount of heat, so the shielding part cannot directly cover the upper surface of the wafer 109. If the heat is not dissipated in time, it will cause the photoresist on the surface of the wafer 109 to wrinkle, deform, and crack, which will directly lead to product failure. In one application scenario, the shielding lower surface of the shielding ring 116 is designed to be 3mm high from the upper surface of the wafer 109.

[0073] The above spacing is achieved by placing the shielding ring 116 on the ceramic ring 112. Since there is no heat dissipation structure in the circumferential direction to affect the heat dissipation rate of the wafer 109, a shielding ring 116 is provided with a ceramic multi-claw support and a hollow structure in the middle that is conducive to heat dissipation, that is, a hole is opened.

[0074] As mentioned above, the ceramic ring 112 is used to support the shielding ring 116. In addition, the ceramic ring 112 also has the function of protecting the aluminum lower electrode ( Figure 1 The lower electrode base 105 in the structure is not damaged during plasma bombardment. The outer diameter of the ceramic ring 112 is designed according to the outer dimensions of the aluminum lower electrode. The shape and size of the center hole match those of ESC110. The groove on the upper surface is used to place the shielding ring 116 in the groove after the ejector pin 111 descends, preventing the shielding ring 116 from moving on the ceramic ring 112 and affecting the protection effect.

[0075] In some embodiments, the device for protecting the wafer from etching damage further includes a wafer carrier ring 117 , wherein the wafer carrier ring 117 is in the shape of an open ring, and the inner ring of the wafer carrier ring 117 is smaller than the outer ring of the wafer 109 and the outer ring of the shielding ring 116 ;

[0076] When the wafer 109 is fed into the wafer bombardment device, the wafer 109 is placed on the inner ring of the carrier ring 117 , and the shielding ring 116 is placed above the wafer 109 .

[0077] In some embodiments, the wafer carrier ring 117 is provided with fingers 202 , and when the wafer 109 is fed into a wafer bombardment device, the fingers 202 support the wafer 109 .

[0078] In some embodiments, a hole is provided on the upper surface of the wafer carrier ring 117 , and the wafer carrier ring 117 is connected to a device for transferring wafers through the hole.

[0079] In some embodiments, the carrier ring 117 is provided with a first groove 203 for supporting the wafer 109 and a second groove 204 for supporting the shielding ring 116 ; the first groove 203 and the second groove 204 form a step shape.

[0080] For example, in an embodiment of the present invention, the ceramic ring 112 is generally disposed in the process chamber 106 , and the shielding ring 116 enters or exits the process chamber 106 together with the wafer 109 .

[0081] A specially designed carrier ring 117 is used to connect to the robot 101 to transfer the wafer 109 and the shielding ring 116 from the process chamber 106 to the loadlock chamber 102, or to transfer the wafer 109 and the shielding ring 116 from the loadlock chamber 102 to the unified chamber.

[0082] like Figure 4 As shown, the wafer carrier ring 117 is an open ring. In one application scenario, the outer contour is shaped like the letter C. The wafer carrier ring 117 is connected to the robot 101, and its upper surface is used to support the shielding ring 116 and the wafer 109. The open ring can avoid unnecessary interference when the shielding ring 116 and the wafer 109 are transferred in and out.

[0083] In some application scenarios, the carrier ring 117 is provided with fingers 202. As we know, the center of gravity of the wafer 109 should fall on the supported part of the carrier ring 117. The carrier ring 117 with fingers 202 obviously has more contact points with the wafer 109, and the support is more stable, reducing the possibility of the wafer 109 falling from the carrier ring 117 due to tilting or unstable center of gravity.

[0084] Two stepped grooves are provided at the supporting portion of the carrier ring 117 , with the smaller groove being located at the bottom for limiting the position of the wafer 109 , and the larger groove being located at the top for limiting the position of the shielding ring 116 .

[0085] Connecting holes are provided at the corresponding positions of the wafer carrier ring 117 and the robot arm 101 for connecting the wafer carrier ring 117 and the robot arm 101 together.

[0086] In an embodiment of the device for protecting a wafer from etching damage of the present invention, a shielding ring 116 and a ceramic ring 112 are included. The wedge surface 201 on the upper surface of the shielding ring 116 is designed to reduce the influence of reflected power and etching uniformity. A hole is provided on the side of the shielding ring 116, through which the heat generated by the upper surface of the wafer 109 during the etching process can be discharged, thereby preventing the deformation, cracking or wrinkling of the photoresist on the surface of the wafer 109 due to the untimely dissipation of heat. By adapting the height of the ceramic ring 112 to the wafer 109, a gap of a reasonable width is provided between the shielding ring 116 and the wafer 109 to ensure a better protection effect.

[0087] A groove is provided on the ceramic ring 112 to limit the shielding ring 116 so as to prevent the shielding ring 116 from moving on the ceramic ring 112 and affecting the protection effect.

[0088] The shielding ring 116 and the wafer 109 are transferred into or out of the process chamber 106 through the open carrier ring 117. The carrier ring 117 is provided with fingers 202 and grooves for supporting the wafer 109 and the shielding ring 116 respectively. Therefore, when transferring into or out of the process chamber 106, it is more stable.

[0089] Figure 5-8 The schematic diagrams of the various working steps of the shielding ring 116, the wafer 109, the carrier ring 117 and the ceramic ring 112 in the wafer etching equipment are respectively shown.

[0090] Figure 9 A flow chart of a method for protecting wafers from etching damage is shown.

[0091] like Figure 5-9 As shown, an embodiment of the present invention provides a method for protecting wafers from etching damage, which is applied to a wafer etching device. The wafer etching device is provided with the device for protecting wafers from etching damage as described above. The method includes:

[0092] Step 901: output an incoming instruction, wherein the incoming instruction is used to instruct the conveying device to convey the shielding ring 116 and the wafer 109 into the etching chamber, wherein the shielding ring 116 is located above the wafer 109;

[0093] Step 902 , outputting a lifting instruction, wherein the lifting instruction is used to instruct the wafer 109 to be lifted up and the conveying device to exit the etching chamber;

[0094] Step 903: Output an etching instruction, wherein the etching instruction is used to instruct the wafer 109 to be dropped and placed on the ESC 110 of the etching equipment to etch the wafer 109, wherein the ceramic ring 112 is located below the wafer 109, the upper surface of the ceramic ring 112 is lower than the upper surface of the ESC 110, and the shielding ring 116 is supported by the groove of the ceramic ring 112;

[0095] Step 904: Output an outgoing instruction, which is used to instruct the wafer 109 to be lifted up and the shielding ring 116 and the wafer 109 to be transferred out of the etching chamber by the conveying device.

[0096] In one possible implementation, the conveying device is equipped with the wafer carrier ring 117, and the opening direction of the wafer carrier ring 117 is the same as the feeding direction of the conveying device; the ceramic ring 112 is disposed in the etching chamber.

[0097] For example, in one application scenario, the etching steps are as follows:

[0098] 1) If Figure 5 As shown, the cover of the Loadlock chamber 102 is opened (not shown in the figure), and a wafer ring 117 is installed on the robot 101. The wafer ring 117 can hold the wafer 109 and the shielding ring 116 at the same time;

[0099] 2) placing the wafer 109 and the shielding ring 116 on the carrier ring 117;

[0100] 3) The robot 101 transfers the wafer 109 and the shield ring 116 to the top of the ESC 110 in the process chamber 106 via the wafer carrier ring 117 of the loadlock chamber 102;

[0101] 4) If Figure 6 As shown, the ejector pin 111 rises from the helium injection hole to lift the wafer 109 and the shielding ring 116 to separate from the robot 101, and the robot 101 returns to the Loadlock chamber 102; Figure 7 As shown, the ejector pin 111 descends, the wafer 109 is placed on the ESC 110 , and the shielding ring 116 is placed in the groove of the ceramic ring 112 with the limiting groove. At this time, a gap of 1.5 mm is formed between the lower surface of the shielding ring 116 and the upper surface of the wafer 109 .

[0102] 5) Run the through-hole etching process, at this time, the shield ring 116 is placed 3 mm above the wafer 109, blocking the radial width of the wafer 109 by 1.5 mm;

[0103] 6) After the etching process is completed, the ejector pins 111 are raised to lift the wafer 109 and the shield ring 116;

[0104] 7) The robot 101 enters the process chamber 106 directly above the ESC 110;

[0105] 8) The ejector pin 111 descends, and the wafer 109 and the shielding ring 116 are placed on the wafer carrier ring 117;

[0106] 9) If Figure 8 As shown, the manipulator 101 retracts to the Loadlock chamber 102;

[0107] In the method for protecting wafers from etching damage in an embodiment of the present invention, the shielding ring 116 only enters and exits the reaction chamber together with the wafer 109 when the wafer 109 is processed, greatly reducing the impact of the material and structure of the protective device placed in the chamber for a long time on the equipment and process.

[0108] It should be understood that the size of the serial numbers of each step in the above embodiment does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.

[0109] The following is an embodiment of the device of the present invention. For details not described in detail, please refer to the corresponding method embodiment described above.

[0110] Figure 10 This is a functional block diagram of a terminal provided by an embodiment of the present invention. Figure 10 As shown, the terminal 10 of this embodiment includes: a processor 1000 and a memory 1001, wherein the memory 1001 stores a computer program 1002 that can be run on the processor 1000. When the processor 1000 executes the computer program 1002, the steps in the above-mentioned methods and embodiments for protecting wafers from etching damage are implemented, for example Figure 9 Steps 901 to 904 are shown.

[0111] Illustratively, the computer program 1002 may be divided into one or more modules / units, and the one or more modules / units are stored in the memory 1001 and executed by the processor 1000 to implement the present invention.

[0112] The terminal 10 may be a computing device such as a desktop computer, a notebook, a PDA, or a cloud server. The terminal 10 may include, but is not limited to, a processor 1000 and a memory 1001. Those skilled in the art will understand that Figure 10 This is merely an example of the terminal 10 and does not constitute a limitation on the terminal 10 . The terminal may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the terminal may also include input and output devices, network access devices, buses, etc.

[0113] The processor 1000 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0114] The memory 1001 may be an internal storage unit of the terminal 10, such as a hard disk or memory of the terminal 10. The memory 1001 may also be an external storage device of the terminal 10, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (Secure Digital), an SD card, a Flash Card, etc. equipped on the terminal 10. Furthermore, the memory 1001 may include both an internal storage unit of the terminal 10 and an external storage device. The memory 1001 is used to store the computer program and other programs and data required by the terminal. The memory 1001 may also be used to temporarily store data that has been output or is about to be output.

[0115] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the implementation method can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method implementation method, and will not be repeated here.

[0116] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0117] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0118] In the embodiments provided herein, it should be understood that the disclosed devices / terminals and methods can be implemented in other ways. For example, the device / terminal embodiments described above are merely illustrative. For example, the division of modules or units is merely a logical functional division. In actual implementation, there may be other division methods, such as multiple units or components being combined or integrated into another system, or some features being ignored or not implemented. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interface, or the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0119] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of this embodiment.

[0120] In addition, the functional units in various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0121] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, it can implement the steps of the above-mentioned various methods for protecting wafer etching damage. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device that can carry the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory Read-Only Memory, ROM, random access memory Random Access Memory, RAM, electrical carrier signal, telecommunication signal and software distribution medium, etc. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practices in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practices, computer-readable media does not include electrical carrier signals and telecommunication signals.

[0122] The above-described embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A device for protecting wafers from etching damage, characterized in that: include: A shielding ring (116) and a ceramic ring (112); The inner diameter of the shielding ring (116) is smaller than the diameter of the wafer (109), the upper portion of the inner diameter of the shielding ring (116) is a wedge surface (201), and a hole is provided on the side surface of the shielding ring (116); The inner ring of the ceramic ring (112) is adapted to the outer ring of the shielding ring (116); when the wafer (109) is bombarded, the shielding ring (116) is arranged above the ceramic ring (112); a gap is provided between the shielding ring (116) and the wafer (109); and the upper surface of the ceramic ring (112) is lower than the lower surface of the wafer (109); The device for protecting the wafer from etching damage further comprises a wafer carrier ring (117), wherein the wafer carrier ring (117) is in the shape of an open ring as a whole, and the inner ring of the wafer carrier ring (117) is smaller than the outer ring of the wafer (109) and the outer ring of the shielding ring (116); The carrier ring (117) is provided with a first groove (203) for supporting the wafer (109) and a second groove (204) for supporting the shielding ring (116); the first groove (203) and the second groove (204) form a step shape.

2. The device for protecting wafers from etching damage according to claim 1, wherein: A groove is provided on the upper surface of the ceramic ring (112), and the groove has the same shape as the outer ring of the shielding ring (116). When the wafer (109) is bombarded, the ceramic ring (112) supports the shielding ring (116) through the groove.

3. The device for protecting wafers from etching damage according to claim 1, wherein: When the wafer (109) is fed into a device for bombarding wafers, the wafer (109) is arranged on the inner ring of the carrier ring (117), and the shielding ring (116) is arranged above the wafer (109).

4. The device for protecting wafers from etching damage according to claim 3, wherein: The carrier ring (117) is provided with fingers (202), and when the wafer (109) is fed into a device for bombarding wafers, the fingers (202) support the wafer (109).

5. The device for protecting wafers from etching damage according to claim 3, wherein: The upper surface of the wafer carrier ring (117) is provided with a hole, and the wafer carrier ring (117) is connected to a device for conveying wafers through the hole.

6. A method for protecting wafers from etching damage, characterized in that: Applied to a wafer etching device, the wafer etching device is provided with the device for protecting wafer etching damage according to any one of claims 3 to 5, and the method comprises: Outputting an incoming instruction, the incoming instruction is used to instruct a conveying device to convey a shielding ring (116) and a wafer (109) into the etching chamber, wherein the shielding ring (116) is located above the wafer (109); Outputting a lifting instruction, wherein the lifting instruction is used to instruct the wafer (109) to be lifted and the conveying device to be withdrawn from the etching chamber; Outputting an etching instruction, the etching instruction is used to instruct the wafer (109) to drop and place on the ESC (110) of the etching equipment to etch the wafer (109), wherein the ceramic ring (112) is located below the wafer (109), the upper surface of the ceramic ring (112) is lower than the upper surface of the ESC (110), and the shielding ring (116) is supported by a groove of the ceramic ring (112); Outputting an outgoing instruction, wherein the outgoing instruction is used to instruct the wafer (109) to be lifted up, and the shielding ring (116) and the wafer (109) to be transferred out of the etching chamber through the conveying device.

7. The method for protecting wafers from etching damage according to claim 6, wherein: The conveying device is equipped with the wafer carrier ring (117), and the opening direction of the wafer carrier ring (117) is the same as the feeding direction of the conveying device; the ceramic ring (112) is arranged in the etching chamber.

8. A terminal comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to claim 6 or 7 are implemented.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to claim 6 or 7 are implemented.

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