Three-dimensional memory and methods of making the same

Abstract

This application provides a three-dimensional memory and a method for fabricating the same. The method for fabricating the three-dimensional memory includes: forming a predetermined via on a stacked structure, wherein the stacked structure includes alternately stacked dielectric layers and sacrificial layers, the predetermined via extending to a corresponding sacrificial layer and exposing a portion of the corresponding sacrificial layer; forming a predetermined layer connected to the exposed portion of the sacrificial layer within the predetermined via; removing at least a portion of the predetermined layer and the sacrificial layer to form a void; and filling the void with a conductive material to form a conductive layer and a gate layer interconnected with each other.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and manufacturing, and more specifically, to the structure of a three-dimensional memory (3D NAND) and its fabrication method. Background Technology

[0002] With the continuous development of technology, people have increasingly higher requirements for memory chips, the core component of electronic products. 3D NAND, as an emerging memory device, has the structural characteristics of three-dimensional stacking, and its storage performance can be improved by increasing the number of stacked layers of memory cells in the three-dimensional structure.

[0003] In the 3D NAND fabrication process, combining different structures for processing can reduce the number of process steps and open up design windows between different structures, thereby reducing processing difficulty and saving production costs.

[0004] It should be understood that the content described in the background section is only for the purpose of helping to understand the technical solutions disclosed in this application, and is not necessarily prior art before the filing date of this application. Summary of the Invention

[0005] This application provides a method for fabricating a three-dimensional memory. The method includes: forming a pre-defined via on a stacked structure, wherein the stacked structure includes alternately stacked dielectric layers and sacrificial layers, the pre-defined via extending to a corresponding sacrificial layer and exposing a portion of the corresponding sacrificial layer; forming a pre-defined layer connected to the exposed portion of the sacrificial layer within the pre-defined via; removing at least a portion of the pre-defined layer and the sacrificial layer to form a void; and filling the void with a conductive material to form a conductive layer and a gate layer interconnected with each other.

[0006] In one embodiment, the stacked structure includes a core region through which a channel structure penetrates and a dummy step region through which a dummy channel structure penetrates, the preset hole being located within the dummy step region, and before forming the gap, the method further includes: forming a plurality of grid line slots through the stacked structure, wherein at least one of the grid line slots extends from the core region to the dummy step region.

[0007] In one embodiment, the sacrificial layer at least includes a first portion and a second portion, wherein the first portion includes a portion of the sacrificial layer located in the dummy step region and near the gate gap, and the second portion includes a portion of the sacrificial layer located in the core region and a portion of the sacrificial layer near the preset layer. The step of forming the gap includes: removing the first portion of the sacrificial layer to form a first gap; and removing the preset layer and the second portion of the sacrificial layer to form a second gap, wherein the first gap and the second gap are interconnected to form the gap.

[0008] In one embodiment, after the preset layer is formed, the remaining portion of the exposed portion of the sacrificial layer that is not connected to the preset layer is exposed. The method further includes: removing the remaining portion to expose a portion of the dielectric layer below the remaining portion; and forming a filling layer in the gap formed after removing the remaining portion and in the remaining space of the preset hole, wherein the filling layer is connected to the exposed portion of the dielectric layer.

[0009] In one embodiment, the step of forming the first gap includes: after forming the filling layer, removing a first portion of the sacrificial layer via the portion of the grid line slot located in the dummy step region and filling the gap formed after removing the first portion of the sacrificial layer with a second protective layer; and after forming the second gap, removing the second protective layer located in the gap to form the first gap.

[0010] In one embodiment, before removing the first portion of the sacrificial layer, the method further includes forming a first protective layer covering the core region portion of the filler layer, the preset layer, and the gate gap.

[0011] In one embodiment, the step of forming the second gap includes: exposing the portion of the gate slot located in the core region and the preset layer; and removing the second portion of the sacrificial layer via the portion of the gate slot located in the core region, and removing the preset layer via the portion exposed by the preset layer, to form the second gap.

[0012] In one embodiment, the step of exposing the portion of the gate wire slot located in the core region and the preset layer includes: removing the first protective layer to expose the gate wire slot and the preset layer; and forming a second protective layer within the portion of the gate wire slot located in the dummy step region.

[0013] In one embodiment, the steps of forming the conductive layer and the gate layer include:

[0014] Conductive material is simultaneously filled in the first gap and the second gap, wherein the portion of the conductive material located between two adjacent dielectric layers forms the gate layer, and the portion of the conductive material located within the preset hole forms the conductive layer, wherein one of the two adjacent dielectric layers is connected to the filling layer.

[0015] In one embodiment, the critical dimension of the dummy channel structure is smaller than the critical dimension of the preset hole.

[0016] In one embodiment, the step of forming the preset hole includes: forming an initial preset hole on the stacked structure, the initial preset hole extending to a dielectric layer and exposing a portion of the dielectric layer; forming an isolation layer on the sidewall of the initial preset hole; and removing the exposed portion of the dielectric layer to form the preset layer exposing the sacrificial layer.

[0017] This application also provides a three-dimensional memory, comprising: a stacked structure including alternately stacked dielectric layers and gate layers; and a plurality of conductive structures extending through a first surface of the stacked structure and respectively to gate layers with different numbers of stacked layers, wherein each of the conductive structures includes a conductive layer and a fill layer, the conductive layer being connected to one of the gate layers with different numbers of stacked layers and surrounding the fill layer, and a dielectric layer located on the side of the fill layer away from the first surface being connected to the fill layer and a first gate layer, the first gate layer being a gate layer among the gate layers connected to the conductive layer.

[0018] In one embodiment, the entire surface of the first gate layer near the dielectric layer is covered with a high dielectric constant layer.

[0019] In one embodiment, the three-dimensional memory includes a core region and a dummy step region. The core region has a channel structure penetrating the stacked structure, the dummy step region has a dummy channel structure penetrating the stacked structure, and the conductive structure is located in the dummy step region, wherein the critical dimension of the dummy channel structure is smaller than the critical dimension of the conductive structure.

[0020] In one embodiment, the conductive structure further includes: an isolation layer located between the stacked structure and the conductive structure and surrounding the conductive layer, and a dielectric layer extending from the first surface to be connected to and located on the first gate layer.

[0021] In one embodiment, the portion of the stacked structure located in the core region includes alternately stacked dielectric and gate layers, and in the step region, the gate layer and sacrificial layer are located on the same stacked layer, the dielectric and gate layers are alternately stacked, and the dielectric and sacrificial layers are alternately stacked.

[0022] In another aspect, this application provides a three-dimensional memory system, comprising: a three-dimensional memory as described in any of the above embodiments, wherein the three-dimensional memory includes a storage string for storing data; and a controller electrically connected to the three-dimensional memory and configured to control the operation of the storage string.

[0023] In one embodiment, the three-dimensional memory includes a 3D NAND memory.

[0024] The method for fabricating the three-dimensional memory provided in this application can have at least one of the following beneficial effects:

[0025] According to some embodiments of this application, the conductive layer and the gate layer can be formed in one processing step, reducing the number of processing steps and thus saving costs.

[0026] According to some embodiments of this application, combining the gate layer and the conductive layer in the same process can free up design windows between different structures and reduce processing difficulty.

[0027] According to some embodiments of this application, gate layer warping defects caused by the etching of the high dielectric constant layer surrounding the gate layer during the formation of the conductive structure can be avoided. Attached Figure Description

[0028] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:

[0029] Figure 1 This is a partial structural schematic diagram of a three-dimensional memory according to an exemplary embodiment;

[0030] Figures 2 to 3 This is a process diagram illustrating a method for fabricating a three-dimensional memory according to an exemplary embodiment;

[0031] Figure 4 This is a flowchart of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application;

[0032] Figures 5 to 16 This is a schematic diagram of the fabrication method of a three-dimensional memory according to an exemplary embodiment of this application;

[0033] Figures 17a to 18b This is a schematic diagram of the structure of a three-dimensional memory according to an exemplary embodiment of this application; and

[0034] Figure 19 This is a schematic diagram of a three-dimensional memory system according to an exemplary embodiment of this application. Detailed Implementation

[0035] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0036] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first portion of the high dielectric constant layer discussed herein may also be referred to as the second portion of the high dielectric constant layer, and the first void may also be referred to as the second void, and vice versa.

[0037] In the accompanying drawings, the thickness, dimensions, and shapes of the components have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. For example, the thickness of the stacked structure depicted in the drawings of this application is not proportional to actual production. Terms such as “approximately,” “about,” and similar expressions used herein are used as terms of approximation, not as terms of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by those skilled in the art.

[0038] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0039] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0040] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0041] The features, principles and other aspects of this application are described in detail below.

[0042] The inventors of this application have discovered that, in some embodiments, it is necessary to bring out the word lines in the 3D NAND memory through conductive structures to achieve electrical connection between the memory cells and external circuits. Figure 1 This is a schematic diagram showing the connection between the conductive structure 100 and the gate layer 113. Figure 2 This is a schematic diagram illustrating the process of forming the conductive structure 100. (Example) Figure 2 As shown, the steps to form the gate layer 113 are to etch away a portion of the sacrificial layer 112 in the stacked structure 110, and then deposit a conductive material (e.g., tungsten metal) in the gap formed by removing the sacrificial layer 112. In order to reduce the gate capacitance, a high dielectric constant layer 114 is also needed to be coated around the gate layer 113.

[0043] The fabrication of the conductive structure 100 must be performed after the formation of the gate layer 113. To achieve the connection between the conductive structure 100 and the gate layer 113, a portion of the sacrificial layer 112 connected to the high-dielectric-constant layer 114 (e.g., ...) is etched away via a pre-defined via 115 during the process. Figure 3 As shown). This process requires a certain overcut window to ensure that the conductive structure on each layer can be connected to the gate layer 113. However, due to the excessively high etching rate of the high dielectric constant layer 114, the etching liquid (such as phosphoric acid solution) / etching gas will remove the entire high dielectric constant layer 114 in a very short time after contacting it, causing the gate layer 113 to be suspended, thus causing the gate layer 113 to warp. Figure 3 (As shown in the dashed area), this can lead to problems such as device damage or electrical performance defects. Gate layer 113 warpage defects have become one of the challenges in 3D NAND fabrication processes.

[0044] This application proposes a three-dimensional memory and its manufacturing method, which can at least partially improve or solve the above-mentioned problems. The conductive layer and gate layer can be formed in a single processing step, reducing processing steps, opening up design windows between different structures, thereby saving costs, reducing processing difficulty, and avoiding gate layer warping defects caused by the etching of the high-dielectric-constant layer surrounding the gate layer during the formation of the conductive structure.

[0045] Figure 4 This is a flowchart of a method 1000 for fabricating a three-dimensional memory according to an embodiment of this application. For example... Figure 4 As shown, this application provides a method 1000 for fabricating a three-dimensional memory, comprising:

[0046] Step S1100: A preset hole is formed on the stacked structure, wherein the stacked structure includes alternately stacked dielectric layers and sacrificial layers, and the preset hole extends to the corresponding sacrificial layer and exposes a portion of the corresponding sacrificial layer;

[0047] Step S1200: A preset layer connected to the exposed portion of the sacrificial layer is formed within the preset hole;

[0048] Step S1300: Remove at least a portion of the preset layer and the sacrificial layer to form a void; and

[0049] In step S1400, conductive material is filled into the gaps to form a conductive layer and a gate layer that are connected to each other.

[0050] It should be understood that the steps shown in method 1000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. Furthermore, some steps shown may be performed simultaneously or in a manner different from [the steps described in the original text]. Figure 4 The execution is performed in the order shown.

[0051] Figures 5 to 16 This is a schematic diagram of the fabrication method 1000 of the three-dimensional memory according to an embodiment of this application. The following is in conjunction with... Figures 5 to 16 The above steps S1100 to S1400 are further described.

[0052] Step S1100: A preset hole is formed on the stacked structure, wherein the stacked structure includes alternately stacked dielectric layers and sacrificial layers, and the preset hole extends to the corresponding sacrificial layer and exposes a portion of the corresponding sacrificial layer.

[0053] like Figure 5As shown, in step S1100, a stacked structure 220 may be formed on the substrate 210. The stacked structure 220 may be formed by sequentially stacking a dielectric layer 130 and a sacrificial layer 140. In some embodiments, the material of the substrate 210 may include, for example, silicon (e.g., single-crystal silicon, polycrystalline silicon), silicon-germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any combination thereof. In some examples, the substrate 210 may include a substrate 211 and a composite layer 212 located on the substrate, wherein the substrate 211 has a certain thickness and can serve as a structural support for the device structure (e.g., the stacked structure 220) formed thereon. Alternatively, the substrate 211 may be removed in some subsequent process steps.

[0054] In some embodiments, the stacked structure 220 may include a direction perpendicular to or substantially perpendicular to the substrate 210. z Multiple dielectric layers 230 and multiple sacrificial layers 240 are alternately stacked in the same direction. Under the same etching conditions, the sacrificial layer 240 and the dielectric layer 230 can have a high etch selectivity so that when the sacrificial layer 240 is removed in a subsequent process, the dielectric layer 230 is hardly removed. In some examples, the material used for the sacrificial layer 240 includes, for example, silicon nitride, and the material used for the dielectric layer 230 includes silicon oxide.

[0055] For example, a stacked structure 220 may be formed on substrate 210 by alternatingly forming a plurality of sacrificial layers 240 and dielectric layers 230 through thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0056] It should be understood that the number of layers in the stacked structure 220 is not limited to the number shown in the figure. Rather, the number of stacked layers and the stacking height of the stacked structure 220 can be designed according to actual needs. This application does not make any specific limitations in this regard.

[0057] In some embodiments, multiple dummy channel structures 250 may be formed in the stacked structure 220. Exemplarily, the method of forming the dummy channel structure 250 includes, for example, first forming a dummy channel via within the stacked structure 250, and then sequentially forming a barrier layer, a charge trapping layer, a tunneling layer, and a channel layer within the dummy channel via to form the dummy channel structure 250. The dummy channel structure 250 can provide mechanical support for subsequent sacrificial layer 240 removal processes.

[0058] In other embodiments, the dummy channel structure 250 can be formed by filling the dummy channel hole with insulating material.

[0059] In some embodiments, a channel structure 251 is also included (see reference). Figure 17b As shown), the channel structure 251 and the virtual channel structure 250 can be along y The orientation is aligned. The channel structure 251 can be located within the core area 20 of the three-dimensional memory, and the preset hole 260 and the virtual channel structure 250 can be located within the virtual step area 10 of the three-dimensional memory. The virtual step area 10 and the core area 20 are also aligned. y Orientation. A method for forming the channel structure 251 includes, for example, first forming a channel via within the stacked structure 250, and then sequentially forming a barrier layer, a charge trapping layer, a tunneling layer, and a channel layer within the channel via to form the channel structure 251. Exemplarily, the barrier layer, charge trapping layer, and tunneling layer may be a silicon oxide-silicon nitride-silicon oxide (ONO) structure. In some examples, the channel layer can be used to transport the desired charge (electrons or holes). The material of the channel layer includes p-type doped polysilicon. The space defined by the channel layer may be filled with a channel filling layer, the material of which includes, for example, silicon oxide or silicon oxynitride.

[0060] For example, a barrier layer, a charge trapping layer, and a tunneling layer can be deposited sequentially using one or more thin film deposition processes (such as ALD, CVD, PVD, or combinations thereof), after which a trench layer can be deposited on the side of the tunneling layer away from the trench aperture.

[0061] Figure 6 This is a schematic diagram illustrating the formation of a preset hole 260 and an isolation layer 270 in a three-dimensional memory according to an embodiment of this application. Figure 6 As shown, it can be on the upper side of the stacked structure 220 (along...) z The process of forming the preset hole 260 includes first forming an initial preset hole 260' (shown in the dashed box) on the upper side of the laminated structure 220, with the initial preset hole 260' along... zThe etching process penetrates the portion of the dielectric layer 230 and sacrificial layer 240 located on the upper side of the stacked structure 220 in the opposite direction, exposing the dielectric layer 230 located below the initial preset hole 260'. Then, an isolation layer 270 is formed on the sidewall of the initial preset hole 260', which protects the sacrificial layer 240 and dielectric layer 230 exposed on the sidewall of the initial preset hole 260' from removal in subsequent etching processes. Finally, the portion of the dielectric layer 230 exposed at the bottom of the initial preset hole 260' is etched away to form the preset hole 260. After the preset hole 260 is formed, the isolation layer 270 is located on the sidewall of the preset hole 260, and the preset hole 260 extends to the corresponding sacrificial layer 240 located below it, exposing a portion of the corresponding sacrificial layer 240. Exemplarily, processes such as photolithography and etching can be used to remove a portion of the upper side of the stacked structure 220 to form the preset hole 260. In some embodiments, the critical dimension of the preset hole 260 is larger than the critical dimension of the dummy channel structure 250. It should be noted that in semiconductor structures, critical dimensions are used to describe structural features. For the pre-defined via 260, the critical dimension may refer to the dimension H1 at its bottom. For the dummy channel structure 250, the critical dimension may refer to its... x The dimension H2 in the direction.

[0062] In some embodiments, an isolation layer 270 is also formed on the upper surface of the stacked structure 220. Exemplarily, the isolation layer 270 can be formed by a thin film deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The material for forming the isolation layer 270 may be, for example, silicon oxide.

[0063] In some embodiments, the upper side of the stacked structure 220 may have a plurality of preset holes 260, each of the plurality of preset holes 260 exposing a sacrificial layer 240 located below it. The sacrificial layer 240 exposed by each preset hole 260 is located on a different number of stacked layers.

[0064] It should be noted that, Figure 6 The shape of the preset hole 260 shown is merely illustrative and is not a limitation on the configuration of the preset hole 260. Those skilled in the art can design a suitable shape of the preset hole 260 according to the specific structural requirements of different storage devices, and this application does not limit it in this regard.

[0065] Step S1200: A preset layer is formed in the preset hole, which is connected to the exposed portion of the sacrificial layer.

[0066] Figure 7 This is a schematic diagram illustrating the formation of a preset layer 280 in a three-dimensional memory according to an embodiment of this application. For example... Figure 7As shown, a preset layer 280 can be formed inside the isolation layer 270 located on the sidewall of the preset hole 260, and the lower end of the preset layer 280 ( z (in the opposite direction) connected to the exposed portion of the sacrificial layer 240. In some embodiments, the lower end of the preset layer 280 does not completely cover the exposed portion of the sacrificial layer 240; after the preset layer 280 is formed, a portion of the sacrificial layer 240 remains (in the opposite direction). Figure 6 The sacrificial layer 240 shown is located in Figure 7 The portion within the gap 241', i.e., the third part 241 of the sacrificial layer shown in the dashed box, is exposed by the remaining portion of the preset hole 260.

[0067] In some embodiments, a preset layer 280 is also formed on the upper surface of the isolation layer 270 located on the upper side of the stacked structure 220. This portion of the preset layer 280 can be removed using processes such as chemical mechanical polishing, and planarized to form a flat or substantially flat plane on the upper surface of the isolation layer 270 on the stacked structure 220. In some embodiments, the preset layer 280 is also formed at the bottom of the preset hole 260. This portion of the preset layer is removed during the gap 241' etching process to ensure that the filling layer 290 extends onto the dielectric layer 230, thereby providing a supporting structure for the filling layer 290 to prevent collapse during the subsequent formation of the second gap 312. The preset layer 280 located within the preset hole 260 is retained, and its upper end is exposed. The isolation layer 270 is... x By completely isolating the sacrificial layer 240 and dielectric layer 230 from the preset layer 280 in the directional direction, it is possible to prevent the etching solution or etching gas from affecting the outer surface of the preset layer 280 (including the surface) during subsequent etching processes of the preset layer 280. x direction and x The sacrificial layer 240 (in the opposite direction) causes mis-etching.

[0068] For example, the material of the preset layer 280 may be the same as that of the sacrificial layer 240, such as silicon nitride. The preset layer 280 may be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0069] In some embodiments, after the preset layer 280 is formed, the portion of the preset layer 280 located at the bottom of the preset hole 260 and the third portion 241 of the sacrificial layer can be removed to form a gap 241', which exposes a portion of the dielectric layer 230 located below the third portion 241 of the sacrificial layer. The portion of the preset layer 280 located at the bottom of the preset hole 260 and the third portion 241 of the sacrificial layer can be removed using processes such as etching.

[0070] like Figure 8As shown, after forming the preset layer 280, a filling layer 290 is also formed in the remaining space of the preset hole 260 and in the gap 241' formed after removing the third portion 241 of the sacrificial layer. The lower surface of the filling layer 290 is in contact with the dielectric layer 230. The sacrificial layer 240 can have a higher etching selectivity than the filling layer 290, thereby removing the second portion 243 of the sacrificial layer in a subsequent etching process. Figure 10b When (as shown), make the etching direction include along x The etching is performed in the reverse direction to improve the etching efficiency of the second portion 243 of the sacrificial layer. Exemplarily, the material forming the filler layer 290 includes an insulating material, such as an oxide. The filler layer 290 can be formed using thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0071] Step S1300: Remove at least a portion of the preset layer and the sacrificial layer to form a void.

[0072] Figure 9 This is a schematic diagram illustrating the formation of a first protective layer 300 and gate line gaps 310 in a three-dimensional memory according to an embodiment of this application. Figure 9 As shown, it can form along z The opposite direction penetrates the laminated structure 220 and along y A grid line slot 310 extending in a certain direction. Exemplarily, the grid line slot 310 may extend along... y In the opposite direction, it sequentially penetrates the virtual step area 10 and the storage area 20 (reference). Figure 10a The gate gap 310 is located on the side of the preset layer 280 near the dummy channel structure 250, for example, it may include the area along the preset layer 280. x The opposite side.

[0073] Figure 10a This is a top view of a three-dimensional memory according to an embodiment of this application. For example... Figure 10a As shown, after forming the gate line gap 310, a first protective layer 300 is formed, which completely covers the isolation layer 270, the preset layer 280, and the fill layer 290. In some embodiments, the first protective layer 300 is also located within the core region 20 and fills the portion of the gate line gap 310 located within the core region 20. Exemplarily, the first protective layer 300 can be formed using one or more thin film deposition processes (e.g., ALD, CVD, PVD, or combinations thereof). The material of the first protective layer 300 includes, for example, carbon materials, polycrystalline silicon, etc.

[0074] Figure 10b yes Figure 10a Cross-sectional view along the AA direction. (See image) Figure 10bAs shown, the portion of the gate gap 310 located within the dummy step region 10 is not filled. A gap 242' can be formed by removing the first portion of the sacrificial layer (not shown) through the unfilled portion of the gate gap 310. The amount of sacrificial layer 240 removed can be controlled by adjusting process parameters such as time, temperature, and etchant concentration to ensure that the area containing the gap 242' is permeated by the dummy channel structure 250. The dummy channel structure 250 provides mechanical support to the dielectric layer 230 during and after the removal of the first portion of the sacrificial layer, maintaining the stability of its physical configuration. During this process, since the portion of the gate gap 310 located within the core region 20 is covered by the first protective layer 300, the first protective layer 300 protects the preset layer 280 and the layers connected to and extending into the core region 20 (e.g., along...). y The second part of the sacrificial layer 243 in the direction extension) Figure 10b (As shown in the dashed box) is not removed, thus ensuring that the amount of the second part 243 of the sacrificial layer removed in subsequent processes is controllable.

[0075] For example, repeated etch-trimming processes, such as photolithography and etching, can be used to form the gate gaps 310. The first portion of the sacrificial layer can be removed using processes such as wet etching.

[0076] Figure 11 This is a process diagram illustrating the formation of the second protective layer 320 in a three-dimensional memory according to an embodiment of this application. (See diagram for example.) Figure 11 As shown, after the gap 242' is formed, the first protective layer 300 can be removed by processes such as etching and chemical mechanical polishing, and a second protective layer 320 can be formed in the portion of the gap 242' and the gate line gap 310 located in the dummy step region 10. Exemplarily, the material of the second protective layer 320 can be the same as the material of the first protective layer 300, such as carbon or polycrystalline silicon. The process for forming the second protective layer 320 can include one or more thin film deposition processes (e.g., ALD, CVD, PVD, or combinations thereof).

[0077] Figure 12 This is a process diagram illustrating the formation of the second gap 312 in a three-dimensional memory according to an embodiment of this application. (See diagram for example.) Figure 12 As shown, a second gap 312 can be formed by removing the preset layer 280 and the second portion 243 of the sacrificial layer. A portion of the second gap 312 is located between the two dielectric layers 230, one end of which is connected to the second protective layer 320, and its critical dimension is larger than the critical dimension of the dummy channel structure 250. This portion can extend into the core region 20 and expose the portion of the channel structure 251 located between the two dielectric layers 230. In some embodiments, this portion can extend into the core region 20 and can extend along... x Direction and / or yThe direction extends throughout the entire core area 20. Another portion of the second gap 312 is connected to the inner wall of the isolation layer 270 and penetrates a portion of the dielectric layer 370 and sacrificial layer 240 located on the upper side of the stacked structure 220, and communicates with the portion of the second gap 312 located between the two dielectric layers 230. Exemplarily, the second gap 312 can be formed by processes such as wet etching. Each sacrificial layer 240 has a second portion 243 of the sacrificial layer that contacts the preset layer 280.

[0078] like Figure 13 As shown, the second protective layer 320 in the removable gap 242' forms a first gap 311, which communicates with the second gap 312. Specifically, the side of the first gap 311 near the second gap 312 is connected to the portion of the second gap 312 located between the two dielectric layers 230. This process step also includes removing the second protective layer 320 in the gate line gap 310. Exemplarily, a wet etching process can be used to remove the second protective layer 320.

[0079] It should be noted that this application is attached with Figure 13 The portions of the first gap 311 and the second gap 312 located between the two dielectric layers 230 are in x The contact position A1 in the direction is merely illustrative and is not intended to limit the scope of this application. For example, the contact position could also be located at A2, in which case a portion of the preset layer 280 and the sacrificial layer 240 could be removed to form a connected void. The end of this void away from the substrate 210 would be exposed to serve as an opening for filling conductive material in subsequent processes.

[0080] In step S1400, conductive material is filled into the gaps to form a conductive layer and a gate layer that are connected to each other.

[0081] Figures 14 to 16 This is a process diagram illustrating the formation of the gate layer 330 in a three-dimensional memory according to an embodiment of this application. (See diagram for example.) Figure 14As shown, conductive material can be filled into the first gap 311 and the second gap 312 simultaneously. The portion of the conductive material on the inner wall of the isolation layer 270 forms a conductive layer 340; the portion of the conductive material between the two dielectric layers 240 forms a gate layer 330. The portion of the gate layer 330 located within the core region 20 penetrates the channel structure 251, and the portion of the gate layer 330 located within the step region 10 penetrates the dummy channel structure 250 and is connected to the conductive layer 340. In some embodiments, the initial conductive material fills the first gap 311 and the second gap 312, and fills the bottom and sidewalls of the gate line gap 310, as well as the upper surface of the isolation layer 270 located on the stacked structure 220. The portion of the initial conductive material filled in the bottom and sidewalls of the gate line gap 310, and the portion covering the upper surface of the isolation layer 270 located on the stacked structure 220, can be removed to form the aforementioned conductive material ( Figure 15 (As shown).

[0082] In some embodiments, a high dielectric constant layer (not shown) may be formed on the sidewalls of the first gap 311 and the second gap 312 using, for example, a thin film deposition process, and then a conductive material may be filled inside the high dielectric constant layer, which may cover the surface of the conductive material.

[0083] In other embodiments, a high dielectric constant layer, an adhesive layer (not shown), and a gate layer 330 may be sequentially formed in the first gap 311 and the second gap 312 using, for example, a thin-film deposition process. Exemplarily, the high dielectric constant layer may be formed of a high dielectric constant material, such as hafnium dioxide, lanthanum oxide, aluminum oxide, tantalum pentoxide, yttrium oxide, hafnium silicate oxide, silicon oxide, silicon nitride, zirconium dioxide, strontium titanate, or zirconium silicate oxide. The adhesive layer material may include, for example, titanium, titanium nitride, tantalum, tantalum nitride, or any combination thereof. The gate layer 330 may be formed of a conductive material, such as tungsten, cobalt, copper, aluminum, or any combination thereof.

[0084] For example, the initial conductive material / conductive material may include any combination of tungsten, cobalt, copper, aluminum, doped crystalline silicon, or silicides. The initial conductive material may be formed using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The portion of the initial conductive material filling the bottom and sidewalls of the gate gap 310 and covering the upper surface of the isolation layer 270 located on the stacked structure 220 may be removed using processes such as etching and chemical mechanical polishing to form the conductive material.

[0085] In some embodiments, to ensure that the gate layer 330 located between the two dielectric layers 230 is not interconnected, when etching away the initial conductive material on the sidewalls of the gate line gap 310, the conductive material located between the two dielectric layers 230 is also over-etched to form a groove shape. For example... Figure 16 As shown, an insulating material 350 can be filled into the groove using a thin-film deposition process, and a filling material 360 can be deposited in the remaining space of the gate line gap 310. The filling material 360 may be made of insulating material and / or conductive material.

[0086] Another aspect of this application provides a three-dimensional memory. This three-dimensional memory can be fabricated using the fabrication methods described in any of the above embodiments.

[0087] refer to Figure 17a As shown, the three-dimensional memory includes a stacked structure 220' and a plurality of conductive structures 400. In some embodiments, the stacked structure 220' includes alternately stacked dielectric layers 230 and gate layers 330. The plurality of conductive structures 400 are located within the stacked structure 220' and extend through a first surface (upper surface) of the stacked structure 220' to gate layers 330 with different numbers of stacked layers. Each conductive structure 400 may include a conductive layer 340 and a fill layer 290. The conductive layer is connected to one of the gate layers 330 with different numbers of stacked layers, and the conductive layer 340 surrounds the fill layer 290 and is located on the fill layer 290 away from the first surface (along...). z The dielectric layer 230 on the opposite side is connected to the filling layer 290 and the first gate layer 330' respectively. The first gate layer 330' is the gate layer in the gate layer 330 that is connected to the conductive layer 340.

[0088] In some embodiments, the entire surface of the first gate layer 330' adjacent to the dielectric layer 230 (with) x The conductive layer 340 is covered with a high dielectric constant layer (not shown) on its outer side (parallel orientation). In some embodiments, the high dielectric constant layer includes a first portion and a second portion. The first portion covers the entire surface of the first gate layer 330' near the dielectric layer 230, while the second portion is located outside and surrounds the conductive layer 340. The presence of the high dielectric constant layer can reduce the gate capacitance.

[0089] In some embodiments, the conductive structure 400 further includes an isolation layer 270 located outside and surrounding the second portion of the high-dielectric-constant layer. Exemplarily, the three-dimensional configuration of the isolation layer 270 may be the same as that of the conductive layer 340, for example, a ring-shaped pillar structure. In some embodiments, the three-dimensional memory also includes a semiconductor layer 210', and the isolation layer 270 may also be formed on the side of the stacked structure 220' away from the semiconductor layer 210'.

[0090] In some embodiments, the projection shape of the conductive layer 340 onto the semiconductor layer 210' includes an annular shape, and the projection of the filling layer 290 onto the semiconductor layer 210' lies within the area enclosed by this annular shape. The lower end of the filling layer 290 (along...) z (in the opposite direction) it is connected to the dielectric layer 230. Exemplarily, the conductive layer 340 extends through the upper portion of the stacked structure 220' and is connected to the gate layer 330. The three-dimensional configuration of the conductive layer 340 may be a ring-shaped columnar structure.

[0091] Figure 17b This is a top view of a three-dimensional memory according to an embodiment of this application. Figure 17a yes Figure 17b (Cross-sectional view along the BB direction). For example... Figure 17b As shown, the three-dimensional memory includes along y The system comprises a directionally arranged dummy step area 10 and a core area 20. A channel structure 251 runs through the core area 20, and a dummy channel structure 250 and a conductive structure 400 run through the dummy step area 10. The dummy channel structure 250 and the conductive structure 400 can extend along... x The channel structure 251 and the conductive structure 400 are oriented and connected through the gate layer 330. y The orientation is aligned and also connected through the gate layer 330. The critical dimension of the dummy channel structure 250 is smaller than the critical dimension of the conductive structure. It should be noted that... Figure 17b The number and arrangement of the dummy channel structure 250, conductive structure 400 and channel structure 251 shown are merely illustrative examples, intended to facilitate the understanding of the present application by those skilled in the art, and are not intended to limit the present application.

[0092] In some implementations, the portion of the stacked structure 220' located in the core region 20 includes alternately stacked dielectric layers 230 and gate layers 330. In the dummy step region 10, the gate layer 330 and the sacrificial layer 240 are located on the same stacked layer, with the dielectric layers 230 and 240 stacked alternately, and the gate layer 330 and 240 stacked alternately.

[0093] In some embodiments, the three-dimensional memory also includes a gate gap structure 370. Both the dummy channel structure 250 and the gate gap structure 370 penetrate the stacked structure 220' and extend to the semiconductor layer 210'. The dummy channel structure 250 is located in the dummy step region 10 and along the conductive structure 400. x The opposite side. The outer side of the gate gap structure 370 ( x direction or x (In the opposite direction) it is also filled with insulating material 350, which can separate the gate layer 330 from the gate gap structure 370.

[0094] In some embodiments, the upper portion of the stacked structure 220' may have multiple conductive structures 400, each of which is connected to a gate layer 330 located below it. The gate layers 330 connected to different conductive structures 400 are located on different layers in the stacked structure 220'.

[0095] Figure 18a This is a top view of a three-dimensional memory according to other embodiments of this application; Figure 18b yes Figure 18a Cross-sectional view along the CC direction. Figure 18a This illustrates a channel array with multiple rows. For example... Figure 18b As shown, the stacked structure 220' may have multiple conductive structures (including conductive structures 400 and 400'). Conductive structures 400 and 400' are respectively connected to gate layers 330 with different numbers of stacked layers. For example, conductive structure 400' is connected to the first layer of gate layer 330, and conductive structure 400 is connected to the third layer of gate layer 330.

[0096] Since the content and structure described in the preparation method 1000 above can be fully or partially applied to the three-dimensional memory described here, related or similar content will not be repeated.

[0097] Another aspect of this application provides a three-dimensional memory system, such as Figure 19 As shown, the three-dimensional storage system includes a three-dimensional memory 501 and a controller 502 as described in any embodiment of this application. The three-dimensional memory 501 includes multiple storage strings with storage functions, each storage string being composed of multiple storage units. The controller 502 is electrically connected to the three-dimensional memory 301 via peripheral circuitry and is configured to control the operation of the storage strings.

[0098] In some embodiments, memory 501 is electrically connected to and controlled by controller 502. Controller 502 may, for example, control the application of different voltage signals to memory cells (not shown) in memory 501 to control memory 501 to perform at least one of, for example, read operations, programming operations, and erase operations.

[0099] In some implementations, controller 502 may be configured to control the operation of memory 501, such as read, program, and erase operations. Controller 502 may also be configured to manage various functions related to data stored or to be stored in memory 501, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.

[0100] In some embodiments, the three-dimensional memory 501 includes a 3D NAND memory, which comprises a plurality of memory cells arranged in a three-dimensional stacked manner. In some embodiments, the three-dimensional memory system also includes a connector 503, which can be connected to a device such as a host computer for transmitting data.

[0101] In some embodiments, the three-dimensional memory system includes a solid-state drive (SSD), a memory card, or any combination thereof. In some embodiments, the controller 502 and the memory 501 may be integrated onto the SSD to form the three-dimensional memory system. The storage capacity and / or operating speed of the SSD may be higher than that of the memory card. The three-dimensional memory 501 of any embodiment of this application can be applied to storage devices or memory cards such as memory sticks, PC cards, compact flash (CF) cards, smart media (SM) cards, multimedia cards, SD cards, and universal flash memory (UFS).

[0102] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for fabricating a three-dimensional memory, comprising: A pre-defined hole is formed in a stacked structure, wherein the stacked structure includes alternately stacked dielectric layers and sacrificial layers, and the pre-defined hole penetrates a portion of the dielectric layer and the sacrificial layer and extends to the corresponding sacrificial layer and exposes a portion of the corresponding sacrificial layer; A preset layer is formed within the preset hole, which is connected to the exposed portion of the sacrificial layer; Removing the preset layer and a portion of the sacrificial layer to form a void; and The gaps are filled with conductive material to form a conductive layer and a gate layer that are interconnected with each other. The conductive layer extends through the remaining portion of one or more of the sacrificial layers.

2. The method according to claim 1, wherein, The layered structure includes a core area with a channel structure running through it and a dummy step area with a dummy channel structure running through it. The pre-set hole is located within the dummy step area. Before forming the void, the method further includes: Multiple grid line slots are formed that run through the stacked structure, wherein at least one of the grid line slots extends from the core region to the dummy step region.

3. The method according to claim 2, wherein, The sacrificial layer includes at least a first portion and a second portion of the sacrificial layer. The first portion of the sacrificial layer includes the portion of the sacrificial layer located in the dummy step region and near the gate wire gap, and the second portion of the sacrificial layer includes the portion of the sacrificial layer located in the core region and the portion of the sacrificial layer near the preset layer. The steps for forming the void include: Removing the first portion of the sacrificial layer to form a first void; and The second part of the preset layer and the sacrificial layer is removed to form a second gap, and the first gap and the second gap are connected to each other to form the gap.

4. The method according to claim 3, wherein, After the preset layer is formed, the remaining portion of the exposed portion of the sacrificial layer that is not connected to the preset layer is exposed, and the method further includes: Remove the remaining portion to expose a portion of the dielectric layer beneath it; and A filling layer is formed in the gap formed after removing the remaining portion and in the remaining space of the preset hole, wherein the filling layer is connected to the exposed portion of the dielectric layer.

5. The method according to claim 4, wherein, The steps for forming the first gap include: After forming the filler layer, the first portion of the sacrificial layer is removed via the portion of the grid line gap located in the dummy step region, and a second protective layer is filled into the gap formed after removing the first portion of the sacrificial layer; and After the second gap is formed, the second protective layer located within the gap is removed to form the first gap.

6. The method according to claim 5, wherein, Before removing the first portion of the sacrificial layer, the method further includes: A first protective layer is formed covering the core region portion of the filling layer, the preset layer, and the grid line gaps.

7. The method according to claim 6, wherein, The steps for forming the second gap include: Exposing the portion of the gate wire gap located in the core region and the preset layer; and The second portion of the sacrificial layer is removed through the portion of the core region via the grid line gap, and the preset layer is removed through the portion exposed by the preset layer to form the second gap.

8. The method according to claim 7, wherein, The step of exposing the portion of the gate wire slot located in the core region and the preset layer includes: Removing the first protective layer exposes the gate wire gaps and the preset layer; and A second protective layer is formed within the portion of the grid line gap located in the dummy step area.

9. The method according to claim 4, wherein, The steps of forming the conductive layer and the gate layer include: Conductive material is simultaneously filled into the first gap and the second gap, wherein the portion of the conductive material located between two adjacent dielectric layers forms the gate layer, and the portion of the conductive material located within the predetermined hole forms the conductive layer. One of the two adjacent dielectric layers is connected to the filling layer.

10. The method according to claim 6, wherein, The critical dimension of the dummy channel structure is smaller than the critical dimension of the preset hole.

11. The method according to claim 2, wherein, The steps for forming the preset hole include: An initial preset hole is formed on the stacked structure, the initial preset hole extending to the dielectric layer and exposing a portion of the dielectric layer; An isolation layer is formed on the sidewall of the initial preset hole; and The exposed portion of the dielectric layer is removed to form the preset layer that exposes the sacrificial layer.

12. A three-dimensional memory, comprising: A stacked structure, including a first stacked structure and a second stacked structure, wherein the first stacked structure includes a first portion of alternatingly stacked dielectric layers and a gate layer, and the second stacked structure includes a second portion of alternatingly stacked dielectric layers and a sacrificial layer; as well as Multiple conductive structures pass through the first surface of the second stacked structure and extend to gate layers with different numbers of stacked layers, Each of the conductive structures includes a conductive layer and a filling layer. The conductive layer penetrates one or more of the sacrificial layers. The conductive layer is connected to one of the gate layers with different stacking numbers and surrounds the filling layer. A dielectric layer located on the side of the filling layer away from the first surface is connected to the filling layer and the first gate layer, respectively. The first gate layer is the gate layer connected to the conductive layer among the gate layers.

13. The three-dimensional memory according to claim 12, wherein, The entire surface of the first gate layer near the dielectric layer is covered with a high dielectric constant layer.

14. The three-dimensional memory according to claim 12, wherein, The three-dimensional memory includes a core region and a dummy step region. The core region has a channel structure penetrating the first stacked structure, and the dummy step region has a dummy channel structure penetrating the second stacked structure. The conductive structure is located within the dummy step region. The critical dimension of the dummy channel structure is smaller than the critical dimension of the conductive structure.

15. The three-dimensional memory according to claim 12, wherein, The conductive structure further includes: An isolation layer is located between the second stacked structure and the conductive structure, and surrounds the conductive layer, as well as a dielectric layer extending from the first surface to be connected to and located on the first gate layer.

16. The three-dimensional memory according to claim 14, wherein, The first stacked structure is located in the core region, the second stacked structure is located in the step region, and the gate layer and the sacrificial layer are located on the same stacked layer.

17. A three-dimensional memory system, comprising: The three-dimensional memory as described in any one of claims 12-16, wherein the three-dimensional memory includes a storage string for storing data; and A controller, electrically connected to the three-dimensional memory, is configured to control the operation of the memory string.

18. The three-dimensional memory system according to claim 17, wherein, The three-dimensional memory includes 3D NAND memory.

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