A method for preparing a three-dimensional integrated filter and its structure

Abstract

The present invention discloses a method for fabricating a three-dimensional integrated filter and its structure. The method includes etching trenches on the surface of a single-crystalline silicon and etching a single-crystalline silicon nanopore array at the bottom of the trenches; fabricating a capacitor structure on the surface of the single-crystalline silicon nanopores; sequentially depositing an etch stop layer and a first isolation medium on the surface of the trenches and etching a first isolation medium nanopore structure; fabricating an inductor structure on the surface of the first isolation medium nanopores and realizing the series connection of the capacitor and the inductor; and performing metal wiring to obtain two contact electrodes of the filter. The present invention directly integrates the filter on the chip surface, reduces the area it occupies, and effectively improves the integration degree of the active area.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit manufacturing, and particularly relates to a method for fabricating a three-dimensional integrated filter and its structure. Background Art

[0002] With the advent of the intelligent era, people's demand for the integration degree of integrated circuits has been continuously increasing, but the feature size of devices has approached the physical limit. To further improve performance and integration degree, some researchers integrate heterogeneous systems in the three-dimensional direction of the chip, which can greatly improve the functional density of the chip. However, in the process of three-dimensional heterogeneous system integration, the sizes of various components seriously affect the size of system integration. Especially some planar passive devices, such as filters, etc., have large sizes and occupy a large planar area of the system, resulting in a decrease in the density of active devices, which will lead to a decrease in the operation speed of logic circuits and a decrease in the storage capacity of storage devices.

[0003] The prior art discloses CN112018070A, a three-dimensional integrated structure of a nano-capacitor and its preparation method. The capacitor preparation uses chemical vapor deposition process to deposit a layer of SiO2 film on the surface of the trench and single-crystalline silicon nanopores as the first isolation medium 201; subsequently, physical vapor deposition process is used to deposit a layer of TiN film, a layer of Al2O3 film and a layer of TiN film on the surface of the first isolation medium 201 in sequence, as the first bottom metal electrode layer 202, the first insulating medium 203 and the first top metal electrode layer 204 respectively, and the first top metal electrode layer completely fills the silicon nanopores. This capacitor structure deposits a layer of SiO2 film as the first isolation medium before forming the first bottom metal electrode layer, and the first isolation medium occupies a part of the volume of the single-crystalline silicon nanopores, which will cause the aspect ratio of the single-crystalline silicon nanopores to become larger after depositing the first isolation medium, thus being unfavorable for the conformal deposition of the subsequent first metal electrode layer, the first insulating medium and the first top metal electrode layer.

[0004] Therefore, it is urgent to adopt new technologies to directly integrate the filter on the chip surface to reduce the area it occupies and improve the integration degree of the active area. Summary of the Invention

[0005] In order to solve the above technical problems, the present invention provides a method for fabricating a three-dimensional integrated filter and its structure, which realizes directly integrating the filter on the chip surface and improves the integration degree of the active area.

[0006] The present invention is realized according to the following technical solutions:

[0007] On the one hand, the present invention provides a method for fabricating a three-dimensional integrated filter, comprising: etching grooves on the surface of a single crystal silicon and etching a single crystal silicon nanopore array at the bottom of the grooves; fabricating a capacitance structure on the surface of the single crystal silicon nanopores; sequentially depositing an etching stop layer and a first isolation medium on the surface of the grooves and etching a first isolation medium nanopore structure; fabricating an inductance structure on the surface of the first isolation medium nanopores and realizing the series connection of the capacitance and the inductance; and performing metal wiring to obtain two contact electrodes of the filter.

[0008] Preferably, the fabricating of the capacitance structure on the surface of the single crystal silicon nanopores specifically comprises: depositing a transition layer metal on the surfaces of the grooves and the single crystal silicon nanopores; using a rapid thermal annealing process to react the transition layer metal with the single crystal silicon substrate to generate a metal silicide thin film, and using the metal silicide thin film as a first bottom metal electrode layer; sequentially depositing a first insulating dielectric layer and a first top metal electrode layer on the surface of the first bottom metal electrode layer to form a capacitance structure; and the first top metal electrode layer completely fills the single crystal silicon nanopores.

[0009] Preferably, the thickness range of the first bottom metal electrode layer of the metal is 5 - 10 nm, the thickness range of the first insulating dielectric is 10 - 50 nm, and the thickness range of the first top metal electrode layer is 150 - 400 nm.

[0010] Preferably, the sequentially depositing an etching stop layer and a first isolation medium on the surface of the grooves and etching a first isolation medium nanopore structure specifically comprises: depositing an etching stop layer on the surface of the first top metal electrode layer; growing a first isolation medium on the surface of the etching stop layer; removing the first isolation medium on the top of the grooves to make the first isolation medium flush with the etching stop layer on the two side platforms of the grooves; determining the patterns of the first isolation medium nanopores and the grooves on the surface of the right etching stop layer on the surfaces of the first isolation medium and the etching stop layer; and etching the first isolation medium and the right etching stop layer to respectively form a first isolation medium nanopore structure and an etching stop layer groove.

[0011] Preferably, the diameter range of the first isolation medium nanopores is 0.5 - 1 μm, and the depth range is 10 - 20 μm.

[0012] Preferably, preparing an inductance structure on the surface of the first isolation dielectric nanopore and realizing the series connection of a capacitor and an inductor specifically includes: depositing a second metal layer on the surface of the first isolation dielectric nanopore, an etch stop layer, and an etch stop layer trench, and the second metal layer forms the inductance structure; the first top metal electrode layer at the etch stop layer trench is interconnected with the second metal layer to realize the series connection of the capacitor and the inductor; removing a part of the first insulating dielectric, the first top metal electrode layer, the etch stop layer, and the second metal layer on the left side to expose the first bottom metal electrode layer; depositing a second isolation dielectric on the surface of the second metal layer and the exposed first bottom metal electrode layer; and the second isolation dielectric completely fills the first isolation dielectric nanopore structure.

[0013] Preferably, obtaining two contact electrodes of the filter by metal wiring specifically includes: removing a part of the second isolation dielectric on the left and right sides to respectively expose the first bottom metal layer and the second metal layer and form two trench structures; sequentially depositing a copper diffusion barrier layer and a copper seed layer on the surfaces of the two trench structures; removing a part of the copper seed layer and the copper diffusion barrier layer located above the second isolation dielectric, so that the copper seed layer and the copper diffusion barrier layer are broken into left and right two regions; electroplating a layer of copper metal layer on the surface of the copper seed layer; and the left copper metal layer and the right copper metal layer are respectively used as the two contact electrodes of the filter.

[0014] On the other hand, the present invention also provides a three-dimensional integrated filter structure, including

[0015] a single crystal silicon substrate, etching the substrate to form a trench, and etching a single crystal silicon nanopore array at the bottom of the trench;

[0016] a capacitor structure, the basic framework is located on the surface of the single crystal silicon nanopore, including a first bottom metal electrode layer, a first insulating dielectric, and a first top metal electrode layer that are sequentially covered; the first top metal electrode layer completely fills the single crystal silicon nanopore; a layer of etch stop layer is deposited on the surface of the first top metal electrode layer; an etch stop layer trench is provided on the etch stop layer on the right platform of the trench; a part of the first bottom metal electrode layer on the left platform of the trench is exposed, and the part not covered by the first insulating dielectric, the first top metal electrode layer, and the etch stop layer; the surface of the etch stop layer is covered with a first isolation dielectric, and the first isolation dielectric is flush with the etch stop layer on the two platforms on both sides of the trench; the first isolation dielectric is etched to form a first isolation dielectric nanopore structure;

[0017] an inductance structure, the basic framework is located in the first isolation dielectric nanopore structure, and is composed of a second metal layer covering the surface of the first isolation dielectric nanopore, the surface of a part of the etch stop layer, and the surface of the exposed first top metal layer;

[0018] The capacitive structure and the inductive structure are interconnected through the first top metal electrode layer and the second metal layer at the etched termination layer trench, realizing the series connection of the capacitor and the inductor;

[0019] A second isolation medium, the second isolation medium covering the surface of the second metal layer and the exposed first bottom metal electrode layer; the second isolation medium completely fills the first isolation medium nanopore structure; part of the second isolation medium on the left and right is removed to expose the first bottom metal layer and the second metal layer respectively, and two second isolation medium trench structures are formed;

[0020] A top metal contact area for generating two contact electrodes of the filter at the two second isolation medium trenches.

[0021] Preferably, the first bottom metal electrode layer is composed of a metal silicide formed by the reaction of a transition layer metal deposited on the surface of the trench and the single-crystalline silicon nanopore with the silicon substrate.

[0022] Preferably, the top metal contact area includes: a copper diffusion barrier layer, a copper seed layer, and a copper metal layer; the copper diffusion barrier layer and the copper seed layer cover the surfaces of the two second isolation medium trenches and are disconnected in the middle area; the copper seed layer covers the copper diffusion barrier layer and the copper seed layer respectively; the left copper metal layer and the right copper metal layer serve as the two contact electrodes of the filter respectively.

[0023] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0024] The present invention realizes a three-dimensional integrated filter, and the capacitive structure can obtain capacitive structures with different capacitance values by adjusting the aspect ratio of the single-crystalline silicon nanostructure, and the inductive structure can obtain inductive structures with different inductance values by adjusting the aspect ratio of the isolation medium nanostructure; the capacitive and inductive structures of the present invention are vertically stacked together, greatly reducing the planar area occupied by the filter, with high integration, and realizing a filter with a small size; the first bottom metal electrode layer of the capacitive structure in the present invention is formed by the reaction of the transition layer metal with the single-crystalline silicon substrate, and since a part of the single-crystalline silicon substrate is consumed, the single-crystalline silicon nanopore still has a large aspect ratio when forming the first bottom metal electrode layer, which is beneficial to the conformal deposition of the subsequent first insulating medium and the first top metal electrode layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art.

[0026] Figure 1 It is a flowchart of a method for preparing a three-dimensional integrated filter provided by an embodiment of the present invention;

[0027] Figure 2 Schematic diagram of the structure for etching a single-crystalline silicon substrate to form trenches

[0028] Figure 3 Schematic diagram of the structure for etching the single-crystalline silicon region at the bottom of the trench to form a single-crystalline silicon nanopore array

[0029] Figure 4 Schematic diagram of the structure for depositing a transition layer metal on the surfaces of the trench and the single-crystalline silicon nanopores

[0030] Figure 5 Schematic diagram of the structure for successively depositing a first bottom metal electrode layer, an insulating dielectric, and a first top metal electrode layer

[0031] Figure 6 Schematic diagram of the structure for depositing an etching stop layer

[0032] Figure 7 Schematic diagram of the structure for depositing a first isolation dielectric

[0033] Figure 8 Schematic diagram of the structure formed by etching the surfaces of the first isolation dielectric and the right-side etching stop layer

[0034] Figure 9 Schematic diagram of the structure for depositing a second metal layer

[0035] Figure 10 Schematic diagram of the structure obtained by removing a part of the first insulating dielectric, the first top metal electrode layer, the etching stop layer, and the second metal layer on the left side

[0036] Figure 11 Schematic diagram of the structure for depositing a second isolation dielectric

[0037] Figure 12 Schematic diagram of the structure for forming second and third trenches by removing a part of the second isolation dielectric on the left and right sides

[0038] Figure 13 Schematic diagram of the structure for successively depositing a copper diffusion barrier layer and a copper seed layer on the surfaces of the two trench structures

[0039] Figure 14 Schematic diagram of the structure for removing a part of the copper diffusion barrier layer and the copper seed layer located above the second isolation dielectric

[0040] Figure 15 Schematic diagram of the three-dimensional integrated filter structure prepared by the present invention

[0041] Reference numerals: 200, single-crystalline silicon substrate; 201, first bottom metal electrode layer; 202, first insulating dielectric; 203, first top metal electrode layer; 204, etch stop layer; 205, first isolation dielectric; 206, second metal layer; 207, second isolation dielectric; 208, copper diffusion barrier layer; 209, copper seed layer; 210, copper metal layer; 300, transition layer metal. Detailed implementation manners

[0042] The following details the implementation manners of the present invention, and examples of the implementation manners are shown in the drawings. The implementation manners described below with reference to the drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0043] It should be clear that the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0044] The following details the optional embodiments of the present disclosure with reference to the drawings.

[0045] Refer to Figure 1 As shown, it is a flowchart of a method for preparing a three-dimensional integrated filter provided by an embodiment of the present invention. The preparation method includes:

[0046] S1: Etch trenches on the surface of a single-crystalline silicon and etch a single-crystalline silicon nanopore array at the bottom of the trenches. This step specifically includes:

[0047] Determine the position of the trenches on the surface of the single-crystalline silicon;

[0048] Etch the single-crystalline silicon substrate to form trenches;

[0049] Determine the pattern of the single-crystalline silicon nanopores inside the trenches;

[0050] Etch the single-crystalline silicon region at the bottom of the trenches to form a single-crystalline silicon nanopore array.

[0051] Specifically, in some embodiments, first, spin-coat a photoresist and define the position of the trenches through exposure and development processes; then, use a deep reactive ion etching (DRIE) process to etch the single-crystalline silicon substrate 200 to form trenches, and the obtained structure is as Figure 2 shown. Among them, preferably, the width of the trenches is greater than 1 cm, and the depth range is 10 - 20 μm; then, spin-coat a photoresist inside the trenches and define the pattern of the single-crystalline silicon nanopores through exposure and development processes; subsequently, use the DRIE process to etch the single-crystalline silicon 200 region at the bottom of the trenches to form a single-crystalline silicon nanopore array, and the obtained structure is as Figure 3As shown in the figure. Among them, the diameter of the preferred single-crystalline silicon nanopores ranges from 0.5 to 1 μm, and the depth ranges from 10 to 20 μm; the plasma for etching the single-crystalline silicon substrate 200 can be at least one of CF4 and SF6.

[0052] Step S2: Fabricate a capacitive structure on the surface of the single-crystalline silicon nanopores. This step specifically includes:

[0053] Deposit a transition layer metal on the surface of the trenches and the single-crystalline silicon nanopores;

[0054] Use rapid thermal annealing to react the transition layer metal with the single-crystalline silicon substrate to generate a metal silicide film, and use the metal silicide film as the first bottom metal electrode layer;

[0055] Deposit a first insulating dielectric layer and a first top metal electrode layer on the surface of the first bottom metal electrode layer in sequence to form a capacitive structure;

[0056] The first top metal electrode layer completely fills the single-crystalline silicon nanopores.

[0057] In the embodiment of the present application, the capacitive structure uses a single-crystalline silicon nanostructure as the substrate, and realizes a capacitive structure with different capacitance values by adjusting the aspect ratio of the single-crystalline silicon nanostructure.

[0058] Specifically, in some embodiments, first, a physical vapor deposition process is used to deposit a metal Ni film as the transition layer metal 300 on the surface of the trenches and the single-crystalline silicon nanopores, and the obtained structure is as Figure 4 shown; then, the above structure is annealed using a rapid thermal annealing process, and the transition layer 300 reacts with the silicon substrate 200 to generate a metal silicide NiSi as the first bottom metal electrode layer 201. The first bottom metal electrode layer is formed by the reaction of the transition layer metal with the single-crystalline silicon substrate. Since a part of the single-crystalline silicon substrate is consumed, the single-crystalline silicon nanopores still have a large aspect ratio when forming the first bottom metal electrode layer, which is beneficial to the conformal deposition of the subsequent first insulating dielectric and the first top metal electrode layer. Subsequently, a physical vapor deposition process is used to deposit a layer of Al2O3 film 202 and a layer of TiN film 203 on the surface of the first bottom metal electrode layer 201, as the first insulating dielectric and the first top metal electrode layer respectively, and the first top metal electrode layer completely fills the silicon nanopores, and the obtained structure is as Figure 5 shown.

[0059] Preferably, the thickness range of the first insulating dielectric 202 is 5 to 10 nm, the thickness range of the first top metal electrode layer 203 is 10 to 50 nm, and the thickness range of the etch stop layer 204 is 150 to 400 nm.

[0060] In this embodiment, a deep reactive ion etching process is used to obtain the through-silicon via structure. However, the present invention is not limited thereto, and at least one process of dry etching such as ion milling etching, plasma etching, reactive ion etching, deep reactive ion etching, laser ablation, or wet etching using an etchant solution can be selected. In addition, in this embodiment, NiSi is used as the first bottom metal electrode layer, TiN is used as the first top metal electrode layer, and an Al2O3 thin film is used as the first insulating dielectric layer. However, the present invention is not limited thereto, and at least one of NiSi, CoSi, and TiSi can be selected as the first bottom metal electrode layer; at least one of TaN, TiN, WN, MoN, Ni, and Ru can be selected as the first top metal electrode layer; and at least one of Al2O3, ZrO2, TiO2, HfO2, La2O3, HfZrO, HfAlO, and HfTiO can be selected as the first insulating dielectric layer.

[0061] Step S3: Deposit an etch stop layer and a first isolation dielectric on the trench surface in sequence and etch out a first isolation dielectric nanopore structure. This step specifically includes:

[0062] Deposit an etch stop layer on the surface of the first top metal electrode layer;

[0063] Grow a first isolation dielectric on the surface of the etch stop layer;

[0064] Remove the first isolation dielectric on the top of the trench to make the first isolation dielectric flush with the etch stop layer on the platforms on both sides of the trench;

[0065] Determine the pattern of the first isolation dielectric nanopores and the trench on the surface of the right etch stop layer on the surface of the first isolation dielectric and the etch stop layer;

[0066] Etch the first isolation dielectric and the right etch stop layer to form a first isolation dielectric nanopore structure and an etch stop layer trench respectively.

[0067] Specifically, in some embodiments, first, a Si3N4 thin film 204 is deposited on the surface of the first top metal electrode layer 203 as an etch stop layer by chemical vapor deposition, and the obtained structure is as Figure 6 shown. Then, a SiO2 thin film 205 is grown on the surface of the etch stop layer 204 as the first isolation dielectric by chemical vapor deposition, and the first isolation dielectric 205 on the top of the trench is removed by photolithography and etching processes, that is, the first isolation dielectric 205 is flush with the etch stop layer 204 on the platforms on both sides of the trench, and the obtained structure is as Figure 7As shown. Next, a photoresist is spin-coated on the surfaces of the first isolation medium 205 and the etch stop layer 204, and the patterns of the first isolation medium nanopores and the grooves on the surface of the right etch stop layer are defined through exposure and development processes; subsequently, the surfaces of the first isolation medium 205 and the right etch stop layer are etched using the DRIE process, and the obtained structure is as Figure 8 shown.

[0068] Preferably, the diameter of the first isolation medium nanopores ranges from 0.5 to 1 μm, and the depth ranges from 10 to 20 μm. The plasma for etching the first isolation medium 205 can be at least one of CF4 and SF6.

[0069] In this embodiment, an Si3N4 thin film is used as the etch stop layer, and SiO2 is used as the first isolation medium. However, the present invention is not limited thereto, and at least one of Si3N4 and SiON can be selected as the etch stop layer. The growth methods of the etch stop layer and the second isolation medium layer can be at least one of physical vapor deposition, chemical vapor deposition, electron beam evaporation, and pulsed laser deposition.

[0070] Step S4: Fabricate an inductance structure inside the isolation medium nanopores and achieve the series connection of capacitance and inductance. This step specifically includes:

[0071] Deposit a second metal layer on the surfaces of the first isolation medium nanopores, the etch stop layer, and the grooves of the etch stop layer, and the second metal layer forms an inductance structure;

[0072] The first top metal electrode layer at the grooves of the etch stop layer is interconnected with the second metal layer to achieve the series connection of capacitance and inductance;

[0073] Remove a part of the first insulating medium, the first top metal electrode layer, the etch stop layer, and the second metal layer on the left to expose the first bottom metal electrode layer;

[0074] Deposit a second isolation medium on the surfaces of the second metal layer and the exposed first bottom metal electrode layer;

[0075] The second isolation medium completely fills the first isolation medium nanopore structure.

[0076] In the embodiments of the present application, the inductance structure uses an isolation medium nanostructure as a substrate, and inductance structures with different inductance values can be obtained by adjusting the aspect ratio of the isolation medium nanostructure.

[0077] Specifically, in some embodiments, first, a layer of Ni film 206 is deposited as the second metal layer on the surfaces of the first isolation medium nanopores, the etch stop layer, and the grooves of the etch stop layer using physical vapor deposition process. At the same time, the second metal layer 206 forms an inductance structure, and the obtained structure is as Figure 9As shown. Among them, the thickness range of the preferred second metal layer 206 is 100-200 nm. Then, the lithography and etching processes are used to remove part of the first insulating medium 202, the first top metal electrode layer 203, the etch stop layer 204, and the second metal layer 206 on the left side, and the obtained structure is as Figure 10 shown. Next, a SiO2 thin film is grown on the surface of the second metal layer 206 by chemical vapor deposition as the second isolation medium 207, and the second isolation medium 207 completely fills the first isolation medium nanopore structure, and the obtained structure is as Figure 11 shown. The capacitor structure and the inductor structure are interconnected through the first top metal electrode layer 203 and the second metal layer 206, so as to achieve series connection to form a filter. And since the capacitor and inductor structures are vertically stacked together, the planar area occupied by the filter is greatly reduced, so that a small-sized filter can be obtained.

[0078] In this embodiment, a deep reactive ion etching process is used to obtain the first isolation medium nanopore structure, but the present invention is not limited thereto, and dry etching such as ion milling etching, plasma etching, reactive ion etching, deep reactive ion etching, laser ablation, or at least one process of wet etching using an etchant solution can be selected. In addition, in this embodiment, Ni is used as the second metal layer and the SiO2 thin film is used as the second isolation medium, but the present invention is not limited thereto, and at least one of Co, Ni, and Ru can be selected as the second metal layer, and at least one of SiO2, Si3N4, SiON, SiCOH, and SiCOFH can be selected as the second isolation medium. The growth methods of the second metal layer and the second isolation medium can select at least one of physical vapor deposition, chemical vapor deposition, atomic layer deposition, and pulsed laser deposition.

[0079] Step S5: Perform metal wiring to obtain two contact electrodes of the filter. This step specifically includes:

[0080] Remove part of the second isolation medium on the left and right sides, expose the first bottom metal layer and the second metal layer respectively, and form two trench structures;

[0081] Deposit a copper diffusion barrier layer and a copper seed layer on the surfaces of the two trench structures in sequence;

[0082] Remove the part of the copper seed layer and the copper diffusion barrier layer located above the second isolation medium, so that the copper seed layer and the copper diffusion barrier layer are broken into left and right two regions;

[0083] Electroplate a copper metal layer on the surface of the copper seed layer;

[0084] The left copper metal layer and the right copper metal layer are respectively used as the two contact electrodes of the filter.

[0085] Specifically, in some embodiments, first, lithography and etching processes are used to remove part of the second isolation medium 207 on the left and right sides respectively, thereby exposing the first bottom metal layer 201 and the second metal layer 206 respectively, and forming second and third trench structures. The obtained structure is as shown in Figure 12 shown. Then, a TaN thin film 208 and a Co thin film 209 are sequentially deposited on the surfaces of the two trench structures by chemical vapor deposition process, as the copper diffusion barrier layer and the copper seed layer respectively. The obtained structure is as shown in Figure 13 shown. Subsequently, lithography and etching processes are used to remove the part of the copper diffusion barrier layer 208 and the copper seed layer 209 located above the second isolation medium 207, so that the copper diffusion barrier layer 208 and the copper seed layer 209 are broken into left and right two regions. The obtained structure is as shown in Figure 14 shown. Finally, a layer of Cu material 210 is electroplated on the surface of the copper seed layer 209 by electroplating process as the copper metal layer. The obtained structure is as shown in Figure 15 shown.

[0086] In this embodiment, TaN is used as the copper diffusion barrier layer and Co thin film is used as the copper seed layer. However, the present invention is not limited thereto. At least one of TaN, TiN, ZrN, and MnSiO3 can be selected as the copper diffusion barrier layer; at least one of Cu, Ru, Co, RuCo, CuRu, and CuCo can be selected as the copper seed layer. The growth methods of the copper diffusion barrier layer and the copper seed layer can be selected from at least one of physical vapor deposition, chemical vapor deposition, and atomic layer deposition. The left copper metal layer 210 and the right copper metal layer 210 serve as the two contact electrodes of the filter respectively.

[0087] The present invention realizes the direct integration of the filter on the chip surface. The capacitor and inductor structures are vertically stacked together, greatly reducing the planar area occupied by the filter, effectively improving the integration degree of the active region, and realizing the acquisition of a small-sized filter.

[0088] Refer to Figure 15 shown. Another embodiment of the present invention provides a three-dimensional integrated filter structure, which includes:

[0089] A single-crystalline silicon substrate 200, trenches are etched on the substrate, and a single-crystalline silicon nanopore array is etched at the bottom of the trenches;

[0090] A capacitor structure, the basic framework is located on the surface of the single-crystalline silicon nanopores, including a first bottom metal electrode layer 201, a first insulating medium 202, and a first top metal electrode layer 203 that are sequentially covered;

[0091] The first top metal electrode layer 203 completely fills the single-crystalline silicon nanopores; a layer of etch stop layer 204 is deposited on the surface of the first top metal electrode layer 203;

[0092] The etch stop layer 204 on the right platform of the trench is provided with an etch stop layer trench;

[0093] Part of the first bottom metal electrode 201 layer on the left platform of the trench is exposed, that is, the part not covered by the first insulating medium, the first top metal electrode layer and the etch stop layer;

[0094] The surface of the etch stop layer 204 is covered with a first isolation medium 205, and the first isolation medium 205 is flush with the etch stop layer on the platforms on both sides of the trench; the first isolation medium 205 is etched to form a first isolation medium nanopore structure;

[0095] An inductor structure, the basic framework is located in the first isolation medium nanopore structure, and is composed of a second metal layer 206 covering the surface of the first isolation medium nanopore, part of the surface of the etch stop layer 204 and the surface of the exposed first top metal layer 203;

[0096] The capacitor structure and the inductor structure are interconnected through the first top metal electrode layer 203 and the second metal layer 206 at the etch stop layer trench to form a series connection to form a filter;

[0097] A second isolation medium 207, the second isolation medium 207 covers the surface of the second metal layer 206 and the exposed first bottom metal electrode layer 201; the second isolation medium 207 completely fills the first isolation medium nanopore structure; part of the second isolation medium 207 on the left and right is removed to expose the first bottom metal layer 201 and the second metal layer 206 respectively, and two second isolation medium trench structures are formed;

[0098] A top metal contact area for generating two contact electrodes of the filter at the two second isolation medium trenches.

[0099] It can be understood that the inductor structure is located above the capacitor structure; the capacitor and inductor structures are located inside the trench formed by etching the single-crystalline silicon substrate 200.

[0100] Preferably, the width of the trench formed by etching the substrate is greater than 1 cm, and the depth range is 10-20 μm. The diameter range of the single-crystalline silicon nanopores is 0.5-1 μm, and the depth range is 10-20 μm; the plasma for etching the single-crystalline silicon substrate 200 can be at least one of CF4 and SF6.

[0101] Furthermore, the first bottom metal electrode layer 201 is composed of a metal silicide formed by the reaction of a transition layer metal 300 deposited on the surfaces of the trench and the single-crystalline silicon nanopores with the silicon substrate.

[0102] Specifically, in some embodiments, a physical vapor deposition process is used to deposit a metal Ni thin film on the surface of the trench and the single-crystalline silicon nanopores as the transition layer metal 300; then, the above structure is annealed using a rapid thermal annealing process, and the transition layer metal 300 reacts with the silicon substrate 200 to generate a metal silicide NiSi as the first bottom metal electrode layer 201. A layer of Al2O3 thin film 202 and a layer of TiN thin film 203 are sequentially deposited on the surface of the first bottom metal electrode layer 201 as the first insulating medium 202 and the first top metal electrode layer 203, respectively, and the first top metal electrode layer 203 completely fills the silicon nanopores. A layer of Si3N4 thin film 204 is deposited on the surface of the first top metal electrode layer 203 as an etch stop layer.

[0103] Preferably, the thickness range of the first insulating medium 202 is 5 - 10 nm, the thickness range of the first top metal electrode layer 203 is 10 - 50 nm, and the thickness range of the etch stop layer 204 is 150 - 400 nm.

[0104] Preferably, the diameter range of the first isolation medium nanopores is 0.5 - 1 μm, and the depth range is 10 - 20 μm; the plasma for etching the first isolation medium 205 can be at least one of CF4 and SF6.

[0105] Preferably, the thickness range of the second metal layer 206 is 100 - 200 nm.

[0106] Furthermore, the top metal contact region includes: a copper diffusion barrier layer 208, a copper seed layer 209, and a copper metal layer 210; the copper diffusion barrier layer and the copper seed layer cover the surfaces of the two second isolation media and are discontinuous in the middle region; the copper seed layer 210 is used to cover the copper diffusion barrier layer 208 and the copper seed layer 209 respectively; the left copper metal layer 210 and the right copper metal layer 210 serve as the two contact electrodes of the filter respectively.

[0107] It should be noted that the above are only the specific embodiments of the present invention. Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working process formed by the above-described structure can refer to the corresponding process in the foregoing method embodiments and will not be elaborated herein. It should be understood that the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present invention.

Claims

1. A method for preparing a three-dimensional integrated filter, characterized in that: Comprising: Etching grooves on the surface of a single-crystalline silicon and etching a single-crystalline silicon nanopore array at the bottom of the grooves; Preparing a capacitive structure on the surface of the single-crystalline silicon nanopores; Sequentially depositing an etching stop layer and a first isolation medium on the surface of the grooves and etching a first isolation medium nanopore structure; Preparing an inductive structure on the surface of the first isolation medium nanopores and achieving series connection of the capacitor and the inductor; The step of preparing an inductive structure inside the first isolation medium nanopores and achieving series connection of the capacitor and the inductor specifically includes: Depositing a second metal layer on the surfaces of the first isolation medium nanopores, the etching stop layer, and the etching stop layer grooves, and the second metal layer forms the inductive structure; The first top metal electrode layer at the etching stop layer grooves is in communication with the second metal layer to achieve series connection of the capacitor and the inductor; Removing a part of the first insulating medium, the first top metal electrode layer, the etching stop layer, and the second metal layer on the left side to expose the first bottom metal electrode layer; Depositing a second isolation medium on the surfaces of the second metal layer and the exposed first bottom metal electrode layer; The second isolation medium completely fills the first isolation medium nanopore structure; Performing metal wiring to obtain two contact electrodes of the filter.

2. The method for manufacturing a three-dimensional integrated filter according to claim 1, characterized in that: The step of preparing a capacitive structure on the surface of the single-crystalline silicon nanopores specifically includes: Depositing a transition layer metal on the surfaces of the grooves and the single-crystalline silicon nanopores; Using a rapid thermal annealing process to react the transition layer metal with the single-crystalline silicon substrate to generate a metal silicide film, and using the metal silicide film as the first bottom metal electrode layer; Sequentially depositing a first insulating dielectric layer and a first top metal electrode layer on the surface of the first bottom metal electrode layer to form a capacitive structure; The first top metal electrode layer completely fills the single-crystalline silicon nanopores.

3. The method for manufacturing a three-dimensional integrated filter according to claim 2, characterized in that: The thickness range of the first bottom metal electrode layer is 5 - 10 nm, the thickness range of the first insulating dielectric is 10 - 50 nm, and the thickness range of the first top metal electrode layer is 150 - 400 nm.

4. The method for preparing a three-dimensional integrated filter according to claim 2 or 3, Characterized in That: The step of sequentially depositing an etching stop layer and a first isolation medium on the surface of the grooves and etching a first isolation medium Nanopore structure specifically includes: Depositing an etching stop layer on the surface of the first top metal electrode layer; Depositing a first isolation medium on the surface of the etching stop layer; Removing the first isolation medium at the top of the grooves to make the first isolation medium flush with the etching stop layer on the platform on both sides of the grooves; Determining the patterns of the first isolation medium nanopores and the grooves on the surface of the right etching stop layer on the surfaces of the first isolation medium and the etching stop layer; Etching the first isolation medium and the right etching stop layer to respectively form a first isolation medium nanopore structure and an etching stop layer groove.

5. The method for manufacturing a three-dimensional integrated filter according to claim 4, characterized in that: The diameter range of the first isolation medium nanopores is 0.5 - 1 μm, and the depth range is 10 - 20 μm.

6. The method for manufacturing a three-dimensional integrated filter according to claim 5, characterized in that: The step of performing metal wiring to obtain two contact electrodes of the filter specifically includes: Remove partial second isolation media on the left and right sides, respectively exposing the first bottom metal layer and the second metal layer, and form two trench structures; Deposit a copper diffusion barrier layer and a copper seed layer on the surfaces of the two trench structures in sequence; Remove the partial copper seed layer and copper diffusion barrier layer located above the second isolation media, causing the copper seed layer and copper diffusion barrier layer to break into left and right regions; Electroplate a layer of copper metal layer on the surface of the copper seed layer; The left copper metal layer and the right copper metal layer serve as the two contact electrodes of the filter respectively.

7. A three-dimensional integrated filter structure, characterized in that: Comprising: A single-crystalline silicon substrate, etch the substrate to form trenches, and etch single-crystalline silicon nanopore arrays at the bottoms of the trenches; A capacitor structure, the basic framework is located on the surface of the single-crystalline silicon nanopores, including a first bottom metal electrode layer, a first insulating medium, and a first top metal electrode layer that are sequentially covered; the first top metal electrode layer completely fills the single-crystalline silicon nanopores; deposit an etch stop layer on the surface of the first top metal electrode layer; there is an etch stop layer trench on the etch stop layer on the right platform of the trench; a part of the first bottom metal electrode layer on the left platform of the trench is exposed, the part not covered by the first insulating medium, the first top metal electrode layer, and the etch stop layer; the surface of the etch stop layer is covered with a first isolation medium, and the first isolation medium is flush with the etch stop layer on the two side platforms of the trench; the first isolation medium is etched to form a first isolation medium nanopore structure; An inductor structure, the basic framework is located in the first isolation medium nanopore structure, and is composed of a second metal layer covering the surface of the first isolation medium nanopores, part of the surface of the etch stop layer, and the exposed first top metal layer surface; The capacitor structure and the inductor structure are interconnected through the first top metal electrode layer and the second metal layer at the etch stop layer trench, realizing the series connection of the capacitor and the inductor; A second isolation medium, the second isolation medium covers the surface of the second metal layer and the exposed first bottom metal electrode layer; the second isolation medium completely fills the first isolation medium nanopore structure; Remove partial second isolation media on the left and right sides, respectively exposing the first bottom metal layer and the second metal layer, and form two second isolation medium trench structures; A top metal contact area for generating two contact electrodes of the filter at the two second isolation medium trenches.

8. The three-dimensional integrated filter structure according to claim 7, wherein: The first bottom metal electrode layer is composed of a metal silicide formed by the reaction of a transition layer metal deposited on the surfaces of the trenches and the single-crystalline silicon nanopores with the silicon substrate.

9. The three-dimensional integrated filter structure according to claim 7, wherein: The top metal contact area includes: A copper diffusion barrier layer, a copper seed layer, and a copper metal layer; The copper diffusion barrier layer and the copper seed layer cover the surfaces of the two second isolation medium trenches and break and are not connected in the middle region; The copper seed layer is used to cover the copper diffusion barrier layer and the copper seed layer respectively, and the left copper metal layer and the right copper metal layer serve as the two contact electrodes of the filter respectively.

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