Memory Element and Method of Manufacturing the Same

Abstract

The present invention discloses a memory element and a manufacturing method thereof. The memory element includes a floating gate, an inter-gate dielectric layer, a gate coupling layer, and a control gate. The floating gate is disposed on a substrate and has a comb-shaped portion. The comb-shaped portion has a plurality of strip patterns that are laterally spaced apart from each other. The inter-gate dielectric layer covers the upper surface of the comb-shaped portion of the floating gate. The gate coupling layer covers the inter-gate dielectric layer. The control gate includes a conductive plug standing on the gate coupling layer and is electrically connected to the gate coupling layer. The control gate is capacitively coupled to the comb-shaped portion of the floating gate in the vertical direction and the horizontal direction.

Description

Technical Field

[0001] The present invention relates to a memory element and a method for manufacturing the same, and more particularly to a non-volatile memory. Background Art

[0002] In modern electronic products, memories play an indispensable role. In addition to storing user data, memories are also used to store program codes of processors and temporary data required during the operation of processors. Generally, memories can be classified into volatile memories and non-volatile memories. The data stored in volatile memories will disappear after power-off, while non-volatile memories can still retain the stored data after power-off.

[0003] Flash memory is a widely used non-volatile memory. Flash memory is composed of floating gate transistors, which include a control gate and a floating gate separated by an insulating layer. The control gate is used to control the switching of the floating gate transistor. On the other hand, charges can be stored in the floating gate to affect the threshold voltage of the floating gate transistor. Through the change of the threshold voltage, the floating gate transistor can be used to store data. Increasing the capacitive coupling between the control gate and the floating gate can reduce the write voltage of the floating gate transistor and reduce the interference between adjacent floating gate transistors. However, currently, due to limitations in manufacturing processes, it is difficult to increase the above-mentioned capacitive coupling without increasing the area of the floating gate transistor. Summary of the Invention

[0004] The present invention provides a memory element and a method for manufacturing the same, which can increase the capacitive coupling between the floating gate and the control gate.

[0005] One aspect of the present invention provides a memory element, including: a floating gate disposed on a substrate and having a comb-shaped portion, wherein the comb-shaped portion has a plurality of strip patterns laterally spaced apart from each other; an inter-gate dielectric layer covering the upper surface of the comb-shaped portion of the floating gate; a gate coupling layer covering the inter-gate dielectric layer; and a control gate including a conductive plug standing on the gate coupling layer and electrically connected to the gate coupling layer, wherein the control gate is capacitively coupled to the comb-shaped portion of the floating gate in the vertical direction and the horizontal direction.

[0006] In some embodiments, the inter-gate dielectric layer and the gate coupling layer substantially completely cover the upper surface of the comb-shaped portion of the floating gate.

[0007] In some embodiments, the memory element further includes a metal silicide layer. The metal silicide layer is formed on the gate coupling layer. The conductive plug of the control gate is electrically connected to the gate coupling layer via the metal silicide layer.

[0008] In some embodiments, the floating gate further has another portion that extends over the active region of the substrate and contacts the active region through a tunneling dielectric layer.

[0009] In some embodiments, the memory element further includes an isolation structure. The isolation structure is disposed in the substrate and surrounds the active region.

[0010] In some embodiments, the comb-shaped portion of the floating gate, the inter-gate dielectric layer, and the gate coupling layer overlap the isolation structure.

[0011] In some embodiments, the inter-gate dielectric layer also covers the sidewalls of the comb-shaped portion of the floating gate, and the gate coupling layer is also filled in the space between the plurality of strip patterns of the comb-shaped portion of the floating gate.

[0012] In some embodiments, the inter-gate dielectric layer has a plurality of portions that are laterally spaced apart from each other and respectively cover the plurality of strip patterns of the comb-shaped portion of the floating gate. The gate coupling layer also has a plurality of portions that are laterally spaced apart from each other and respectively cover the plurality of portions of the inter-gate dielectric layer.

[0013] In some embodiments, the control gate further includes at least one conductive wall that extends between adjacent strip patterns of the comb-shaped portion of the floating gate.

[0014] Another aspect of the present invention provides a method for manufacturing a memory element, including: forming a floating gate above a substrate, where the floating gate has a comb-shaped portion, and the comb-shaped portion has a plurality of strip patterns that are laterally spaced apart from each other; forming an inter-gate dielectric layer on the comb-shaped portion of the floating gate; forming a gate coupling layer on the inter-gate dielectric layer; and forming a control gate on the substrate, where the control gate includes a conductive plug standing on the gate coupling layer and is electrically connected to the gate coupling layer, and where the control gate is capacitively coupled to the comb-shaped portion of the floating gate in the vertical direction and the horizontal direction.

[0015] Based on the above, by providing a gate coupling layer between the floating gate and the conductive plug of the control gate, the capacitive coupling area between the control gate and the floating gate can be increased. In some embodiments, the gate coupling layer covers the upper surface and sidewalls of the floating gate, so that the control gate electrically connected to the gate coupling layer can be capacitively coupled to the floating gate in the vertical direction and the horizontal direction via the gate coupling layer. In other embodiments, the gate coupling layer can be used to increase the capacitive coupling area between the control gate and the floating gate in the vertical direction, and the control gate can further include a conductive wall extending along the side of the floating gate. In this way, the control gate can still be capacitively coupled to the floating gate in the vertical direction and the horizontal direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1A is a cross-sectional schematic view of a semiconductor structure embedded with a memory element according to some embodiments of the present invention;

[0017] Figure 1B is Figure 1A a plan view of the memory element shown;

[0018] Figure 2 is Figure 1A a manufacturing flow chart of the semiconductor structure shown according to some embodiments;

[0019] Figures 3A to 3I is Figure 2 a cross-sectional schematic view of the structure at each stage during the manufacturing process shown;

[0020] Figure 4A is a cross-sectional schematic view of a semiconductor structure embedded with a memory element according to some embodiments of the present invention;

[0021] Figure 4B is Figure 4A a plan view of the memory element shown;

[0022] Figures 5A to 5B is a cross-sectional schematic view of some stages in the process of manufacturing the semiconductor structure shown. Figure 4A shown

[0023] SYMBOL DESCRIPTION

[0024] 10, 40: Memory element

[0025] 100, 400: Semiconductor structure

[0026] 100A: Memory area

[0027] 100B: Logic area

[0028] 102: Substrate

[0029] 104: Isolation structure

[0030] 106, 136: Gate

[0031] 108, 110, 122, 138, 140: Doped region

[0032] 112, 142: Gate dielectric layer

[0033] 114, 114a, 114b, 126, 126a, 126b, 144, 144a, 144b: Spacer

[0034] 116, 128, 146: Lightly doped region

[0035] 120: Floating gate

[0036] 120e: Extension portion

[0037] 124: Tunneling dielectric layer

[0038] 130, 430: Inter-gate dielectric layer

[0039] 132, 432: Gate coupling layer

[0040] 134, 434: Control gate

[0041] 134a, 152, 434a: Conductive plug

[0042] 150, 450: Metal silicide layer

[0043] 154: Interlayer dielectric layer

[0044] 156: Etch stop layer

[0045] 300: Dielectric layer

[0046] 302: Conductor layer

[0047] 304, 600: Mask pattern

[0048] 434b: Conductive wall

[0049] AA, AA’: Active region

[0050] AT: Access transistor

[0051] BR: Connection portion

[0052] CM: Comb portion

[0053] FT: Floating gate transistor

[0054] S100, S102, S104, S106, S108, S110, S112, S114, S116, S118, S120: Steps

[0055] T: Transistor

[0056] X: Direction

[0057] Y: Direction Detailed implementation manners

[0058] Figure 1A is a cross-sectional schematic view of a semiconductor structure 100 embedded with a memory element 10 according to some embodiments of the present invention. Figure 1B is Figure 1A a plan view of the shown memory element 10.

[0059] Please refer to Figure 1A Figure 1A In some embodiments, the memory element 10 is an embedded memory element. In these embodiments, the memory element 10 may be formed in the memory region 100A of the semiconductor structure 100, while the logic circuit may be formed in the logic region 100B of the semiconductor structure 100. The boundary between the memory region 100A and the logic region 100B may be defined by a portion of the isolation structure 104 formed in the substrate 102. The substrate 102 may be a semiconductor wafer or a semiconductor-on-insulator (SOI) wafer. For example, the semiconductor material in the semiconductor wafer or SOI wafer may include silicon. In addition, in some embodiments, the isolation structure 104 may be a trench isolation structure and may extend from the top surface of the substrate 102 into the substrate 102.

[0060]

[0060] In some embodiments, each memory cell of the memory element 10 includes an access transistor AT and a floating-gate transistor FT. The floating-gate transistor FT is used to store data, and the access transistor AT is connected to the floating-gate transistor FT and can be used to control the access of the floating-gate transistor FT. In some embodiments, the access transistor AT is formed on the surface region of the active region AA. The active region AA may be a well region formed in the substrate 102 and is surrounded by a portion of the isolation structure 104. The access transistor AT includes a gate 106 formed on the active region AA and doped regions 108 and 110 formed in the active region AA. The doped regions 108 and 110 are located on opposite sides of the gate 106 and have a conductivity type different from that of the active region AA, and can serve as the drain and source of the access transistor AT. When the access transistor AT is turned on, a conductive channel can be formed in the portion of the active region AA between the doped regions 108 and 110. On the other hand, when the access transistor AT is turned off, the above conductive channel does not exist. In some embodiments, the access transistor AT and the floating-gate transistor FT are connected to each other through a common drain / source (e.g., the doped region 108). In these embodiments, the potential of one terminal of the floating-gate transistor FT is controlled by the access transistor AT. In this way, the access transistor AT can control the switching of the floating-gate transistor FT and thus control the access of the floating-gate transistor FT.

[0061] As Figure 1AAs shown, a gate dielectric layer 112 is further disposed between the gate 106 and the surface of the active region AA. In some embodiments, the material of the gate dielectric layer 112 includes silicon oxide. In addition, at least one spacer 114 may be disposed around the gate 106 and the gate dielectric layer 112. For example, the spacer 114 may include a spacer 114a and a spacer 114b. The spacer 114b is disposed outside the spacer 114a, and the spacer 114a may have an extension extending below the spacer 114b. In some embodiments, the spacer 114a and the spacer 114b may be respectively composed of silicon oxide or silicon nitride. The doped regions 108 and 110 in the active region AA may be located outside the spacer 114 (e.g., outside the spacer 114b), and may or may not slightly extend below the spacer 114. In some embodiments, the access transistor AT further includes a pair of lightly doped regions 116 in the active region AA. This pair of lightly doped regions 116 is disposed on the facing sides of the doped regions 108 and 110, and may be regarded as an extension of the doped regions 108 and 110. In this way, the lightly doped regions 116 may extend below the spacer 114, and may or may not slightly extend below the gate dielectric layer 112. The conductivity type of the lightly doped regions 116 may be the same as that of the doped regions 108 and 110, and the doping concentration of the lightly doped regions 116 may be lower than that of the doped regions 108 and 110.

[0062] On the other hand, in some embodiments, the floating gate transistor FT includes a floating gate 120, a doped region 122, and a doped region 108 shared with the access transistor AT. A part of the floating gate 120 is formed on the active region AA, and the doped regions 122 and 108 are located in the active region AA and on opposite sides of the part of the floating gate 120. The conductivity types of the doped regions 122 and 108 may be different from that of the active region AA, and may serve as the drain and source of the floating gate transistor FT. When the floating gate transistor FT is turned on, a conductive channel may be formed in the part of the active region AA between the doped regions 122 and 108. On the other hand, when the floating gate transistor FT is turned off, the above-mentioned conductive channel does not exist. In addition, during a write operation, carriers may tunnel from the above-mentioned conductive channel into the floating gate 120. On the other hand, during an erase operation, the carriers stored in the floating gate 120 may return to the active region AA through the tunneling effect. In some embodiments, the floating gate 120 and the gate 106 of the access transistor AT are composed of the same material.

[0063] A tunneling dielectric layer 124 is further disposed between the active region AA and the portion of the floating gate 120 located on the active region AA. In some embodiments, the tunneling dielectric layer 124 is made of the same material as the gate dielectric layer 112 of the access transistor AT. In addition, similar to the spacer 114 of the access transistor AT, at least one spacer 126 may be disposed around the floating gate 120 and the tunneling dielectric layer 124. For example, the spacer 126 may include a spacer 126a and a spacer 126b. The spacer 126b is disposed outside the spacer 126a, and the spacer 126a may have an extension extending below the spacer 126b. In some embodiments, the spacer 126a and the spacer 126b may be made of silicon oxide or silicon nitride respectively. The doped regions 108 and 122 in the active region AA may be located outside the spacer 126 (e.g., outside the spacer 126b), and may or may not slightly extend below the spacer 126. In some embodiments, the access transistor AT further includes a pair of lightly doped regions 128 located in the active region AA. This pair of lightly doped regions 128 are disposed on the facing sides of the doped regions 108 and 122, and may be regarded as extended portions of the doped regions 108 and 122. In this way, the lightly doped regions 128 may extend below the spacer 126, and may or may not slightly extend below the tunneling dielectric layer 124. The conductivity type of the lightly doped regions 128 may be the same as that of the doped regions 108 and 122, and the doping concentration of the lightly doped regions 128 may be lower than the doping concentration of the doped regions 108 and 122.

[0064] Please refer to Figure 1A and Figure 1B , the floating gate 120 further extends beyond the scope of the active region AA. As Figure 1A shown, the extended portion 120e of the floating gate 120 may be located on the isolation structure 104 surrounding the active region AA. As Figure 1B shown, the extended portion 120e of the floating gate 120 may include a comb-shaped portion CM and a connecting portion BR. The comb-shaped portion CM of the floating gate 120 has a plurality of strip patterns laterally spaced apart from each other, and these strip patterns are laterally connected to adjacent strip patterns at one end thereof (e.g., the bottom end as Figure 1B shown). For example, the plurality of strip patterns of the comb-shaped portion CM extend in the direction Y, and the transverse pattern for connecting the plurality of strip patterns may extend in the direction X. On the other hand, the portion of the floating gate 120 located within the active region AA is connected to the comb-shaped portion CM through the connecting portion BR. In some embodiments, the connecting portion BR extends in the direction Y. It should be noted that, in Figure 1A , the portion of the floating gate 120 located on the isolation structure 104 may be a cross-sectional schematic diagram of the plurality of strip patterns of the comb-shaped portion CM of the floating gate 120 (as Figure 1B shown).

[0065] Please refer to Figure 1A , in some embodiments, the tunneling dielectric layer 124 is not disposed between the extension portion 120e of the floating gate 120 and the isolation structure 104. In addition, in some embodiments, the extension portion 120e of the floating gate 120 is also surrounded by the spacer 126. Furthermore, the floating gate transistor FT further includes an inter-gate dielectric layer 130, a gate coupling layer 132, and a control gate 134 located above the extension portion 120e of the floating gate 120. The control gate 134 is electrically connected to the gate coupling layer 132, and the control gate 134 and the gate coupling layer 132 are capacitively coupled to the extension portion 120e of the floating gate 120 through the inter-gate dielectric layer 130. The control gate 134 is used to control the switching of the floating gate transistor FT, and the floating gate 120 capacitively coupled to the control gate 134 affects the threshold voltage of the floating gate transistor FT. By providing the gate coupling layer 132 between the control gate 134 and the floating gate 120, the coupling area between the control gate 134 and the floating gate 120 can be increased, and the capacitive coupling between the control gate 134 and the floating gate 120 can be improved. In this way, the operating voltage and power consumption of the floating gate transistor FT can be effectively reduced. As Figure 1A shown in Figure 1B , the inter-gate dielectric layer 130, the gate coupling layer 132, and the control gate 134 are disposed on the comb-shaped portion CM of the floating gate 120, and may not cover the connecting portion BR of the floating gate 120 and the portion located on the active region AA. In some embodiments, the inter-gate dielectric layer 130 and the gate coupling layer 132 substantially completely cover the upper surface of the comb-shaped portion CM of the floating gate 120. As Figure 1A shown in Figure 1BAs shown, in some embodiments, a plurality of conductive plugs 134a separated from each other may be disposed between adjacent strip patterns of the comb-shaped portion CM of the floating gate 120. The inter-gate dielectric layer 130 may be composed of a dielectric material, while the gate coupling layer 132 and the control gate 134 may be composed of a conductor material. For example, the above dielectric material may include tetraethoxysilane (TEOS) silicon oxide, a high-k (high dielectric constant) dielectric material (e.g., a dielectric material with a dielectric constant greater than 3.9), or a combination thereof. On the other hand, the conductor material forming the gate coupling layer 132 may, for example, include polysilicon, and the conductor material forming the control gate 134 may, for example, include tungsten.

[0066] Please refer to Figure 1A , the semiconductor structure 100 may further include a transistor T located in the logic region 100B. The transistor T may be an active element in a logic circuit. In other words, the logic circuit may further include other active elements and / or passive elements. In some embodiments, the transistor T may be similar or equivalent to the access transistor AT in terms of structure and configuration, but the transistor T and the access transistor AT may have the same or different conduction types. Similar to the access transistor AT, the transistor T is disposed on the surface region of the active region AA' surrounded by the isolation structure 104. The transistor T may include a gate 136 formed on the active region AA' and doping regions 138 and 140 formed in the active region AA'. The doping regions 138 and 140 are located on opposite sides of the gate 136 and have another conduction type different from that of the active region AA', and may serve as the drain and source of the transistor T. In some embodiments, a gate dielectric layer 142 is further disposed under the gate 136, and one or more spacer walls 144 (e.g., including spacer walls 144a and 144b) may be disposed around the gate 136 and the gate dielectric layer 142. Additionally, the transistor T may further include a pair of lightly doped regions 146. The gate 136, the doping regions 138, the doping regions 140, the gate dielectric layer 142, the spacer walls 144, and the lightly doped regions 146 of the transistor T may be similar to the gate 106, the doping regions 108, the doping regions 110, the gate dielectric layer 112, the spacer walls 114, and the lightly doped regions 116 of the access transistor AT, and will not be described in detail here.

[0067] In some embodiments, the semiconductor structure 100 further includes a metal silicide layer 150. The metal silicide layer 150 spans across the memory region 100A and the logic region 100B. Within the memory region 100A, some portions of the metal silicide layer 150 cover the top surfaces of the doped regions 108, 110, and 122, and cover the portions of the gate 106 and the floating gate 120 that are above the active region AA. Additionally, within the memory region 100A, some other portions of the metal silicide layer 150 cover the upper surface of the gate coupling layer 132, such that the control gate 134 (e.g., the conductive plug 134a of the control gate 134) contacts the gate coupling layer 132 through this portion of the metal silicide layer 150. On the other hand, within the logic region 100B, some portions of the metal silicide layer 150 cover the upper surfaces of the gate 136, the doped regions 138, and 140. In some embodiments, the material of the metal silicide layer 150 may include titanium silicide, tungsten silicide, tantalum silicide, molybdenum silicide, cobalt silicide, nickel silicide, or the like.

[0068] In some embodiments, the semiconductor structure 100 further includes a plurality of conductive plugs 152. Some of the conductive plugs 152 stand on the doped regions 110 and 122 within the memory region 100A to establish electrical connections with the access transistor AT and the floating gate transistor FT. In embodiments where the access transistor AT and the floating gate transistor FT are interconnected through the doped region 108, the doped region 108 may be electrically floating and there may not be a conductive plug disposed above it. On the other hand, some other conductive plugs 152 stand on the doped regions 138 and 140 within the logic region 100B to establish electrical connections with the drain and source of the transistor T. Additionally, as Figure 1B shown, another conductive plug 152 may also be disposed on the gate 106 of the access transistor AT. Similarly, although not shown in Figure 1A or Figure 1B a conductive plug 152 (not shown) may also be selectively disposed above the gate 136 of the transistor T within the logic region 100B. In some embodiments, compared to the conductive plug 134a (i.e., a part of the control gate 134) disposed above the floating gate 120, the conductive plug 152 disposed above the gate 106, and the additional conductive plug 152 disposed on the gate 136, the conductive plugs 152 standing on the doped regions 110, 122, 138, and 140 may have a greater height. Additionally, in some embodiments, the conductive plug 134a and the conductive plugs 152 may be formed of the same conductor material (e.g., tungsten).

[0069] In some embodiments, the interlayer dielectric layer 154 comprehensively covers the substrate 102, covering the components disposed on the substrate 102 of the access transistor AT, the floating gate transistor FT, and the transistor T, and laterally surrounding the conductive plug 134a and the conductive plug 152. In this way, the conductive plug 134a and the conductive plug 152 can be regarded as passing through the interlayer dielectric layer 154 to establish electrical connections with the access transistor AT, the floating gate transistor FT, and the transistor T. In addition, in some embodiments, the etch stop layer 156 is further lined under the interlayer dielectric layer 154. In these embodiments, the etch stop layer 156 can conformally cover the substrate 102 and the components disposed on the substrate 102 of the access transistor AT, the floating gate transistor FT, and the transistor T. In addition, the conductive plug 134a can pass through the etch stop layer 156 to be electrically connected to the gate coupling layer 132 (for example, electrically connected to the gate coupling layer 132 via the metal silicide layer 150). Similarly, the conductive plug 152 can pass through the etch stop layer 156 to be electrically connected to the doped regions and the gates 106, 136 of the access transistor AT, the floating gate transistor FT, and the transistor T (for example, electrically connected to these doped regions and gates via the metal silicide layer 150). For example, the interlayer dielectric layer 154 and the etch stop layer 156 can be composed of silicon oxide, silicon nitride, silicon oxynitride, or the like respectively.

[0070] As described above, by providing the gate coupling layer 132, the capacitive coupling between the control gate 134 and the floating gate 120 can be increased. Specifically, compared with forming the control gate into another comb structure and capacitively coupling laterally with the comb portion CM of the floating gate 120, the floating gate 120 of the embodiments of the present invention is capacitively coupled to the control gate 134 both longitudinally and laterally via the gate coupling layer 132. By increasing the capacitive coupling between the floating gate 120 and the control gate 134, the operating voltage of the floating gate transistor FT can be effectively reduced.

[0071] Figure 2 is Figure 1A A manufacturing flow chart of the semiconductor structure 100 according to some embodiments as shown. Figures 3A to 3I is Figure 2 A cross-sectional schematic diagram of the structure at each stage during the manufacturing process as shown.

[0072] Please refer to Figure 2 and Figure 3A, perform step S100 to form isolation structure 104 and active regions AA and AA' in substrate 102. In an embodiment where isolation structure 104 is a trench isolation structure, the method of forming isolation structure 104 may include forming a depression on the surface of substrate 102 through a photolithography process and an etching process, and then filling an insulating material in the depression to form isolation structure 104. On the other hand, active regions AA and AA' may be formed in the exposed regions of substrate 102 through a photolithography process and an ion implantation process. In some embodiments, isolation structure 104 may be formed first and then active regions AA and AA'. In an alternative embodiment, active regions AA and AA' may also be formed first, and then isolation structure 104 may be formed.

[0073] Please refer to Figure 2 and Figure 3B , perform step S102 to form gate dielectric layers 112 and 142, gates 106 and 136, and tunneling dielectric layer 124 and floating gate 120 on substrate 102. In some embodiments, an oxide layer may be selectively formed on the surfaces of active regions AA and AA' through a thermal oxidation process. Subsequently, a blanket gate material layer may be formed on isolation structure 104 and this oxide layer through a deposition process (such as a chemical vapor deposition process). Then, some portions of the gate material layer and the oxide layer below these portions are removed through a photolithography process and an etching process. The remaining portions of the oxide layer may form gate dielectric layers 112 and 142 and tunneling dielectric layer 124. On the other hand, the remaining portions of the gate material layer form gates 106 and 136 and floating gate 120.

[0074] Please refer to Figure 2 and Figure 3C , perform step S104 to form lightly doped regions 116, 128, and 146 in active regions AA and AA'. In some embodiments, the above-mentioned lightly doped regions may be formed through an ion implantation process. During this ion implantation process, gates 106, 136, floating gate 120, and isolation structure 104 may be used as masks, such that only the exposed portions of active regions AA and AA' are ion implanted to form lightly doped regions 116, 128, and 146.

[0075] Please refer to Figure 2 and Figure 3D, perform step S106 to form spacer walls 114, 126, and 144 on active regions AA and AA', and form doped regions 108, 110, 122, 138, and 140 within active regions AA and AA'. In some embodiments, one or more spacer wall material layers are formed on the current structure through a deposition process (such as a chemical vapor deposition process), and then a re-etch process (such as an anisotropic etching process) is performed to remove some portions of the spacer wall material layer. The remaining portions of the spacer wall material layer can form spacer walls 114, 126, and 144. Additionally, in some embodiments, an ion implantation process is performed using gate 106, gate 136, floating gate 120, spacer walls 114, 126, 144, and isolation structure 104 as masks to form doped regions 108, 110, 122, 138, and 140 in the exposed portions of active regions AA and AA'.

[0076] Please refer to Figure 2 and Figure 3E , perform step S108 to form dielectric layer 300 on the current structure. Dielectric layer 300 covers the Figure 3D structure shown. In the steps to be described with reference to Figure 3H , dielectric layer 300 will be patterned to form inter-gate dielectric layer 130. In some embodiments, dielectric layer 300 is formed through a deposition process (such as a chemical vapor deposition process).

[0077] Please refer to Figure 2 and Figure 3F , perform step S110 to form conductor layer 302 on the current structure. Conductor layer 302 covers dielectric layer 300 entirely. In the steps to be described with reference to Figure 3H , conductor layer 302 will be patterned to form gate coupling layer 132. In some embodiments, conductor layer 302 is formed through a deposition process (such as a chemical vapor deposition process).

[0078] Please refer to Figure 2 and Figure 3G, perform step S112 to form a mask pattern 304 on the extended portion 120e of the floating gate 120. The mask pattern 304 covers the extended portion 120e of the floating gate 120, the surrounding spacer 126, the dielectric layer 300 thereabove, and the conductor layer 302. On the other hand, other portions of the floating gate 120, the spacer 126, the dielectric layer 300, the conductor layer 302, as well as the access transistor T and the transistor T are not covered by the mask pattern 304. In some embodiments, the mask pattern 304 is a photoresist pattern. In these embodiments, the mask pattern 304 can be formed through a photolithography process.

[0079] Please refer to Figure 2 and Figure 3H , perform step S114 to remove the portions of the dielectric layer 300 and the conductor layer 302 that are not covered by the mask pattern 304. In this way, the gate 106 of the access transistor AT, the portions of the floating gate 120 of the floating gate transistor FT other than the extended portion 120e, and the gate 136 of the transistor T are exposed. In addition, the doped regions 108, 110, 122, 138, 140, and a portion of the isolation structure 104 are also exposed. The remaining portion of the dielectric layer 300 forms the inter-gate dielectric layer 130, and the remaining portion of the conductor layer 302 forms the gate coupling layer 132. In some embodiments, the above removal step is completed through an etching process. During this etching process, the mask pattern 304 can serve as an etching mask.

[0080] After completing the above removal step, the mask pattern 304 can be removed. After removing the mask pattern 304, the gate coupling layer 132 is exposed. In some embodiments, the mask pattern 304 is removed through a stripping process.

[0081] Please refer to Figure 2 and Figure 3I , perform step S116 to form a metal silicide layer 150. The metal silicide layer 150 is selectively formed on the surfaces of the gate coupling layer 132, the portions of the floating gate 120 other than the extended portion 120e, the gate 106, the gate 136, the doped regions 108, 110, 122, 138, and 140, and may not cover the exposed portion of the isolation structure 104. In some embodiments, a metal layer is first deposited comprehensively on the Figure 3H structure shown by means of a deposition process (such as a physical vapor deposition process), and then a reaction is caused between the silicon-containing material and the metal layer through a heat treatment process to generate a metal silicide. Subsequently, the unreacted portion of the metal layer can be removed. The remaining metal silicide forms the metal silicide layer 150.

[0082] Please refer toFigure 2 With Figure 1A , step S118 is performed to form the etch stop layer 156 and the interlayer dielectric layer 154. The etch stop layer 156 covers the structure shown in Figure 3I completely and conformally, while the interlayer dielectric layer 154 is formed completely on the etch stop layer 156. In some embodiments, the etch stop layer 156 and the interlayer dielectric layer 154 are formed by deposition processes (such as chemical vapor deposition processes) respectively.

[0083] Next, step S120 is performed to form the conductive plug 134a and the conductive plug 152. In some embodiments, the method of forming the conductive plug 134a and the conductive plug 152 includes forming vias through the interlayer dielectric layer 154 and the etch stop layer 156, and then filling conductive materials in these vias by deposition processes, plating processes or a combination thereof to form the conductive plug 134a and the conductive plug 152.

[0084] So far, the semiconductor structure 100 shown in Figure 1A has been completed by the manufacturing method of some embodiments. Although not shown, more metallization layers and interlayer dielectric layers can be formed on the interlayer dielectric layer 154 subsequently, and packaging processes can be performed to form semiconductor chips. It should be noted that even in the manufacturing process without forming the gate coupling layer 132, lithography processes similar to those shown in Figure 3G are required to define the positions where the metal silicide layers are to be formed. In the embodiments of the present invention, the above-mentioned lithography process is used to pattern the conductor layer 302 to form the metal silicide layer 150. In other words, compared with the manufacturing process without forming the gate coupling layer 132, the embodiments of the present invention do not add additional lithography processes due to the additional formation of the gate coupling layer 132.

[0085] Figure 4A is a cross-sectional schematic view of a semiconductor structure 400 embedded with a memory element 40 according to other embodiments of the present invention. Figure 4B is Figure 4A a plan view of the memory element 40 shown in Figure 4A , Figure 4B The semiconductor structure 400 and the memory element 40 shown in Figure 1A , Figure 1B are similar to the semiconductor structure 100 and the memory element 10 shown in

[0086] Please refer to Figure 4A and Figure 4B, the gate coupling layer 432 located above the extension portion 120e of the floating gate 120 extends along the extension portion 120e of the floating gate 120, and may not cover the surrounding spacer 126 and isolation structure 104. However, considering manufacturing process errors, it is also possible that the gate coupling layer 432 partially covers the spacer 126 around the extension portion 120e of the floating gate 120. In addition, the inter-gate dielectric layer 430 is located between the gate coupling layer 432 and the extension portion 120e of the floating gate 120, and may not cover or may partially cover the spacer 126 around the extension portion 120e of the floating gate 120. Furthermore, since the gate coupling layer 432 is stacked on the extension portion 120e of the floating gate 120 instead of comprehensively covering the extension portion 120e of the floating gate 120 and the surrounding spacer 126 and isolation structure 104, the metal silicide layer 450 can be selectively covered on the top surface of the above-mentioned stacked structure, and may not (or only partially) extend above the spacer 126 around the above-mentioned stacked structure.

[0087] In some embodiments, the control gate 434 includes a conductive plug 434a and a conductive wall 434b. As Figure 4A shown, the conductive plug 434a stands on the gate coupling layer 432. As Figure 4B shown, in some embodiments, the conductive wall 434b extends along the sides of the plurality of strip patterns of the comb-shaped portion CM of the floating gate 120, and may be substantially parallel to these strip patterns. In these embodiments, the spacing between the plurality of strip patterns of the comb-shaped portion CM of the floating gate 120 can be adjusted so that the space between these strip patterns is sufficient to accommodate the conductive wall 434b. In this way, as Figure 4A shown, the control gate 434 can be capacitively coupled to the floating gate 120 in the vertical direction via the gate coupling layer 432 and the inter-gate dielectric layer 430 through the conductive plug 434a. On the other hand, the control gate 434 can be capacitively coupled to the floating gate 120 in the horizontal direction via the spacer 126 through the conductive wall 434b. As Figure 4A shown, in some embodiments, the conductive plug 434a can extend from the top surface of the metal silicide layer 450 to the top surface of the interlayer dielectric layer 154, and the conductive wall 434b can extend from the top surface of the isolation structure 104 to the top surface of the interlayer dielectric layer 154. In these embodiments, the height of the conductive wall 434b is greater than the height of the conductive plug 434a. Additionally, in some embodiments, the conductive plug 434a and the conductive wall 434b are connected to each other through additional conductive vias, conductive traces, and / or other conductive components (all not shown).

[0088] Figures 5A to 5B is a cross-sectional schematic diagram of some stages in the process of manufacturing Figure 4A the semiconductor structure 400 shown.

[0089] Regarding Figure 4A the manufacturing process of the semiconductor structure 400 shown, first, steps S100 to S110 described with reference to Figure 2 and Figures 3A to 3F can be carried out. Next, please refer to Figure 2 and Figure 5A . At step S112, a mask pattern 600 is formed on the conductor layer 302. In subsequent steps, the mask pattern 600 will be used to define the inter-gate dielectric layer 430 and the gate coupling layer 432. The mask pattern 600 covers the strip patterns of the comb-shaped portion CM of the floating gate 120 and extends along these strip patterns. In addition, the mask pattern may not (or only partially) cover the spacer walls 126 around these strip patterns. In some embodiments, the mask pattern 600 is a photoresist pattern, and the mask pattern 600 can be formed by a photolithography process.

[0090] Please refer to Figure 2 and Figure 5B . At step S114, the portions of the dielectric layer 300 and the conductor layer 302 that are not covered by the mask pattern 600 are removed. The remaining portion of the dielectric layer 300 forms the inter-gate dielectric layer 430, and the remaining portion of the conductor layer 302 forms the gate coupling layer 432. In some embodiments, the above removal steps are completed by an etching process. During this etching process, the mask pattern 600 can be used as an etching mask. After completing the above removal steps, the mask pattern 600 can be removed. After removing the mask pattern 600, the gate coupling layer 432 is exposed. In some embodiments, the mask pattern 600 is removed by a stripping process.

[0091] Subsequently, at step S116, a metal silicide layer 450 is formed. The metal silicide layer 450 is selectively formed on the exposed surfaces of the floating gate 120, the gate 106, the gate 136, the gate coupling layer 432, the doped regions 108, 110, 122, 138, and 140, and may not cover the exposed surface of the isolation structure 104. In some embodiments, the metal silicide layer 450 shown can be formed by referring to the method of forming the metal silicide layer 150 described with reference to Figure 3I . Figure 5B

[0092] Please refer to Figure 2 and Figure 4A . At step S118, an etch stop layer 156 and an interlayer dielectric layer 154 are formed. The etch stop layer 156 entirely and conformally covers the structure shown in Figure 5B , and the interlayer dielectric layer 154 is entirely formed on the etch stop layer 156.

[0093] ​Subsequently, at step S120, conductive plugs 434a, conductive walls 434b, and conductive plug 152 are formed. In some embodiments, the method of forming conductive plugs 434a, conductive walls 434b, and conductive plug 152 includes forming vias and trenches through the interlayer dielectric layer 154 and the etch stop layer 156, and then filling these vias with a conductive material by a deposition process, a plating process, or a combination thereof to form conductive plugs 434a, conductive walls 434b, and conductive plug 152.

[0094] Thus far, the manufacturing method through some embodiments has been completed Figure 4A of the semiconductor structure 400 shown. Although not shown, more metallization layers and interlayer dielectric layers may subsequently be formed on the interlayer dielectric layer 154, and a packaging process may be performed to form a semiconductor die.

[0095] In summary, by providing a gate coupling layer between the conductive plugs of the floating gate and the control gate, the capacitive coupling area between the control gate and the floating gate can be increased. In some embodiments, the gate coupling layer covers the upper surface and sidewalls of the floating gate, so that the control gate electrically connected to the gate coupling layer can be capacitively coupled to the floating gate in the vertical and horizontal directions via the gate coupling layer. In other embodiments, the gate coupling layer can be used to improve the capacitive coupling between the control gate and the floating gate in the vertical direction, and the control gate may further include a conductive wall extending along the side of the floating gate. In this way, the control gate can still be capacitively coupled to the floating gate in the vertical and horizontal directions.

Claims

1. A memory element, characterized in that, Comprising: A floating gate disposed on a substrate and having a comb-shaped portion, wherein the comb-shaped portion has a plurality of strip patterns laterally spaced apart from each other; An inter-gate dielectric layer covering an upper surface of the comb-shaped portion of the floating gate; A gate coupling layer covering the inter-gate dielectric layer; And A control gate including a conductive plug standing on the gate coupling layer and electrically connected to the gate coupling layer, wherein the gate coupling layer is used to increase a coupling area between the control gate and the floating gate, and the control gate is capacitively coupled to the comb-shaped portion of the floating gate in a vertical direction and a horizontal direction.

2. The memory element according to claim 1, wherein the inter-gate dielectric layer and the gate coupling layer substantially completely cover the upper surface of the comb-shaped portion of the floating gate.

3. The memory element according to claim 1, further comprising a metal silicide layer formed on the gate coupling layer, wherein the conductive plug of the control gate is electrically connected to the gate coupling layer via the metal silicide layer.

4. The memory element according to claim 1, wherein the floating gate further has another portion extending on an active region of the substrate and contacting the active region through a tunneling dielectric layer.

5. The memory element according to claim 4, further comprising an isolation structure disposed in the substrate and surrounding the active region.

6. The memory element according to claim 5, wherein the comb-shaped portion of the floating gate, the inter-gate dielectric layer and the gate coupling layer overlap the isolation structure.

7. The memory element according to claim 1, wherein the inter-gate dielectric layer further covers sidewalls of the comb-shaped portion of the floating gate, and the gate coupling layer further fills a space between the plurality of strip patterns of the comb-shaped portion of the floating gate.

8. The memory element according to claim 1, wherein the inter-gate dielectric layer has a plurality of portions laterally spaced apart from each other, respectively covering the plurality of strip patterns of the comb-shaped portion of the floating gate, and wherein the gate coupling layer also has a plurality of portions laterally spaced apart from each other, respectively covering the plurality of portions of the inter-gate dielectric layer.

9. The memory element according to claim 8, wherein the control gate further includes at least one conductive wall extending between adjacent strip patterns of the comb-shaped portion of the floating gate.

10. A method for manufacturing a memory element, comprising: Forming a floating gate above a substrate, wherein the floating gate has a comb-shaped portion, and the comb-shaped portion has a plurality of strip patterns laterally spaced apart from each other; Forming an inter-gate dielectric layer on the comb-shaped portion of the floating gate; Forming a gate coupling layer on the inter-gate dielectric layer; And Forming a control gate on the substrate, wherein the control gate includes a conductive plug standing on the gate coupling layer and electrically connected to the gate coupling layer, and wherein the gate coupling layer is used to increase a coupling area between the control gate and the floating gate, and the control gate is capacitively coupled to the comb-shaped portion of the floating gate in a vertical direction and a horizontal direction.

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