Indium Phosphide Double Heterojunction Bipolar Transistor

Abstract

The present invention relates to an indium phosphide double heterojunction bipolar transistor, belonging to the technical field of semiconductor devices. The disclosed indium phosphide double heterojunction bipolar transistor structure utilizes a strained indium arsenic phosphide transition region on an indium phosphide substrate to eliminate the conduction band barrier between the indium gallium arsenide base region and the indium phosphide collector region, thereby constructing a double heterojunction bipolar transistor without an electron blocking effect. This improves the transistor's electrical performance in terms of frequency, gain, and breakdown voltage.

Description

Technical Field

[0001] The present invention specifically relates to an indium phosphide double heterojunction bipolar transistor structure, and belongs to the technical field of semiconductor devices. Background Art

[0002] Indium phosphide heterojunction bipolar transistors (InP HBTs) offer advantages such as ultra-high frequency, high efficiency, high linearity, and single-supply operation. They are widely used in high-frequency test instruments, optical communications, radar, and high-reliability electronic systems. To improve the breakdown voltage of InP HBTs, wide-bandgap InP materials are needed to fabricate the collector region, creating a double heterojunction bipolar transistor (DHBT). However, conventional InP NPN-type DHBTs use heavily doped P-type indium gallium arsenide (InGaAs) as the base region. Because its conduction band energy level is lower than that of InP, using InP directly as the collector region results in an electron blocking effect at the base-collector interface, severely degrading the electrical performance of the InP DHBT.

[0003] There are three existing approaches to addressing the electron blocking effect in indium phosphide double heterojunction bipolar transistors (InP DHBTs): First, using an indium gallium arsenide phosphide (InGaAsP) transition layer in the collector region, but this can lead to dry-etch damage and difficulty scaling the collector region. Second, using an indium aluminum arsenide / indium gallium arsenide (InAlAs / InGaAs) superlattice structure in the collector region, but this requires subatomic thickness growth precision, making epitaxial growth difficult and yield control difficult. Third, using an indium arsenide antimony (GaAsSb) base region, but the strong memory effect of the InAsSb material during growth makes material growth challenging. Given the limitations of these existing technologies, new technical solutions are needed to improve the electrical performance of InP DHBTs. Summary of the Invention

[0004] In order to solve the above-mentioned defects, the present invention provides a double heterojunction bipolar transistor structure.

[0005] The present invention provides a double heterojunction bipolar transistor structure, comprising: a single crystal indium phosphide substrate formed of a single crystal semi-insulating indium phosphide material; a sub-collector region, arranged on the single crystal indium phosphide substrate, formed of an N-type III-V semiconductor; a collector region, arranged on the sub-collector region, formed of an N-type III-V semiconductor; a base region, arranged on the collector region, formed of a P-type indium gallium arsenide (P+InGaAs) semiconductor; an emitter region, arranged on the base region, formed of an N-type III-V semiconductor; and an ohmic contact layer, arranged on the emitter region, formed of an N-type III-V semiconductor.

[0006] The indium concentration in the base region changes in a unidirectional gradient, the lattice constant of the base region near the collector region interface matches the single crystal indium phosphide substrate, and the ratio of indium to gallium atoms in the base region near the emitter region interface is lower than 53:47.

[0007] The P-type InGaAs base region is carbon-doped, and the effective carbon doping concentration in the base region varies in a unidirectional gradient, and the effective carbon doping concentration of the P-type InGaAs semiconductor in the base region at the interface of the emitter region is higher than the effective carbon doping concentration of the base region at the interface of the collector region.

[0008] The N-type doping concentration of the collector region changes in a unidirectional gradient, and the effective N-type doping concentration of the collector region at the base region interface is lower than the effective N-type doping concentration of the collector region at the sub-collector region interface.

[0009] The collector region uses three N-type III-V semiconductor materials to form a composite collector region, and its material components are arranged in sequence according to the order of indium gallium arsenide layer (InGaAs), strained indium arsenic phosphide layer (InAsP), and indium phosphide layer (InP). The indium gallium arsenide layer (InGaAs) is adjacent to the base region, the indium phosphide layer (InP) is adjacent to the sub-collector region, and the strained indium arsenic phosphide layer (InAsP) is arranged between the indium gallium arsenide layer (InGaAs) and the indium phosphide layer (InP).

[0010] The subcollector region includes a heavily doped N-type indium phosphide layer (N+InP) and a heavily doped N-type indium gallium arsenide layer (N+InGaAs), wherein the heavily doped N-type indium gallium arsenide layer (N+InGaAs) is arranged on the heavily doped N-type indium phosphide layer (N+InP), and the heavily doped N-type indium phosphide layer (N+InP) is arranged on the semi-insulating single crystal indium phosphide (SI-InP) substrate.

[0011] The material component of the emission region includes one of indium phosphide (InP), indium gallium phosphide (InGaP), indium arsenic phosphide (InAsP), indium gallium arsenic phosphide (InGaAsP), or a combination of at least two of them.

[0012] The ohmic contact layer uses a heavily doped N-type high-indium-content indium gallium arsenide layer (N+InGaAs, In component greater than 0.7) to reduce the ohmic contact resistance of the emitter and improve the frequency characteristics of the transistor.

[0013] The effective carbon doping concentration range of the P-type indium gallium arsenide (P+InGaAs) base region is 1×10 18 ~2×10 20 atoms / cm 3 .

[0014] The arsenic atomic concentration in the strained indium arsenic phosphide layer (N-InAsP) (the number of arsenic atoms in the strained indium arsenic phosphide layer divided by the sum of the number of arsenic and phosphide atoms) varies in a unidirectional gradient to eliminate the conduction band barrier between the indium gallium arsenide layer (N-InGaAs) and the indium phosphide layer (N-InP) in the collector region. The arsenic atomic concentration at the interface of the strained indium arsenic phosphide layer adjacent to the indium phosphide layer (N-InP) is zero, and the arsenic atomic concentration at the interface of the strained indium arsenic phosphide layer adjacent to the indium gallium arsenide layer (N-InGaAs) is 10% to 60%.

[0015] The indium gallium arsenide layer (N-InGaAs) in the collector region has a lattice constant that matches the single crystal indium phosphide substrate, a thickness ranging from 0.3 nm to 50 nm, and an N-type doping concentration of 1×10 15 ~2×10 17 atoms / cm 3 .

[0016] The indium phosphide layer (N-InP) in the collector region has N-type non-uniform doping inside, and its function is to achieve a higher breakdown voltage of the collector region.

[0017] The strained indium arsenide phosphide layer (N-InAsP) in the collector region has a thickness ranging from 0.3 nm to 30 nm and an N-type doping concentration of 1×10 15 ~1×10 18 atoms / cm 3 .

[0018] The strained indium arsenide phosphide layer (N-InAsP) in the collector region has compressive strain inside because the diameter of arsenic atoms is larger than that of phosphorus atoms. Its thickness should be thin enough to ensure that the lattice of the strained indium arsenide phosphide layer does not relax.

[0019] The indium phosphide layer (N-InP) in the collector region has N-type non-uniform doping inside, and its impurity distribution includes one of linear gradient, exponential gradient, step gradient, delta doping, or a combination of at least two of them.

[0020] The structure of the indium phosphide double heterojunction bipolar transistor of the present invention uses strained indium arsenide phosphide (N-InAsP) as a transition region to eliminate the conduction band barrier between the indium gallium arsenide (P+InGaAs) base region and the indium phosphide (N-InP) collector region, thereby constructing a double heterojunction bipolar transistor without an electron blocking effect. This improves the electrical performance of the indium phosphide double heterojunction bipolar transistor (InPDHBT) in terms of frequency, gain, and breakdown voltage, and has significant technical progress and economic benefits. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of the epitaxial structure of the indium phosphide double heterojunction bipolar transistor provided by the present invention;

[0022] Figure 2 A schematic diagram of the structure of an indium phosphide double heterojunction bipolar transistor device provided by the present invention;

[0023] Figure 3 A schematic diagram of the energy band structure of the indium phosphide double heterojunction bipolar transistor provided by the present invention; DETAILED DESCRIPTION

[0024] In order to make the purpose, content, and advantages of the present invention clearer, the specific embodiments of the present invention are described in further detail below in conjunction with the accompanying drawings and examples. The following examples are only used to more clearly illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention.

[0025] This embodiment is specifically described by taking an N-type lightly doped indium phosphide / P-type heavily doped indium gallium arsenide / N-type lightly doped indium arsenide phosphide / indium phosphide double heterojunction bipolar transistor ( / N-InP / P+InGaAs / N-InAsP / InP DHBT) as an example. Figure 1 This is a schematic diagram of the epitaxial structure of the indium phosphide double heterojunction bipolar transistor provided by the present invention.

[0026] The epitaxial structure of the InP double heterojunction bipolar transistor is as follows Figure 1 As shown, the device comprises: a semi-insulating single crystal indium phosphide substrate 101, a sub-collector region 102, a collector region 103, a base region 104, an emitter region 105, and an ohmic contact layer 106. The sub-collector region 102 is disposed on the semi-insulating single crystal indium phosphide substrate 101, the collector region 103 is disposed on the sub-collector region 102, the base region 104 is disposed on the collector region 103, the emitter region 105 is disposed on the base region 104, and the ohmic contact layer 106 is disposed on the emitter region 105.

[0027] Figure 2The schematic diagram of the indium phosphide double heterojunction bipolar transistor device structure provided by the present invention, wherein the indium phosphide double heterojunction bipolar transistor (InP DHBT) device structure specifically includes:

[0028] The semi-insulating single crystal indium phosphide substrate 101 is generally a single crystal indium phosphide (InP) substrate doped with iron (Fe) with a 100 crystal orientation, and the resistivity of the substrate is greater than 1×10 7 ohm-cm to reduce high-frequency loss of the substrate;

[0029] The sub-collector region 102 includes a 400 nm heavily doped indium phosphide (InP) conductive layer 1022 and a 20 nm heavily doped indium gallium arsenide (InGaAs) contact layer 1021, with a doping concentration typically greater than 3×10 19 atoms / cm 3 The collector metal 109 is formed on the heavily doped InGaAs layer to obtain a lower ohmic contact resistance, such as Figure 2 shown.

[0030] The collector region 103 includes a 20 nm N-type lightly doped indium gallium arsenide (N-InGaAs) layer 1031, a 30 nm N-type lightly doped indium arsenide phosphide (N-InAsP) layer 1032, a 150 nm N-type lightly doped indium phosphide (N-InP) layer 1033, and a 50 nm heavily doped N-type indium phosphide (N+InP) layer 1034. Figure 2 As shown; the arsenic atomic concentration in the N-type lightly doped indium arsenide phosphide (N-InAsP) layer 1032 (the number of arsenic atoms in the strained indium arsenide phosphide layer divided by the sum of the number of arsenic and phosphorus atoms) changes in a unidirectional gradient to eliminate the conduction band barrier between the N-type lightly doped indium gallium arsenide (N-InGaAs) layer 1031 and the N-type lightly doped indium phosphide (N-InP) layer 1033 in the collector region 103, the arsenic atomic concentration near the interface of the N-type lightly doped indium phosphide (N-InP) layer 1033 is zero (at this time, N-InAsP becomes N-InP), and the arsenic atomic concentration near the interface of the N-type lightly doped indium gallium arsenide (N-InGaAs) layer 1031 is 40% (at this time, the component of N-InAsP is N-InP). 0.6 As 0.4 P), such as Figure 3 The collector region 103 includes an N-type lightly doped indium gallium arsenide (N-InGaAs) layer 1031, an N-type lightly doped indium arsenide phosphide (N-InAsP) layer 1032, and an N-type lightly doped indium phosphide (N-InP) layer 1033, the doping concentration of which is 3×10 16 atoms / cm 3 The doping concentration of the heavily doped N-type indium phosphide (N+InP) layer 1034 is 3×10 19 atoms / cm 3The N-type lightly doped indium phosphide (N-InP) layer 1033 in the collector region 103 has a delta-doped insertion layer, the delta-doped insertion layer has a thickness of 2 nanometers and a doping concentration of 1×10 18 atoms / cm 3 , whose function is to make the conduction band of the collector region 103 drop rapidly to eliminate the current blocking effect caused by the conduction band discontinuity, such as Figure 3 shown.

[0031] The base region 104 is P-type heavily doped indium gallium arsenide (P+InGaAs), and the concentration of indium in the base region changes linearly. The interface between the base region 104 and the collector region 103 is In. 0.53 Ga 0.47 As, the interface between the base region 104 and the emitter region 105 is In 0.44 Ga 0.56 As; the P+InGaAs in the base region 104 is carbon-doped, and the effective carbon doping concentration in the base region 104 changes linearly, and the effective carbon doping concentration at the interface of the base region 104 near the collector region 103 is 4×10 19 atoms / cm 3 The effective carbon doping concentration at the interface between the base region 104 and the emitter region 105 is 8×10 19 atoms / cm 3 The base metal 108 is formed on the base region 104, 8×10 19 atoms / cm 3 Heavy carbon doping can achieve very low base contact resistance, such as Figure 2 The P-type heavily doped indium gallium arsenide (P+InGaAs) disclosed in the present invention adopts a dual gradient design of indium component and carbon doping. Its function is to reduce the transit time of the base region 104 and increase the cutoff frequency of the device. In addition, the gradient base region 104 allows for a larger base region 104 thickness, thereby effectively reducing the resistance of the base region 104. This plays an important role in improving the high-frequency gain of the device and reducing noise.

[0032] The material component of the emitter region 105 is N-type indium phosphide (InP). The second portion 1052 of the emitter region 105 close to the base region 104 is N-type doped with Si, with a doping concentration of 5×10 17 atoms / cm 3 , with a thickness of 50 nanometers; the first portion 1051 of the emitter region 105 close to the ohmic contact layer 106 is N-type heavily doped indium phosphide (N+InP), with a doping concentration of 3×10 19 atoms / cm 3 , with a thickness of 100 nm, such as Figure 3 shown.

[0033] The material component of the ohmic contact layer 106 is N-type heavily doped indium gallium arsenide (N+InGaAs), with a doping concentration greater than 4×10 19 atoms / cm 3 The emitter metal 107 is formed on the ohmic contact layer 106. The N+InGaAs layer uses a high indium component to reduce the band gap. The In component is usually greater than 0.7 to reduce the ohmic contact resistance of the emitter. Figure 2 shown.

[0034] The 0.25 micron emitter self-aligned InGaAs / InAsP / InP DHBT radio frequency device developed by the indium phosphide double heterojunction bipolar transistor structure provided by the present invention has a cutoff frequency F T The frequency exceeds 300 GHz, the breakdown voltage is higher than 5 V, and the current gain is greater than 70, indicating that the present invention has significant technical advantages and important economic value in high-frequency and high-speed applications.

[0035] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A double heterojunction bipolar transistor, characterized in that: include: A single crystal indium phosphide substrate, formed of a single crystal semi-insulating indium phosphide material; a sub-collector region, disposed on the single crystal indium phosphide substrate and formed of an N-type III-V semiconductor; a collector region, disposed on the sub-collector region and formed of an N-type III-V semiconductor; A base region, disposed on the collector region and formed of a P-type indium gallium arsenide semiconductor; an emitter region, disposed on the base region and formed of an N-type III-V semiconductor; an ohmic contact layer, disposed on the emitter region and formed of an N-type III-V semiconductor; The collector region uses three N-type III-V semiconductor materials to form a composite collector region, and its material components are arranged in sequence according to the order of indium gallium arsenide layer, strained indium arsenic phosphide layer, and indium phosphide layer. The indium gallium arsenide layer is adjacent to the base region, the indium phosphide layer is adjacent to the sub-collector region, and the strained indium arsenic phosphide layer is arranged between the indium gallium arsenide layer and the indium phosphide layer.

2. The double heterojunction bipolar transistor according to claim 1, wherein: The concentration of indium in the base region changes in a unidirectional gradient, the lattice constant of the base region near the collector region interface matches the single crystal indium phosphide substrate, and the ratio of the number of indium and gallium atoms in the base region near the emitter region interface is lower than 53:

47.

3. The double heterojunction bipolar transistor according to claim 1, wherein: The base region is carbon-doped, and the effective carbon doping concentration in the base region varies in a unidirectional gradient, and the effective carbon doping concentration of the base region at the interface of the emitter region is higher than the effective carbon doping concentration of the base region at the interface of the collector region.

4. The double heterojunction bipolar transistor according to claim 1, wherein: The N-type doping concentration of the collector region changes in a unidirectional gradient, and the effective N-type doping concentration of the collector region at the base region interface is lower than that of the collector region at the sub-collector region interface.

5. The double heterojunction bipolar transistor according to claim 1, wherein: The subcollector region includes a heavily doped N-type indium phosphide layer and a heavily doped N-type indium gallium arsenide layer. The heavily doped N-type indium gallium arsenide layer is arranged on the heavily doped N-type indium phosphide layer, and the heavily doped N-type indium phosphide layer is arranged on the single crystal indium phosphide substrate.

6. The double heterojunction bipolar transistor according to claim 1, wherein: The emission region material component includes one of indium phosphide, indium gallium phosphide, indium arsenic phosphide, indium gallium arsenic phosphide, or a combination of at least two of them.

7. The double heterojunction bipolar transistor according to claim 1, wherein: The ohmic contact layer is a heavily doped N-type high indium component indium gallium arsenide layer.

8. The double heterojunction bipolar transistor according to claim 3, wherein: The effective carbon doping concentration range of the base region is 1×10 18 ~2×10 20 atoms / cm 3 .

9. The double heterojunction bipolar transistor according to claim 1, wherein: The arsenic atomic concentration of the strained indium arsenic phosphide layer changes in a unidirectional gradient to eliminate the conduction band barrier between the indium gallium arsenic layer and the indium phosphide layer in the collector region. The arsenic atomic concentration at the interface of the strained indium arsenic phosphide layer adjacent to the indium phosphide layer is zero, and the arsenic atomic concentration at the interface of the strained indium arsenic phosphide layer adjacent to the indium gallium arsenic layer is 10% to 60%.

10. The double heterojunction bipolar transistor according to claim 1, wherein: The lattice constant of the InGaAs layer matches that of the single crystal InP substrate, the thickness of the InGaAs layer ranges from 0.3 nm to 50 nm, and the N-type doping concentration of the InGaAs layer is 1×10 15 ~2×10 17 atoms / cm 3 .

11. The double heterojunction bipolar transistor according to claim 1, wherein: N-type non-uniform doping exists inside the indium phosphide layer.

12. The double heterojunction bipolar transistor according to claim 11, wherein: The N-type non-uniform doping impurity distribution forms inside the indium phosphide layer include linear gradient, exponential gradient, step gradient, One of the doping methods or a combination of at least two of the doping methods may be used.

13. The double heterojunction bipolar transistor according to claim 1 or 9, wherein: The thickness of the strained InAsP layer ranges from 0.3 nm to 30 nm, and the N-type doping concentration is 1×10 15 ~1×10 18 atoms / cm 3 .

14. The double heterojunction bipolar transistor according to claim 1 or 9, wherein: There is compressive strain inside the strained indium arsenide phosphide layer.

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