Capacitor integrated structure, capacitor unit and manufacturing method thereof

Abstract

The present invention discloses a capacitive integrated structure, a capacitive unit and a manufacturing method thereof. Among them, the manufacturing method of the capacitive unit includes forming a plurality of capacitive stack structures on a substrate having an insulating layer, performing a first cutting process on an insulating spacer portion formed between two adjacent capacitive stack structures to form a plurality of grooves exposing a first conductive portion and a second conductive portion of each capacitive stack structure; filling each groove with a metal material to form a plurality of metal spacer portions electrically connected to the first conductive portion and the second conductive portion; then performing a second cutting process on each metal spacer portion to form a plurality of independent capacitive units, and forming metal sidewalls on opposite sides of each capacitive unit, thereby constituting a capacitive unit having two end electrodes. Thus, it is not necessary to additionally provide an electrical connection hole structure for electrically connecting the conductive portions of each layer in each capacitive stack structure in the capacitive unit, and the electrical connection manufacturing process of the conductive portions of each layer inside the capacitive unit can be simplified.

Description

Technical Field

[0001] The present invention relates to a semiconductor technology, and more particularly to a capacitive integration structure, a capacitive unit and a manufacturing method thereof. Background Art

[0002] The complete manufacturing process of existing capacitors (such as MLCC) includes many process steps. For example, slurry preparation, ceramic film forming, printing, stacking, voltage equalization, cutting, degumming, sintering, chamfering, silver dipping, firing, electroplating, testing, packaging and other steps. Although this product manufacturing process is complex, it is very mature. Suppliers in the relevant industrial chain or production volume have long shown a stable state of sufficient supply. Until recently, with the progress of technology, applications in various new fields such as the Internet of Things, 5G communication, artificial intelligence, and electric vehicles have been developed, and the functions of various types of electronic products have been increasingly improved. The types and quantities of components used are becoming more and more numerous; the increase in the number of active components used and the improvement in precision have led to a multiple increase in the number of passive components to be matched, and the multilayer ceramic capacitor (MLCC) is the most prominent among them. Therefore, the market has gradually started to show a situation of supply falling short of demand, and the recent production increase plans of passive component suppliers cannot fully meet the market demand. The shortage situation will affect the development of the overall industry. On the other hand, how to layout and display all components within a limited space is a major issue. In order to cope with the high-density component layout and display, it is imperative to shrink the component area or even volume. The traditional capacitor manufacturing process has faced challenges in both area reduction and product precision.

[0003] In view of this, the present invention uses a material, structure and manufacturing process different from the traditional multilayer ceramic capacitor (MLCC) to provide another choice of capacitor for the market supply. The present invention can also reduce the difficulty of reducing the capacitor area and thereby improve the product precision. On the other hand, it can avoid the high-temperature calcination process in the manufacturing process of traditional multilayer ceramic capacitors (MLCC), thereby achieving energy conservation and carbon reduction and reducing its manufacturing cost. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the present invention provides a capacitive unit, a manufacturing method thereof, and a capacitive integration structure, which can simplify the process of manufacturing internal connections in the capacitor and manufacture two-terminal electrodes the same as those of multilayer ceramic capacitors.

[0005] To achieve the above and other related objectives, an embodiment of the present invention provides a method for manufacturing a capacitor unit, including providing a substrate; forming an insulating layer on the substrate; forming a plurality of capacitor stack structures on the insulating layer, with an insulating spacer formed between two adjacent capacitor stack structures, and each capacitor stack structure having a first pad, a first conductive portion, a second pad, and a second conductive portion; performing a first cutting process on each insulating spacer to form a plurality of grooves exposing the first conductive portion and the second conductive portion of each capacitor stack structure; filling each groove with a metal material to form a plurality of metal spacers electrically connected to the first conductive portion and the second conductive portion; performing a second cutting process on each metal spacer to form a plurality of independent capacitor units, and forming a first metal sidewall and a second metal sidewall on opposite sides of each capacitor unit; wherein, in each capacitor unit, the first pad is electrically connected to the first conductive portion through the first metal sidewall to form a first electrode, and the second pad is electrically connected to the second conductive portion through the second metal sidewall to form a second electrode.

[0006] Optionally, the substrate is a silicon substrate.

[0007] Optionally, the step of forming a plurality of capacitor stack structures on the insulating layer further includes: forming a stack structure layer on the insulating layer, wherein the stack structure layer includes at least one interlayer conductive layer and at least one interlayer dielectric layer arranged alternately, and each interlayer conductive layer has a first conductive portion and a second conductive portion; and forming the first pad and the second pad on the stack structure layer.

[0008] Optionally, the step of forming a stack structure layer on the insulating layer further includes: forming a first interlayer conductive layer having a first dielectric on the insulating layer, and defining the first conductive portion and the second conductive portion of the first interlayer conductive layer through the first dielectric; forming a first interlayer dielectric layer on the first interlayer conductive layer; forming a second interlayer conductive layer having a second dielectric on the first interlayer dielectric layer, and defining the first conductive portion and the second conductive portion of the second interlayer conductive layer through the second dielectric; forming an isolation layer on the second interlayer conductive layer; forming a first metal via and a second metal via arranged at intervals on the isolation layer; and forming a passivation layer to cover the interlayer dielectric layer and expose a part of the first metal via and the second metal via respectively, so as to form the first pad through the exposed part of the first metal via and form the second pad through the exposed part of the second metal via.

[0009] Optionally, the plurality of capacitor stack structures are arranged on the substrate at intervals in a matrix form along an X-axis direction and a Y-axis direction of the substrate; and wherein, the method further includes: laying an auxiliary layer under the substrate; along the X-axis direction of the substrate, performing a first cutting process on each of the insulating spacer portions with a first cutting depth and a first cutting width to form each of the grooves, wherein the first cutting depth extends from the top of each capacitor stack structure to the insulating layer, and the first cutting width is not less than a preset interval width of the insulating spacer portion; performing a filling process on each of the grooves to form each of the metal spacer portions electrically connected to each capacitor stack structure; along the X-axis direction of the substrate, performing a second cutting process on each of the metal spacer portions with a second cutting depth and a second width to form a plurality of capacitor sets each including a plurality of the capacitor units, wherein the second cutting depth extends from the top of each capacitor stack structure to the auxiliary layer, and the second cutting width is less than the first cutting width, so as to form the first metal sidewall and the second metal sidewall on opposite sides of each capacitor unit along the Y-axis direction of the substrate; and cutting each of the capacitor sets along the Y-axis direction of the substrate to form each of the capacitor units.

[0010] Optionally, the auxiliary layer is a tape layer laid under the substrate.

[0011] Optionally, the first cutting process includes any one of a dicing wheel cutting method, a dry etching cutting method, and a laser scribing cutting method; the filling process includes any one of a screen printing method and an electroplating method; the second cutting process includes a dicing wheel cutting method.

[0012] Another embodiment of the present invention provides a capacitor unit, including a substrate; an insulating layer formed on the substrate; a capacitor stack structure formed on the insulating layer and having a first pad, a first conductive portion, a second pad, and a second conductive portion; a first metal sidewall and a second metal sidewall located on opposite sides of the capacitor stack structure; wherein, the first pad is electrically connected to the first conductive portion through the first metal sidewall to form a first electrode, and the second pad is electrically connected to the second conductive portion through the second metal sidewall to form a second electrode.

[0013] Optionally, the substrate is made of a wafer, and the capacitor unit is welded to a printed circuit board through the first pad and the second pad.

[0014] Optionally, the first metal sidewall and the second metal sidewall are located on opposite sides of the capacitor stack structure along the Y-axis direction of the substrate, and the capacitor unit further includes a first insulating sidewall and a second insulating sidewall, and the first insulating sidewall and the second insulating sidewall are located on opposite sides of the capacitor stack structure along the X-axis direction of the substrate, wherein the Y-axis direction is perpendicular to the X-axis direction.

[0015] Another embodiment of the present invention provides a capacitive integrated structure, comprising: a wafer; and a plurality of capacitive stack structures, each of which is disposed on the wafer at intervals in a matrix form along an X-axis direction and a Y-axis direction of the wafer; a plurality of metal spacer portions, which are arranged along the X-axis direction of the wafer between two adjacent capacitive stack structures; and a plurality of insulating spacer portions, which are arranged along the Y-axis direction of the wafer between two adjacent capacitive stack structures.

[0016] Optionally, the capacitive integrated structure can be cut along the X-axis direction and the Y-axis direction respectively to form a plurality of independent capacitive units. Among them, each capacitive unit includes: a part of the wafer; a capacitive stack structure having a first pad, a first conductive portion, a second pad and a second conductive portion; a first metal sidewall and a second metal sidewall formed on opposite sides of a capacitive stack structure by cutting the metal spacer portion; and a first insulating sidewall and a second insulating sidewall formed on opposite sides of a capacitive stack structure by cutting the insulating spacer portion; wherein the first pad is electrically connected to the first conductive portion through the first metal sidewall to form a first electrode, and the second pad is electrically connected to the second conductive portion through the second metal sidewall to form a second electrode.

[0017] In summary, the present invention uses a wafer to make a capacitive integrated structure containing a plurality of capacitors, so that capacitors can be manufactured in a batch manner, and independent capacitors can be formed by cutting. Compared with the manufacturing process of traditional multilayer ceramic capacitors, the present invention can simplify the manufacturing process of capacitors, avoid the high-temperature calcination process in the traditional multilayer ceramic capacitor manufacturing process, and can also use existing semiconductor equipment to manufacture the capacitive integrated structure of the present invention to achieve the purpose of reducing manufacturing costs.

[0018] Furthermore, the present invention can use semiconductor manufacturing processes to form metal sidewalls on opposite sides of a capacitive unit respectively, so as to form a capacitive unit with two end electrodes, and there is no need to additionally provide an electrical connection hole structure for electrically connecting each layer of conductive portions in each capacitive stack structure in the capacitive unit, which can simplify the semiconductor manufacturing process of the capacitive unit, that is, it can simplify the electrical connection manufacturing process of each layer of conductive portions inside the capacitive unit, be used to simplify the manufacturing process of built-in capacitor connections, and manufacture two end electrodes the same as those of multilayer ceramic capacitors. Description of the Drawings

[0019] Figures 1 to 12 It is a schematic flow chart of the manufacturing method of the capacitive unit of the present invention;

[0020] Figures 13A to 14 It is a schematic structural diagram of the capacitive unit and the capacitive integrated structure of the present invention.

[0021] Symbol Description

[0022] 1 Capacitor unit

[0023] 11 Substrate / wafers

[0024] 12 Insulating layer

[0025] 13, 13A, 13B Capacitor stack structure

[0026] 130 Auxiliary layer

[0027] 131 Insulating spacer

[0028] 132 First pad / first metal stud

[0029] 133 First conductive part

[0030] 134 Second pad / second metal stud

[0031] 135 Second conductive part

[0032] 136 Interlayer conductive layer

[0033] 1360 Gap

[0034] 1361 First dielectric / second dielectric

[0035] 1365 Dielectric material

[0036] 137 Interlayer dielectric layer

[0037] 1375 Isolation layer

[0038] 138 Passivation layer

[0039] 14 Groove

[0040] 15 Metal spacer

[0041] 16 First metal sidewall

[0042] 17 Second metal sidewall

[0043] 18 Capacitor assembly

[0044] 191 First insulating sidewall

[0045] 192 Second insulating sidewall

[0046] 20 Capacitor integrated structure Detailed implementation manners

[0047] The following content will be accompanied by drawings to illustrate the technical content of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the spirit of this application. In particular, the proportional relationships and relative positions of various elements in the drawings are only for illustrative purposes and do not represent the actual situation of the implementation of the present invention.

[0048] An embodiment of the present invention provides a method for manufacturing a capacitor unit.

[0049] Refer to Figure 1 , first, a substrate 11 is provided, and an insulating layer 12 is formed on the substrate 11.

[0050] In this embodiment, the substrate 11 is made of a wafer. Among them, the substrate 11 is, for example, a silicon substrate, but not limited thereto. The substrate 11 can also be other types of substrates such as a glass substrate or a quartz substrate. In this embodiment, the insulating layer 12 is made of a dielectric material and is used as a bottom insulating layer.

[0051] Next, a plurality of capacitor stack structures 13 are formed on the insulating layer 12. Among them, a plurality of insulating spacer portions 131 are formed between two adjacent capacitor stack structures 13, and each capacitor stack structure 13 has a first pad 132, a first conductive portion 133, a second pad 134, and a second conductive portion 135 (to be described in detail later in Figures 2A to 9 ).

[0052] In this embodiment, the plurality of capacitor stack structures 13 are arranged on the substrate 11 at intervals in a matrix form along an X-axis direction and a Y-axis direction of the substrate 11.

[0053] Specifically, a stack structure layer can be first formed on the insulating layer 12. Among them, the stack structure layer includes at least one interlayer conductive layer 136 and at least one interlayer dielectric layer 137 arranged alternately. Each interlayer conductive layer 136 has a first conductive portion 133 and a second conductive portion 135. Then, a first pad 132 and a second pad 134 are formed on the stack structure layer to form the capacitor stack structure 13.

[0054] The following will combine Figures 2A to 9 to describe in detail the specific steps of forming a capacitor stack structure 13 on the insulating layer 12:

[0055] As shown in the side view of Figure 2A and Figure 2BAs shown in the top view, a first interlayer conductive layer 136 is formed as an electrode layer, and the first interlayer conductive layer 136 is etched to form a gap 1360.

[0056] As Figure 3 and Figure 4A shown, a dielectric material 1365 is deposited in the gap 1360 of the first interlayer conductive layer 136 (refer to Figure 3 ), and then a planarization process is performed to form a first dielectric body 1361 on the first interlayer conductive layer 136, and the first conductive part 133 and the second conductive part 135 of the first interlayer conductive layer 136 are defined by the first dielectric body 1361 (refer to Figure 4A the side view shown in Figure 4B and the top view shown in

[0057] As Figure 5 shown, a first interlayer dielectric layer 137 is formed on the first interlayer conductive layer 136.

[0058] As Figure 6 shown, the above steps of forming the first interlayer conductive layer 136 and the first interlayer dielectric layer 137 are repeated (i.e., the steps shown in Figures 2A to 5 ) to form a second interlayer conductive layer 136 with a second dielectric body 1361 on the first interlayer dielectric layer 137, and the first conductive part 133 and the second conductive part 135 of the second interlayer conductive layer 136 are defined by the second dielectric body 1361; then a second interlayer dielectric layer 137 is formed on the second interlayer conductive layer 136 until the number of the interlayer conductive layers 136 and the interlayer dielectric layers 137 in the capacitor stack structure 13 meets the expectation, and an isolation layer 1375 is formed on the topmost interlayer conductive layer 136.

[0059] As Figure 7 shown, a first metal stud 132 and a second metal stud 134 arranged at intervals are formed on the isolation layer 1375.

[0060] As Figures 8 to 9 shown, a passivation layer 138 is formed to cover the interlayer dielectric layer 137 and expose a part of the first metal stud 132 and the second metal stud 134 respectively, so as to form a first pad 132 through the exposed part of the first metal stud 132 and form a second pad 134 through the exposed part of the second metal stud 134.

[0061] As Figure 10 shown, after the capacitor stack structure 13 is formed on the insulating layer 12, a first cutting process can be performed on each insulating spacer 131 to form a plurality of grooves 14 that expose the first conductive part 133 and the second conductive part 135 of each capacitor stack structure 13.

[0062] Optionally, an auxiliary layer 130 may be disposed under the substrate 11 before performing the first cutting process to increase the strength of the substrate 11 during the cutting process. In this embodiment, the auxiliary layer 130 is a tape layer disposed under the substrate 11.

[0063] Specifically, the first cutting process may be performed along the X-axis direction of the substrate 11 with a first cutting depth and a first cutting width for each insulating spacer 131 to form respective grooves 14.

[0064] In this embodiment, the first cutting depth extends from the top of each capacitor stack structure 13 to the insulating layer 12, and the first cutting width is not less than the preset interval width of the insulating spacer 131.

[0065] Optionally, the first cutting process includes any one of a dicing wheel cutting method, a dry etching cutting method, and a laser scribing cutting method.

[0066] As Figure 11 、 Figures 13C to 13D shown, each groove 14 is filled with a metal material to form a plurality of metal spacers 15 electrically connected to the first conductive portion 133 and the second conductive portion 135.

[0067] In this embodiment, the filling process includes any one of a screen printing method and an electroplating method.

[0068] As Figure 12 、 Figure 13F shown, a second cutting process is performed on each metal spacer 15 to form a plurality of independent capacitor units 1.

[0069] In this embodiment, the second cutting process includes performing a second cutting process along the X-axis direction of the substrate 11 with a second cutting depth and a second width for each metal spacer 15 to form a plurality of capacitor sets 18 each including a plurality of capacitor units 1 (refer to Figure 13D ), and then cutting each capacitor set 18 along the Y-axis direction of the substrate 11 to form respective independent capacitor units 1 (refer to Figure 13F ).

[0070] Optionally, the second cutting process includes a dicing wheel cutting method.

[0071] Optionally, the second cutting depth extends from the top of each capacitor stack structure 13 to the auxiliary layer 130, and the second cutting width is less than the first cutting width.

[0072] In this embodiment, a first metal sidewall 16 and a second metal sidewall 17 are respectively formed on opposite sides of each capacitor unit 1. And in each capacitor unit 1, the first pad 132 is electrically connected to the first conductive portion 133 through the first metal sidewall 16 to form a first electrode, and the second pad 134 is electrically connected to the second conductive portion 135 through the second metal sidewall 17 to form a second electrode.

[0073] Optionally, the first metal sidewall 16 and the second metal sidewall 17 are respectively formed on opposite sides of each capacitor unit 1 along the Y-axis direction. In addition, a first insulating sidewall 191 and a second insulating sidewall 192 are respectively formed on opposite sides of each capacitor unit 1 along the X-axis direction (refer to Figure 13F ).

[0074] Refer to Figures 13A to 13F 、 Figure 14 Another embodiment of the present invention provides a capacitor unit 1, which includes: a substrate 11, an insulating layer 12, a capacitor stack structure 13, a first metal sidewall 16, and a second metal sidewall 17.

[0075] Wherein, the substrate 11 is made of a wafer, the insulating layer 12 is formed on the substrate 11, the capacitor stack structure 13 is formed on the insulating layer 12, and has a first pad 132, a first conductive portion 133, a second pad 134, and a second conductive portion 135. The first metal sidewall 16 and the second metal sidewall 17 are located on opposite sides of the capacitor stack structure 13.

[0076] In this embodiment, the first pad 132 is electrically connected to the first conductive portion 133 through the first metal sidewall 16 to form a first electrode, and the second pad 134 is electrically connected to the second conductive portion 135 through the second metal sidewall 17 to form a second electrode.

[0077] In this embodiment, the first metal sidewall 16 and the second metal sidewall 17 are located on opposite sides of the capacitor stack structure 13 along the Y-axis direction of the substrate 11. And the capacitor unit 1 further includes a first insulating sidewall 191 and a second insulating sidewall 192, which are located on opposite sides of the capacitor stack structure 13 along the X-axis direction of the substrate 11. Wherein, the Y-axis direction is perpendicular to the X-axis direction.

[0078] Please refer to Figure 13A 、 Figure 13E Another embodiment of the present invention further provides a capacitor integrated structure 20, which includes a wafer 11; and a plurality of capacitor stack structures 13.

[0079] In this embodiment, each of the capacitor stack structures is arranged on the wafer 11 at intervals in a matrix form along an X-axis direction and a Y-axis direction of the wafer 11;

[0080] In this embodiment, there is a metal spacer 15 between two adjacent capacitor stack structures 13 along the X-axis direction of the wafer 1, and there is an insulating spacer 131 between two adjacent capacitor stack structures 13 along the Y-axis direction of the wafer 1.

[0081] Optionally, the capacitor integration structure 20 is cut along the X-axis direction and the Y-axis direction respectively to form a plurality of independent capacitor units 1.

[0082] Please refer to Figure 13F 、 Figure 14 , in this embodiment, each capacitor unit 1 includes a part of the wafer 1; a capacitor stack structure 13 having a first pad 132, a first conductive part 133, a second pad 134 and a second conductive part 135; a first metal sidewall 16 and a second metal sidewall 17 formed on opposite sides of the capacitor stack structure 13 by cutting the metal spacer 15; and a first insulating sidewall 191 and a second insulating sidewall 192 formed on opposite sides of the capacitor stack structure 13 by cutting the insulating spacer 131; wherein, the first pad 132 is electrically connected to the first conductive part 133 through the first metal sidewall 16 to form a first electrode, and the second pad 134 is electrically connected to the second conductive part 135 through the second metal sidewall 17 to form a second electrode.

[0083] In summary, by using the manufacturing method of the capacitor unit of the present invention, a first metal sidewall and a second metal sidewall can be formed on opposite sides of the capacitor unit, so that the first pad in the capacitor unit is electrically connected to the first conductive part through the first metal sidewall to form a first electrode, and the second pad in the capacitor unit is electrically connected to the second conductive part through the second metal sidewall to form a second electrode, and a capacitor unit with two end electrodes can be manufactured by using semiconductor manufacturing processes.

[0084] In this way, the present invention can achieve the electrical connection between the first pad and the first conductive part through the first metal sidewall, and achieve the electrical connection between the second pad and the second conductive part through the second metal sidewall, without additionally providing an electrical connection hole structure for electrically connecting each layer of conductive parts in each capacitor stack structure in the capacitor unit, and the semiconductor manufacturing process of the capacitor unit can be simplified, that is, the electrical connection manufacturing process of each layer of conductive parts inside the capacitor can be simplified.

[0085] In addition, in the present invention, a plurality of capacitor stack structures are formed on a wafer to constitute a capacitor integrated structure including a plurality of capacitor units. Therefore, a large number of capacitor units that can be used as capacitors can be formed by cutting. Compared with the manufacturing process of traditional multilayer ceramic capacitors, the present invention can simplify the manufacturing process and capacitor structure of capacitors, thereby reducing the difficulty of reducing the capacitor area and improving the product precision. Moreover, the high-temperature sintering process in the manufacturing process of traditional multilayer ceramic capacitors can be avoided, so as to achieve the purpose of reducing the manufacturing cost.

Claims

1. A manufacturing method of a capacitor unit, comprising: providing a substrate; forming an insulating layer on the substrate; forming a plurality of capacitor stack structures on the insulating layer, with an insulating spacer formed between two adjacent capacitor stack structures, and each capacitor stack structure having a first pad, a first conductive portion, a second pad, and a second conductive portion; performing a first cutting process on each insulating spacer to form a plurality of grooves exposing the first conductive portion and the second conductive portion of each capacitor stack structure; filling each groove with a metal material to form a plurality of metal spacers electrically connected to the first conductive portion and the second conductive portion; performing a second cutting process on each metal spacer to form a plurality of independent capacitor units, and forming a first metal sidewall and a second metal sidewall on opposite sides of each capacitor unit; wherein, in each capacitor unit, the first pad is electrically connected to the first conductive portion through the first metal sidewall to form a first electrode, and the second pad is electrically connected to the second conductive portion through the second metal sidewall to form a second electrode.

2. The manufacturing method of a capacitor unit according to claim 1, wherein, the substrate is a silicon substrate.

3. The manufacturing method of a capacitor unit according to claim 1, wherein, the step of forming a plurality of capacitor stack structures on the insulating layer further includes: forming a stack structure layer on the insulating layer, wherein the stack structure layer includes at least one interlayer conductive layer and at least one interlayer dielectric layer arranged alternately, and each interlayer conductive layer has a first conductive portion and a second conductive portion; and forming the first pad and the second pad on the stack structure layer.

4. The manufacturing method of a capacitor unit according to claim 3, wherein, the step of forming a stack structure layer on the insulating layer further includes: forming a first interlayer conductive layer having a first dielectric on the insulating layer, and defining the first conductive portion and the second conductive portion of the first interlayer conductive layer through the first dielectric; forming a first interlayer dielectric layer on the first interlayer conductive layer; forming a second interlayer conductive layer having a second dielectric on the first interlayer dielectric layer, and defining the first conductive portion and the second conductive portion of the second interlayer conductive layer through the second dielectric; forming an isolation layer on the second interlayer conductive layer; forming a first metal via and a second metal via arranged at intervals on the isolation layer; and forming a passivation layer to cover the interlayer dielectric layer and expose a part of the first metal via and the second metal via respectively, so as to form the first pad through the exposed part of the first metal via, and form the second pad through the exposed part of the second metal via.

5. The manufacturing method of a capacitor unit according to claim 1, wherein, the plurality of capacitor stack structures are arranged on the substrate at intervals in a matrix form along the X-axis direction and the Y-axis direction of the substrate; and wherein, the method further includes: providing an auxiliary layer under the substrate; Along the X-axis direction of the substrate, a first cutting process is performed on each of the insulating spacers with a first cutting depth and a first cutting width to form each of the grooves, wherein the first cutting depth extends from the top of each of the capacitor stack structures to the insulating layer, and the first cutting width is not less than the preset interval width of the insulating spacer; A filling process is performed on each of the grooves to form each of the metal spacers that is electrically connected to each of the capacitor stack structures; Along the X-axis direction of the substrate, a second cutting process is performed on each of the metal spacers with a second cutting depth and a second width to form a plurality of capacitor sets each including a plurality of the capacitor units, wherein the second cutting depth extends from the top of each of the capacitor stack structures to the auxiliary layer, and the second cutting width is less than the first cutting width to form the first metal sidewall and the second metal sidewall on opposite sides of each of the capacitor units along the Y-axis direction of the substrate; and Each of the capacitor sets is cut along the Y-axis direction of the substrate to form each of the capacitor units.

6. The method for manufacturing a capacitor unit according to claim 5, wherein, the auxiliary layer is a tape layer disposed under the substrate.

7. The method for manufacturing a capacitor unit according to claim 1, wherein, the first cutting process includes any one of a dicing wheel cutting method, a dry etching cutting method, and a laser scribing cutting method; the filling process includes any one of a screen printing method and an electroplating method; the second cutting process includes a dicing wheel cutting method.

8. A capacitor unit, characterized in that, the capacitor unit is for being welded to a printed circuit board and includes: a substrate; an insulating layer formed on the substrate; a capacitor stack structure formed on the insulating layer and having a first pad, a first conductive portion, a second pad, and a second conductive portion; a first metal sidewall and a second metal sidewall located on opposite sides of the capacitor stack structure; wherein the first pad is electrically connected to the first conductive portion through the first metal sidewall to form a first electrode, the second pad is electrically connected to the second conductive portion through the second metal sidewall to form a second electrode, and wherein, the capacitor unit is welded to the printed circuit board through the first pad and the second pad, wherein the first metal sidewall and the second metal sidewall are located on opposite sides of the capacitor stack structure along the Y-axis direction of the substrate, and the capacitor unit further includes a first insulating sidewall and a second insulating sidewall, the first insulating sidewall and the second insulating sidewall are located on opposite sides of the capacitor stack structure along the X-axis direction of the substrate, wherein the Y-axis direction is perpendicular to the X-axis direction, and the plane formed by the Y-axis and the X-axis is the extending plane of the substrate.

9. The capacitor unit according to claim 8, wherein, the substrate is made of a wafer.

10. A capacitor integrated structure, characterized in that, the capacitor integrated structure includes: a wafer; a plurality of capacitor stack structures, each of the capacitor stack structures is disposed on the wafer at intervals in a matrix form along the X-axis direction and the Y-axis direction of the wafer; a plurality of metal spacers disposed between two adjacent ones of the capacitor stack structures along the X-axis direction of the wafer; and A plurality of insulating spacers are disposed between two adjacent capacitor stack structures along the Y-axis direction of the wafer.

11. The capacitor integration structure according to claim 10, wherein, the capacitor integration structure is cut along the X-axis direction and the Y-axis direction respectively to form a plurality of independent capacitor units. Each of the capacitor units is used for being welded to a printed circuit board, and each of the capacitor units includes: a part of the wafer; the capacitor stack structure, which has a first pad, a first conductive part, a second pad and a second conductive part; a first metal sidewall and a second metal sidewall, which are formed on opposite sides of the capacitor stack structure by cutting the metal spacer; and a first insulating sidewall and a second insulating sidewall, which are formed on opposite sides of the capacitor stack structure by cutting the insulating spacer; wherein, the first pad is electrically connected to the first conductive part through the first metal sidewall to form a first electrode, and the second pad is electrically connected to the second conductive part through the second metal sidewall to form a second electrode; and wherein, each of the capacitor units is welded to the printed circuit board through the first pad and the second pad.

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