An interface control circuit of digital-analog hybrid

Abstract

The application provides a digital-analog hybrid interface control circuit, which comprises a shared pin, a mode detection circuit for detecting whether bus transmission is started and outputting a mode judgment signal mode through an output end based on a detection result, and a pin logic circuit, an input end of which is connected with the output end of the mode detection circuit, and an output end of which is connected with the shared pin, wherein the pin logic circuit configures the shared pin as a data signal pin in a digital mode or an analog signal pin in an analog mode based on the mode judgment signal mode output by the mode detection circuit. Compared with the prior art, the application can make the same pin undertake two functions of a data signal pin in a digital mode or an analog signal pin in an analog mode.

Description

[0001] The present application relates to the technical field of chip design, and in particular to a digital-analog mixed interface control circuit.

[0002] In current mixed chip design, the number of required pins is increasingly less, and the demand for integrated interface circuit of pad (i.e. pin or lead) is enhanced. The existing method is to increase a dedicated pin in the internal chip for analog signal output of the circuit and another dedicated pin for digital circuit input and output. This increases the chip layout area, package size and pin number, and is very costly.

[0003] Therefore, there is an urgent need to provide a new technical solution to solve the above problems.

[0004] One of the purposes of the present application is to provide a digital-analog mixed interface control circuit which can make the same pin assume the functions of a data signal pin in digital mode or an analog signal pin in analog mode.

[0005] According to one aspect of the present application, a digital-analog mixed interface control circuit is provided, which comprises a shared pin, a mode detection circuit for detecting whether bus transmission is started and outputting a mode judgment signal mode through its output end based on the detection result, and a pin logic circuit whose input end is connected to the output end of the mode detection circuit and whose output end is connected to the shared pin. The pin logic circuit configures the shared pin as a data signal pin in digital mode or an analog signal pin in analog mode based on the mode judgment signal mode output by the mode detection circuit.

[0006] Further, when it is detected that bus transmission has started, the mode detection circuit outputs a first logic level of the mode judgment signal mode; otherwise, the mode detection circuit outputs a second logic level of the mode judgment signal mode; when the mode judgment signal mode is the first logic level, the pin logic circuit configures the shared pin as a data signal pin in digital mode; and when the mode judgment signal mode is the second logic level, the pin logic circuit configures the shared pin as an analog signal pin in analog mode.

[0007] Further, the bus transmission is I2C bus transmission; the input end of the mode detection circuit is connected to a serial clock line pin; and the mode detection circuit detects whether the bus transmission is started by judging whether a predetermined number of clock signals arrive at the serial clock line pin within a predetermined time length. ​​​

[0008] Further, the digital-analog mixed interface control circuit further comprises a first resistor R1, and the serial clock line pin is connected to the power supply end VDDIO through the resistor R1.

[0009] Further, the digital-analog mixed interface control circuit further comprises a second resistor R2, and the shared pin is a serial data line pin; the shared pin is connected to the power supply end VDDIO through the resistor R1.

[0010] Further, the mode detection circuit comprises: a clock detector for detecting whether the serial clock line pin has a clock pulse, and outputting a digital mode start signal start through an output end based on a detection result; when the serial clock line pin has a clock pulse, the clock detector outputs a first logic level of the digital mode start signal start; otherwise, the clock detector outputs a second logic level of the digital mode start signal start; and a mode detection unit, an enable end of which is connected to the output end of the clock detector; when the digital mode start signal start is the second logic level, the mode detection unit is disabled; when the digital mode start signal start is the first logic level, the mode detection unit is enabled; at this time, the mode detection unit is used for judging whether a predetermined number of clock signals arrive at the serial clock line pin within a predetermined time length, and outputting the mode judgment signal mode through an output end based on a judgment result.

[0011] Further, when a predetermined number of clock signals arrive at the SCL pin within a predetermined time length, it indicates that the I2C bus transmission is detected to have been started, and the mode detection unit outputs a first logic level of the mode judgment signal mode; otherwise, the mode detection unit outputs a second logic level of the mode judgment signal mode.

[0012] Further, the mode detection unit comprises: a time length generator, an enable terminal of which is connected to an output terminal of the clock detector, when the digital mode start signal start is the second logic level, the time length generator is disabled, when the digital mode start signal start is the first logic level, the time length generator is enabled, at this time, the time length generator starts timing, and outputs the first logic level of the time length signal tims through its output terminal when the predetermined time length arrives, otherwise, the time length generator outputs the second logic level of the time length signal tims through its output terminal; a clock counter, an enable terminal of which is connected to the output terminal of the clock detector, and a first input terminal of which is connected to the serial clock line pin, when the digital mode start signal start is the second logic level, the clock counter is disabled, when the digital mode start signal start is the first logic level, the clock counter is enabled, at this time, the clock counter counts the clock number of the serial clock line pin, and outputs the first logic level of the count signal counter through its output terminal when the count value reaches the predetermined number, otherwise, the clock counter outputs the second logic level of the count signal counter through its output terminal; a mode judging unit, a first input terminal of which is connected to the output terminal of the time length generator, and a second input terminal of which is connected to the output terminal of the clock counter, the mode judging unit judges whether the predetermined number of clock signals of the SCL pin arrive within the predetermined time length based on the time length signal tims and the count signal counter, and outputs the mode judging signal mode through its output terminal based on the judging result.

[0013] Further, a second input terminal of the clock counter is connected to the output terminal of the time length generator.

[0014] When the time length generator outputs the first logic level of the time length signal tims through its output terminal when the predetermined time length arrives, the clock counter is reset or cleared.

[0015] Further, the predetermined time length is 1 millisecond, and the predetermined number is 8.

[0016] Further, the pin logic circuit configures the shared pin as the data input and output pin in the digital mode or the analog signal output pin in the analog mode based on the mode judging signal mode output by the mode detection circuit.

[0017] Compared with the prior art, the application can make the same pin undertake the two functions of the data signal pin in the digital mode or the analog signal pin in the analog mode, thereby reducing the pin number, saving the chip area and manufacturing cost, saving the packaging and testing cost, and greatly reducing the total cost of the final product. BRIEF DESCRIPTION OF DRAWINGS

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0019] Figure 1 This is a structural block diagram of a mixed-signal interface control circuit in one embodiment of the present invention;

[0020] Figure 2 For example, in one embodiment of the present invention Figure 1 The timing diagram shown is for the clock signal of the SCL pin and the counter signal output by the clock counter.

Detailed Implementation Methods

[0021] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the invention. The phrase "in one embodiment" appearing in different places throughout this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that excludes other embodiments. Unless otherwise specified, the terms "connected," "linked," and "connected" used herein to indicate electrical connection refer to direct or indirect electrical connection.

[0023] In the description of this invention, it should be understood that the terms "upper," "lower," "left," "right," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0024] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," "fixing," and "coupling" should be interpreted broadly; for example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0025] Please refer to Figure 1 As shown, it is a structural block diagram of the mixed-signal interface control circuit of the present invention in one embodiment. Figure 1 The mixed-signal interface control circuit shown includes a mode detection circuit 110, a pin logic circuit 120, and an SDA pin (which may also be referred to as a shared pin).

[0026] The mode detection circuit 110 is used to detect whether bus transmission (or digital mode) has started, and outputs a mode judgment signal mode through its output terminal based on the detection result. When it is detected that bus transmission (or digital mode) has started, the mode detection circuit 110 outputs the first logic level of the mode judgment signal mode; otherwise, the mode detection circuit 110 outputs the second logic level of the mode judgment signal mode.

[0027] The input of the pin logic circuit 120 is connected to the output of the mode detection circuit 110, and its output is connected to the SDA pin (which can also be called the shared pin). The pin logic circuit 120 configures the function of the SDA pin (which can also be called the shared pin) based on the mode judgment signal mode output by the mode detection circuit 110. When the mode judgment signal mode is at the first logic level (i.e., when bus transmission is detected or digital mode has been started), the pin logic circuit 120 configures the SDA pin as the data signal pin in digital mode; when the mode judgment signal mode is at the second logic level (i.e., when bus transmission is detected or digital mode has not been started), the pin logic circuit 120 configures the SDA pin as the analog signal VOUT pin in analog mode.

[0028] exist Figure 1 In the specific embodiment shown, the bus transmission is an I2C bus transmission. The I2C bus consists of a serial data line SDA and a serial clock line SCL. The SCL pin is connected to the serial clock line SCL, and the SDA pin is connected to the serial data line SDA. Using the I2C communication protocol, the interface circuit is an open-drain output and requires a pull-up resistor connected to an external power supply VDDIO. Specifically, Figure 1The mixed-signal interface control circuit shown also includes a first resistor R1 and a second resistor R2. The input of the mode detection circuit 110 is connected to the SCL (serial clock line) pin. The mode detection circuit 110 detects whether I2C bus transmission (or I2C digital mode) has started by determining whether a predetermined number of clock signals arrive at the SCL pin within a predetermined time period. When a predetermined number of clock signals arrive at the SCL pin within the predetermined time period, it indicates that I2C bus transmission has been detected, and the mode detection circuit 110 outputs the first logic level of the module judgment signal mode; otherwise, the mode detection circuit 110 outputs the second logic level of the module judgment signal mode. The SCL pin is connected to the power supply (or external interface power supply) VDDIO via the first resistor R1; the SDA pin is connected to the power supply (or external interface power supply) VDDIO via the second resistor R2. In other words, this invention directly uses the SDA (serial data line) pin of the digital communication interface as a shared pin.

[0029] exist Figure 1 In the specific embodiment shown, the pattern detection circuit 110 includes a clock detector (or external clock detector) 112 and a pattern detection unit 114.

[0030] Clock detector 112 is used to detect whether there is a clock pulse (or level switching) on ​​the SCL pin, and outputs a digital mode start signal start through its output terminal based on the detection result. When a clock pulse is detected on the SCL pin, clock detector 112 outputs the first logic level of the digital mode start signal start; otherwise, clock detector 112 outputs the second logic level of the digital mode start signal start.

[0031] The enable terminal of the mode detection unit 114 is connected to the output terminal of the clock detector 112. When the digital mode start signal start is at the second logic level, the mode detection unit 114 does not work; when the digital mode start signal start is at the first logic level, the mode detection unit 114 is enabled to work. At this time, the mode detection unit 114 is used to determine whether a predetermined number of clock signals arrive at the SCL pin within a predetermined time period, and outputs the corresponding mode judgment signal mode through its output terminal based on the judgment result. When a predetermined number of clock signals arrive at the SCL pin within a predetermined time period, it indicates that the I2C bus transmission (or I2C digital mode) has been detected to have started, and the mode detection unit 114 outputs the first logic level of the module judgment signal mode; otherwise, the mode detection unit 114 outputs the second logic level of the module judgment signal mode.

[0032] exist Figure 1In the specific embodiment shown, the pattern detection unit 114 includes a duration generator 1142, a clock counter (or an external clock counter) 1144, and a pattern judgment unit 1146.

[0033] The enable terminal of the duration generator 1142 is connected to the output terminal of the clock detector 112. When the digital mode start signal start is at the second logic level, the duration generator 1142 does not work; when the digital mode start signal start is at the first logic level, the duration generator 1142 is enabled to work. At this time, the duration generator 1142 starts timing and outputs the duration signal tims at the first logic level through its output terminal after the predetermined duration is reached. Otherwise, the duration generator 1142 outputs the duration signal tims at the second logic level through its output terminal.

[0034] The enable terminal of clock counter 1144 is connected to the output terminal of clock detector 112, its first input terminal is connected to the SCL pin, and its second input terminal is connected to the output terminal of duration generator 1142. When the digital mode start signal start is at the second logic level, clock counter 1144 does not work; when the digital mode start signal start is at the first logic level, clock counter 1144 is enabled to work. At this time, clock counter 1144 counts the number of clock cycles on the SCL pin, and after the count value reaches a predetermined number, it outputs the first logic level of the count signal counter through its output terminal. Otherwise, clock counter 1144 outputs the second logic level of the count signal counter. When duration generator 1142 outputs the first logic level of the duration signal tims through its output terminal after the predetermined duration has elapsed, clock counter 1144 is reset or cleared.

[0035] Please refer to Figure 2 As shown, this is an embodiment of the present invention. Figure 1 The timing diagram shown is for the clock signal of the SCL pin and the counter signal output by the clock counter 1144. Figure 2 In the embodiment shown, the predetermined number of clock signals arriving at the SCL pin within a predetermined time period is 8; the clock counter 1144 outputs a low level through its output terminal before the count value of the clock signal at the SCL pin reaches 8, and outputs a high level through its output terminal after the count value of the clock signal at the SCL pin reaches 8, that is, the first logic level of the counter signal is high and the second logic level of the counter signal is low.

[0036] The first input terminal of the mode judgment unit 1146 is connected to the output terminal of the duration generator 1142, and its second input terminal is connected to the output terminal of the clock counter 1144. Based on the duration signal tims output by the duration generator 1142 and the count signal counter output by the clock counter 1144, the mode judgment unit 1146 determines whether a predetermined number of clock signals have arrived at the SCL pin within a predetermined duration, and outputs the corresponding mode judgment signal mode through its output terminal based on the judgment result.

[0037] The following is based on Figure 2 Detailed introduction Figure 1 The operation of the mixed-signal interface control circuit shown in one embodiment is illustrated. In this embodiment, the duration generator 1142 is a 1-millisecond generator with a predetermined duration of 1 millisecond; in the clock counter 1144, the predetermined number of clock signals arriving at the SCL pin within the predetermined duration is 8.

[0038] When the I2C bus is idle (i.e., I2C bus transmission is not required or I2C digital mode is not required), the level of the SCL pin will always be high. At this time, the pin logic circuit 120 configures the SDA pin as the analog signal VOUT pin in analog mode (or the pin logic circuit 120 configures the SDA pin as the analog output mode).

[0039] If I2C bus transmission is started, the host will control SCL after generating a start signal. The SCL pin will be controlled by an external clock to generate 8 clock pulses. That is to say, the SCL pin will switch from high to low level, triggering the clock detector 112 to output the first logic level of the digital mode start signal start.

[0040] The duration generator 1142 and the clock counter 1144 start working when they receive the first logic level of the digital mode start signal start. The duration generator 1142 will output the first logic level of the duration signal tims after 1 millisecond (which is a predetermined duration) has elapsed. The clock counter 1144 counts the number of clock cycles on the SCL pin, and after the count value reaches 8 (which is a predetermined number), it outputs the first logic level of the count signal counter through its output terminal.

[0041] The mode determination unit 1146 determines whether eight clock signals have arrived at the SCL pin within one millisecond based on the duration signal tims output by the duration generator 1142 and the count signal counter output by the clock counter 1144. Based on the determination result, it outputs a mode determination signal mode. When eight clock signals arrive at the SCL pin within one millisecond, it indicates that I2C bus transmission (or I2C digital mode) has been detected, and the mode detection unit 114 outputs the first logic level of the mode determination signal; otherwise, the mode detection unit 114 outputs the second logic level of the mode determination signal.

[0042] The pin logic circuit 120 configures the SDA pin (which can also be called a shared pin) based on the mode judgment signal mode output by the mode detection circuit 110. When the module judges the signal mode to be at the first logic level, the pin logic circuit 120 configures the SDA pin as a data input / output pin in digital mode; when the module judges the signal mode to be at the second logic level, the pin logic circuit 120 configures the SDA pin as an output pin of the analog signal VOUT in analog mode.

[0043] It should be noted that the first logic level and the second logic level in the upper-level system are two logic states of the same signal. For example, if the module determines that the first logic level of the signal mode is high, its second logic level is low; or if the module determines that the first logic level of the signal mode is low, its second logic level is high.

[0044] In summary, this invention directly utilizes the SDA (Serial Data Line) pin of the digital communication interface. By determining whether a predetermined number of clock signals arrive at the SCL pin within a predetermined time period, a mode judgment signal (mode) is provided to determine the state of the SDA pin (or shared pin), thereby correctly configuring the SDA pin function. When the module determines that the mode signal is at the first logic level, it indicates that bus transmission has started, and the pin logic circuit 120 configures the SDA pin as a data signal pin in digital mode; otherwise, the pin logic circuit 120 configures the SDA pin as an analog signal VOUT pin in analog mode. In this way, a single pin can be used for data input / output in digital mode or output of the analog signal VOUT, thereby reducing the number of pins, saving chip area and manufacturing costs, as well as packaging and testing costs, resulting in a significant reduction in the final product cost.

[0045] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0046] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications and variations to the above embodiments within the scope of the present invention.

Claims

1. A mixed-signal interface control circuit, characterized in that, It includes: Shared pins; The mode detection circuit is used to detect whether bus transmission has started, and outputs a mode judgment signal (mode) through its output terminal based on the detection result. A pin logic circuit, the input of which is connected to the output of the mode detection circuit, and the output of which is connected to the shared pin, configures the shared pin as a data signal pin in digital mode or an analog signal pin in analog mode based on the mode judgment signal "mode" output by the mode detection circuit. When bus transmission is detected to have started, the mode detection circuit outputs the first logic level of the mode judgment signal mode; otherwise, the mode detection circuit outputs the second logic level of the mode judgment signal mode. When the mode determination signal `mode` is at a first logic level, the pin logic circuit configures the shared pin as a data signal pin in digital mode; when the mode determination signal `mode` is at a second logic level, the pin logic circuit configures the shared pin as an analog signal pin in analog mode. The bus transmission is an I2C bus transmission; The input terminal of the pattern detection circuit is connected to the serial clock line pin. The mode detection circuit detects whether the bus transmission has started by determining whether a predetermined number of clock signals arrive at the serial clock line pin within a predetermined time period. The pattern detection circuit includes: A clock detector is used to detect whether there is a clock pulse on the serial clock line pin, and outputs a digital mode start signal start through its output terminal based on the detection result. When a clock pulse is detected on the serial clock line pin, the clock detector outputs a first logic level of the digital mode start signal start; otherwise, the clock detector outputs a second logic level of the digital mode start signal start. The mode detection unit has its enable terminal connected to the output terminal of the clock detector. When the digital mode start signal start is at the second logic level, the mode detection unit is disabled; when the digital mode start signal start is at the first logic level, the mode detection unit is enabled. At this time, the mode detection unit is used to determine whether a predetermined number of clock signals have arrived at the serial clock line pin within a predetermined time period, and outputs the mode judgment signal mode through its output terminal based on the judgment result.

2. The mixed-signal interface control circuit according to claim 1, characterized in that, It also includes a first resistor R1, The serial clock line pin is connected to the power supply terminal VDDIO via the resistor R1.

3. The mixed-signal interface control circuit according to claim 2, characterized in that, It also includes a second resistor R2, The shared pin is a serial data line pin; The shared pin is connected to the power supply terminal VDDIO via the resistor R2.

4. The mixed-signal interface control circuit according to claim 1, characterized in that, When a predetermined number of clock signals arrive at the SCL pin within a predetermined time period, it indicates that the I2C bus transmission has been started, and the mode detection unit outputs the first logic level of the mode judgment signal mode. Otherwise, the mode detection unit outputs the second logic level of the mode judgment signal mode.

5. The mixed-signal interface control circuit according to claim 4, characterized in that, The pattern detection unit includes: A duration generator, whose enable terminal is connected to the output terminal of the clock detector, disables the duration generator when the digital mode start signal start is at the second logic level; enables the duration generator when the digital mode start signal start is at the first logic level, at which time the duration generator starts timing and outputs the duration signal tims at the first logic level through its output terminal after the predetermined duration has elapsed; otherwise, the duration generator outputs the duration signal tims at the second logic level through its output terminal. A clock counter, whose enable terminal is connected to the output terminal of the clock detector and whose first input terminal is connected to the serial clock line pin, disables the clock counter when the digital mode start signal start is at the second logic level; enables the clock counter when the digital mode start signal start is at the first logic level, in which case the clock counter counts the number of clock cycles on the serial clock line pin, and outputs the first logic level of the counting signal counter through its output terminal after the count value reaches a predetermined number; otherwise, the clock counter outputs the second logic level of the counting signal counter. The mode determination unit has its first input terminal connected to the output terminal of the duration generator and its second input terminal connected to the output terminal of the clock counter. Based on the duration signal tims and the counting signal counter, the mode determination unit determines whether a predetermined number of clock signals arrive at the SCL pin within a predetermined duration, and outputs a mode determination signal mode through its output terminal based on the determination result.

6. The mixed-signal interface control circuit according to claim 5, characterized in that, The second input terminal of the clock counter is connected to the output terminal of the duration generator; When the duration generator outputs the first logic level of the duration signal tims through its output terminal after the predetermined duration has elapsed, the clock counter is reset or cleared.

7. The mixed-signal interface control circuit according to claim 1, characterized in that, The predetermined duration is 1 millisecond; the predetermined number is 8.

8. The mixed-signal interface control circuit according to claim 1, characterized in that, The pin logic circuit configures the shared pin as a data input / output pin in digital mode or an analog signal output pin in analog mode based on the mode judgment signal "mode" output by the mode detection circuit.

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