Photoelectric conversion device, A / D converter, and equipment

Abstract

The present disclosure relates to a photoelectric conversion device, an A / D converter, and equipment. The photoelectric conversion device includes a light receiving circuit configured to convert light into an electrical signal, a readout circuit configured to read out an analog signal corresponding to the electrical signal, a ΔΣ A / D converter configured to convert the analog signal into a digital signal, and a control circuit configured to change the gain of the photoelectric conversion device according to a change in the drive mode of the photoelectric conversion device. The analog signal read out by the readout circuit is an analog current signal. The readout circuit includes a variable resistor on a signal path for supplying the analog current signal to the ΔΣ A / D converter. The control circuit changes the gain of the photoelectric conversion device by changing the resistance value of the variable resistor.

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device, an A / D converter, and equipment. Background Art

[0002] Various techniques have been proposed to widen the range of an input signal in a photoelectric conversion device. According to International Publication No. 2019 / 069614, sample-and-hold circuits for separately holding a noise signal and a data signal are each composed of a plurality of capacitive elements, and the number of capacitive elements for holding each signal is changed to change the gain. Summary of the Invention

[0003] According to some embodiments, there is provided a photoelectric conversion device including: a light receiving circuit configured to convert light into an electrical signal; a readout circuit configured to read out an analog signal corresponding to the electrical signal; a ΔΣ A / D converter configured to convert the analog signal into a digital signal; and a control circuit configured to change the gain of the photoelectric conversion device according to a change in a drive mode of the photoelectric conversion device, wherein the analog signal read out by the readout circuit is an analog current signal, the readout circuit includes a variable resistor on a signal path for supplying the analog current signal to the ΔΣ A / D converter, and the control circuit changes the gain of the photoelectric conversion device by changing a resistance value of the variable resistor.

[0004] According to some other embodiments, there is provided a photoelectric conversion device including: a light receiving circuit configured to convert light into an electrical signal; a readout circuit configured to read out an analog signal corresponding to the electrical signal; a ΔΣ A / D converter configured to convert the analog signal into a digital signal; and a control circuit configured to change the gain of the photoelectric conversion device according to a change in a drive mode of the photoelectric conversion device, wherein the control circuit changes the gain of the photoelectric conversion device by changing settings of the ΔΣ A / D converter.

[0005] According to still some other embodiments, there is provided an A / D converter for converting an analog current signal into a digital signal, including: a subtractor configured to be supplied with the analog current signal; an integrator configured to integrate an output from the subtractor; a quantizer configured to quantize an integration result of the integrator; a decimation filter configured to perform a decimation process on an output from the quantizer; and a D / A converter configured to supply an analog current corresponding to the output from the quantizer to the subtractor so as to be subtracted from the analog current signal, wherein the D / A converter can change a value of the analog current supplied from the D / A converter to the subtractor with respect to the same output from the quantizer.

[0006] According to still other embodiments, there is provided a photoelectric conversion device including: a light receiving circuit configured to convert light into an electric signal; a readout circuit configured to read out an analog current signal corresponding to the electric signal; a ΔΣ A / D converter configured to convert the analog current signal into a digital signal; and a control circuit configured to change settings of the ΔΣ A / D converter, where the ΔΣ A / D converter includes a subtractor configured to be supplied with the analog current signal, an integrator configured to integrate an output from the subtractor, a quantizer configured to quantize an integration result of the integrator, a decimation filter configured to perform a decimation process on an output from the quantizer, and a D / A converter configured to supply an analog current corresponding to an output from the quantizer to the subtractor to be subtracted from the analog current signal, the integrator includes a variable capacitor configured to be charged with the output from the subtractor to integrate the output, and changing the settings of the ΔΣ A / D converter includes changing a capacitance value of the variable capacitor.

[0007] Other features of the present invention will become clear from the following description of exemplary embodiments (with reference to the accompanying drawings). BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram illustrating an example of an arrangement of a photoelectric conversion device 100 according to some embodiments;

[0009] Figure 2 is a circuit diagram illustrating an example of a circuit arrangement of a pixel circuit 111 according to some embodiments;

[0010] Figure 3 is a circuit diagram illustrating an example of a circuit arrangement of a readout circuit 121 according to some embodiments;

[0011] Figure 4A and Figure 4B are block diagrams each illustrating an example of a circuit arrangement of an A / D converter 131 according to some embodiments;

[0012] Figure 5A and Figure 5B are circuit diagrams each illustrating an example of a circuit arrangement of a ΔΣ modulator according to some embodiments;

[0013] Figure 6 is a circuit diagram illustrating an example of a circuit arrangement of a current generation circuit according to some embodiments;

[0014] Figure 7 is a circuit diagram illustrating another example of a circuit arrangement of a ΔΣ modulator according to some embodiments;

[0015] Figure 8is a view showing an example of the arrangement of the photoelectric conversion device 100 according to some embodiments;

[0016] Figure 9 is a circuit diagram showing an example of the circuit arrangement of the pixel circuit 111 according to some embodiments;

[0017] Figure 10 is a circuit diagram showing an example of the circuit arrangement of the readout circuit 121 according to some embodiments;

[0018] Figure 11A and Figure 11B are views each showing an example of the circuit arrangement of the A / D converter 131 according to some embodiments;

[0019] Figure 12A and Figure 12B are circuit diagrams each showing an example of the circuit arrangement of the ΔΣ modulator according to some embodiments;

[0020] Figure 13 is a circuit diagram showing an example of the circuit arrangement of the current generation circuit according to some embodiments;

[0021] Figure 14 is a circuit diagram showing an example of the circuit arrangement of the variable capacitor according to some embodiments; and

[0022] Figures 15A to 15C is a view showing an example of the arrangement of the equipment according to some embodiments. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments will be described in detail with reference to the drawings. Note that the following embodiments are not intended to limit the scope of the claimed invention. Multiple features are described in the embodiments, but the invention is not limited to the invention that requires all these features, and multiple such features can be appropriately combined. In addition, in the drawings, the same reference numerals are given to the same or similar configurations, and repeated descriptions thereof are omitted.

[0024] (First Embodiment)

[0025] As in International Publication No. 2019 / 069614, an arrangement for changing the gain by changing the number of capacitance elements of a sample-and-hold circuit requires many capacitance elements, thereby increasing the chip size. This embodiment provides a technique that enables changing the gain of the photoelectric conversion device while suppressing an increase in chip size.

[0026] Embodiments in which the photoelectric conversion device 100 is used for image capture will be mainly described below. In this case, the photoelectric conversion device 100 can be used as an image sensor for generating images. In addition, other examples of the photoelectric conversion device 100 are distance measurement elements (sensors for distance measurement using focus detection or TOF (Time of Flight)), photometry elements (sensors for measuring the amount of incident light, etc.), and LiDAR (Light Detection and Ranging) sensors. The embodiments described below are applicable to any photoelectric conversion device.

[0027] Reference will be made to Figure 1 an example of the arrangement of the photoelectric conversion device 100 according to some embodiments will be described with reference to the block diagram shown in Figure 1 In the example shown in

[0028] the photoelectric conversion device 100 includes a pixel unit 110, a readout unit 120, an A / D conversion unit 130, a horizontal scan circuit 140, a signal processing circuit 150, an output circuit 160, a vertical scan circuit 170, and a timing control circuit 180. Figure 1 The pixel unit 110 includes a plurality of pixel circuits 111 arranged in a two-dimensional array, a plurality of driving lines 112 provided for each pixel row, and a plurality of signal lines 113 provided for each pixel column. A pixel row indicates a plurality of pixel circuits 111 arranged in the Figure 1 horizontal direction in

[0029] The pixel circuit 111 converts incident light into an electrical signal. Therefore, the pixel circuit 111 can also be referred to as a light receiving circuit. The vertical scan circuit 170 supplies a control signal to each of the plurality of pixel circuits 111 via a corresponding one of the driving lines 112. The readout unit 120 reads out the electrical signal from the pixel circuit 111 supplied with the control signal at an effective level via a corresponding one of the signal lines 113.

[0030] The readout unit 120 includes a plurality of readout circuits 121 provided for the signal lines 113 and a control circuit 122 for controlling the operation of the readout circuits 121. Each readout circuit 121 reads out an analog signal corresponding to the electrical signal generated by the pixel circuit 111 and supplies it to the A / D conversion unit 130.

[0031] The A / D conversion unit 130 includes a plurality of A / D converters 131 provided for the signal lines 113 and a control circuit 132 for controlling the operation of the A / D converters 131. Each A / D converter 131 converts the analog signal supplied from the readout circuit 121 into a digital signal. In the following description, each A / D converter 131 is a Δ∑ A / D converter.

[0032] The horizontal scanning circuit 140 sequentially reads out digital signals from the plurality of A / D converters 131 and supplies them to the signal processing circuit 150. The photoelectric conversion device 100 may include a memory circuit for storing digital signals between the A / D conversion unit 130 and the horizontal scanning circuit 140. The signal processing circuit 150 processes the digital signals corresponding to the electrical signals generated in each pixel circuit 111. The signal processing circuit 150 may perform, for example, correction processing, complement processing, etc. on the digital signals.

[0033] The digital signals processed by the signal processing circuit 150 are output from the output circuit 160 to an external device 190 outside the photoelectric conversion device 100. The external device 190 may be, for example, a control device of equipment incorporating the photoelectric conversion device 100. The timing control circuit 180 controls the overall operation of the photoelectric conversion device 100 by supplying control signals to each circuit of the photoelectric conversion device 100. For example, the timing control circuit 180 may change the driving mode of the photoelectric conversion device 100 according to an instruction from the external device 190. The timing control circuit 180 changes the gain of the photoelectric conversion device 100 according to the change in the driving mode of the photoelectric conversion device 100. A detailed example of the gain change method will be described later. The change in the driving mode may include a change between a still image capture mode and a moving image capture mode of shooting using the photoelectric conversion device 100. The change in the driving mode may include a change in the sensitivity of shooting using the photoelectric conversion device 100. The change in the driving mode may include a change in the A / D conversion resolution of the A / D converter 131. The change in the driving mode may include a change in the frame rate of moving image capture using the photoelectric conversion device 100. The change in the driving mode may include at least one of the above examples.

[0034] Reference will be made to Figure 2 the circuit diagrams shown in Figure 2 to describe a detailed example of the circuit arrangement of the pixel circuit 111. The pixel circuit 111 may have any arrangement for converting incident light into an electrical signal. Examples will be described with reference to

[0035] but the pixel circuit 111 may have another arrangement. Figure 2 In the example described with reference to Figure 2 the pixel circuit 111 includes a photoelectric conversion element 201, a transfer transistor 202, a reset transistor 203, an amplification transistor 204, and a selection transistor 205. In the example shown in

[0036] The photoelectric conversion element 201 converts incident light into charges and accumulates them. The photoelectric conversion element 201 can be, for example, a photodiode or a phototransistor. The photoelectric conversion element 201 can be a CMOS (complementary metal oxide semiconductor) sensor. Alternatively, the photoelectric conversion element 201 can be a SPAD (single photon avalanche diode) sensor.

[0037] The photoelectric conversion element 201 is connected to the floating diffusion 206 via the transfer transistor 202. The vertical scan circuit 170 supplies a control signal PTX to the gate of the transfer transistor 202. When the control signal PTX is set to the effective level, the transfer transistor 202 is set to the conducting state. The signal charges accumulated in the photoelectric conversion element 201 are accordingly transferred to the floating diffusion 206.

[0038] The floating diffusion 206 is also connected to the gate of the amplification transistor 204. One main electrode of the amplification transistor 204 is connected to the signal line 113 via the selection transistor 205. The other main electrode of the amplification transistor 204 is connected to the supply potential VDD. The vertical scan circuit 170 supplies a control signal PSEL to the gate of the selection transistor 205. When the control signal PSEL is set to the effective level, the selection transistor 205 is set to the conducting state. One main electrode of the amplification transistor 204 is accordingly connected to the current source of the readout circuit 121. This causes the amplification transistor 204 to operate as a source follower, and the signal corresponding to the potential of the floating diffusion 206 is read out into the signal line 113.

[0039] The reset transistor 203 is connected between the floating diffusion 206 and the supply potential VDD. The vertical scan circuit 170 supplies a control signal PRES to the gate of the reset transistor 203. When the control signal PRES is set to the effective level, the reset transistor 203 is set to the conducting state. The potential of the floating diffusion 206 is accordingly reset to the supply potential VDD.

[0040] Refer to Figure 3 the circuit diagram shown in to describe a detailed example of the circuit arrangement of the readout circuit 121. The readout circuit 121 can have any arrangement for reading out the electrical signal generated in the pixel circuit 111. Refer to Figure 3 the example for description, but the readout circuit 121 can have another arrangement.

[0041] In the example described in Figure 3 the readout circuit 121 includes current sources 301, 308, and 309, sample-and-hold circuits 302 and 303, amplifiers 304 and 306, transistors 305 and 307, and a resistor 312.

[0042] The current source 301 supplies a bias current to the pixel circuit 111 (more specifically, the amplifying transistor 204). Each of the sample-and-hold circuits 302 and 303 holds the output voltage from the pixel circuit 111. The timing control circuit 180 controls the pixel circuit 111 to output each of an electrical signal (hereinafter referred to as a noise signal) when the photoelectric conversion element 201 is in a reset state and an electrical signal corresponding to incident light (hereinafter referred to as a data signal). According to an instruction from the timing control circuit 180, the control circuit 122 controls the readout circuit 121 to read out the noise signal and hold it in the sample-and-hold circuit 302. Further, according to an instruction from the timing control circuit 180, the control circuit 122 controls the readout circuit 121 to read out the data signal from the pixel circuit 111 and hold it in the sample-and-hold circuit 303.

[0043] The amplifier 304 and the transistor 305 function as a source follower. The current source 308 supplies a bias current to this source follower. The potential of the node 310 between the current source 308 and the transistor 305 has a value corresponding to the voltage (noise signal) held in the sample-and-hold circuit 302.

[0044] The amplifier 306 and the transistor 307 function as a source follower. The current source 309 supplies a bias current to this source follower. The potential of the node 311 between the current source 309 and the transistor 307 has a value corresponding to the voltage (data signal) held in the sample-and-hold circuit 303.

[0045] The resistor 312 is connected between the nodes 310 and 311. Therefore, the voltage applied to the resistor 312 is the potential difference between the nodes 310 and 311. Accordingly, the readout circuit 121 supplies an analog current signal corresponding to the difference between the data signal and the noise signal to the A / D converter 131. The readout circuit 121 has a function of performing correlated double sampling (CDS).

[0046] In some embodiments, resistor 312 may be a variable resistor. Resistor 312 is located on the signal path for supplying an analog current signal from readout circuit 121 to A / D converter 131. Thus, control circuit 122 can change the value of the analog current signal to A / D converter 131 relative to the same data signal by changing the resistance value of resistor 312. More specifically, by decreasing the resistance value of resistor 312, the value of the analog current signal to A / D converter 131 increases relative to the same data signal, resulting in a large gain of photoelectric conversion device 100. Conversely, by increasing the resistance value of resistor 312, the value of the analog current signal to A / D converter 131 decreases relative to the same data signal, resulting in a small gain of photoelectric conversion device 100. In this way, control circuit 122 can change the gain of photoelectric conversion device 100 by changing the resistance value of resistor 312.

[0047] Reference will be made to Figure 4A and Figure 4B each of the block diagrams shown in to describe a detailed example of the circuit arrangement of A / D converter 131. A / D converter 131 is a ΔΣ A / D converter. A / D converter 131 converts an input analog signal into a digital signal. Figure 4A The A / D converter 131 shown in includes a first-order ΔΣ modulator 404 and a decimation filter 405. Figure 4B The A / D converter 131 shown in includes a second-order ΔΣ modulator 407 and a decimation filter 405. Alternatively, A / D converter 131 may include a third-order or higher-order ΔΣ modulator. By using a higher-order ΔΣ modulator, the noise shaping effect is improved. Each of ΔΣ modulators 404 and 407 converts an input analog signal into a string of 1-bit digital signals. Decimation filter 405 performs a decimation process (sparse process) on the string of 1-bit digital signals.

[0048] For example, decimation filter 405 generates a digital signal corresponding to the ratio of the time when 1 is obtained in the string of 1-bit digital signals relative to a predetermined time length. ΔΣ modulator 404 may convert an input analog signal into a string of two or more bits of digital signals.

[0049] As Figure 4A shown in, the first-order ΔΣ modulator 404 includes a subtracter 401, an integrator 402, a quantizer 403, and a D / A converter (DAC) 406. The input of A / D converter 131 (i.e., the analog signal from readout circuit 121) is supplied to subtracter 401. In addition, the analog signal of D / A converter (DAC) 406 is supplied to subtracter 401.

[0050] The subtractor 401 supplies the difference between the analog signal from the readout circuit 121 and the analog signal from the D / A converter 406 to the integrator 402.

[0051] The integrator 402 integrates the output from the subtractor 401. The quantizer 403 quantizes the integration result of the integrator 402. For example, the quantizer 403 generates a 1-bit digital signal string based on the integration result and supplies it to the decimation filter 405. The output from the quantizer 403 is the output from the ΔΣ modulator 404.

[0052] The output from the quantizer 403 is also supplied to the D / A converter 406. The D / A converter 406 generates a signal corresponding to the output of the quantizer 403 and supplies it to the subtractor 401. As described above, the signal supplied to the subtractor 401 from the D / A converter 406 is subtracted from the analog signal supplied from the readout circuit 121.

[0053] As Figure 4B shown, the second-order ΔΣ modulator 407 includes a subtractor 401, a subtractor 408, an integrator 402, an integrator 409, a quantizer 403, a D / A converter (DAC) 406, and a D / A converter (DAC) 410. The arrangement of the subtractor 401, the integrator 402, the quantizer 403, and the D / A converter (DAC) 406 is the same as that in the first-order ΔΣ modulator 404.

[0054] The output from the integrator 402 is supplied to the subtractor 408. In addition, the analog signal of the D / A converter 410 is supplied to the subtractor 408. The subtractor 408 supplies the difference between the analog signal from the integrator 402 and the analog signal from the D / A converter 410 to the integrator 409. The integrator 409 integrates the output from the subtractor 408. The quantizer 403 quantizes the integration result of the integrator 409.

[0055] The output from the quantizer 403 is also supplied to the D / A converter 410. The D / A converter 410 generates a signal corresponding to the output from the quantizer 403 and supplies it to the subtractor 408. As described above, the signal supplied to the subtractor 408 from the D / A converter 410 is subtracted from the analog signal supplied from the integrator 402.

[0056] Examples of the circuit arrangements of the ΔΣ modulators 404 and 407 when the input to the A / D converter 131 is an analog current signal will be described with reference to Figure 5A and Figure 5B respectively. Figure 5A An example of the circuit arrangement of the first-order ΔΣ modulator 404 is shown, and Figure 5B an example of the circuit arrangement of the second-order ΔΣ modulator 407 is shown.

[0057] First, an example of the circuit arrangement of the first-order ΔΣ modulator 404 will be described. The subtractor 401 is constituted by a node 501 connected to the readout circuit 121, the D / A converter 406, and the integrator 402. An analog current signal supplied from the readout circuit 121 to the node 501 is subtracted from the analog current from the D / A converter 406, and the resulting current is supplied to the integrator 402.

[0058] The integrator 402 is constituted by a capacitor 502. The capacitor 502 is charged by the output from the subtractor 401 to integrate the output. The voltage of the capacitor 502 is supplied to the quantizer 403. The quantizer 403 is constituted by a comparator 503. The comparator 503 outputs a high-level or low-level voltage according to the value of the voltage supplied from the integrator 402.

[0059] The D / A converter 406 is constituted by a switching element 504 and a current generation circuit 505. The current generation circuit 505 generates an analog current supplied to the subtractor 401. The switching element 504 is located on the signal path between the subtractor 401 and the current generation circuit 505. The ON / OFF of the switching element 504 is switched by the output from the quantizer 403. If the output from the quantizer 403 is high level, then the switching element 504 is turned on, so that the current from the current generation circuit 505 is supplied to the subtractor 401. On the other hand, if the output from the quantizer 403 is low level, then the switching element 504 is turned off, so that no current is supplied from the current generation circuit 505 to the subtractor 401. In this way, the value of the analog current supplied from the D / A converter 406 to the subtractor 401 changes according to the output from the quantizer 403.

[0060] Next, an example of the circuit arrangement of the second-order ΔΣ modulator 407 will be described. The ΔΣ modulator 407 includes subtractors 401 and 408, integrators 402 and 409, a Gm amplifier 506, a quantizer 403, and D / A converters 406 and 410. The circuit arrangements of the subtractor 401, the integrator 402, the quantizer 403, and the D / A converter 406 are the same as those in the first-order ΔΣ modulator 404. The Gm amplifier 506 is an amplifier, and converts the analog voltage signal supplied from the integrator 402 into an analog current signal and supplies it to the subtractor 408. The integrator 402 supplies an analog voltage signal to the inverting input terminal of the Gm amplifier 506, and the control circuit 132 supplies a reference voltage Vref to the non-inverting input terminal of the Gm amplifier 506.

[0061] The subtractor 408 is constituted by a node 507 connected to the Gm amplifier 506, the D / A converter 410, and the integrator 409. An analog current signal supplied from the Gm amplifier 506 to the node 507 has an analog current from the D / A converter 410 subtracted therefrom, and the resulting current is supplied to the integrator 409. The integrator 409 is constituted by a capacitor 508. The capacitor 508 is charged by the output from the Gm amplifier 506 to integrate the output. The voltage of the capacitor 508 is supplied to the quantizer 403.

[0062] The D / A converter 410 is constituted by a switching element 509 and a current generation circuit 510. The current generation circuit 510 generates an analog current supplied to the subtractor 408. The switching element 509 is located on the signal path between the subtractor 408 and the current generation circuit 510. The ON / OFF of the switching element 509 is switched by the output from the quantizer 403. If the output from the quantizer 403 is at a high level, then the switching element 509 is turned on, thereby supplying the current from the current generation circuit 510 to the subtractor 408. On the other hand, if the output from the quantizer 403 is at a low level, then the switching element 509 is turned off, so that no current is supplied from the current generation circuit 510 to the subtractor 408. In this way, the value of the analog current supplied from the D / A converter 416 to the subtractor 408 changes according to the output from the quantizer 403.

[0063] Refer to Figure 6 the circuit diagram shown in to describe a detailed example of the circuit arrangement of the current generation circuit 505. The current generation circuit 505 can have any arrangement capable of changing the amount of current to be generated. Refer to Figure 6 the example for description, but the current generation circuit 505 can have another arrangement. The current generation circuit 510 can have the same circuit arrangement as the current generation circuit 505.

[0064] The current generation circuit 505 includes transistors 601 and 602, switching elements 603 and 604, and a capacitor 605. The transistor 601 is connected between the switching element 504 and the ground. The transistor 602 and the switching element 603 are connected in series between the switching element 504 and the ground. The control circuit 132 supplies a bias voltage Vbias to the gates of the transistors 601 and 602 via the switching element 604. The bias voltage Vbias is also supplied to the capacitor 605.

[0065] The switching element 604 and the capacitor 605 constitute a sample-and-hold circuit. When the switching element 604 is turned off, the bias voltage Vbias held in the capacitor 605 is supplied to the gates of the transistors 601 and 602.

[0066] Each of the transistors 601 and 602 serves as a current source that generates a current corresponding to the bias voltage Vbias supplied to the gate. The current generated by the transistor 601 is supplied to the switching element 504. When the switching element 603 is ON, the current generated by the transistor 602 is supplied to the switching element 504. When the switching element 603 is OFF, the current generated by the transistor 602 is not supplied to the switching element 504. The ON / OFF of each of the switching elements 603 and 604 is controlled by a control signal supplied from the control circuit 132.

[0067] As described above, the value of the analog current supplied from the current generation circuit 505 to the switching element 504 changes according to the ON / OFF of the switching element 603. More specifically, when the switching element 603 is ON, a larger value of current is supplied compared to the case where the switching element 603 is OFF. By changing the value of the bias voltage Vbias, the value of the current generated by each of the transistors 601 and 602 can also be changed. By providing the current generation circuit 505, the D / A converter 406 can change the value of the analog current supplied from the D / A converter 406 to the subtractor 401 with respect to the same output (a high level in the above example) from the quantizer 403.

[0068] A reference will be made Figure 7 to an example of the circuit arrangement of the first-order ΔΣ modulator 404 when the input of the A / D converter 131 is an analog voltage signal. The subtractor 401 is constituted by a capacitor 701. One terminal of the capacitor 701 is connected to the readout circuit 121 and the D / A converter 406. The other terminal of the capacitor 701 is connected to the integrator 402. An analog voltage signal supplied from the readout circuit 121 to the capacitor 701 is subtracted from the analog voltage from the D / A converter 406, and the resulting voltage is supplied to the integrator 402.

[0069] The integrator 402 is constituted by an operational amplifier 702 and capacitors 703 and 704. The capacitor 703 is connected between the input terminal and the output terminal of the operational amplifier 702. The capacitor 704 is connected between the operational amplifier 702 and the subtractor 401. The quantizer 403 is constituted by a comparator 705. The comparator 705 outputs a high-level or low-level voltage according to the value of the voltage supplied from the integrator 402.

[0070] The D / A converter 406 is composed of the switching element 706. The control circuit 132 supplies the voltage VH and VL to the switching element 706. The voltage VH is higher than the voltage VL. Based on the output from the quantizer 403, the switching element 706 supplies one of the voltage VH and VL to the subtractor 401. As described above, the value of the analog voltage supplied from the D / A converter 406 to the subtractor 401 changes according to the output from the quantizer 403. The control circuit 132 may supply the voltage VH and VL supplied from the outside to the switching element 706, or generate the voltage VH and VL.

[0071] As described above, the timing control circuit 180 changes the gain of the photoelectric conversion device 100 according to the change in the driving mode of the photoelectric conversion device 100. As described above, the timing control circuit 180 may change the gain of the photoelectric conversion device 100 by changing the resistance value of the resistor 312. Instead of or in addition to this, the timing control circuit 180 may change the gain of the photoelectric conversion device 100 by changing the setting of the A / D converter 131.

[0072] More specifically, when an analog current signal is supplied to the A / D converter 131, changing the setting of the A / D converter 131 may include changing the value of the analog current supplied from the D / A converter 406 to the subtractor 401 with respect to the same output from the quantizer 403. In addition, when an analog current signal is supplied to the A / D converter 131, changing the setting of the A / D converter 131 may include changing the value of the analog current supplied from the D / A converter 410 to the subtractor 408 with respect to the same output from the quantizer 403. The former case will be described in detail below. Changing the value of the analog current supplied from the D / A converter 406 to the subtractor 401 may include changing the number of transistors among the plurality of transistors 601 and 602 connected to the subtractor 401 or 408, as described above. Instead of or in addition to this, changing the value of the analog current supplied from the D / A converter 406 to the subtractor 401 may include changing the value of the voltage Vbias supplied to each gate of the transistors 601 and 602. Compared with the case of changing the number of transistors, the current can be changed more finely by changing the value of the voltage Vbias.

[0073] When an analog current signal is supplied to the A / D converter 131, changing the setting of the A / D converter 131 may include changing the value of the reference voltage Vref supplied to the Gm amplifier 506. By changing the value of the reference voltage Vref, the output from the Gm amplifier 506 changes with respect to the same output from the integrator 402. This also changes the gain of the A / D converter 131.

[0074] When an analog voltage signal is supplied to the A / D converter 131, changing the settings of the A / D converter 131 may include changing the value of the analog voltage supplied from the D / A converter 406 to the subtractor 401 relative to the same output from the quantizer 403. When an analog voltage signal is supplied to the A / D converter 131, changing the settings of the A / D converter 131 may include changing the value of the analog voltage supplied from the D / A converter 410 to the subtractor 408 relative to the same output from the quantizer 403. For example, the control circuit 132 may change one or both of the voltages VH and VL described in Figure 7 Since this changes the value subtracted from the input analog voltage signal relative to the same output from the quantizer 403, the gain of the A / D converter 131 also changes.

[0075] Changing the settings of the A / D converter 131 may include changing the settings of the decimation filter 405. The setting to be changed may be, for example, the constant of the decimation filter 405 or the frequency of the clock signal of the decimation filter 405.

[0076] Any of the above methods of changing the gain of the photoelectric conversion device 100 can suppress an increase in chip size as compared with the case of changing the number of capacitors. In the above embodiment, the photoelectric conversion device 100 includes one A / D converter 131 for each pixel column. Alternatively, the photoelectric conversion device 100 may include a common A / D converter 131 for a plurality of pixel columns. In the above embodiment, the readout circuit 121 performs correlated double sampling. Alternatively, each of the noise signal and the data signal may be supplied to the A / D converter 131 without performing correlated double sampling in the readout circuit 121. The A / D converter 131 performs A / D conversion on each of the noise signal and the data signal. The signal processing circuit 150 may obtain the difference between the noise signal and the data signal after A / D conversion.

[0077] (Second Embodiment)

[0078] International Publication No. 2019 / 069614 describes a technique of converting an analog current signal from a sample-and-hold circuit into a digital signal using a subsequent-stage ΔΣ A / D (analog-to-digital) converter. The settings of this A / D converter cannot be changed. Therefore, for example, if the input signal to the A / D converter is small, the number of inversions of the output of the comparator of the ΔΣ converter may decrease, thereby reducing the accuracy of A / D conversion. If the settings of the A / D converter can be changed, then the degree of freedom in the design of the photoelectric conversion device is improved. The technique to be described below relates to a technique that enables changing the settings of a ΔΣ A / D converter for converting an analog current signal into a digital signal.

[0079] Embodiments in which the photoelectric conversion device 100 is used for image capture will be mainly described below. In this case, the photoelectric conversion device 100 can be used as an image sensor for generating images. In addition, other examples of the photoelectric conversion device 100 are distance measurement elements (sensors for distance measurement using focus detection or TOF (time of flight)), photometry elements (sensors for measuring the amount of incident light, etc.), and LiDAR (light detection and ranging) sensors. The embodiments described below are applicable to any photoelectric conversion device.

[0080] Reference will be made to Figure 8 the block diagram shown in Figure 8 to describe an example of the arrangement of the photoelectric conversion device 100 according to some embodiments. In the example shown in

[0081] the photoelectric conversion device 100 includes a pixel unit 110, a readout unit 120, an A / D conversion unit 130, a horizontal scan circuit 140, a signal processing circuit 150, an output circuit 160, a vertical scan circuit 170, and a timing control circuit 180. Figure 8 The pixel unit 110 includes a plurality of pixel circuits 111 arranged in a two-dimensional array, a plurality of driving lines 112 provided for each pixel row, and a plurality of signal lines 113 provided for each pixel column. A pixel row indicates a plurality of pixel circuits 111 arranged in the Figure 8 horizontal direction in

[0082] The pixel circuits 111 convert incident light into an electrical signal. Therefore, the pixel circuits 111 can also be referred to as light receiving circuits. A control signal is supplied from the vertical scan circuit 170 to each of the plurality of pixel circuits 111 via a corresponding one of the driving lines 112. The readout unit 120 reads out the electrical signal from the pixel circuit 111 supplied with the active level control signal via a corresponding one of the signal lines 113.

[0083] The readout unit 120 includes a plurality of readout circuits 121 provided for the signal lines 113 and a control circuit 122 for controlling the operation of the readout circuits 121. Each readout circuit 121 reads out an analog signal corresponding to the electrical signal generated by the pixel circuit 111 and supplies it to the A / D conversion unit 130.

[0084] The A / D conversion unit 130 includes a plurality of A / D converters 131 provided for the signal lines 113 and a control circuit 132 for controlling the operation of the A / D converters 131. Each A / D converter 131 converts the analog signal supplied from the readout circuit 121 into a digital signal. In the following description, each A / D converter 131 is a Δ∑ A / D converter.

[0085] The horizontal scanning circuit 140 sequentially reads digital signals from the plurality of A / D converters 131 and supplies them to the signal processing circuit 150. The photoelectric conversion device 100 may include a memory circuit for storing digital signals between the A / D conversion unit 130 and the horizontal scanning circuit 140. The signal processing circuit 150 processes digital signals corresponding to the electrical signals generated in each pixel circuit 111. The signal processing circuit 150 may perform, for example, correction processing, two's complement processing, etc. on the digital signals.

[0086] The digital signals processed by the signal processing circuit 150 are output from the output circuit 160 to an external device 190 outside the photoelectric conversion device 100. The external device 190 may be, for example, a control device of equipment incorporating the photoelectric conversion device 100. The timing control circuit 180 controls the overall operation of the photoelectric conversion device 100 by supplying control signals to each circuit of the photoelectric conversion device 100. For example, the timing control circuit 180 may change the driving mode of the photoelectric conversion device 100 according to an instruction from the external device 190. The timing control circuit 180 changes the gain of the photoelectric conversion device 100 according to the change in the driving mode of the photoelectric conversion device 100. A detailed example of the gain change method will be described later. The change in the driving mode may include a change between a still image capture mode and a moving image capture mode of shooting using the photoelectric conversion device 100. The change in the driving mode may include a change in the sensitivity of shooting using the photoelectric conversion device 100. The change in the driving mode may include a change in the resolution of the A / D conversion of the A / D converter 131. The change in the driving mode may include a change in the frame rate of moving image capture using the photoelectric conversion device 100. The change in the driving mode may include at least one of the above examples.

[0087] Reference will be made to Figure 9 a circuit diagram shown in Figure 9 to describe a detailed example of the circuit arrangement of the pixel circuit 111. The pixel circuit 111 may have any arrangement for converting incident light into an electrical signal. Reference will be made to

[0088] In the example described with reference to Figure 9 the pixel circuit 111 includes a photoelectric conversion element 201, a transfer transistor 202, a reset transistor 203, an amplification transistor 204, and a selection transistor 205. In the example shown in 9, the pixel unit 110 includes three driving lines 112 for each pixel row, which supply control signals PRES, PTX, and PSEL to the pixel circuit 111, respectively.

[0089] The photoelectric conversion element 201 converts incident light into charges and accumulates them. The photoelectric conversion element 201 can be, for example, a photodiode or a phototransistor. The photoelectric conversion element 201 can be a CMOS (complementary metal oxide semiconductor) sensor. Alternatively, the photoelectric conversion element 201 can be a SPAD (single photon avalanche diode) sensor.

[0090] The photoelectric conversion element 201 is connected to the floating diffusion 206 via the transfer transistor 202. The vertical scan circuit 170 supplies a control signal PTX to the gate of the transfer transistor 202. When the control signal PTX is set to the effective level, the transfer transistor 202 is set to the on state. The signal charges accumulated in the photoelectric conversion element 201 are accordingly transferred to the floating diffusion 206.

[0091] The floating diffusion 206 is also connected to the gate of the amplification transistor 204. One main electrode of the amplification transistor 204 is connected to the signal line 113 via the selection transistor 205. The other main electrode of the amplification transistor 204 is connected to the supply potential VDD. The vertical scan circuit 170 supplies a control signal PSEL to the gate of the selection transistor 205. When the control signal PSEL is set to the effective level, the selection transistor 205 is set to the on state. One main electrode of the amplification transistor 204 is accordingly connected to the current source of the readout circuit 121. This causes the amplification transistor 204 to operate as a source follower, and the signal corresponding to the potential of the floating diffusion 206 is read out into the signal line 113.

[0092] The reset transistor 203 is connected between the floating diffusion 206 and the supply potential VDD. The vertical scan circuit 170 supplies a control signal PRES to the gate of the reset transistor 203. When the control signal PRES is set to the effective level, the reset transistor 203 is set to the on state. The potential of the floating diffusion 206 is accordingly reset to the supply potential VDD.

[0093] Refer to Figure 10 the circuit diagram shown in to describe a detailed example of the circuit arrangement of the readout circuit 121. The readout circuit 121 can have any arrangement for reading out the electrical signal generated in the pixel circuit 111. Refer to Figure 10 the example for description, but the readout circuit 121 can have another arrangement.

[0094] In the example described in reference Figure 10 the readout circuit 121 includes current sources 301, 308, and 309, sample-and-hold circuits 302 and 303, amplifiers 304 and 306, transistors 305 and 307, and a resistor 312.

[0095] The current source 301 supplies a bias current to the pixel circuit 111 (more specifically, the amplification transistor 204). Each of the sample-and-hold circuits 302 and 303 holds the output voltage from the pixel circuit 111. The timing control circuit 180 controls the pixel circuit 111 to output each of an electrical signal (hereinafter referred to as a noise signal) when the photoelectric conversion element 201 is in a reset state and an electrical signal corresponding to incident light (hereinafter referred to as a data signal). According to an instruction from the timing control circuit 180, the control circuit 122 controls the readout circuit 121 to read out the noise signal and hold it in the sample-and-hold circuit 302. Further, according to an instruction from the timing control circuit 180, the control circuit 122 controls the readout circuit 121 to read out the data signal from the pixel circuit 111 and hold it in the sample-and-hold circuit 303.

[0096] The amplifier 304 and the transistor 305 function as a source follower. The current source 308 supplies a bias current to this source follower. The potential of the node 310 between the current source 308 and the transistor 305 has a value corresponding to the voltage (noise signal) held in the sample-and-hold circuit 302.

[0097] The amplifier 306 and the transistor 307 function as a source follower. The current source 309 supplies a bias current to this source follower. The potential of the node 311 between the current source 309 and the transistor 307 has a value corresponding to the voltage (data signal) held in the sample-and-hold circuit 303.

[0098] The resistor 312 is connected between the nodes 310 and 311. Accordingly, the voltage applied to the resistor 312 is the potential difference between the nodes 310 and 311. Accordingly, the readout circuit 121 supplies an analog current signal corresponding to the difference between the data signal and the noise signal to the A / D converter 131. The readout circuit 121 has a function of performing correlated double sampling (CDS).

[0099] Refer to Figure 11A and Figure 11B each of the block diagrams shown in Figure 11A for a detailed example of the circuit arrangement of the A / D converter 131. The A / D converter 131 is a Δ∑ A / D converter. The A / D converter 131 converts an input analog signal into a digital signal. Figure 11BThe A / D converter 131 shown in [Figure] includes a second-order ΔΣ modulator 407 and a decimation filter 405. Alternatively, the A / D converter 131 may include a third-order or higher-order ΔΣ modulator. By using a higher-order ΔΣ modulator, the noise shaping effect is improved. Each of the ΔΣ modulators 404 and 407 converts an input analog signal into a string of 1-bit digital signals. The decimation filter 405 performs decimation processing (downsampling processing) on the string of 1-bit digital signals.

[0100] For example, the decimation filter 405 generates a digital signal corresponding to the ratio of the time when a 1 is obtained in the string of 1-bit digital signals with respect to a predetermined time length. The ΔΣ modulator 404 may convert the input analog signal into a string of two or more bits of digital signals.

[0101] As Figure 11A shown in [Figure], the first-order ΔΣ modulator 404 includes a subtractor 401, an integrator 402, a quantizer 403, and a D / A converter (DAC) 406. The input of the A / D converter 131 (i.e., the analog signal from the readout circuit 121) is supplied to the subtractor 401. In addition, the analog signal of the D / A converter 406 is supplied to the subtractor 401.

[0102] The subtractor 401 supplies the difference between the analog signal from the readout circuit 121 and the analog signal from the D / A converter 406 to the integrator 402.

[0103] The integrator 402 integrates the output from the subtractor 401. The quantizer 403 quantizes the integration result of the integrator 402. For example, the quantizer 403 generates a string of 1-bit digital signals based on the integration result and supplies it to the decimation filter 405. The output from the quantizer 403 is the output from the ΔΣ modulator 404.

[0104] The output from the quantizer 403 is also supplied to the D / A converter 406. The D / A converter 406 generates a signal corresponding to the output of the quantizer 403 and supplies it to the subtractor 401. As described above, the signal supplied to the subtractor 401 from the D / A converter 406 is subtracted from the analog signal supplied from the readout circuit 121.

[0105] As Figure 11B shown in [Figure], the second-order ΔΣ modulator 407 includes a subtractor 401, a subtractor 408, an integrator 402, an integrator 409, a quantizer 403, a D / A converter (DAC) 406, and a D / A converter (DAC) 410. The arrangement of the subtractor 401, the integrator 402, the quantizer 403, and the D / A converter (DAC) 406 is the same as that in the first-order ΔΣ modulator 404.

[0106] The output from integrator 402 is supplied to subtracter 408. In addition, the analog signal from D / A converter 410 is supplied to subtracter 408. Subtracter 408 supplies the difference between the analog signal from integrator 402 and the analog signal from D / A converter 410 to integrator 409. Integrator 409 integrates the output from subtracter 408. Quantizer 403 quantizes the integration result of integrator 409.

[0107] The output from quantizer 403 is also supplied to D / A converter 410. D / A converter 410 generates a signal corresponding to the output from quantizer 403 and supplies it to subtracter 408. As described above, the signal supplied from D / A converter 410 to subtracter 408 is subtracted from the analog signal supplied from integrator 402.

[0108] Examples of the circuit arrangements of ΔΣ modulators 404 and 407 will be described with reference to Figure 12A and Figure 12B when the input to A / D converter 131 is an analog current signal. Figure 12A FIG. shows an example of the circuit arrangement of first-order ΔΣ modulator 404, and Figure 12B FIG. shows an example of the circuit arrangement of second-order ΔΣ modulator 407.

[0109] First, an example of the circuit arrangement of first-order ΔΣ modulator 404 will be described. Subtracter 401 is formed by node 501 connected to readout circuit 121, D / A converter 406, and integrator 402. The analog current signal supplied from readout circuit 121 to node 501 is subtracted from the analog current from D / A converter 406, and the resulting current is supplied to integrator 402.

[0110] Integrator 402 is formed by capacitor 502. Capacitor 502 can be a variable capacitor whose capacitance value varies according to an instruction from control circuit 132. Capacitor 502 is charged by the output from subtracter 401 to integrate the output. The voltage of capacitor 502 is supplied to quantizer 403. Quantizer 403 is formed by comparator 503. Comparator 503 outputs a high-level or low-level voltage according to the value of the voltage supplied from integrator 402.

[0111] The D / A converter 406 is composed of a switching element 504 and a current generation circuit 505. The current generation circuit 505 generates an analog current to be supplied to the subtractor 401. The switching element 504 is located on the signal path between the subtractor 401 and the current generation circuit 505. The ON / OFF of the switching element 504 is switched by the output from the quantizer 403. If the output from the quantizer 403 is at a high level, the switching element 504 is turned on, thereby supplying the current from the current generation circuit 505 to the subtractor 401. On the other hand, if the output from the quantizer 403 is at a low level, the switching element 504 is turned off, so that no current is supplied from the current generation circuit 505 to the subtractor 401. In this way, the value of the analog current supplied from the D / A converter 406 to the subtractor 401 changes according to the output from the quantizer 403.

[0112] Next, an example of the circuit arrangement of the second-order ΔΣ modulator 407 will be described. The ΔΣ modulator 407 includes subtractors 401 and 408, integrators 402 and 409, a Gm amplifier 506, a quantizer 403, and D / A converters 406 and 410. The circuit arrangements of the subtractor 401, the integrator 402, the quantizer 403, and the D / A converter 406 are the same as those in the first-order ΔΣ modulator 404. The Gm amplifier 506 is an amplifier that converts the analog voltage signal supplied from the integrator 402 into an analog current signal and supplies it to the subtractor 408. The integrator 402 supplies an analog voltage signal to the inverting input terminal of the Gm amplifier 506, and the control circuit 132 supplies a reference voltage Vref to the non-inverting input terminal of the Gm amplifier 506.

[0113] The subtractor 408 is composed of a node 507 connected to the Gm amplifier 506, the D / A converter 410, and the integrator 409. The analog current signal supplied from the Gm amplifier 506 to the node 507 is subtracted from the analog current from the D / A converter 410, and the resulting current is supplied to the integrator 409. The integrator 409 is composed of a capacitor 508. The capacitor 508 can be a variable capacitor whose capacitance value changes according to an instruction from the control circuit 132. The capacitor 508 is charged by the output from the Gm amplifier 506 to integrate the output. The voltage of the capacitor 508 is supplied to the quantizer 403.

[0114] The D / A converter 410 is composed of a switching element 509 and a current generation circuit 510. The current generation circuit 510 generates an analog current supplied to the subtractor 408. The switching element 509 is located on the signal path between the subtractor 408 and the current generation circuit 510. The ON / OFF of the switching element 509 is switched by the output from the quantizer 403. If the output from the quantizer 403 is at a high level, the switching element 509 is turned on, and thus the current from the current generation circuit 510 is supplied to the subtractor 408. On the other hand, if the output from the quantizer 403 is at a low level, the switching element 509 is turned off, and thus no current is supplied from the current generation circuit 510 to the subtractor 408. In this way, the value of the analog current supplied from the D / A converter 416 to the subtractor 408 changes according to the output from the quantizer 403.

[0115] Refer to Figure 13 the circuit diagram shown in to describe a detailed example of the circuit arrangement of the current generation circuit 505. The current generation circuit 505 can have any arrangement capable of changing the amount of current to be generated. Refer to Figure 13 the example for description, but the current generation circuit 505 can have another arrangement. The current generation circuit 510 can have the same circuit arrangement as the current generation circuit 505.

[0116] The current generation circuit 505 includes transistors 601 and 602, switching elements 603 and 604, and a capacitor 605. The transistor 601 is connected between the switching element 504 and the ground. The transistors 602 and the switching element 603 are connected in series between the switching element 504 and the ground. The control circuit 132 supplies a bias voltage Vbias to the gates of the transistors 601 and 602 via the switching element 604. The bias voltage Vbias is also supplied to the capacitor 605.

[0117] The switching element 604 and the capacitor 605 constitute a sample-and-hold circuit. When the switching element 604 is turned off, the bias voltage Vbias held in the capacitor 605 is supplied to the gates of the transistors 601 and 602.

[0118] Each of the transistors 601 and 602 serves as a current source that generates a current corresponding to the bias voltage Vbias supplied to the gate. The current generated by the transistor 601 is supplied to the switching element 504. When the switching element 603 is ON, the current generated by the transistor 602 is supplied to the switching element 504. When the switching element 603 is OFF, the current generated by the transistor 602 is not supplied to the switching element 504. The ON / OFF of each of the switching elements 603 and 604 is controlled by a control signal supplied from the control circuit 132.

[0119] As described above, the value of the analog current supplied from the current generation circuit 505 to the switching element 504 changes according to the ON / OFF of the switching element 603. More specifically, when the switching element 603 is ON, a larger value of current is supplied compared to the case where the switching element 603 is OFF. By changing the value of the bias voltage Vbias, the current value generated by each of the transistors 601 and 602 can also be changed. By providing the current generation circuit 505, the D / A converter 406 can change the value of the analog current supplied from the D / A converter 406 to the subtractor 401 with respect to the same output (high level in the above example) from the quantizer 403.

[0120] Reference will be made Figure 14 to the circuit diagram shown in Figure 14 to describe a detailed example of the circuit arrangement of the capacitor 502. The capacitor 502 can have any arrangement capable of changing the capacitance value. Reference will be made

[0121] to the example, but the capacitor 502 can have another arrangement. The capacitor 508 can have the same arrangement as the capacitor 502. Figure 14 Three sets of unit capacitors 1401 and switching elements 1402 are shown, but the present invention is not limited thereto. In Figure 14 the example shown in

[0122] the switching element 1402 is connected to the node 501 side, but it can also be connected to the ground side.

[0123] The method of changing the settings of the A / D converter 131 described above will be described. In Figure 11AIn the first-order ΔΣ modulator 404 shown in the figure, the control circuit 132 can change the capacitance value of at least one of the capacitors 502 and 508. The case of changing the capacitance value of the capacitor 502 will be described below. By increasing the capacitance value of the capacitor 502, the time taken to charge the capacitor 502 is extended. Therefore, the inversion frequency of the output of the quantizer 403 decreases, and the gain of the A / D converter 131 decreases. Conversely, by decreasing the capacitance value of the capacitor 502, the time taken to charge the capacitor 502 is shortened. Therefore, the inversion frequency of the output of the quantizer 403 increases, and the gain of the A / D converter 131 increases. In this way, the driving timing of the A / D converter 131, the range of the input signal, and the gain can be adjusted by making the capacitance value of the capacitor 502 variable, thereby optimizing the AD conversion settings. For example, when the shooting target is a low-brightness object, the control circuit 132 can decrease the capacitance value of the capacitor 502 compared to the case where the shooting target is a high-brightness object. This can ensure that the output of the quantizer 403 has a sufficient inversion frequency.

[0124] The control circuit 132 can change the value of the analog current supplied from the D / A converter 406 to the subtractor 401 with respect to the same output from the quantizer 403 in synchronization with the change in the capacitance value of the capacitor 502. Changing the value of the analog current supplied from the D / A converter 406 to the subtractor 401 can include changing the number of transistors among the plurality of transistors 601 and 602 connected to the subtractor 401, as described above. Alternatively or in addition to this, changing the value of the analog current supplied from the D / A converter 406 to the subtractor 401 can include changing the value of the voltage Vbias supplied to each gate of the transistors 601 and 602. Compared with the case of changing the number of transistors, the current can be changed more finely by changing the value of the voltage Vbias.

[0125] If the control circuit 132 increases the capacitance value of the capacitor 502, it can decrease the value of the analog current supplied from the D / A converter 406 to the subtractor 401. Conversely, if the control circuit 132 decreases the capacitance value of the capacitor 502, it can increase the value of the analog current supplied from the D / A converter 406 to the subtractor 401. By performing control in this way, the control circuit 132 can appropriately adjust the operating point at the start of integration of the integrator 402. More specifically, the operating point at the start of integration of the integrator 402 can be made constant before and after the change in the capacitance value of the capacitor 502, thereby reducing the change caused by the difference in the operating point.

[0126] Alternatively or in addition thereto, the control circuit 132 may include changing the settings of the decimation filter 405 in synchronization with a change in the capacitance value of the capacitor 502. The setting to be changed may be, for example, a constant of the decimation filter 405 or the frequency of the clock signal of the decimation filter 405. By performing the control synchronously in this way, the control circuit 132 can appropriately adjust the settings of the A / D converter 131.

[0127] In Figure 11B the second-order ΔΣ modulator 407 shown in, the control circuit 132 may change the gain of the photoelectric conversion device 100 by changing the capacitance values of the capacitors 502 and 508. The control circuit 132 may change only the capacitance value of the capacitor 502, change only the capacitance value of the capacitor 508, or change both the capacitance values of the capacitors 502 and 508. The operation of the A / D converter 131 performed by changing the capacitor 508 is the same as the operation when changing the capacitor 502. If only one of the capacitance values of the capacitors 502 and 508 is changed, the capacitor that is not changed does not have to be a variable capacitor.

[0128] In synchronization with the change in the capacitance value of the capacitor 508, the control circuit 132 may change the value of the analog current supplied from the D / A converter 410 to the subtractor 408 with respect to the same output from the quantizer 403. Alternatively or in addition thereto, the control circuit 132 may include changing the settings of the decimation filter 405 in synchronization with the change in the capacitance value of the capacitor 508.

[0129] The control circuit 132 may be able to change the capacitance values of the capacitors 502 and 508 individually. For example, the control circuit 132 may set different values as the capacitance values of the capacitors 502 and 508. For example, the control circuit 132 may adjust the change in the circuit characteristics of the pixel circuit 111 and the readout circuit 121 by changing the capacitance value of the capacitor 502, and may adjust the change in the characteristics of the A / D converter 131 by changing the capacitance value of the capacitor 508.

[0130] In the above embodiment, the readout circuit 121 performs correlated double sampling. Alternatively, each of the noise signal and the data signal may be supplied to the A / D converter 131 without performing correlated double sampling in the readout circuit 121. The A / D converter 131 performs A / D conversion on each of the noise signal and the data signal. The signal processing circuit 150 may obtain the difference between the noise signal and the data signal after A / D conversion. This can reduce the variation in the characteristics of the A / D converter 131 for each pixel column.

[0131] The control circuit 132 can change the value of capacitor 502 (and the value of capacitor 508) between the case where the A / D converter 131 performs A / D conversion on the data signal and the case where the A / D converter 131 performs A / D conversion on the noise signal. The value of the noise signal is generally smaller than the value of the data signal. Therefore, the control circuit 132 can make the capacitance value of capacitor 502 when the A / D converter 131 performs A / D conversion on the noise signal smaller than the capacitance value of capacitor 502 when the A / D converter 131 performs A / D conversion on the data signal. Therefore, since the inversion count of the comparator 503 increases during the A / D conversion of the noise signal, the noise shaping effect can be improved. If different gains are set for each of the A / D conversion of the data signal and the A / D conversion of the noise signal, the signal processing circuit 150 adjusts the gain difference.

[0132] In the above embodiment, the photoelectric conversion device 100 includes one A / D converter 131 for each pixel column. Alternatively, the photoelectric conversion device 100 may include a common A / D converter 131 for a plurality of pixel columns.

[0133] Note that the first embodiment and the second embodiment can be combined.

[0134] Alternatively, a part of the first embodiment and a part of the second embodiment can be combined. For example, an example of applying a part of the second embodiment to the first embodiment will be described. The timing control circuit 180 according to the second embodiment changes the gain of the photoelectric conversion device 100 according to a change in the driving mode of the photoelectric conversion device 100. In order to change the gain of the photoelectric conversion device 100, the resistance value of the resistor 312 shown in Figure 3 can be changed. The change in the driving mode may include a change in the shooting sensitivity of the photoelectric conversion device 100. The change in the driving mode may include a change in the resolution of the A / D conversion of the A / D converter 131. The change in the driving mode may include a change in the frame rate of the moving image capture using the photoelectric conversion device 100. The change in the driving mode may include at least one of the above examples.

[0135] According to the change in the driving mode, Figure 3 the resistance value of the resistor 312 shown in Figure 12A and the capacitance value of the capacitor 502 shown in Figure 3 can be changed in combination. According to the change in the driving mode, Figure 12B the resistance value of the resistor 312 shown in

[0136] (Other Embodiments)

[0137] Reference will be made to Figure 15ADescribe in detail an embodiment of the apparatus 800 including the semiconductor device 803. The semiconductor device 803 may be a photoelectric conversion device according to any of the above embodiments. The semiconductor device 803 may include a semiconductor device 801 and a package 802 that houses the semiconductor device 801. The package 802 may include a base on which the semiconductor device 801 is fixed and a cover made of glass or the like facing the semiconductor device 801. The package 802 may further include connection members such as bonding wires and bumps for connecting the terminals of the base and the terminals (pads) of the semiconductor device 801.

[0138] The apparatus 800 may include at least one of an optical device 804, a control device 805, a processing device 806, a display device 807, a storage device 808, and a mechanical device 809. The optical device 804 is implemented by, for example, a lens, a shutter, and a mirror. The optical device 804 corresponds to the photoelectric conversion device. The control device 805 controls the semiconductor device 803. The control device 805 is a semiconductor device such as an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit), for example.

[0139] The processing device 806 processes the signal output from the semiconductor device 803. The processing device 806 is a semiconductor device such as a CPU (Central Processing Unit) or an ASIC for forming an AFE (Analog Front End) or a DFE (Digital Front End). The display device 807 is an EL (Electro-Luminescence) display device or a liquid crystal display device that displays the information (image) obtained by the semiconductor device 803. The storage device 808 is a magnetic device or a semiconductor device that stores the information (image) obtained by the semiconductor device 803. The storage device 808 is a volatile memory such as an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory) or a non-volatile memory such as a flash memory or a hard disk drive.

[0140] The mechanical device 809 includes a moving or propulsion unit such as a motor or an engine. In the apparatus 800, the mechanical device 809 displays the signal output from the semiconductor device 803 on the display device 807 and performs external transmission through a communication device (not shown) of the apparatus 800. For this purpose, in addition to the memory circuit and the arithmetic circuit included in the semiconductor device 803, the apparatus 800 may further include the storage device 808 and the processing device 806. The mechanical device 809 may be controlled based on the signal output from the semiconductor device 803.

[0141] In addition, the apparatus 800 is applicable to electronic apparatuses such as information terminals having a photographing function (e.g., a smart phone or a wearable terminal) or cameras (e.g., an interchangeable-lens camera, a compact camera, a video camera, or a surveillance camera). The mechanical device 809 in the camera can drive components of the optical device 804 to perform zooming, focusing operations, and shutter operations. Alternatively, the mechanical device 809 in the camera can move the semiconductor device 803 to perform an anti-shake operation.

[0142] Furthermore, the apparatus 800 can be a transportation apparatus such as a vehicle, a ship, or an airplane. The mechanical device 809 in the transportation apparatus can be used as a moving device. The apparatus 800 as a transportation apparatus can be used as an apparatus for transporting the semiconductor device 803 or an apparatus that uses the photographing function to assist and / or automate (operate). The processing device 806 for assisting and / or automating (operating) can perform processing for operating the mechanical device 809 as a moving device based on information obtained by the semiconductor device 803. Alternatively, the apparatus 800 can be a medical apparatus such as an endoscope, a measuring apparatus such as an analysis ranging sensor, an analysis apparatus such as an electron microscope, or an office apparatus such as a copying machine.

[0143] Reference will be made to Figure 15B and Figure 15C describe embodiments of an image capturing system and a moving body. Figure 15B An example of an image capturing system 810 for an in-vehicle camera is shown. The image capturing system 810 includes a photoelectric conversion device 811. The photoelectric conversion device 811 can be any one of the photoelectric conversion devices described in the above embodiments. The image capturing system 810 includes an image processing unit 812 as a processing device that performs image processing on a plurality of pieces of image data acquired by the photoelectric conversion device 811. The image capturing system 810 further includes a parallax acquisition unit 813 as a processing device that calculates a parallax (phase difference of a parallax image) based on the plurality of pieces of image data acquired by the photoelectric conversion device 811. In addition, the image capturing system 810 includes a distance acquisition unit 814 as a processing device that calculates a distance to a target object based on the calculated parallax, and a collision determination unit 815 as a processing device that determines whether there is a possibility of collision based on the calculated distance. In this example, the parallax acquisition unit 813 and the distance acquisition unit 814 are examples of information acquisition units that acquire information such as distance information to a target object. That is, the distance information is information about parallax, defocus amount, distance to a target object, etc. The collision determination unit 815 can determine the possibility of collision using one of these pieces of distance information. Each of the above various processing devices can be implemented by specially designed hardware or by general-purpose hardware for performing arithmetic processing based on software modules. Alternatively, each processing device can be implemented by an FPGA, an ASIC, etc., or a combination thereof.

[0144] The image capture system 810 is connected to the vehicle information acquisition device 816 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The image capture system 810 is connected to the control ECU 817 as a control device, which outputs a control signal based on the determination result of the collision determination unit 815 to generate a braking force for the vehicle. That is, the control ECU 817 is an example of a moving body control unit that controls the movement of the moving body based on the distance information. The image capture system 810 is also connected to the alarm device 818, and the alarm device 818 generates an alarm to the driver based on the determination result of the collision determination unit 815. For example, if the collision possibility is high as the determination result of the collision determination unit 815, the control ECU 817 performs vehicle control to avoid collision or reduce damage by, for example, applying brakes, returning the accelerator, or suppressing the engine output. The alarm device 818 warns the user by, for example, generating an alarm sound, displaying alarm information on the screen of the car navigation system, or vibrating the seat belt or the steering wheel.

[0145] In this embodiment, the image capture system 810 captures the surroundings, such as the front or rear of the vehicle.

[0146] Figure 15C The image capture system 810 in the case of capturing the front of the vehicle (image capture range 819) is shown. The vehicle information acquisition device 816 sends an instruction to operate the image capture system 810 and perform image capture.

[0147] Examples of performing control to avoid collision with another vehicle have been described above. However, the image capture system can also be applied to the control for autonomous driving to follow another vehicle or autonomous driving without deviating from the lane. In addition, the image capture system can be applied not only to vehicles such as cars but also to moving bodies (transport equipment) such as ships, airplanes, or industrial robots. The moving devices in the moving body (transport equipment) include various moving units such as engines, motors, wheels, and propellers.

[0148] In addition, the image capture system can be applied not only to moving bodies but also to equipment that widely uses object recognition, such as intelligent transportation systems (ITS).

[0149] Without departing from the technical concept, the above-described embodiments can be appropriately changed. Note that the content disclosed in this specification includes not only the content described in this specification but also all items that can be grasped from this specification and its drawings. The content disclosed in this specification includes complementary groups of the concepts described in this specification. That is, for example, if "A is greater than B" is described in this specification, then even if the description of "A is not greater than B" is omitted, this specification is considered to have disclosed "A is not greater than B". This is because if "A is greater than B" is described, then the case of "A is not greater than B" is assumed to have been considered. In order to enable the public to understand the scope of the present invention, the appended claims are presented.

[0150] Using the above technology, the gain of the photoelectric conversion device can be changed while suppressing an increase in the chip size.

[0151] Although the present invention has been described with reference to exemplary embodiments, it should be understood that the present invention is not limited to the disclosed exemplary embodiments. The scope of the appended claims should be given the broadest interpretation so as to cover all such modifications as well as equivalent structures and functions.

Claims

1. A photoelectric conversion device, comprising: a light receiving circuit configured to convert light into an electrical signal; a readout circuit configured to read out an analog signal corresponding to the electrical signal; a ΔΣ A / D converter configured to convert the analog signal into a digital signal; and a control circuit configured to change the gain of the photoelectric conversion device according to a change in the drive mode of the photoelectric conversion device, wherein the analog signal read out by the readout circuit is an analog current signal, the readout circuit includes a variable resistor on a signal path for supplying the analog current signal to the ΔΣ A / D converter, a voltage of a data signal is input to one node of the variable resistor, a voltage of a noise signal is input to the other node of the variable resistor, and an analog current signal corresponding to a difference between the data signal and the noise signal is generated by a current flowing through the variable resistor, and the control circuit changes the gain of the photoelectric conversion device by changing the resistance value of the variable resistor.

2. The device according to claim 1, wherein the ΔΣ A / D converter includes: a subtractor configured to be supplied with the analog current signal, an integrator configured to integrate an output from the subtractor, a quantizer configured to quantize an integration result of the integrator, a decimation filter configured to perform a decimation process on an output from the quantizer, and a D / A converter configured to supply an analog current corresponding to an output from the quantizer to the subtractor so as to be subtracted from the analog current signal, and changing the settings of the ΔΣ A / D converter includes changing the value of the analog current supplied from the D / A converter to the subtractor with respect to the same output from the quantizer.

3. The device according to claim 2, wherein the integrator includes a variable capacitor configured to be charged with an output from the subtractor to integrate the output, and the control circuit changes the gain of the photoelectric conversion device by changing the resistance value of the variable resistor and changing the capacitance value of the variable capacitor.

4. The device according to claim 2, wherein the D / A converter includes a current generation circuit configured to generate the analog current supplied to the subtractor, the current generation circuit includes a plurality of current sources, and changing the settings of the ΔΣ A / D converter includes changing the number of current sources among the plurality of current sources connected to the subtractor.

5. The device according to claim 4, wherein each of the plurality of current sources includes a transistor, and changing the settings of the ΔΣ A / D converter includes changing the value of the voltage to be supplied to the gate of the transistor.

6. The device according to claim 2, wherein the subtractor, the integrator, the analog current signal, the analog current, and the D / A converter are a first subtractor, a first integrator, a first analog current signal, a first analog current, and a first D / A converter, respectively, the ΔΣ A / D converter further includes: a second subtractor configured to be supplied with a second analog current signal from the first integrator, a second integrator configured to integrate an output from the second subtractor, an amplifier configured to convert an output from the first integrator into a current, and A second D / A converter, configured to supply a second analog current corresponding to an output from a quantizer to a second subtractor so as to be subtracted from the second analog current signal, and Changing the settings of the ΔΣ A / D converter includes changing the value of a reference voltage supplied to an amplifier.

7. The apparatus according to claim 4, wherein the subtractor, the integrator, the analog current signal, the analog current, and the D / A converter are a first subtractor, a first integrator, a first analog current signal, a first analog current, and a first D / A converter, respectively, The ΔΣ A / D converter further includes: A second subtractor, configured to be supplied with a second analog current signal from the first integrator, A second integrator, configured to integrate an output from the second subtractor, An amplifier, configured to convert an output from the first integrator into a current, and A second D / A converter, configured to supply a second analog current corresponding to an output from a quantizer to a second subtractor so as to be subtracted from the second analog current signal, and Changing the settings of the ΔΣ A / D converter includes changing the value of a reference voltage supplied to an amplifier.

8. The apparatus according to claim 2, wherein changing the settings of the ΔΣ A / D converter includes changing the settings of a decimation filter.

9. The apparatus according to claim 1, wherein the change in the driving mode includes at least one of the following: A change between a still image capture mode and a moving image capture mode of shooting using the photoelectric conversion device, A change in the sensitivity of shooting using the photoelectric conversion device, A change in the resolution of the A / D conversion performed by the ΔΣ A / D converter, and A change in the frame rate of moving image capture using the photoelectric conversion device.

10. An apparatus, comprising: The photoelectric conversion device according to any one of claims 1-9; And At least one of the following: An optical device corresponding to the photoelectric conversion device, A control device, configured to control the photoelectric conversion device, A processing device, configured to process a signal output from the photoelectric conversion device, A display device, configured to display information obtained by the photoelectric conversion device, A storage device, configured to store information obtained by the photoelectric conversion device, and A mechanical device, configured to operate based on information obtained by the photoelectric conversion device.

11. A photoelectric conversion device, comprising: A light receiving circuit, configured to convert light into an electrical signal; A readout circuit, configured to read out an analog signal corresponding to the electrical signal; A ΔΣ A / D converter, configured to convert the analog signal into a digital signal; And A control circuit, configured to change the gain of the photoelectric conversion device according to a change in the driving mode of the photoelectric conversion device, wherein the readout circuit includes a resistor on a signal path for supplying the analog signal to the ΔΣ A / D converter, A voltage of a data signal is input to one node of the resistor, a voltage of a noise signal is input to the other node of the resistor, and an analog signal corresponding to a difference between the data signal and the noise signal is generated by a current flowing through the resistor, The control circuit changes the gain of the photoelectric conversion device by changing the settings of the ΔΣ A / D converter.

12. The apparatus according to claim 11, wherein the analog signal read out by the readout circuit is an analog current signal, the ΔΣ A / D converter includes: a subtractor configured to be supplied with the analog current signal, an integrator configured to integrate the output from the subtractor, a quantizer configured to quantize the integration result of the integrator, a decimation filter configured to perform a decimation process on the output from the quantizer, and a D / A converter configured to supply an analog current corresponding to the output from the quantizer to the subtractor so as to be subtracted from the analog current signal, and changing the settings of the ΔΣ A / D converter includes changing the value of the analog current supplied from the D / A converter to the subtractor with respect to the same output from the quantizer.

13. The apparatus according to claim 12, wherein the integrator includes a variable capacitor configured to be charged with the output from the subtractor so as to integrate the output, and changing the settings of the ΔΣ A / D converter includes changing the capacitance value of the variable capacitor.

14. The apparatus according to claim 12, wherein the D / A converter includes a current generation circuit configured to generate the analog current to be supplied to the subtractor, the current generation circuit includes a plurality of current sources, and changing the settings of the ΔΣ A / D converter includes changing the number of current sources among the plurality of current sources connected to the subtractor.

15. The apparatus according to claim 11, wherein the analog signal read out by the readout circuit is an analog voltage signal, the ΔΣ A / D converter includes: a subtractor configured to be supplied with the analog voltage signal, an integrator configured to integrate the output from the subtractor, a quantizer configured to quantize the integration result of the integrator, a decimation filter configured to perform a decimation process on the output from the quantizer, and a D / A converter configured to supply an analog voltage corresponding to the output from the quantizer to the subtractor so as to be subtracted from the analog voltage signal, and changing the settings of the ΔΣ A / D converter includes changing the value of the analog voltage supplied from the D / A converter to the subtractor with respect to the same output from the quantizer.

16. An apparatus, comprising: the photoelectric conversion device according to any one of claims 11-15; and at least one of the following: an optical device corresponding to the photoelectric conversion device, a control device configured to control the photoelectric conversion device, a processing device configured to process the signal output from the photoelectric conversion device, a display device configured to display the information obtained by the photoelectric conversion device, a storage device configured to store the information obtained by the photoelectric conversion device, and a mechanical device configured to operate based on the information obtained by the photoelectric conversion device.

17. A photoelectric conversion device, comprising: a light receiving circuit configured to convert light into an electrical signal; a readout circuit configured to read out an analog current signal corresponding to the electrical signal and a noise signal from the light receiving circuit in a reset state; a ΔΣ A / D converter configured to convert each of the analog current signal and the noise signal into a digital signal; and A control circuit configured to change the settings of a ΔΣ A / D converter, wherein the ΔΣ A / D converter includes: A subtractor configured to be supplied with an analog current signal, An integrator configured to integrate the output from the subtractor, A quantizer configured to quantize the integration result of the integrator, A decimation filter configured to perform decimation processing on the output from the quantizer, and A D / A converter configured to supply an analog current corresponding to the output from the quantizer to the subtractor so as to be subtracted from the analog current signal, The integrator includes a variable capacitor configured to be charged with the output from the subtractor to integrate the output, Changing the settings of the ΔΣ A / D converter includes changing the capacitance value of the variable capacitor, and The control circuit changes the value of the variable capacitor between the case where the ΔΣ A / D converter converts an analog current signal and the case where the ΔΣ A / D converter converts the value of a noise signal.

18. The apparatus according to claim 17, wherein the control circuit changes the value of the analog current supplied from the D / A converter to the subtractor relative to the same output from the quantizer synchronously with the change in the capacitance value of the variable capacitor.

19. The apparatus according to claim 17, wherein the control circuit changes the settings of the decimation filter synchronously with the change in the capacitance value of the variable capacitor.

20. The apparatus according to claim 17, wherein The subtractor, the integrator, the analog current signal, the analog current, and the D / A converter are a first subtractor, a first integrator, a first analog current signal, a first analog current, and a first D / A converter, respectively, and The ΔΣ A / D converter further includes: A second subtractor configured to be supplied with a second analog current signal from the first integrator, A second integrator configured to integrate the output from the second subtractor, and A second D / A converter configured to supply a second analog current corresponding to the output from the quantizer to the second subtractor so as to be subtracted from the second analog current signal.

21. The apparatus according to claim 20, wherein The variable capacitor is a first variable capacitor, and The second integrator includes a second variable capacitor configured to be charged with the output from the second subtractor to integrate the output.

22. The apparatus according to claim 21, wherein the control circuit changes the value of the second analog current supplied from the second D / A converter to the second subtractor relative to the same output from the quantizer synchronously with the change in the capacitance value of the second variable capacitor.

23. The apparatus according to claim 22, wherein the control circuit changes the settings of the decimation filter synchronously with the change in the capacitance value of the second variable capacitor.

24. The apparatus according to claim 21, wherein the control circuit is capable of changing the value of the first variable capacitor and the value of the second variable capacitor independently.

25. The apparatus according to claim 17, further comprising a variable resistor on the signal path for supplying the analog current signal to the ΔΣ A / D converter, wherein the control circuit changes the resistance value of the variable resistor.

26. The apparatus according to claim 20 further includes a variable resistor on a signal path for supplying an analog current signal to the ΔΣ A / D converter, wherein the control circuit changes a resistance value of the variable resistor.

27. The apparatus according to claim 21 further includes a variable resistor on a signal path for supplying an analog current signal to the ΔΣ A / D converter, wherein the control circuit changes a resistance value of the variable resistor.

28. The apparatus according to claim 22 further includes a variable resistor on a signal path for supplying an analog current signal to the ΔΣ A / D converter, wherein the control circuit changes a resistance value of the variable resistor.

29. The apparatus according to claim 23 further includes a variable resistor on a signal path for supplying an analog current signal to the ΔΣ A / D converter, wherein the control circuit changes a resistance value of the variable resistor.

30. The apparatus according to claim 24 further includes a variable resistor on a signal path for supplying an analog current signal to the ΔΣ A / D converter, wherein the control circuit changes a resistance value of the variable resistor.

31. The apparatus according to claim 18, wherein a capacitance value of the variable capacitor is less when the ΔΣ A / D converter converts a noise signal than when the ΔΣ A / D converter converts an analog current signal value.

32. An equipment, comprising: the photoelectric conversion device according to any one of claims 18-31; and at least one of the following: an optical device corresponding to the photoelectric conversion device, a control device configured to control the photoelectric conversion device, a processing device configured to process a signal output from the photoelectric conversion device, a display device configured to display information obtained by the photoelectric conversion device, a storage device configured to store information obtained by the photoelectric conversion device, and a mechanical device configured to operate based on information obtained by the photoelectric conversion device.

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