Construction method, device, medium and electronic device of quantum discriminator

Abstract

The present invention discloses a method, apparatus, medium, and electronic device for constructing a quantum discriminator. The present invention determines a first quantum logic gate that performs a superposition operation on the quantum state of a single quantum bit, determines a second quantum logic gate that performs a superposition operation on the quantum state of two quantum bits, determines a third quantum logic gate that performs an entanglement operation on the quantum state of the two quantum bits, and determines a fourth quantum logic gate for solving the fidelity of two different quantum states. The first, second, and third quantum logic gates are applied to data bits, and the fourth quantum logic gate is applied to the data bits and a preset auxiliary bit, thereby obtaining a quantum discriminator. The quantum discriminator can be used to construct a quantum GAN or a quantum-classical hybrid GAN, thereby utilizing the characteristics of quantum superposition to efficiently process mathematical problems and addressing the problems of large GAN computational complexity and convergence failure during training.

Description

Technical Field

[0001] The present invention belongs to the field of quantum computing technology, and in particular relates to a construction method, device, medium and electronic device of a quantum discriminator. Background Art

[0002] Generative Adversarial Networks (GANs) are an important generative model in the field of deep learning. Two networks, a generator and a discriminator, are trained simultaneously and compete in a minimax algorithm. This adversarial approach avoids some of the practical difficulties of traditional generative models, cleverly approximating unsolvable loss functions through adversarial learning. It has found widespread application in generating data such as images, videos, natural language, and music. However, GANs are computationally intensive, and classic GANs are prone to convergence failure during training. The emergence of quantum computers offers a potential solution to this problem.

[0003] A quantum computer is a physical device that follows the laws of quantum mechanics to perform high-speed mathematical and logical operations, store, and process quantum information. When a device processes and computes quantum information and runs quantum algorithms, it is considered a quantum computer. Quantum computers are a key technology under research because they can handle mathematical problems more efficiently than conventional computers. For example, they can reduce the time required to crack RSA keys from hundreds of years to just hours. Constructing a quantum discriminator that can be applied to quantum computers is a key step in addressing the computational complexity and convergence failures of GAN training. Summary of the Invention

[0004] The purpose of the present invention is to provide a method, device, medium and electronic device for constructing a quantum discriminator, aiming to construct a quantum discriminator that can be applied to a quantum computer to solve the problems of large GAN computational complexity and convergence failure during training.

[0005] One embodiment of the present invention provides a method for constructing a quantum discriminator, the method comprising:

[0006] determining a first quantum logic gate for performing a superposition operation on a quantum state of a single qubit, determining a second quantum logic gate for performing a superposition operation on a quantum state of two qubits, determining a third quantum logic gate for performing an entanglement operation on the quantum state of the two qubits, and determining a fourth quantum logic gate for solving the fidelity of two different quantum states;

[0007] The first quantum logic gate, the second quantum logic gate, and the third quantum logic gate are applied to data bits, and the fourth quantum logic gate is applied to the data bits and a preset auxiliary bit to obtain a quantum discriminator.

[0008] Optionally, determining a fourth quantum logic gate for solving the fidelity of two different quantum states includes:

[0009] The SWAP test logic gate is identified as the fourth quantum logic gate for solving the fidelity of two different quantum states.

[0010] Optionally, the data bit includes a first quantum bit and a second quantum bit, the SWAP test logic gate includes an H gate and a controlled SWAP gate, and applying the fourth quantum logic gate to the data bit and a preset auxiliary bit includes:

[0011] The H gate is applied to a preset auxiliary bit, the controlled SWAP gate is applied to the auxiliary bit, the first quantum bit, and the second quantum bit corresponding to the first quantum bit, and the H gate is applied to the auxiliary bit again. The control bit of the controlled SWAP gate is the auxiliary bit.

[0012] Optionally, applying the first quantum logic gate to a data bit includes:

[0013] The first quantum logic gate is applied to each of the first quantum bits respectively.

[0014] Optionally, applying the second quantum logic gate to a data bit includes:

[0015] The second quantum logic gate acts on every two adjacent first quantum bits.

[0016] Optionally, applying the third quantum logic gate to a data bit includes:

[0017] The third quantum logic gate is applied to every two adjacent first quantum bits.

[0018] Optionally, determining a first quantum logic gate for performing a superposition operation on a quantum state of a single quantum bit includes:

[0019] The RY gate was identified as the first quantum logic gate that performs a superposition operation on the quantum state of a single qubit.

[0020] Optionally, determining a second quantum logic gate for performing a superposition operation on the quantum states of the two quantum bits includes:

[0021] Get four RX gates, two CNOT gates and one RZ gate;

[0022] The output items of two of the RX gates are used as input items of one of the CNOT gates, one of the output items of one of the CNOT gates is used as input items of the RZ gate, the other output item of one of the CNOT gates and the output item of the RZ gate are used as input items of another CNOT gate, and the two output items of the other CNOT gate are respectively used as input items of the other two RX gates, to obtain a second quantum logic gate that performs a superposition operation on the quantum state of two quantum bits.

[0023] Optionally, determining a third quantum logic gate for performing an entanglement operation on the quantum state of the two quantum bits includes:

[0024] The controlled RY gate is identified as a third quantum logic gate that performs entanglement operations on the quantum states of two qubits.

[0025] Yet another embodiment of the present invention provides a device for constructing a quantum discriminator, the device comprising:

[0026] a determining unit, configured to determine a first quantum logic gate for performing a superposition operation on a quantum state of a single quantum bit, determine a second quantum logic gate for performing a superposition operation on a quantum state of two quantum bits, determine a third quantum logic gate for performing an entanglement operation on the quantum state of the two quantum bits, and determine a fourth quantum logic gate for solving the fidelity of two different quantum states;

[0027] An acting unit is configured to act on a data bit by applying the first quantum logic gate, the second quantum logic gate, and the third quantum logic gate, and to act on the data bit and a preset auxiliary bit by applying the fourth quantum logic gate, to obtain a quantum discriminator.

[0028] Optionally, in determining a fourth quantum logic gate for solving the fidelity of two different quantum states, the determining unit is configured to:

[0029] The SWAP test logic gate is identified as the fourth quantum logic gate for solving the fidelity of two different quantum states.

[0030] Optionally, the data bit includes a first quantum bit and a second quantum bit, the SWAP test logic gate includes an H gate and a controlled SWAP gate, and in terms of applying the fourth quantum logic gate to the data bit and the preset auxiliary bit, the applying unit is specifically configured to:

[0031] The H gate is applied to a preset auxiliary bit, the controlled SWAP gate is applied to the auxiliary bit, the first quantum bit, and the second quantum bit corresponding to the first quantum bit, and the H gate is applied to the auxiliary bit again. The control bit of the controlled SWAP gate is the auxiliary bit.

[0032] Optionally, in the aspect of applying the first quantum logic gate to a data bit, the applying unit is specifically configured to:

[0033] The first quantum logic gate is applied to each of the first quantum bits respectively.

[0034] Optionally, in the aspect of applying the second quantum logic gate to a data bit, the applying unit is specifically configured to:

[0035] The second quantum logic gate acts on every two adjacent first quantum bits.

[0036] Optionally, in the aspect of applying the third quantum logic gate to a data bit, the applying unit is specifically configured to:

[0037] The third quantum logic gate is applied to every two adjacent first quantum bits.

[0038] Optionally, in determining the first quantum logic gate for performing a superposition operation on the quantum state of a single quantum bit, the determining unit is specifically configured to:

[0039] The RY gate was identified as the first quantum logic gate that performs a superposition operation on the quantum state of a single qubit.

[0040] Optionally, in determining the second quantum logic gate for performing a superposition operation on the quantum state of two quantum bits, the determining unit is specifically configured to:

[0041] Get four RX gates, two CNOT gates and one RZ gate;

[0042] The output items of two of the RX gates are used as input items of one of the CNOT gates, one of the output items of one of the CNOT gates is used as input items of the RZ gate, the other output item of one of the CNOT gates and the output item of the RZ gate are used as input items of another CNOT gate, and the two output items of the other CNOT gate are respectively used as input items of the other two RX gates, to obtain a second quantum logic gate that performs a superposition operation on the quantum state of two quantum bits.

[0043] Optionally, in determining the third quantum logic gate for performing an entanglement operation on the quantum state of two quantum bits, the determining unit is specifically configured to:

[0044] The controlled RY gate is identified as a third quantum logic gate that performs entanglement operations on the quantum states of two qubits.

[0045] Yet another embodiment of the present invention provides a storage medium storing a computer program, wherein the computer program is configured to execute any of the above methods when running.

[0046] Yet another embodiment of the present invention provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform any of the above methods.

[0047] Compared with the prior art, the present invention determines a first quantum logic gate for performing a superposition operation on the quantum state of a single quantum bit, determines a second quantum logic gate for performing a superposition operation on the quantum state of two quantum bits, determines a third quantum logic gate for performing an entanglement operation on the quantum state of the two quantum bits, and determines a fourth quantum logic gate for solving the fidelity of two different quantum states;

[0048] The first, second, and third quantum logic gates are applied to data bits, and the fourth quantum logic gate is applied to the data bits and preset auxiliary bits to obtain a quantum discriminator. This quantum discriminator can be used to construct a quantum GAN or a quantum-classical hybrid GAN, thereby utilizing the characteristics of quantum superposition to efficiently process mathematical problems and address the issues of large GAN computational complexity and convergence failure during training. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A hardware structure block diagram of a computer terminal for a method for constructing a quantum discriminator provided by an embodiment of the present invention;

[0050] Figure 2 A schematic flow chart of a method for constructing a quantum discriminator provided by an embodiment of the present invention;

[0051] Figure 3 A schematic structural diagram of a second quantum logic gate provided by an embodiment of the present invention;

[0052] Figure 4 A schematic diagram of the structure of a SWAP test logic gate provided by an embodiment of the present invention;

[0053] Figure 5 A schematic diagram of the structure of a quantum discriminator provided by an embodiment of the present invention;

[0054] Figure 6A schematic diagram of a device for constructing a quantum discriminator according to an embodiment of the present invention. DETAILED DESCRIPTION

[0055] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and are not to be construed as limiting the present invention.

[0056] The embodiment of the present invention first provides a method for constructing a quantum discriminator. The method can be applied to electronic devices such as computer terminals, specifically ordinary computers, quantum computers, etc.

[0057] The following describes it in detail by taking running on a computer terminal as an example. Figure 1 The hardware structure block diagram of a computer terminal for a method of constructing a quantum discriminator provided by an embodiment of the present invention. Figure 1 As shown, the computer terminal may include one or more ( Figure 1 Only one is shown in the figure) processor 102 (processor 102 may include but is not limited to a microprocessor MCU or a programmable logic device FPGA and other processing devices) and a memory 104 for storing the construction method of the quantum discriminator based on the quantum circuit. Optionally, the above-mentioned computer terminal may also include a transmission device 106 for communication functions and an input and output device 108. It will be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above-mentioned computer terminal. For example, the computer terminal may also include Figure 1 More or fewer components than shown, or with Figure 1 Different configurations shown.

[0058] Memory 104 can be used to store software programs and modules for application software, such as the program instructions / modules corresponding to the method for constructing a quantum discriminator in an embodiment of the present invention. Processor 102 executes the software programs and modules stored in memory 104 to perform various functional applications and data processing, thereby implementing the aforementioned method. Memory 104 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, memory 104 may further include memory remotely located relative to processor 102, and such remote memory may be connected to a computer terminal via a network. Examples of such networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0059] The transmission device 106 is used to receive or send data via a network. A specific example of the aforementioned network may include a wireless network provided by a communications provider of a computer terminal. In one embodiment, the transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0060] It's important to note that a true quantum computer has a hybrid architecture, consisting of two main components: a classical computer, responsible for performing classical computations and control, and a quantum device, responsible for running quantum programs and thus achieving quantum computations. A quantum program is a sequence of instructions written in a quantum language, such as QRunes, that can be executed on a quantum computer. This supports quantum logic gate operations and ultimately enables quantum computations. Specifically, a quantum program is a sequence of instructions that operate quantum logic gates in a specific time sequence.

[0061] In practical applications, due to the limitations of the development of quantum device hardware, quantum computing simulations are usually required to verify quantum algorithms, quantum applications, and the like. Quantum computing simulation is the process of simulating the operation of quantum programs corresponding to specific problems using a virtual architecture (i.e., a quantum virtual machine) built with the resources of an ordinary computer. Generally, it is necessary to construct a quantum program corresponding to a specific problem. The quantum program referred to in the embodiments of the present invention is a program written in a classical language to characterize quantum bits and their evolution, in which quantum bits, quantum logic gates, and the like related to quantum computing are represented by corresponding classical codes.

[0062] Quantum circuits, as a manifestation of quantum programs, also known as quantum logic circuits, are the most commonly used general quantum computing model. They represent circuits that operate on quantum bits in an abstract concept. Their components include quantum bits, circuits (timelines), and various quantum logic gates. Finally, the results often need to be read out through quantum measurement operations.

[0063] Unlike traditional circuits, which are connected by metal wires to transmit voltage or current signals, in quantum circuits, the circuits can be seen as connected by time. In other words, the state of the quantum bit naturally evolves over time, following the instructions of the Hamiltonian operator until it encounters a logic gate and is operated.

[0064] A quantum program as a whole corresponds to a single quantum circuit. The quantum program described in this disclosure refers to this quantum circuit, where the total number of qubits in this quantum circuit is the same as the total number of qubits in the quantum program. A quantum program can be understood as consisting of a quantum circuit, measurement operations on the qubits in the quantum circuit, registers storing the measurement results, and control flow nodes (jump instructions). A quantum circuit can contain dozens, hundreds, or even thousands of quantum logic gate operations. The execution of a quantum program is the process of executing all quantum logic gates in a specific time sequence. It should be noted that the time sequence refers to the chronological order in which individual quantum logic gates are executed.

[0065] It's important to note that in classical computing, the most basic unit is the bit, and the most fundamental control mode is the logic gate. Circuit control can be achieved through combinations of logic gates. Similarly, quantum logic gates are used to manipulate qubits. Quantum logic gates enable quantum states to evolve. They form the basis of quantum circuits. Quantum logic gates include single-bit quantum logic gates such as the Hadamard gate (H gate), Pauli-X gate (X gate), Pauli-Y gate (Y gate), Pauli-Z gate (Z gate), RX gate, RY gate, and RZ gate; and multi-bit quantum logic gates such as the CNOT gate, CR gate, iSWAP gate, and Toffoli gate. Quantum logic gates are generally represented using unitary matrices. Unitary matrices are not only a matrix form but also a type of operation and transformation. A typical quantum logic gate operates on a quantum state by multiplying the unitary matrix on the left by the matrix corresponding to the quantum state's right vector.

[0066] See also Figure 2 , Figure 2 A schematic flow chart of a method for constructing a quantum discriminator provided in an embodiment of the present invention. The method comprises:

[0067] Step 201: determining a first quantum logic gate for performing a superposition operation on a quantum state of a single quantum bit, determining a second quantum logic gate for performing a superposition operation on a quantum state of two quantum bits, determining a third quantum logic gate for performing an entanglement operation on the quantum state of the two quantum bits, and determining a fourth quantum logic gate for solving the fidelity of two different quantum states;

[0068] The first quantum logic gate may include at least one of the following: an H gate, an RX gate, an RY gate, and an RZ gate.

[0069] In a specific embodiment of the present invention, determining a first quantum logic gate for performing a superposition operation on a quantum state of a single quantum bit includes:

[0070] The RY gate was identified as the first quantum logic gate that performs a superposition operation on the quantum state of a single qubit.

[0071] The second quantum logic gate may be, for example, a CNOT gate, a SWAP gate, a CZ gate, a CR gate, an ISWAP gate, or the like.

[0072] In a specific embodiment of the present invention, determining a second quantum logic gate for performing a superposition operation on the quantum states of two quantum bits includes:

[0073] Get four RX gates, two CNOT gates and one RZ gate;

[0074] The output items of two of the RX gates are used as input items of one of the CNOT gates, one of the output items of one of the CNOT gates is used as input items of the RZ gate, the other output item of one of the CNOT gates and the output item of the RZ gate are used as input items of another CNOT gate, and the two output items of the other CNOT gate are respectively used as input items of the other two RX gates, to obtain a second quantum logic gate that performs a superposition operation on the quantum state of two quantum bits.

[0075] like Figure 3 As shown, Figure 3 A schematic structural diagram of a second quantum logic gate provided by an embodiment of the present invention.

[0076] The third quantum logic gate may include at least one of the following: a CNOT gate, a controlled RX gate, a controlled RY gate, and a controlled RZ gate.

[0077] In a specific embodiment of the present invention, the third quantum logic gate for determining to perform an entanglement operation on the quantum state of two quantum bits includes:

[0078] The controlled RY gate is identified as a third quantum logic gate that performs entanglement operations on the quantum states of two qubits.

[0079] In a specific embodiment of the present invention, determining a fourth quantum logic gate for solving the fidelity of two different quantum states includes:

[0080] The SWAP test logic gate is identified as the fourth quantum logic gate for solving the fidelity of two different quantum states.

[0081] like Figure 4 As shown, Figure 4 The SWAP test circuit includes a controlled SWAP gate and an H gate acting on q0, q1, and q2. The controlled SWAP gate and the H gate are SWAP test logic gates used to convert the input state Evolved to if Then the probability of measuring q0 to be |0> is Therefore, multiple measurements can be used to determine How big the difference between <φ> is determines the fidelity of the two different quantum states.

[0082] Step 202: Apply the first quantum logic gate, the second quantum logic gate, and the third quantum logic gate to a data bit, and apply the fourth quantum logic gate to the data bit and a preset auxiliary bit, to obtain a quantum discriminator.

[0083] Among them, the quantum discriminator is used to determine whether the input data is generated data generated by the quantum generator or real data.

[0084] The data bits include a first quantum bit and a second quantum bit.

[0085] In a specific embodiment of the present invention, applying the first quantum logic gate to a data bit includes:

[0086] The first quantum logic gate is applied to each of the first quantum bits respectively.

[0087] In a specific embodiment of the present invention, applying the second quantum logic gate to a data bit includes:

[0088] The second quantum logic gate acts on every two adjacent first quantum bits.

[0089] Furthermore, in addition to applying the second quantum logic gate to every two adjacent first qubits, the second quantum logic gate may also be applied to the first and last first qubits.

[0090] In a specific embodiment of the present invention, applying the third quantum logic gate to a data bit includes:

[0091] The third quantum logic gate is applied to every two adjacent first quantum bits.

[0092] Furthermore, in addition to applying the third quantum logic gate to every two adjacent first quantum bits, the third quantum logic gate can also be applied to the first and last first quantum bits. The first first quantum bit can be the control bit and the last first quantum bit can be the controlled bit; or the last first quantum bit can be the control bit and the first first quantum bit can be the controlled bit.

[0093] In a specific embodiment of the present invention, the data bit includes a first quantum bit and a second quantum bit, the SWAP test logic gate includes an H gate and a controlled SWAP gate, and applying the fourth quantum logic gate to the data bit and a preset auxiliary bit includes:

[0094] The H gate is applied to a preset auxiliary bit, the controlled SWAP gate is applied to the auxiliary bit, the first quantum bit, and the second quantum bit corresponding to the first quantum bit, and the H gate is applied to the auxiliary bit again. The control bit of the controlled SWAP gate is the auxiliary bit.

[0095] Furthermore, if the number of the first qubit and the second qubit is more than one, a controlled SWAP gate needs to be applied to the auxiliary bit, each first qubit and its corresponding second qubit.

[0096] like Figure 5 As shown, Figure 5 This is a schematic diagram of the structure of a quantum discriminator provided by an embodiment of the present invention. The figure includes 9 data bits: q0, q1, q2, q3, q4, q5, q6, q7, q8. q0 is an auxiliary bit, q1, q2, q3, q4 are the first quantum bits, and q5, q6, q7, q8 are the second quantum bits. The first quantum logic gate RY gate acts on q0, q1, q2, q3 respectively, and the second quantum logic gate acts on q0 and q1, q1 and q2, q2 and q3 respectively. The second quantum logic gate is Figure 3 The structure shown in the figure, the third quantum logic gate controlled by the RY gate acts on q0 and q1, q1 and q2, q2 and q3 respectively, and the control bits are q0, q1, and q2 in sequence. The fourth quantum logic gate is as follows Figure 4 In the structure shown, the first H gate acts on q0, the first controlled SWAP gate acts on q0, q1, and q5, the second controlled SWAP gate acts on q0, q2, and q6, the third controlled SWAP gate acts on q0, q3, and q7, the second controlled SWAP gate acts on q0, q4, and q8, and the first H gate acts on q0.

[0097] Compared with the prior art, the present invention determines a first quantum logic gate for performing a superposition operation on the quantum state of a single quantum bit, determines a second quantum logic gate for performing a superposition operation on the quantum state of two quantum bits, determines a third quantum logic gate for performing an entanglement operation on the quantum state of the two quantum bits, and determines a fourth quantum logic gate for solving the fidelity of two different quantum states;

[0098] The first, second, and third quantum logic gates are applied to data bits, and the fourth quantum logic gate is applied to the data bits and preset auxiliary bits to obtain a quantum discriminator. This quantum discriminator can be used to construct a quantum GAN or a quantum-classical hybrid GAN, thereby utilizing the characteristics of quantum superposition to efficiently process mathematical problems and address the issues of large GAN computational complexity and convergence failure during training.

[0099] See also Figure 6 , Figure 6 A schematic diagram of a device for constructing a quantum discriminator according to an embodiment of the present invention is provided, wherein the device comprises:

[0100] a determining unit 601, configured to determine a first quantum logic gate for performing a superposition operation on a quantum state of a single quantum bit, determine a second quantum logic gate for performing a superposition operation on a quantum state of two quantum bits, determine a third quantum logic gate for performing an entanglement operation on the quantum state of the two quantum bits, and determine a fourth quantum logic gate for solving the fidelity of two different quantum states;

[0101] The action unit 602 is configured to apply the first quantum logic gate, the second quantum logic gate, and the third quantum logic gate to a data bit, and to apply the fourth quantum logic gate to the data bit and a preset auxiliary bit, to obtain a quantum discriminator.

[0102] Optionally, in determining the fourth quantum logic gate for solving the fidelity of two different quantum states, the determining unit 601 is configured to:

[0103] The SWAP test logic gate is identified as the fourth quantum logic gate for solving the fidelity of two different quantum states.

[0104] Optionally, the data bit includes a first quantum bit and a second quantum bit, the SWAP test logic gate includes an H gate and a controlled SWAP gate, and in terms of applying the fourth quantum logic gate to the data bit and the preset auxiliary bit, the applying unit 602 is specifically configured to:

[0105] The H gate is applied to a preset auxiliary bit, the controlled SWAP gate is applied to the auxiliary bit, the first quantum bit, and the second quantum bit corresponding to the first quantum bit, and the H gate is applied to the auxiliary bit again. The control bit of the controlled SWAP gate is the auxiliary bit.

[0106] Optionally, in the aspect of applying the first quantum logic gate to a data bit, the applying unit 602 is specifically configured to:

[0107] The first quantum logic gate is applied to each of the first quantum bits respectively.

[0108] Optionally, in the aspect of applying the second quantum logic gate to a data bit, the applying unit 602 is specifically configured to:

[0109] The second quantum logic gate acts on every two adjacent first quantum bits.

[0110] Optionally, in the aspect of applying the third quantum logic gate to a data bit, the applying unit 602 is specifically configured to:

[0111] The third quantum logic gate is applied to every two adjacent first quantum bits.

[0112] Optionally, in determining the first quantum logic gate for performing a superposition operation on the quantum state of a single quantum bit, the determining unit 601 is specifically configured to:

[0113] The RY gate was identified as the first quantum logic gate that performs a superposition operation on the quantum state of a single qubit.

[0114] Optionally, in determining the second quantum logic gate for performing a superposition operation on the quantum states of two quantum bits, the determining unit 601 is specifically configured to:

[0115] Get four RX gates, two CNOT gates and one RZ gate;

[0116] The output items of two of the RX gates are used as input items of one of the CNOT gates, one of the output items of one of the CNOT gates is used as input items of the RZ gate, the other output item of one of the CNOT gates and the output item of the RZ gate are used as input items of another CNOT gate, and the two output items of the other CNOT gate are respectively used as input items of the other two RX gates, to obtain a second quantum logic gate that performs a superposition operation on the quantum state of two quantum bits.

[0117] Optionally, in determining the third quantum logic gate for performing an entanglement operation on the quantum state of two quantum bits, the determining unit 601 is specifically configured to:

[0118] The controlled RY gate is identified as a third quantum logic gate that performs entanglement operations on the quantum states of two qubits.

[0119] Compared with the prior art, the present invention determines a first quantum logic gate for performing a superposition operation on the quantum state of a single quantum bit, determines a second quantum logic gate for performing a superposition operation on the quantum state of two quantum bits, determines a third quantum logic gate for performing an entanglement operation on the quantum state of the two quantum bits, and determines a fourth quantum logic gate for solving the fidelity of two different quantum states;

[0120] The first, second, and third quantum logic gates are applied to data bits, and the fourth quantum logic gate is applied to the data bits and preset auxiliary bits to obtain a quantum discriminator. This quantum discriminator can be used to construct a quantum GAN or a quantum-classical hybrid GAN, thereby utilizing the characteristics of quantum superposition to efficiently process mathematical problems and address the issues of large GAN computational complexity and convergence failure during training.

[0121] The embodiment of the present invention further provides a storage medium, wherein the storage medium stores a computer program, wherein the computer program is configured to execute the above-mentioned Figure 2 The steps of any one of the method embodiments.

[0122] Specifically, in this embodiment, the above-mentioned storage medium may be configured to store a computer program for performing the following steps:

[0123] determining a first quantum logic gate for performing a superposition operation on a quantum state of a single qubit, determining a second quantum logic gate for performing a superposition operation on a quantum state of two qubits, determining a third quantum logic gate for performing an entanglement operation on the quantum state of the two qubits, and determining a fourth quantum logic gate for solving the fidelity of two different quantum states;

[0124] The first quantum logic gate, the second quantum logic gate, and the third quantum logic gate are applied to data bits, and the fourth quantum logic gate is applied to the data bits and a preset auxiliary bit to obtain a quantum discriminator.

[0125] Specifically, in this embodiment, the above-mentioned storage medium may include but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store computer programs.

[0126] Yet another embodiment of the present invention provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above method embodiments.

[0127] Specifically, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0128] Specifically, in this embodiment, the processor may be configured to execute the following steps through a computer program:

[0129] determining a first quantum logic gate for performing a superposition operation on a quantum state of a single qubit, determining a second quantum logic gate for performing a superposition operation on a quantum state of two qubits, determining a third quantum logic gate for performing an entanglement operation on the quantum state of the two qubits, and determining a fourth quantum logic gate for solving the fidelity of two different quantum states;

[0130] The first quantum logic gate, the second quantum logic gate, and the third quantum logic gate are applied to data bits, and the fourth quantum logic gate is applied to the data bits and a preset auxiliary bit to obtain a quantum discriminator.

[0131] The above describes in detail the structure, features and effects of the present invention based on the embodiments shown in the drawings. The above is only a preferred embodiment of the present invention, but the scope of implementation of the present invention is not limited to what is shown in the drawings. Any changes made in accordance with the concept of the present invention, or modifications to equivalent embodiments with equivalent changes, which do not exceed the spirit covered by the description and drawings, should be within the scope of protection of the present invention.

Claims

1. A method for constructing a quantum discriminator, characterized in that: The method comprises: Determine a first quantum logic gate that performs a superposition operation on the quantum state of a single quantum bit, obtain four RX gates, two CNOT gates, and one RZ gate, use the output items of two of the RX gates as input items of one of the CNOT gates, use one output item of one of the CNOT gates as input item of the RZ gate, use the other output item of one of the CNOT gates and the output item of the RZ gate as input items of another CNOT gate, and use the two output items of another CNOT gate as input items of two other RX gates, respectively, to obtain a second quantum logic gate that performs a superposition operation on the quantum state of two quantum bits, determine a third quantum logic gate that performs an entanglement operation on the quantum state of the two quantum bits, and determine a SWAP test logic gate for solving the fidelity of two different quantum states, wherein the SWAP test logic gate includes an H gate and a controlled SWAP gate; The first quantum logic gate is applied to each first quantum bit, the second quantum logic gate is applied to every two adjacent first quantum bits, the third quantum logic gate is applied to every two adjacent first quantum bits, the H gate is applied to a preset auxiliary bit, the controlled SWAP gate is applied to the auxiliary bit, the first quantum bit, and the second quantum bit corresponding to the first quantum bit, the H gate is applied to the auxiliary bit again, and the control bit of the controlled SWAP gate is the auxiliary bit, to obtain a quantum discriminator.

2. The method according to claim 1, wherein The determining of a first quantum logic gate for performing a superposition operation on a quantum state of a single quantum bit comprises: The RY gate was identified as the first quantum logic gate that performs a superposition operation on the quantum state of a single qubit.

3. The method according to claim 1, wherein The determining of a third quantum logic gate for performing an entanglement operation on the quantum states of the two quantum bits includes: The controlled RY gate is identified as a third quantum logic gate that performs entanglement operations on the quantum states of two qubits.

4. A device for constructing a quantum discriminator, characterized in that: The device comprises: a determination unit, configured to determine a first quantum logic gate that performs a superposition operation on a quantum state of a single quantum bit, obtain four RX gates, two CNOT gates, and one RZ gate, use output items of two of the RX gates as input items of one of the CNOT gates, use one output item of one of the CNOT gates as an input item of the RZ gate, use another output item of one of the CNOT gates and the output item of the RZ gate as input items of another CNOT gate, and use two output items of another CNOT gate as input items of two other RX gates, respectively, to obtain a second quantum logic gate that performs a superposition operation on the quantum state of two quantum bits, determine a third quantum logic gate that performs an entanglement operation on the quantum state of the two quantum bits, and determine a SWAP test logic gate for solving the fidelity of two different quantum states, wherein the SWAP test logic gate includes an H gate and a controlled SWAP gate; an action unit, configured to apply the first quantum logic gate to each first qubit, apply the second quantum logic gate to every two adjacent first qubits, apply the third quantum logic gate to every two adjacent first qubits, apply the H gate to a preset auxiliary bit, apply the controlled SWAP gate to the auxiliary bit, the first qubit, and a second qubit corresponding to the first qubit, apply the H gate again to the auxiliary bit, and wherein the control bit of the controlled SWAP gate is the auxiliary bit, thereby obtaining a quantum discriminator.

5. A storage medium, characterized in that: The storage medium stores a computer program, wherein the computer program is configured to execute the method according to any one of claims 1 to 3 when executed.

6. An electronic device comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to run the computer program to perform the method according to any one of claims 1 to 3.

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