Packaging method

Abstract

This application discloses a packaging method, which includes: applying soldering material to first pads on a carrier substrate; providing a chip, wherein a first insulating layer is formed on the functional surface of the chip, the first insulating layer has an opening region to expose at least a second pad on the chip, wherein a first height of the first insulating layer protruding from the second pad is greater than a second height of the soldering material, and the difference between the first height and the second height is within a preset range; flip-chip bonding the chip onto the carrier substrate so that the soldering material is accommodated in the opening region on the first insulating layer; and reflow soldering the carrier substrate with the flip-chip bonded to electrically connect the first pad to the second pad through the soldering material. The packaging method provided by this application can improve production efficiency and reduce the thickness of the formed package.

Description

Technical Field

[0001] This application relates to the field of packaging technology, and in particular to a packaging method. Background Technology

[0002] Currently, for chips with solder joints on the same side, the common packaging method is to first fix the chip to the metal frame with insulating glue, then use bonding to connect the solder joints on the chip to the pads on the metal frame, and finally use resin to encapsulate the entire chip.

[0003] The inventors of this application have discovered that the packaged products formed by the above-mentioned packaging method are large in size, which does not meet the market demand for smaller and thinner products. Therefore, a more advanced packaging method is needed to achieve this. Summary of the Invention

[0004] The main technical problem addressed by this application is to provide a packaging method that can improve production efficiency and reduce the thickness of the formed package.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing a packaging method, the method comprising: coating a soldering material on a first pad of a carrier board; providing a chip, wherein a first insulating layer is formed on the functional surface of the chip, the first insulating layer has an opening area to at least expose a second pad on the chip, wherein a first height of the first insulating layer protruding from the second pad is greater than a second height of the soldering material, and the difference between the first height and the second height is within a preset range; flip-chip bonding the chip onto the carrier board so that the soldering material is accommodated in the opening area on the first insulating layer; and performing a reflow soldering process on the carrier board with the flip-chip bonded, so that the first pad is electrically connected to the second pad through the soldering material.

[0006] The step of providing chips includes: covering the front side of a wafer with a second insulating layer; patterning the second insulating layer to expose a third pad on the front side of the wafer; and dicing the wafer to obtain a plurality of chips.

[0007] The welding material includes at least one of conductive adhesive, solder paste, and solder pads.

[0008] The method further includes, before applying soldering material to the first pad of the carrier board, the following steps: sequentially depositing a dielectric layer and a second conductive layer on the first conductive layer; patterning the second conductive layer to form the first pad, thereby obtaining the carrier board.

[0009] The step of sequentially disposing a dielectric layer and a second conductive layer on the first conductive layer includes: disposing the dielectric layer on the first conductive layer; forming a via on the dielectric layer to expose the first conductive layer; filling the via with a conductive material; and forming the second conductive layer on the side of the dielectric layer away from the first conductive layer, so that the second conductive layer is electrically connected to the first conductive layer through the conductive material in the via.

[0010] The step of sequentially disposing a dielectric layer and a second conductive layer on the first conductive layer includes: fixing the first conductive layer to a support plate; and sequentially forming the dielectric layer and the second conductive layer electrically connected to the first conductive layer on the side of the first conductive layer away from the support plate.

[0011] The process further includes, after reflow soldering the carrier board on which the flip chip is mounted, removing the support plate and patterning the first conductive layer of the carrier board to form a fourth pad electrically connected to the first pad.

[0012] The step of fixing the first conductive layer to the support plate includes: fixing the first conductive layer to the support plate by means of an adhesive material.

[0013] The adhesive material is adhesive tape.

[0014] The process further includes, after reflow soldering the carrier board on which the flip chip is mounted, forming a plastic encapsulation layer on the side of the carrier board where the chip is located; and cutting between two adjacent chips on the carrier board to obtain multiple packages.

[0015] The beneficial effects of this application are as follows: This application pre-coats the soldering material onto the first pad of the carrier board, which reduces the difficulty of picking up the chip compared to pre-coating it onto the second pad of the chip (if the soldering material is coated on the chip, displacement or falling of the soldering material must be avoided when picking up the chip), thereby improving production efficiency. At the same time, the first height of the first insulating layer protruding from the second pad is greater than the second height of the soldering material, and the difference between the first height and the second height is within a preset range. This can avoid problems such as leakage and short circuit caused by the soldering material overflowing into the opening area during the soldering process, and can also avoid phenomena such as poor soldering and internal collapse caused by insufficient soldering material. In addition, the flip-chip method of mounting the chip on the substrate can reduce the thickness of the final packaged product and give the package better heat dissipation performance. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0017] Figure 1 This is a flowchart illustrating one embodiment of the packaging method of this application;

[0018] Figure 2 It corresponds Figure 1 Partial preparation process diagram;

[0019] Figure 3 yes Figure 2 The subsequent process diagram;

[0020] Figure 4 yes Figure 3 The subsequent process diagram;

[0021] Figure 5 yes Figure 3 A diagram illustrating the chip fabrication process. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0023] See Figures 1 to 4 The packaging method of this application includes:

[0024] S110: Apply soldering material 1102 to the first pad 1101 of the carrier board 1100.

[0025] Specifically, soldering material 1102 is formed on the first pad 1101 by coating. Soldering material 1102 includes at least one of conductive adhesive, solder paste, and solder pad. That is, soldering material 1102 can be one of conductive adhesive, solder paste, and solder pad, or it can be a combination of any two or three of conductive adhesive, solder paste, and solder pad.

[0026] In one application scenario, in order to ensure that the final packaged product is thinner, the method for preparing the carrier board 1100 includes: sequentially depositing a dielectric layer 1120 and a second conductive layer 1130 on the first conductive layer 1110; patterning the second conductive layer 1130 to form a first pad 1101, thereby obtaining the carrier board 1100.

[0027] Specifically, the dielectric layer 1120 mainly serves a supporting function, and its material can be any insulating material that can be used as a circuit board substrate. For example, the material of the dielectric layer 1120 can be a reinforcing material (e.g., paper, textiles, glass cloth, glass non-woven fabric, etc.) impregnated with resin (phenolic, epoxy, polyimide, etc.) to form a circuit board.

[0028] The first conductive layer 1110 and the second conductive layer 1130 may be made of the same or different materials. For example, the first conductive layer 1110 and the second conductive layer 1130 may both be made of copper, such as copper foil.

[0029] The first pad 1101 can be formed by laser ablation of the second conductive layer 1130 or by chemical etching; there are no restrictions on this.

[0030] It is understandable that the carrier plate 1100 obtained by the above method is different from the metal frame in the prior art. It is an ultra-thin carrier plate, which can reduce the thickness of the final packaged product.

[0031] In one application scenario, the steps of sequentially setting a dielectric layer 1120 and a second conductive layer 1130 on a first conductive layer 1110 specifically include: setting a dielectric layer 1120 on the first conductive layer 1110; forming a via 1121 on the dielectric layer 1120 to expose the first conductive layer 1110; filling the via 1121 with a conductive material 11211; and forming a second conductive layer 1130 on the side of the dielectric layer 1120 away from the first conductive layer 1110, so that the second conductive layer 1130 is electrically connected to the first conductive layer 1110 through the conductive material 11211 in the via 1121.

[0032] Specifically, the via 1121 can be formed by laser ablation or chemical etching, etc. Meanwhile, the conductive material 11211 filling the via 1121 can be the same as the material of the first conductive layer 1110 and the second conductive layer 1130. For example, the materials of the first conductive layer 1110, the conductive material 11211 filling the via 1121, and the second conductive layer 1130 are all copper.

[0033] Continue reading Figure 1 In one application scenario, considering that the first conductive layer 1110 is relatively thin and its support capacity is not strong, in order to facilitate the subsequent formation of the dielectric layer 1120 and the second conductive layer 1130 on the first conductive layer 1110, in one application scenario, the first conductive layer 1110 is fixed on the support plate 1140, and then the dielectric layer 1120 and the second conductive layer 1130 electrically connected to the first conductive layer 1110 are formed sequentially on the side of the first conductive layer 1110 away from the support plate 1140.

[0034] Specifically, the support plate 1140 can be any plate with supporting capabilities, such as a steel plate, a wooden board, etc.

[0035] Meanwhile, to facilitate the subsequent removal of the support plate 1140, the first conductive layer 1110 can be fixed to the support plate 1140 with an adhesive material. For example, the adhesive material is tape, and the tape is not a high-temperature tape that is resistant to high temperatures. Alternatively, the adhesive material can be a liquid adhesive, and the first conductive layer 1110 can be fixed to the support plate 1140 by curing the liquid adhesive.

[0036] S120: A chip 1200 is provided, and a first insulating layer 1210 is formed on the functional surface of the chip 1200. The first insulating layer 1210 has an opening region 1211 to at least expose a second pad 1220 on the chip 1200. The first height of the first insulating layer 1210 protruding from the second pad 1220 is greater than the second height of the soldering material 1102, and the difference between the first height and the second height is within a preset range.

[0037] In one application scenario, refer to Figure 5 Step S120 specifically includes: covering the front side of the wafer 1300 with a second insulating layer 1310; patterning the second insulating layer 1310 to expose the third pad 1320 on the front side of the wafer 1300; and dicing the wafer 1300 to obtain multiple chips 1200.

[0038] Specifically, firstly, a liquid insulating material (e.g., resin) is coated on the front side of the wafer 1300, and then the liquid insulating material is cured to form a second insulating layer 1310 (or a film-like second insulating layer 1310 can be directly covered on the front side of the wafer 1300). Next, an opening region 1211 is formed on the second insulating layer 1310 by means such as exposure and development (or the opening region 1211 can be formed by laser ablation or mechanical cutting). The formed opening region 1211 exposes part or all of the third pad 1320 on the wafer 1300. Finally, the wafer 1300 is cut along the dicing track (not shown) to obtain multiple chips 1200.

[0039] In other application scenarios, the wafer 1300 can be cut first, and then the second insulating layer 1310 and the opening region 1211 can be formed on the second insulating layer 1310.

[0040] S130: The chip 1200 is flip-chipped onto the carrier 1100 so that the solder material 1102 is contained within the opening region 1211 on the first insulating layer 1210.

[0041] Specifically, the first insulating layer 1210 is provided to protect the functional surface of the chip 1200 and prevent the chip 1200 from being scratched during the flip-chip mounting process on the carrier board 1100. On the other hand, it can confine the soldering material 1102 within the opening area 1211 to prevent the subsequent soldering material 1102 from overflowing and causing problems such as leakage and short circuit.

[0042] Meanwhile, the first height of the first insulating layer 1210 protruding from the second pad 1220 is greater than the second height of the welding material 1102, and the difference between the first height and the second height is within a preset range. This can prevent the welding material 1102 from overflowing into the opening area 1211 and causing problems such as leakage and short circuit, and can also prevent phenomena such as poor soldering and internal collapse caused by insufficient welding material 1102.

[0043] S140: Reflow soldering is performed on the carrier board 1100 with the flip-chip 1200 so that the first pad 1101 is electrically connected to the second pad 1220 through the soldering material 1102.

[0044] Specifically, the carrier board 1100 with the flip-chip 1200 is placed in a reflow oven for reflow soldering, so that the chip 1200 is fixed on the carrier board 1100, and the first pad 1101 is electrically connected to the second pad 1220 through the soldering material 1102.

[0045] S150: A molding layer 1400 is formed on the side of the carrier board 1100 where the chip 1200 is disposed, encapsulating the chip 1200.

[0046] Specifically, the formed molding layer 1400 is used to protect the various surfaces of the chip 1200. The material of the molding layer 1400 can be epoxy resin, ceramic, or other materials, and there are no restrictions on this.

[0047] In one application scenario, when the first conductive layer 1110 is fixed using the support plate 1140, after the molding compound 1400 is formed, the support plate 1140 is removed and the first conductive layer 1110 of the pattern substrate 1100 is patterned to form a fourth pad 1111 that is electrically connected to the first pad 1101.

[0048] When the first conductive layer 1110 is fixed to the support plate 1140 using an adhesive material, the support plate 1140, the adhesive material and the first conductive layer 1110 can be separated directly, or the adhesiveness of the adhesive material can be reduced by means of light irradiation, and then the support plate 1140, the adhesive material and the first conductive layer 1110 can be separated.

[0049] Meanwhile, the second conductive layer 1130 of the pattern is in the same manner as the first conductive layer 1110 of the pattern described above. For details, please refer to the above embodiments, which will not be repeated here.

[0050] S160: Cut between two adjacent chips 1200 on the carrier board 1100 to obtain multiple packages 1500.

[0051] Specifically, the method of cutting the carrier plate 1100 is not limited to mechanical cutting, laser cutting, etc.

[0052] Meanwhile, the package 1500 prepared by the above packaging method can be applied to the consumer electronics field.

[0053] In the above embodiment, during the packaging process, the soldering material 1102 is pre-coated on the first pad 1101 of the carrier board 1100. Compared with pre-coating it on the second pad 1220 of the chip 1200, this reduces the difficulty of picking up the chip 1200 (if the soldering material 1102 is coated on the chip 1200, displacement or falling of the soldering material 1102 must be avoided when picking up the chip 1200), thereby improving production efficiency. At the same time, the first height of the first insulating layer 1210 protruding from the second pad 1220 is greater than the second height of the soldering material 1102, and the difference between the first height and the second height is within a preset range. This can avoid problems such as leakage and short circuit caused by the soldering material 1102 overflowing into the opening area 1211 during the soldering process, and can also avoid phenomena such as poor soldering and internal collapse caused by insufficient soldering material 1102. In addition, the flip-chip method is used to mount the chip on the substrate, which can reduce the thickness of the final packaged product and give the package better heat dissipation performance.

[0054] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A packaging method, characterized in that, The method includes: The first conductive layer is fixed to the upward-facing support plate; A dielectric layer and a second conductive layer electrically connected to the first conductive layer are sequentially formed on the side of the first conductive layer away from the support plate. The second conductive layer is patterned to form the first pad, thereby obtaining the carrier board; Apply soldering material to the upper surface of the first pad of the carrier board, with the soldering material facing upwards; A chip is provided, wherein a first insulating layer is formed on the functional surface of the chip, the first insulating layer has an opening area to expose at least a second pad on the chip, wherein a first height of the first insulating layer protruding from the second pad is greater than a second height of the soldering material, and the difference between the first height and the second height is within a preset range; The chip is flipped over the carrier board so that the soldering material enters the opening area from bottom to top and is accommodated in the opening area on the first insulating layer; The carrier board on which the flip chip is mounted is reflow soldered so that the first pad is electrically connected to the second pad through the soldering material.

2. The packaging method according to claim 1, characterized in that, The step of providing the chip includes: A second insulating layer is applied to the front side of the wafer; The pattern of the second insulating layer exposes the third pad on the front side of the wafer; The wafer is diced to obtain multiple chips.

3. The packaging method according to claim 1, characterized in that, The welding material includes at least one of conductive adhesive, solder paste, and solder pads.

4. The packaging method according to claim 1, characterized in that, The step of sequentially forming a dielectric layer and a second conductive layer electrically connected to the first conductive layer on the side of the first conductive layer away from the support plate includes: The dielectric layer is disposed on the first conductive layer; A via is formed on the dielectric layer to expose the first conductive layer; The via is filled with conductive material; A second conductive layer is formed on the side of the dielectric layer away from the first conductive layer, so that the second conductive layer is electrically connected to the first conductive layer through the conductive material in the via.

5. The packaging method according to claim 4, characterized in that, After the reflow soldering process is performed on the carrier board on which the flip-chip is mounted, the process further includes: Remove the support plate; The first conductive layer of the substrate shown in the pattern forms a fourth pad that is electrically connected to the first pad.

6. The packaging method according to claim 1, characterized in that, The step of fixing the first conductive layer to the upward-facing support plate includes: The first conductive layer is fixed to the support plate using an adhesive material.

7. The packaging method according to claim 6, characterized in that, The adhesive material is tape.

8. The packaging method according to claim 1, characterized in that, After the reflow soldering process is performed on the carrier board on which the flip-chip is mounted, the process further includes: A plastic encapsulation layer is formed on the side of the carrier board where the chip is disposed; The carrier board is cut between two adjacent chips to obtain multiple packages.

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