Semiconductor memory structure and fabrication method

Abstract

The application discloses a semiconductor memory structure and a preparation method, which can eliminate the recesses in the process of filling the trench with multiple material layers and improve the yield of the semiconductor memory. The semiconductor memory structure comprises a substrate, at least one first trench on the upper surface of the substrate, and an arc-shaped edge angle at the top of the first trench; a first dielectric layer is distributed along the inner wall of the first trench; a second dielectric layer is formed on the surface of the first dielectric layer and fills the first trench; the top of the first dielectric layer is lower than the top of the second dielectric layer and the upper surface of the substrate, so that a first recess is formed between the second dielectric layer and the substrate; and a metal filling layer is located in the first recess and fills part of the space in the first recess.

Description

Technical Field

[0001] This application relates to the field of semiconductor memory structures, specifically to semiconductor memory structures and fabrication methods. Background Technology

[0002] In the manufacturing process of semiconductor memories, it is usually necessary to form trenches on the substrate surface and fill the trenches with other material layers. During the filling of these material layers, it is possible for issues such as… Figure 1 As shown, unwanted grooves appear on the substrate surface. Please refer to [link / reference]. Figure 1 The trench containing the shallow trench isolation structure is sequentially filled with a first material layer 103, a second material layer 104, and a third material layer 105. The top height of the first material layer 103 is lower than the surface height of the substrate 101 and the top height of the second material layer 104, resulting in a groove 102 between the second material layer 104 and the substrate 101. These grooves 102 are difficult to fill and level in the subsequent semiconductor memory manufacturing process, and may collapse as the material layers accumulate during the subsequent semiconductor memory manufacturing process, affecting the flatness of the semiconductor memory and thus affecting the yield of the semiconductor memory. Summary of the Invention

[0003] In view of this, this application provides a semiconductor memory structure and fabrication method that can eliminate the grooves that occur during the process of filling multiple material layers in the trench, thereby improving the yield of the semiconductor memory.

[0004] This application provides a semiconductor memory structure, comprising: a substrate; at least one first trench located on the upper surface of the substrate, wherein the top edge corner of the first trench is arc-shaped; a first dielectric layer distributed along the inner wall of the first trench; a second dielectric layer formed on the surface of the first dielectric layer and filling the first trench; the top of the first dielectric layer being lower than the top of the second dielectric layer and the upper surface of the substrate, thereby forming a first groove between the second dielectric layer and the substrate; and a metal filling layer located within the first groove, filling a portion of the space within the first groove.

[0005] Optionally, it may also include: a third dielectric layer located above the metal filler layer and within the first groove, filling the first groove.

[0006] Optionally, the second dielectric layer includes a first sublayer and a second sublayer, wherein the first sublayer is formed on the surface of the first dielectric layer, the second sublayer is formed on the surface of the first sublayer, and fills the first trench.

[0007] Optionally, the first dielectric layer comprises an oxide dielectric layer, and / or the second dielectric layer comprises a nitride dielectric layer.

[0008] Optionally, the first sub-layer comprises a nitride dielectric layer, and the second sub-layer comprises an oxide dielectric layer.

[0009] Optionally, a fourth dielectric layer is further included, which covers the inner wall of the first recess and fills part of the space of the first recess.

[0010] Optionally, an insulating layer is further included, which is formed above the top of the second dielectric layer, above the top of the metal filling layer, and on the upper surface of the substrate.

[0011] Optionally, a gate stack structure is further included, which is formed above the top of the substrate, and / or a load stack structure is further included, which is formed above the top of the second dielectric layer.

[0012] Optionally, the gate stack structure at least comprises a first polysilicon layer, a first conductive layer, and a first mask layer, which are sequentially distributed upwards along the direction perpendicular to the upper surface of the substrate, and / or the load stack structure comprises a second polysilicon layer, a second conductive layer, and a second mask layer, which are sequentially distributed upwards along the direction perpendicular to the upper surface of the substrate.

[0013] Optionally, the preparation material of the metal filling layer is the same as that of the first conductive layer and the second conductive layer.

[0014] The application provides a preparation method of a semiconductor memory structure, comprising the following steps: providing a substrate, of which the upper surface is formed with a first groove; sequentially forming a first dielectric material layer and a second dielectric material layer along the inner wall of the first groove; partially removing the first dielectric material layer and the second dielectric material layer, so that the edge angle of the top of the first groove is in a circular arc shape, and the first dielectric layer and the second dielectric layer are respectively formed correspondingly, and the top of the first dielectric layer is lower than the top of the second dielectric layer and the upper surface of the substrate, thereby forming a first recess between the second dielectric layer and the substrate; forming a metal filling layer in the first recess to partially fill the first recess.

[0015] Optionally, after the step of forming the metal filling layer in the first recess, the method further comprises the following step: forming a third dielectric layer above the top of the metal filling layer, which fills the first recess.

[0016] Optionally, the step of partially removing the first dielectric material layer and the second dielectric material layer comprises the following step: using at least one of dry etching or wet etching to partially remove the first dielectric material layer and the second dielectric material layer, and the etching rate of the etching gas or etching liquid selected for the first dielectric material layer is greater than that for the second dielectric material layer.

[0017] Optionally, the second dielectric layer comprises a first sub-layer and a second sub-layer, and forming the second dielectric layer comprises the following steps: forming the first sub-material layer on the surface of the first dielectric layer; and forming the second sub-material layer on the surface of the first sub-material layer, and the second sub-material layer fills the first trench.

[0018] Optionally, before forming the metal filling layer in the first recess, the method further comprises the following step: forming a fourth dielectric layer on the inner wall of the first recess.

[0019] Optionally, forming the metal filling layer in the first recess comprises: forming a metal layer on the top of the second dielectric layer and on the upper surface of the substrate in the first recess, and the metal layer at least fills the first recess; and performing a back etching on the metal layer, and retaining the metal layer in the first recess as the metal filling layer.

[0020] Optionally, forming the third dielectric layer on the upper surface of the metal filling layer comprises: forming a dielectric material layer on the top of the metal filling layer, on the top of the second dielectric layer and on the upper surface of the substrate, and the dielectric material layer at least fills the first recess; and performing a back etching on the dielectric material layer, and retaining the dielectric material layer in the first recess as the third dielectric layer.

[0021] The semiconductor memory structure and the preparation method thereof of the present application fill part of the space of the first recess with a metal filling layer. Since the metal filling layer has a large strength and a certain ductility, after the first recess is filled with the metal filling layer, the probability of collapse of the first recess in the subsequent preparation process of the semiconductor memory structure is obviously reduced, which can effectively eliminate the undesired recess on the upper surface of the substrate and reduce the possibility of collapse of the filled first recess, thereby having a better recess filling effect and effectively improving the yield of the semiconductor memory structure.

[0022] In addition, since the first recess is filled with a metal material, in the subsequent preparation process of the semiconductor memory structure, the opacity and good light reflection performance of the metal filling layer can be used to position the boundary of the first trench, so as to determine the center position of the first trench, thereby achieving a better film layer alignment effect. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0024] Figure 1 The semiconductor memory structure is described in the prior art;

[0025] Figure 2 The semiconductor memory structure is described in the prior art;

[0026] Figures 3 to 16 The semiconductor memory structure is described in the prior art;

[0027] Figure 17 The semiconductor memory structure is described in the prior art;

[0028] Figure 18 The semiconductor memory structure is described in the prior art. DETAILED DESCRIPTION

[0029] The semiconductor memory structure and the preparation method thereof are further described below in combination with the accompanying drawings and embodiments.

[0030] The present application provides a preparation method of a semiconductor memory structure in a first aspect.

[0031] Please refer to Figures 2 to 16 , wherein Figure 2 The semiconductor memory structure is described in the prior art; Figures 3 to 16 The semiconductor memory structure is described in the prior art.

[0032] In this embodiment, the preparation method of the semiconductor memory structure includes the following steps: step S101: providing a substrate 201, a first trench 200 is formed on the upper surface of the substrate 201 (please refer to Figure 3 ); step S102: sequentially forming a first dielectric material layer 2031 (please refer to Figure 4 ), a second dielectric material layer along the inner wall of the first trench 200; step S103: partially removing the first dielectric material layer 2031 and the second dielectric material layer, so that the edge angle at the top of the first trench 200 is in a circular arc shape, and a first dielectric layer 203 and a second dielectric layer 204 are respectively formed, and the top of the first dielectric layer 203 is lower than the top of the second dielectric layer 204 and the upper surface of the substrate 201, thereby forming a first groove 202 between the second dielectric layer 204 and the substrate 201 (please refer to Figure 7 ); step S104: forming a metal filling layer 207 in the first groove 202 to partially fill the first groove 202 (please refer to Figure 10 ).

[0033] The method for preparing the semiconductor memory structure in the embodiment uses the metal filling layer 207 to fill the partial space of the first recess 202. Since the metal filling layer 207 has great strength and certain ductility, after the first recess 202 is filled by the metal filling layer 207, the probability of collapse of the first recess 202 in the subsequent process of preparing the semiconductor memory structure is obviously reduced, which can effectively eliminate the undesired recess on the upper surface of the substrate 201 and reduce the possibility of collapse of the filled first recess 202, thereby having better recess filling effect and effectively improving the yield of the semiconductor memory structure.

[0034] In addition, since the first recess 202 is filled by metal, in the subsequent process of preparing the semiconductor memory structure, the opacity and good light reflection performance of the metal filling layer can be used to position the boundary of the first trench 200 and determine the center position of the first trench 200, thereby achieving better film layer alignment effect.

[0035] In some embodiments, after the metal filling layer 207 is formed in the first recess 202, the method further includes the following steps: forming a third dielectric layer 208 above the top of the metal filling layer 207, and the third dielectric layer 208 fills the first recess 202 (see Figure 12 ).

[0036] In these embodiments, the third dielectric layer 208 is also used to fill the remaining part of the first recess 202, which can effectively isolate the metal filling layer 207 from the electrical connection with other conductive structures, thereby achieving certain insulation effect and preventing the metal filling layer 207 from shorting with other conductive structures and causing damage to the semiconductor memory structure.

[0037] In some embodiments, the partial removal of the first dielectric material layer 2031 and the second dielectric material layer includes the following steps: at least one of dry etching or wet etching is used to partially remove the first dielectric material layer 2031 and the second dielectric material layer, and the etching rate of the etching gas or etching liquid selected for the first dielectric material layer 2031 is greater than that for the second dielectric material layer, so that the top height of the first dielectric layer 203 formed after etching is lower than the top height of the second dielectric layer 204.

[0038] In some embodiments, the partially removing the first dielectric material layer 2031 and the second dielectric material layer further comprises the following steps: forming a third mask layer 2080 on the top surface of the first dielectric layer 203, the third mask layer 2080 is patterned to expose the first dielectric material layer 2031 and the second dielectric material layer filled in the first trench 200, and a portion of the first dielectric material layer 2031 at the edge of the first trench 200, so that the etching gas or etching liquid can only etch the first trench 200 and the edge of the first trench 200, to obtain the desired shape, please refer to Figure 6 .

[0039] In some further embodiments, the etching rate of the etching gas or etching liquid on the first dielectric material layer 2031 is greater than the etching rate on the substrate 201, so that after etching, the top height of the first dielectric layer 203 formed is also lower than the height of the top surface of the substrate 201, please refer to Figure 7 .

[0040] In some embodiments, the second dielectric layer 204 comprises a first sub-layer 205 and a second sub-layer 206, and forming the second dielectric layer 204 comprises the following steps: forming the first sub-material layer 2051 on the surface of the first dielectric layer 203; forming the second sub-material layer 2061 on the surface of the first sub-material layer 2051, and the second sub-material layer 2061 fills the first trench 200, please refer to Figure 5 .

[0041] In the embodiment shown in Figure 7 , the first dielectric layer 203 comprises an oxide dielectric layer, the first sub-layer 205 comprises a nitride dielectric layer, and the second sub-layer 206 comprises an oxide dielectric layer. After etching, the top of the first sub-layer 205 is higher than the top of the first dielectric layer 203, and also higher than the top of the second sub-layer 206. The middle region of the filler in the first trench 200 is concave.

[0042] In the embodiment shown in Figure 18 , the second dielectric layer 204 only comprises a single dielectric layer, and does not comprise multiple separate sub-layers. In some embodiments, the first dielectric layer 203 comprises an oxide dielectric layer, and the second dielectric layer 204 comprises a nitride dielectric layer.

[0043] Before forming the metal filling layer 207 in the first recess 202, the following steps are further included: forming a fourth dielectric layer 209 on the inner wall surface of the first recess 202, please refer to Figure 8 .

[0044] The fourth dielectric layer 209 is partially between the metal fill layer 207 and the substrate 201, which can be used to isolate the metal fill layer 207 from the substrate 201, prevent short circuit between the metal fill layer 207 and the substrate 201, and prevent the semiconductor memory structure from being damaged due to the metal fill layer 207.

[0045] The forming of the metal fill layer 207 in the first recess 202 includes forming a metal layer 2071 in the first recess 202, on top of the second dielectric layer 204, and on the top surface of the substrate 201, the metal layer 2071 at least fills the first recess 202, see Figure 9 ; and performing a back etching on the metal layer 2071, and retaining the metal layer 2071 in the first recess 202 as the metal fill layer 207, see Figure 10 .

[0046] In some embodiments, the metal layer 2071 is formed in the first recess 202 by at least one of physical vapor deposition, chemical vapor deposition, etc. The back etching on the metal layer 2071 can be performed by at least one of dry etching or wet etching. The back etching method used has a high etching selectivity ratio for the fourth dielectric layer 209 and the metal layer 2071.

[0047] The forming of the third dielectric layer 208 on the top surface of the metal fill layer 207 includes forming a dielectric material layer 2081 on top of the metal fill layer 207, on top of the second dielectric layer 204, and on the top surface of the substrate 201, the dielectric material layer 2081 at least fills the first recess 202, see Figure 11 ; and performing a back etching on the dielectric material layer 2081, and retaining the dielectric material layer 2081 in the first recess 202 as the third dielectric layer 208, see Figure 12 .

[0048] In some embodiments, the dielectric material layer 2081 is prepared by at least one of physical vapor deposition, chemical vapor deposition, or atomic layer deposition, etc. The dielectric material layer 2081 includes a silicon nitride layer, etc. The third dielectric layer 208 can be used to isolate the metal fill layer 207 from other conductive structures, thus having an insulating effect, preventing the metal fill layer 207 from short circuiting with other conductive structures, and causing the semiconductor memory structure to be damaged.

[0049] In some embodiments, the preparation method further includes preparing a gate stack structure 300 on the top surface of the substrate 201. See Figure 13On the surface of the fourth dielectric layer 209 and the surface of the third dielectric layer 208, a first polysilicon layer 210, a first conductive layer 211 and a first mask layer 212 in the gate stack structure 300 are sequentially formed on the surface of the substrate 201. Then, refer to Figure 14 A fourth mask layer 213 is formed on the surface of the first mask layer 212, and the patterned fourth mask layer 213 exposes the first mask layer 212 above the first trench 200.

[0050] Then, refer to Figure 15 The first mask layer 212, the first conductive layer 211 and the first polysilicon layer 210 are etched in a direction perpendicular to the first mask layer 212, so as to expose the fourth dielectric layer 209. Refer to Figure 16 An insulating layer 214 is further formed on the surface of the exposed fourth dielectric layer 209, so as to complete the preparation of the gate stack structure 300. The insulating layer 214 includes a silicon oxide layer.

[0051] In some embodiments, the preparation method further includes preparing a load stack structure 301 above the top of the second dielectric layer, so as to make the gate stack structure 300 have a better etching loading effect. The first recess 202 filled with the metal filling layer is used for positioning when the load stack structure 301 is prepared.

[0052] Specifically, the first mask layer 212 and the second mask layer 2121 are formed by partially removing the same mask material layer, the first conductive layer 211 and the second conductive layer 2111 are formed by partially removing the same conductive material layer, and the first polysilicon layer 210 and the second polysilicon layer 2101 are formed by partially removing the same polysilicon material layer. Therefore, only the patterned mask layer on the uppermost mask material layer is needed to be formed, and the area corresponding to the position marked by the metal filling layer is exposed, so as to form the load stack structure 301 and the gate stack structure 300.

[0053] The first patterned photomask needs to expose the area corresponding to the metal filling layer.

[0054] In some embodiments, the load stack structure 301 includes a second polysilicon layer, a second conductive layer and a second mask layer which are sequentially distributed in a direction perpendicular to the surface of the substrate. Refer to Figure 17 .

[0055] The present application provides a semiconductor memory structure in the second aspect.

[0056] Please refer to Figure 12Fig. 1 is a schematic view of a semiconductor memory structure according to an embodiment of the present application.

[0057] In this embodiment, the semiconductor memory structure comprises a substrate 201, at least one first trench 200 on the top surface of the substrate 201, and the edge of the top of the first trench 200 is arc-shaped; a first dielectric layer 203 distributed along the inner wall of the first trench 200; a second dielectric layer 204 formed on the surface of the first dielectric layer 203 and filling the first trench 200; the top of the first dielectric layer 203 is lower than the top of the second dielectric layer 204 and the top surface of the substrate 201, so that a first groove 202 is formed between the second dielectric layer 204 and the substrate 201; and a metal filling layer 207 in the first groove 202, filling part of the space in the first groove 202.

[0058] The semiconductor memory structure of the present application uses the metal filling layer 207 to fill part of the space of the first groove 202. Since the metal filling layer 207 has great strength and certain ductility, after the first groove 202 is filled with the metal filling layer 207, the probability of collapse of the first groove 202 in the subsequent semiconductor memory structure preparation process is significantly reduced, which can effectively eliminate the undesired groove on the top surface of the substrate 201 and reduce the possibility of collapse of the filled first groove 202, thereby having better groove filling effect and effectively improving the yield of the semiconductor memory structure.

[0059] In addition, since the first groove 202 is filled with metal, the opacity and good light reflection performance of the metal filling layer can be used to position the boundary of the first trench 200 in the subsequent process of preparing the semiconductor memory structure, so as to determine the center position of the first trench 200 and achieve better film layer alignment effect.

[0060] In some other embodiments, the semiconductor memory structure further comprises a third dielectric layer 208 above the top of the metal filling layer 207 and in the first groove 202, filling the first groove 202.

[0061] The third dielectric layer 208 fills the remaining part of the first groove 202, which can effectively isolate the metal filling layer 207 from the electrical connection with other conductive structures, thereby achieving certain insulation effect and preventing the metal filling layer 207 from short-circuiting with other conductive structures, which may cause damage to the semiconductor memory structure.

[0062] In this embodiment, the first groove 200 is formed with an arc-shaped edge at the top of the first groove 200, instead of a sharp corner, to reduce the risk of electrical discharge at the sharp corner of the edge of the first groove 200.

[0063] In some embodiments, the method of forming the arc-shaped edge at the top of the first groove 200 includes forming the first groove 200 first, and then forming the first dielectric layer 203 and the second dielectric layer 204 along the inner wall of the first groove 200, and the first dielectric layer 203 is also formed on the upper surface of the substrate 201. Then, a photo mask is formed on the upper surface of the first dielectric layer 203, and the photo mask is patterned to expose the filler of the first groove 200 and a first portion of the first dielectric layer 203 on the upper surface of the substrate 201, and the first portion is distributed along the edge of the first groove 200. Then, the filler of the first groove 200 and the first portion of the first dielectric layer 203 on the upper surface of the substrate 201 are partially removed along the exposed area of the patterned photo mask, so as to achieve the arc-shaped treatment of the edge of the first groove 200.

[0064] In this embodiment, the first dielectric layer 203 and the second dielectric layer 204 are made of different materials.

[0065] In this embodiment, the first dielectric layer 203 and the second dielectric layer 204 are made of different materials. Figure 18 In the embodiment shown in the figure, the second dielectric layer 204 only includes a single dielectric layer, and does not include multiple individual sub-layers. In some embodiments, the first dielectric layer 203 includes an oxide dielectric layer, and the second dielectric layer 204 includes a nitride dielectric layer.

[0066] In the process of arc-shaped treatment, since the first dielectric layer 203 and the second dielectric layer 204 are made of different materials, the etching rate of the etching gas or etching liquid on the first dielectric layer 203 and the second dielectric layer 204 is also different. In this embodiment, the etching rate of the etching gas or etching liquid on the first dielectric layer 203 is greater than the etching rate of the etching gas or etching liquid on the second dielectric layer 204, and the etching rate of the etching gas or etching liquid on the first dielectric layer 203 is greater than the etching rate of the etching gas or etching liquid on the substrate 201. Figure 3 In the embodiment shown in the figure, the etching rate of the etching gas or etching liquid on the first dielectric layer 203 is greater than the etching rate of the etching gas or etching liquid on the second dielectric layer 204, and the etching rate of the etching gas or etching liquid on the first dielectric layer 203 is greater than the etching rate of the etching gas or etching liquid on the substrate 201. After etching, the height of the top of the first dielectric layer 203 is lower than the height of the top of the second dielectric layer 204, and is also lower than the height of the upper surface of the substrate 201.

[0067] In this embodiment, the etching rate of the etching gas or etching liquid on the first dielectric layer 203 is greater than the etching rate of the etching gas or etching liquid on the second dielectric layer 204, and the etching rate of the etching gas or etching liquid on the first dielectric layer 203 is greater than the etching rate of the etching gas or etching liquid on the substrate 201. Figure 12As shown, the second dielectric layer 204 includes a first sublayer 205 and a second sublayer 206. The first sublayer 205 is formed on the surface of the first dielectric layer 203, and the second sublayer 206 is formed on the surface of the first sublayer 205 and fills the first trench 200.

[0068] In some embodiments, the first dielectric layer 203 comprises an oxide dielectric layer, the first sublayer 205 comprises a nitride dielectric layer, and the second sublayer 206 comprises an oxide dielectric layer. After etching, the top of the first sublayer 205 is higher than the top of the first dielectric layer 203 and also higher than the top of the second sublayer 206, thus the central region of the filler in the first trench 200 is recessed.

[0069] In some other embodiments, the specific material of the second dielectric layer 204 may also be set as needed.

[0070] The semiconductor memory structure further includes a fourth dielectric layer 209, which covers the inner wall of the first groove 202 and the upper surface of the substrate 201, and fills a portion of the space in the first groove 202. The fourth dielectric layer 209 is partially located between the metal filler layer 207 and the substrate 201, and can be used to isolate the electrical connection between the metal filler layer 207 and the substrate 201, preventing short circuits between them, thereby preventing electrical damage to the semiconductor memory structure due to the metal filler layer 207.

[0071] In some other embodiments, the semiconductor memory structure further includes an insulating layer 214 formed over the second dielectric layer 204, over the metal filling layer 207, and on the upper surface of the substrate 201. Specifically, it is distributed in a portion of the upper surface of the substrate 201 and is located near the first trench 200.

[0072] In some other embodiments, a third dielectric layer 208 is also formed above the metal filler layer 207, and the insulating layer 214 is also located on top of the third dielectric layer 208.

[0073] In some embodiments, the semiconductor memory structure further includes: a gate stack structure 300 formed on top of the substrate, and / or: a load stack structure 301 formed on top of the second dielectric layer.

[0074] In some embodiments, the gate stack structure 300 includes at least a first polysilicon layer 210, a first conductive layer 211, and a first mask layer 212 that are sequentially distributed upward along a direction perpendicular to the upper surface of the substrate 201, for forming connection lines.

[0075] In some other embodiments, the load stack structure 301 includes a second polysilicon layer 2101, a second conductive layer 2111, and a second mask layer 2121 sequentially distributed upwards along a direction perpendicular to the upper surface of the substrate, as shown here. Figure 17 As shown.

[0076] In some embodiments, the first conductive layer 211 and the second conductive layer 2111 comprise at least one conductive material layer selected from copper, tungsten, titanium nitride, etc. Figure 12 In the illustrated embodiment, the first conductive layer 211 and / or the second conductive layer 2111 comprises only one conductive material, which may be a tungsten metal layer, a titanium nitride layer, or a copper layer. In some other embodiments, the first conductive layer 211 and / or the second conductive layer 2111 may also comprise two adjacent conductive material layers. In some embodiments, the conductive material layer closer to the substrate is a tungsten metal layer or a titanium nitride layer, and the conductive material layer farther from the substrate is a titanium nitride layer or a tungsten metal layer.

[0077] In some embodiments, the top of the first polysilicon layer 210 is flush with the top of the second polysilicon layer 2101, the top of the first conductive layer 211 is flush with the top of the second conductive layer 2111, and the tops of the first mask layer 212 and the second mask layer 2121 are flush.

[0078] In some embodiments, the material used to prepare the metal filling layer 207 is the same as the material used to prepare the first conductive layer 211. Therefore, the same set of metal deposition equipment and metal target can be used to prepare the metal filling layer 207 and the first conductive layer 211, reducing the difficulty of preparation.

[0079] In some embodiments, the metal filler layer 207 is formed using conductive materials such as titanium, tungsten, or titanium nitride. In practice, the specific materials used to prepare the first conductive layer 211 and the metal filler layer 207 can also be selected as needed.

[0080] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A semiconductor memory structure, characterized by, The application relates to a substrate, at least one first groove on the upper surface of the substrate, the edge of the top of the first groove being arc-shaped, a first dielectric layer distributed along the inner wall of the first groove, a second dielectric layer formed on the surface of the first dielectric layer and filling the first groove, the top of the first dielectric layer being lower than the top of the second dielectric layer and the upper surface of the substrate, so that a first groove is formed between the second dielectric layer and the substrate, a fourth dielectric layer covering the inner wall of the first groove and filling part of the space of the first groove, the fourth dielectric layer also covering the second dielectric layer, a metal filling layer in the first groove, filling part of the space in the first groove, the fourth dielectric layer being partially between the metal filling layer and the substrate, so as to cut off the electrical connection between the metal filling layer and the substrate, and a load stack structure formed on the fourth dielectric layer and above the top of the second dielectric layer. The application also relates to a third dielectric layer above the top of the metal filling layer and in the first groove, filling the first groove. The second dielectric layer comprises a first sub-layer and a second sub-layer, the first sub-layer is formed on the surface of the first dielectric layer, and the second sub-layer is formed on the surface of the first sub-layer and fills the first groove. The first dielectric layer comprises an oxide dielectric layer, and / or: The second dielectric layer comprises a nitride dielectric layer. The first sub-layer comprises a nitride dielectric layer, and the second sub-layer comprises an oxide dielectric layer. The application also relates to a gate stack structure formed above the top of the substrate. The gate stack structure at least comprises a first polysilicon layer, a first conductive layer and a first mask layer distributed in turn in the direction perpendicular to the upper surface of the substrate, and / or the load stack structure comprises a second polysilicon layer, a second conductive layer and a second mask layer distributed in turn in the direction perpendicular to the upper surface of the substrate. The preparation material of the metal filling layer is the same as that of the first conductive layer and the second conductive layer.

2. The semiconductor memory structure of claim 1, wherein, The application also relates to a method for manufacturing a substrate, which comprises the following steps. A substrate is provided, and a first groove is formed on the upper surface of the substrate.

3. The semiconductor memory structure of claim 1, wherein, A first dielectric material layer and a second dielectric material layer are formed in turn along the inner wall of the first groove.

4. The semiconductor memory structure of claim 1, wherein, Part of the first dielectric material layer and the second dielectric material layer is removed, so that the edge of the top of the first groove is circularly arc-shaped, and the first dielectric layer and the second dielectric layer are respectively formed correspondingly, the top of the first dielectric layer is lower than the top of the second dielectric layer and the upper surface of the substrate, and a first groove is formed between the second dielectric layer and the substrate. A fourth dielectric layer is formed on the inner wall of the first groove, the fourth dielectric layer covers the inner wall of the first groove and fills part of the space of the first groove, and the fourth dielectric layer also covers the second dielectric layer.

5. The semiconductor memory structure of claim 3, wherein, A metal filling layer is formed in the first groove to partially fill the first groove, and the fourth dielectric layer is partially between the metal filling layer and the substrate, so as to cut off the electrical connection between the metal filling layer and the substrate.

6. The semiconductor memory structure of claim 1, wherein, ​ ​ 7. The semiconductor memory structure of claim 6, wherein, ​ 8. The semiconductor memory structure of claim 7, wherein, ​ 9. A method of fabricating a semiconductor memory structure, comprising: ​ ​ ​ ​ ​ ​ forming a load stack structure on the fourth dielectric layer and above the top of the second dielectric layer.

10. The method of claim 9, wherein, after the step of forming the metal fill layer in the first recess, further comprising the steps of: forming a third dielectric layer on the top of the metal fill layer, the third dielectric layer filling the first recess.

11. The preparation method according to claim 9, characterized in that, the step of partially removing the first and second dielectric material layers comprises the steps of: at least one of dry etching or wet etching is used to partially remove the first and second dielectric material layers, and the etching gas or etching liquid used has a higher etching rate for the first dielectric material layer than for the second dielectric material layer.

12. The method of claim 9, wherein, the second dielectric layer comprises a first sub-layer and a second sub-layer, and the step of forming the second dielectric layer comprises the steps of: forming the first sub-layer on the surface of the first dielectric layer; forming the second sub-layer on the surface of the first sub-layer, and the second sub-layer filling the first trench.

13. The preparation method according to claim 9, characterized in that, the step of forming the metal fill layer in the first recess comprises: forming a metal layer in the first recess, on the top of the second dielectric layer, and on the top surface of the substrate, the metal layer at least filling the first recess; back-etching the metal layer and retaining the metal layer in the first recess as the metal fill layer.

14. The method of claim 10, wherein, the step of forming the third dielectric layer on the top surface of the metal fill layer comprises: forming a dielectric material layer on the top of the metal fill layer, on the top of the second dielectric layer, and on the top surface of the substrate, the dielectric material layer at least filling the first recess; back-etching the dielectric material layer and retaining the dielectric material layer in the first recess as the third dielectric layer.

15. A semiconductor memory structure, characterized by, comprising: a substrate; at least one first trench on the top surface of the substrate, and the edge of the top of the first trench being arc-shaped; a first dielectric layer distributed along the inner wall of the first trench; a second dielectric layer formed on the surface of the first dielectric layer and filling the first trench; the top of the first dielectric layer being lower than the top of the second dielectric layer and the top surface of the substrate, so that a first recess is formed between the second dielectric layer and the substrate; a fourth dielectric layer covering the inner wall of the first recess and filling part of the space of the first recess, the fourth dielectric layer also covering the second dielectric layer; a metal fill layer in the first recess, filling part of the space of the first recess, and the fourth dielectric layer being partially between the metal fill layer and the substrate; a load stack structure on the fourth dielectric layer and above the top of the second dielectric layer.

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