LDMOS device and method of manufacturing the same

Abstract

The application provides an LDMOS device and a preparation method thereof. The method comprises the following steps: S1, providing a semiconductor substrate, and forming a first shallow trench and a second shallow trench; S2, forming an isolation structure, a gate structure and a P-type body region filled in the first shallow trench; S3, forming a side wall; S4, performing ion implantation to form an N-type source region and a P-type source region; S5, forming a conductive material layer on the surface of the N-type source region, the P-type source region and the gate structure to obtain a pretreatment structure; and S6, forming an interlayer dielectric layer covering the pretreatment structure, and forming a plurality of contact holes in the interlayer dielectric layer, which are electrically connected with the N-type source region, the P-type source region and the conductive material layer on the surface of the gate structure respectively. By using the application, most of the process steps required for separately forming a P-type body region trench can be omitted, the complexity of the process is reduced, the alignment difficulty is greatly reduced, the possibility of device characteristic deviation caused by misalignment can be significantly reduced, the use of masks can be reduced, and the production cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to an LDMOS device and its fabrication method. Background Technology

[0002] Laterally Diffused Metal Oxide Semiconductor (LDMOS) devices on the BCD platform typically need to possess both low on-resistance and high breakdown voltage characteristics, but these two characteristics are technically contradictory. To achieve a significant breakthrough in on-resistance for devices with high breakdown voltage, one approach is to form a trench structure in the P-type body region of the LDMOS device. This widens the channel in the on-state, thereby reducing on-resistance and improving device performance.

[0003] Existing technologies mainly include two processes to achieve the desired effect: forming P-type body trenches using a self-aligned process with a spacer-like structure, or adding additional dry etching and cleaning steps using an additional mask. While the first process doesn't require an additional mask, it introduces excessive thermal processes, leading to deviations in device characteristics and potential reliability issues, which will not be elaborated upon here. Taking the second process as an example, the general steps for forming P-type body trenches are as follows (from P-type body ion implantation to contact hole formation):

[0004] 1. After the gate is formed, the P-type body region is etched and corresponding ion implantation is performed;

[0005] 2. Form a sidewall barrier layer;

[0006] 3. Optical masking is performed using a P-type volume region trench mask, followed by dry etching to obtain the P-type volume region trench;

[0007] 4. Perform subsequent ion implantation and growth of conductive materials;

[0008] 5. Growth medium layer and formation of contact holes.

[0009] The shortcomings of this process are: 1) It requires an additional photomask, which increases the process cost; 2) Since it is generally not desirable for the LDMOS source end to be too wide, the optical masking process in step 3 is prone to photoresist tilting due to the sidewalls being too close to the trench, forming defects and affecting subsequent etching; 3) Step 3 may also cause the trench position to shift due to insufficient optical alignment accuracy, resulting in different trench distances from the two sides, causing device performance mismatch, and causing contact hole misalignment in step 5. Summary of the Invention

[0010] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an LDMOS device and its fabrication method, which solves the problems in the prior art where a new photomask is required when manufacturing an LDMOS device with a P-type body trench, which not only increases the cost, but may also cause the device characteristics to deviate from the design due to misalignment.

[0011] To achieve the above and other related objectives, the present invention provides a method for fabricating an LDMOS device, comprising the following steps:

[0012] S1: Provide a semiconductor substrate, and form a plurality of spaced first shallow trenches and second shallow trenches in the semiconductor substrate, wherein the second shallow trenches serve as P-type body region trenches;

[0013] S2: Form an isolation structure, a gate structure, and a P-type body region filling a first shallow trench. The gate structure is located on a portion of the semiconductor substrate surface between the first and second shallow trenches. The P-type body region is located in a semiconductor substrate adjacent to the gate structure and is adjacent to the second shallow trench.

[0014] S3: Form a sidewall that extends from the side of the gate structure to a portion of the surface of the semiconductor substrate and to a portion of the surface of the P-type body region;

[0015] S4: Perform ion implantation to form an N-type source region and a P-type source region, wherein the N-type source region is located on the surface of the semiconductor substrate between the sidewall and the first shallow trench, and the P-type source region is located on the surface of the exposed P-type body region, wherein the P-type source region is located on the surface of the second shallow trench.

[0016] S5: Form conductive material layers located on the surfaces of the N-type source region, P-type source region, and gate structure to obtain a pre-processed structure;

[0017] S6: Form an interlayer dielectric layer covering the pre-processed structure, and form a plurality of contact holes in the interlayer dielectric layer, wherein the plurality of contact holes are electrically connected to the conductive material layer on the surface of the N-type source region, the P-type source region and the gate structure, respectively.

[0018] Optionally, the first shallow trench and the second shallow trench have the same depth, there are multiple first shallow trenches, and the second shallow trench is located between the multiple first shallow trenches.

[0019] Optionally, the steps of forming the gate structure, the P-type body region, and the isolation structure filled in the first shallow trench include:

[0020] An isolation material layer is formed, which fills the first shallow trench and the second shallow trench and covers the semiconductor substrate between the first shallow trench and the second shallow trench. The isolation material layer located in the first shallow trench constitutes an isolation structure.

[0021] Surface planarization is performed to expose the semiconductor substrate located between the first shallow trench and the second shallow trench;

[0022] A sacrificial oxide layer is formed on the surface of the semiconductor substrate between the first shallow trench and the second shallow trench;

[0023] Ion implantation is performed to form P-type and N-type well regions, with a second shallow trench located within the P-type well region, after which the sacrificial oxide layer is removed;

[0024] A gate oxide layer and a polysilicon gate layer located on the surface of the gate oxide layer are formed. The polysilicon gate layer and the gate oxide layer are etched to form a gate structure composed of the gate oxide layer and the polysilicon gate layer, the gate structure extending to a portion of the surface of the P-type well region and the N-type well region.

[0025] A photoresist layer is formed covering the gate structure, the first shallow trench and the second shallow trench, and then exposed and developed to expose the region corresponding to the P-type body region. Ion implantation is then performed to form the P-type body region located in the P-type well region.

[0026] Remove the insulating material layer located in the second shallow trench.

[0027] Optionally, the material of the isolation material layer includes silicon oxide, the method for forming the isolation material layer is chemical vapor deposition, and the method for removing the isolation material layer in the second shallow trench is wet etching.

[0028] Optionally, both the sacrificial oxide layer and the gate oxide layer are silicon oxide layers, both formed by thermal oxidation, and the method for removing the sacrificial oxide layer is wet etching.

[0029] Optionally, the polysilicon gate layer is formed by chemical vapor deposition, and the gate oxide layer and the polysilicon gate layer are etched by dry etching.

[0030] Optionally, the P-type well region and the N-type well region are spaced apart from each other.

[0031] Alternatively, the method for forming the sidewall is as follows:

[0032] A sidewall material layer is formed using a chemical vapor deposition process. The sidewall material layer covers the structure obtained after step S2. The material of the sidewall material layer includes silicon nitride.

[0033] Etching removes the sidewall material layer excluding the sidewalls.

[0034] Optionally, the conductive material layer is a metal silicide layer, and the conductive material layer located on the surface of the P-type body region extends to connect with the conductive material layer located on the surface of the P-type source region; the interlayer dielectric layer includes an oxide layer.

[0035] The present invention also provides an LDMOS device, which is fabricated using the fabrication method described in any of the above embodiments.

[0036] As described above, the LDMOS device and its fabrication method of the present invention have the following beneficial effects: The improved process and technology design of the present invention eliminates most of the process steps required to separately form the P-type body region trench, reducing the complexity of the process, and the entire fabrication process is compatible with the existing BCD process; In the present invention, it is only necessary to ensure the alignment of the active region during contact hole photolithography, which greatly reduces the alignment difficulty, significantly reduces the possibility of device characteristic shift due to misalignment, and can reduce the use of photomasks, thereby reducing production costs. Attached Figure Description

[0037] Figure 1 The flowchart shown is a method for fabricating an LDMOS device provided by the present invention.

[0038] Figure 2-6 The diagram shows an exemplary structural schematic of each step in the fabrication of an LDMOS device according to the fabrication method provided by the present invention.

[0039] Component designation explanation

[0040] 11 Semiconductor substrate

[0041] 12 First shallow trench

[0042] 13 P-type body region trench

[0043] 14 Gate Structure

[0044] 15 P-type body region

[0045] 16. Isolation Structure

[0046] 17 Side walls

[0047] 18 N-type source regions

[0048] 19 P-type source region

[0049] 20 conductive material layers

[0050] 21 Interlayer dielectric layer

[0051] 22 Contact Hole

[0052] 23 Photoresist layer Detailed Implementation

[0053] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. For ease of explanation, when detailing the embodiments of the present invention, the cross-sectional views showing the device structure are partially enlarged, not according to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0054] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0055] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0056] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components related to the present invention and are not drawn according to the actual number, shape, and size of the components in the actual implementation. In the actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex. To keep the illustrations as concise as possible, not all structures are shown in the figures.

[0057] Please see Figures 1 to 6 .

[0058] like Figure 1 As shown, the present invention provides a method for fabricating an LDMOS device, comprising the following steps:

[0059] S1: A semiconductor substrate 11 is provided, in which a plurality of spaced first shallow trenches 12 (STI) and second shallow trenches are formed. The second shallow trenches serve as P-type body region 15 trenches, which can effectively improve the breakdown voltage of the device. The semiconductor substrate 11 includes, but is not limited to, silicon substrates, germanium substrates, germanium-silicon substrates, silicon-on-insulator substrates, silicon carbide substrates, gallium arsenide substrates, or a combination of the above substrates. That is, the semiconductor substrate 11 can be a single-layer structure, such as a silicon wafer, or a composite structure, such as an epitaxial layer formed on the surface of a silicon wafer (in which case, each trench is formed on the epitaxial layer). In the same etching process, the first shallow trench 12 and the second shallow trench are preferably formed simultaneously, so they usually have the same depth. Their morphologies are not limited; for example, they can be completely identical. In this embodiment, for ease of description, trenches with different functions are defined as "first shallow trench" and "second shallow trench." In this embodiment, there are two or more first shallow trenches 12, and the second shallow trenches are located between multiple first shallow trenches 12. Of course, there can also be multiple second shallow trenches. When an array including multiple LDMOS devices is formed, a structure is essentially formed where multiple second shallow trenches are surrounded by first shallow trenches. The structure obtained in this step is as follows: Figure 2As shown; S2: An isolation structure 16, a gate structure 14, and a P-type body region 15 are formed and filled within the first shallow trench 12. The gate structure 14 is located on a portion of the semiconductor substrate 11 surface between the first shallow trench 12 and the second shallow trench, meaning the gate structure 14 does not completely cover the semiconductor substrate 11 between the first shallow trench 12 and the second shallow trench. The P-type body region 15 is located within the semiconductor substrate 11 adjacent to the gate structure 14 and is adjacent to the second shallow trench. The P-type body region 15 is typically formed by P-type ion implantation into the corresponding region. The preferred embodiment provided in this example... In this example, the specific process of this step is as follows: forming an isolation material layer, the isolation material layer filling the first shallow trench 12 and the second shallow trench and covering the semiconductor substrate 11 between the first shallow trench 12 and the second shallow trench, the isolation material layer located in the first shallow trench 12 constitutes an isolation structure 16; the isolation material layer includes, but is not limited to, a silicon oxide layer, and may also be other high-k dielectric material layers, the preferred formation method is chemical vapor deposition, and in this example, silicon oxide is used as the isolation material; then, surface planarization treatment is performed, for example, chemical mechanical polishing (CMP), to plan the first shallow trench... The isolation material layer on the surface of the semiconductor substrate 11 between the first shallow trench 12 and the second shallow trench is removed until the semiconductor substrate 11 located between the first shallow trench 12 and the second shallow trench is exposed; a sacrificial oxide layer is formed on the surface of the semiconductor substrate 11 between the first shallow trench 12 and the second shallow trench. The sacrificial oxide layer is preferably a silicon oxide layer, and the formation method is preferably thermal oxidation, which has the advantages of fast formation speed, fine pores in the generated silicon oxide layer, which facilitates subsequent ion implantation, and easy removal in subsequent steps; ion implantation is performed on the exposed semiconductor substrate 11 to form a P-type well region (Pwe). The doping process typically involves light doping of the P-type and N-type well regions. A certain spacing is usually present between the P-type and N-type well regions, although this spacing may be omitted depending on device requirements. The first shallow trench 12 can be located within the N-type well region, or the N-type well region can occupy a portion of the first shallow trench. The second shallow trench is located within the P-type well region, and the depth of the second shallow trench is typically less than the depth of the P-type well region. The sacrificial oxide layer is then removed, preferably by wet cleaning, which effectively reduces surface damage to the semiconductor substrate 11 and removes impurities.Next, a gate oxide layer and a polysilicon gate layer located on the surface of the gate oxide layer (i.e., the gate oxide layer is located on the surface of the semiconductor substrate 11) are formed. The gate oxide layer is specifically a silicon oxide layer, preferably formed by thermal oxidation. The polysilicon gate layer is preferably formed by chemical vapor deposition. The polysilicon gate layer and the gate oxide layer are etched, for example, by dry etching under the action of a mask layer, to form a gate structure 14 composed of the gate oxide layer and the polysilicon gate layer. The gate structure 14 extends to a portion of the surface of the P-type well region and the N-type well region. In other words, the gate structure 14 is located on the surface of the semiconductor substrate 11 and extends outward to a portion of the P-type well region and the N-type well region. The surface is divided (but not completely covering the N-type well region and the P-type well region); a photoresist layer 23 covering the gate structure 14, the first shallow trench 12 and the second shallow trench is formed using a spin coating process, including but not limited to. Exposure and development are performed to expose the region corresponding to the P-type body region 15. This region is the semiconductor substrate 11 region located between the gate structure 14 and the second shallow trench. Ion implantation is performed on this region to form the P-type body region 15 located in the P-type well region. The ion doping type of the P-type body region 15 and the P-type well region is the same, but the doping concentration of the P-type body region 15 can be higher than that of the P-type well region, or they can be the same. There is no strict limitation on this. This step can be referred to. Figure 3 As shown; the isolation material layer located in the second shallow trench is removed, for example by wet etching, and then the residual photoresist layer 23 is removed to expose the gate structure 14, the first shallow trench 12 and the second shallow trench.

[0060] S3: Forming sidewall 17, which extends from the side of gate structure 14 to a portion of the surface of semiconductor substrate 11 and to a portion of the surface of P-type body region 15; specifically, this step can be as follows: first, a sidewall 17 material layer is formed using chemical vapor deposition. The sidewall 17 material layer preferably includes a silicon nitride layer and / or a silicon oxide layer, for example, a single silicon nitride layer or a composite layer of silicon nitride and silicon oxide layers. The silicon oxide layer is located between the silicon nitride layer and gate structure 14. The sidewall 17 material layer covers the structure obtained after step S2, i.e., it covers gate structure 14, first shallow trench 12, second shallow trench, and P-type body region 15. Then, photolithography is performed to remove the sidewall 17 material layer except for the sidewall 17 itself, i.e., removing the sidewall 17 material layer located in the first shallow trench 12, second shallow trench, and part of the surface of semiconductor substrate 11. The structure obtained after this step is as follows: Figure 4 As shown;

[0061] S4: Ion implantation is performed to form N-type source region 18 and P-type source region 19. This step is typically heavy doping, with concentrations greater than those used in well region doping. The N-type source region 18 is located on the surface of the semiconductor substrate 11 between the sidewall 17 and the first shallow trench 12. The N-type source region 18 is adjacent to both the first shallow trench 12 and the sidewall 17, and also on the exposed surface of the P-type body region 15 (including the upper surface and slope of the P-type body region 15). The P-type source region 19 is located on the surface of the second shallow trench, including the bottom and side surfaces of the second shallow trench. In this embodiment, the bottom surface is mainly used as an example. The structure obtained after this step is as follows: Figure 5 As shown;

[0062] S5: A conductive material layer 20 is formed on the surfaces of the N-type source region 18, the P-type source region 19, and the gate structure 14 to obtain a pre-processed structure; In the preferred example provided in this embodiment, the conductive material layer 20 is a metal silicide, which is formed by forming a thin metal layer on the surface of the corresponding structural layer (these structural layers are all semiconductor materials, such as silicon), and then reacting silicon and metal to form a metal silicide by high-temperature annealing; The conductive material layer 20 on the surface of the P-type body region 15 will extend to connect with the conductive material layer 20 on the surface of the P-type source region 19.

[0063] S6: Form an interlayer dielectric layer 21 covering the pre-processed structure. Form a plurality of contact holes 22 in the interlayer dielectric layer 21. The contact holes 22 are electrically connected to the conductive material layer 20 on the surfaces of the N-type source region 18, the P-type source region 19, and the gate structure 14, respectively. The interlayer dielectric layer 21 is preferably, but not limited to, a silicon oxide layer. Its formation method is preferably chemical vapor deposition. Subsequently, a plurality of vias are formed in the interlayer dielectric layer 21 using photolithography etching, and the vias are filled with metal to form contact holes 22, thereby bringing out the electrical properties of the corresponding structures. The structure obtained after this step is as follows: Figure 6 As shown.

[0064] In existing technologies, fabricating LDMOS devices with P-type body trenches requires simultaneous alignment of the active area, gate, and P-type body trench during contact hole photolithography. This alignment precision control is challenging and costly. The improved process and design of this invention eliminate most of the steps required to separately form the P-type body trench, reducing process complexity. Furthermore, the entire fabrication process is compatible with existing BCD processes. In this invention, only the alignment of the active area during contact hole photolithography is required, significantly reducing alignment difficulty and the likelihood of device characteristic shifts due to misalignment. It also reduces the use of photomasks, lowering production costs.

[0065] This invention also provides an LDMOS device, which is fabricated using the fabrication method described in any of the above embodiments; therefore, the foregoing content can be incorporated herein by reference in its entirety. Figure 6 As described above, the LDMOS device includes a semiconductor substrate 11, a first shallow trench 12 and a second shallow trench located within the semiconductor substrate 11, a gate structure 14, sidewalls 17, an N-type source region 18, a P-type source region 19, a P-type body region 15, a conductive material layer 20, an interlayer dielectric layer 21, and contact holes 22. The second shallow trench serves as a P-type body region trench 13, which is filled by the interlayer dielectric layer. An isolation structure 16 is filled within the first shallow trench 12. The gate structure 14 is located on the surface of the semiconductor substrate 11 between the first shallow trench 12 and the second shallow trench. The sidewalls 17 are located on the sides of the gate structure 14 and extend to the semiconductor substrate 11. Partially, the N-type source region 18 is located within the semiconductor substrate 11 between the first shallow trench 12 and the sidewall 17, and on the inner surface of the P-type body region 15. The P-type body region 15 is located within the semiconductor substrate 11 between the second shallow trench and the sidewall 17. The P-type source region 19 is located on the surface of the second shallow trench, including the bottom surface. A conductive material layer 20 is located on the surfaces of the gate structure 14, the N-type source region 18, and the P-type source region 19. An interlayer dielectric layer 21 covers the aforementioned structures, and a contact hole 22 penetrates the interlayer dielectric layer 21 and contacts the conductive material layer 20 on the surfaces of the N-type source region 18, the P-type source region 19, and the gate structure 14 to electrically lead out the corresponding structures. For a more detailed description of the LDMOS device, please refer to the foregoing content, which will not be repeated for the sake of brevity. Because it is fabricated using the aforementioned method, the LDMOS device provided by this invention can significantly reduce its manufacturing difficulty and cost while possessing both low on-resistance and high breakdown voltage characteristics.

[0066] In summary, this invention provides an LDMOS device and its fabrication method. The fabrication method includes the following steps: S1: providing a semiconductor substrate, and forming a plurality of spaced first shallow trenches and second shallow trenches in the semiconductor substrate, wherein the second shallow trenches serve as P-type body region trenches; S2: filling the first shallow trenches with an isolation structure, forming a gate structure and a P-type body region, wherein the gate structure is located on a portion of the semiconductor substrate surface between the first and second shallow trenches, and the P-type body region is located in the semiconductor substrate adjacent to the gate structure and adjacent to the second shallow trenches; S3: forming sidewalls, wherein the sidewalls extend from the side of the gate structure to a portion of the semiconductor substrate surface and extend to the P-type body region. S4: Perform ion implantation to form an N-type source region and a P-type source region, wherein the N-type source region is located on the surface of the semiconductor substrate between the sidewall and the first shallow trench, and the P-type source region is located on the exposed surface of the second shallow trench; S5: Form a conductive material layer on the surfaces of the N-type source region, the P-type source region, and the gate structure to obtain a pre-treated structure; S6: Form an interlayer dielectric layer covering the pre-treated structure, and form a plurality of contact holes in the interlayer dielectric layer, wherein the plurality of contact holes are electrically connected to the conductive material layer on the surfaces of the N-type source region, the P-type source region, and the gate structure, respectively. The improved process and technology design of this invention eliminates most of the process steps required to separately form the P-type source region trench, reducing the complexity of the process, and the entire fabrication process is compatible with existing BCD processes; in this invention, only the alignment of the active region during contact hole photolithography is required, greatly reducing the alignment difficulty and significantly reducing the possibility of device characteristic shift due to misalignment, and also reducing the use of photomasks and lowering production costs. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0067] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating an LDMOS device, characterized in that, Including the following steps: S1: Provide a semiconductor substrate, and form a plurality of spaced first shallow trenches and second shallow trenches in the semiconductor substrate. The first shallow trenches and second shallow trenches are formed simultaneously, and the second shallow trenches serve as P-type body region trenches. S2: Form an isolation structure, a gate structure, and a P-type body region filling a first shallow trench. The gate structure is located on a portion of the semiconductor substrate surface between the first and second shallow trenches. The P-type body region is located in a semiconductor substrate adjacent to the gate structure and is adjacent to the second shallow trench. S3: Form a sidewall that extends from the side of the gate structure to a portion of the surface of the semiconductor substrate and to a portion of the surface of the P-type body region; S4: Perform ion implantation to form an N-type source region and a P-type source region, wherein the N-type source region is located on the surface of the semiconductor substrate between the sidewall and the first shallow trench, and the P-type source region is located on the surface of the exposed P-type body region, wherein the P-type source region is located on the surface of the second shallow trench. S5: Form conductive material layers on the surfaces of the N-type source region, P-type source region, and gate structure to obtain a pre-processed structure; S6: Form an interlayer dielectric layer covering the pre-processed structure, and form a plurality of contact holes in the interlayer dielectric layer, wherein the plurality of contact holes are electrically connected to the conductive material layer on the surface of the N-type source region, the P-type source region and the gate structure, respectively.

2. The method for fabricating an LDMOS device according to claim 1, characterized in that, The first shallow trench and the second shallow trench have the same depth. There are multiple first shallow trenches, and the second shallow trench is located between the multiple first shallow trenches.

3. The method for fabricating an LDMOS device according to claim 1, characterized in that, The steps of forming the gate structure, the P-type body region, and the isolation structure filled in the first shallow trench include: An isolation material layer is formed, which fills the first shallow trench and the second shallow trench and covers the semiconductor substrate between the first shallow trench and the second shallow trench. The isolation material layer located in the first shallow trench constitutes an isolation structure. Surface planarization is performed to expose the semiconductor substrate located between the first shallow trench and the second shallow trench; A sacrificial oxide layer is formed on the surface of the semiconductor substrate between the first shallow trench and the second shallow trench; Ion implantation is performed to form P-type and N-type well regions, with a second shallow trench located within the P-type well region, after which the sacrificial oxide layer is removed; A gate oxide layer and a polysilicon gate layer located on the surface of the gate oxide layer are formed. The polysilicon gate layer and the gate oxide layer are etched to form a gate structure composed of the gate oxide layer and the polysilicon gate layer, the gate structure extending to a portion of the surface of the P-type well region and the N-type well region. A photoresist layer is formed covering the gate structure, the first shallow trench and the second shallow trench, and then exposed and developed to expose the region corresponding to the P-type body region. Ion implantation is then performed to form the P-type body region located in the P-type well region. Remove the insulating material layer located in the second shallow trench.

4. The method for fabricating an LDMOS device according to claim 3, characterized in that, The isolation material layer is made of silicon oxide, the isolation material layer is formed by chemical vapor deposition, and the isolation material layer in the second shallow trench is removed by wet etching.

5. The method for fabricating an LDMOS device according to claim 3, characterized in that, Both the sacrificial oxide layer and the gate oxide layer are silicon oxide layers, which are formed by thermal oxidation. The method for removing the sacrificial oxide layer is wet etching.

6. The method for fabricating an LDMOS device according to claim 3, characterized in that, The polysilicon gate layer is formed by chemical vapor deposition, and the gate oxide layer and the polysilicon gate layer are etched by dry etching.

7. The method for fabricating an LDMOS device according to claim 3, characterized in that, The P-type well region and the N-type well region are spaced apart from each other.

8. The method for fabricating an LDMOS device according to claim 1, characterized in that, The method for forming the sidewall is to form a sidewall material layer using a chemical vapor deposition process, wherein the sidewall material layer covers the structure obtained after step S2, and the material of the sidewall material layer includes silicon nitride and / or silicon oxide; Etching removes the sidewall material layer excluding the sidewalls.

9. The method for fabricating an LDMOS device according to claim 1, characterized in that, The conductive material layer is a metal silicide layer, and the conductive material layer located on the surface of the P-type body region extends to connect with the conductive material layer located on the surface of the P-type source region; the interlayer dielectric layer includes an oxide layer.

10. An LDMOS device, characterized in that, The LDMOS device is fabricated using the fabrication method described in any one of claims 1-9.

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