Switching converter, controller and control method thereof

Abstract

A switching converter, a controller and a control method thereof are disclosed. The controller includes a comparison circuit, a valley current limit circuit, a peak current limit circuit, a conduction time control circuit and a switch control circuit. The comparison circuit compares a feedback signal representing an output voltage with an output voltage reference to generate a voltage comparison signal. The valley current limit circuit compares a sampling signal representing a current flowing through the switching circuit with a first current threshold to generate a valley current comparison signal. The peak current limit circuit generates an operation signal based on the valley current comparison signal and a switch control signal, and generates a peak current comparison signal based on the operation signal and a second current threshold. The switch control circuit generates the switch control signal based on the voltage comparison signal, the valley current comparison signal, the peak current comparison signal and the conduction time control signal to control the turn-on and turn-off of the switching circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to an electronic circuit, and more particularly, to a switching converter, and a controller and a control method thereof. BACKGROUND

[0002] Switching converters are widely used in converting input voltage to output voltage to power loads due to their high efficiency, high current carrying capability and other advantages. Switching converters include at least one power switch, and the output voltage is obtained by controlling the opening and closing of the power switch. Switching converters include buck converters, boost converters, flyback converters and so on.

[0003] In a switching converter, the current of its output stage is usually needed to be detected. If the current flowing through the power switch or other components is greater than the maximum current limit that they can bear when short circuit occurs, the power switch or other components will be damaged. Therefore, the current in the switching converter needs to be detected. SUMMARY

[0004] Therefore, the purpose of the present application is to solve the above technical problems of the prior art, and to provide a switching converter, and a controller and a control method thereof.

[0005] According to an embodiment of the present application, a controller of a switching converter is provided, the switching converter including a switching circuit which is turned on and off under the control of a switching control signal and converts an input voltage to an output voltage, the controller including a comparison circuit which generates a voltage comparison signal according to the comparison between a feedback signal representing the output voltage and an output voltage reference value; a valley current limiting circuit which generates a valley current comparison signal according to the comparison between a sampling signal representing the current flowing through the switching circuit and a first current threshold value; a peak current limiting circuit which generates an operation signal according to the valley current comparison signal and the switching control signal, and generates a peak current comparison signal according to the comparison between the operation signal and a second current threshold value; a turn-on duration control circuit which generates a turn-on duration control signal according to the switching control signal; and a switching control circuit which generates the switching control signal according to the voltage comparison signal, the valley current comparison signal, the peak current comparison signal and the turn-on duration control signal, so as to control the turn-on and off of the switching circuit.

[0006] According to an embodiment of the present application, a switching converter is also provided, including the controller as described above.

[0007] According to the embodiment of the present application, a control method of a switching converter is also provided, the switching converter comprising a switching circuit converting an input voltage into an output voltage under the control of a switching control signal, the control method comprising: generating a voltage comparison signal according to the comparison between the output voltage and an output voltage reference value; generating a valley current comparison signal by comparing a current flowing through the switching circuit with a first current threshold value; generating a peak current comparison signal according to the valley current comparison signal, the switching control signal and a second current threshold value; and controlling the on-time of the switching circuit according to the voltage comparison signal and the valley current comparison signal, and controlling the off-time of the switching circuit according to the peak current comparison signal and an on-time duration control signal.

[0008] According to the embodiment of the present application, the peak value of the output current ripple of the switching converter can be obtained simply, so that the limitation of the peak current can be realized. BRIEF DESCRIPTION OF DRAWINGS

[0009] For better understanding of the present application, the present application will be described in detail with reference to the following drawings:

[0010] Figure 1 a circuit schematic diagram of the switching converter 100 according to the embodiment of the present application;

[0011] Figures 2A-2B a circuit schematic diagram of the peak current limiting circuit 14 according to the embodiment of the present application;

[0012] Figures 3A-3B a circuit schematic diagram of the peak current limiting circuit 14 according to another embodiment of the present application;

[0013] Figure 4 a circuit schematic diagram of the on-time duration control circuit 15 according to the embodiment of the present application;

[0014] Figure 5 a schematic diagram of the switching control circuit 16 according to the embodiment of the present application;

[0015] Figure 6 a waveform diagram of the switching converter 100 according to the embodiment of the present application;

[0016] Figure 7 a flow chart 700 of the control method of the switching converter according to the embodiment of the present application.

[0017] In the drawings, the same or corresponding reference numerals are used to denote the same or corresponding elements. DETAILED DESCRIPTION

[0018] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the invention.

[0019] Throughout this specification, references to “an embodiment,” “an example,” or “an example” mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases “in an embodiment,” “in an embodiment,” “an example,” or “an example” appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes and are not necessarily drawn to scale. It should be understood that when an element is referred to as “coupled to” or “connected to” another element, it can be directly coupled to or coupled to the other element, or there may be intermediate elements. Conversely, when an element is referred to as “directly coupled to” or “directly connected to” another element, there are no intermediate elements. The same reference numerals indicate the same elements. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0020] Figure 1 This is a circuit diagram of a switching converter 100 according to an embodiment of the present invention. The switching converter 100 includes a switching circuit 10 and a controller 20. The switching circuit 10 is turned on and off under the control of a switching control signal PWM, and converts the input voltage Vin into an output voltage Vo. In one embodiment, the switching circuit 10 may be part of a buck converter, for example... Figure 1 As shown, it includes an upper switching transistor S1 and a lower switching transistor S2. Those skilled in the art will understand that this invention can also be applied to other switching converter topologies. For example... Figure 1As shown, the first terminal of the upper switch S1 receives the input voltage Vin, the first terminal of the lower switch S2 is coupled to the second terminal of the upper switch S1, and the second terminal of the lower switch S2 is coupled to a reference ground. The upper switch S1 and the lower switch S2 are complementaryly turned on and off under the control of the switching control signal PWM. In one embodiment, the upper switch S1 and the lower switch S2 are transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs). In one embodiment, the switching converter 100 further includes an inductor Lo and a capacitor Co. The first terminal of the inductor Lo is coupled to the second terminal of the upper switch S1 and the first terminal of the lower switch S1. The second terminal of the inductor Lo and the first terminal of the capacitor Co are coupled together to provide the output voltage Vo. The second terminal of the capacitor Co is coupled to a reference ground.

[0021] The controller 20 includes a comparator circuit 11, a valley current limiting circuit 12, a peak current limiting circuit 14, an on-time control circuit 15, and a switch control circuit 16. The comparator circuit 11 receives a feedback signal Vfb representing the output voltage Vo and an output voltage reference value Vref, and compares the feedback signal Vfb with the output voltage reference value Vref to generate a voltage comparison signal Cmp1. In one embodiment, the comparator circuit 11 includes a non-inverting input, an inverting input, and an output. The non-inverting input of the comparator circuit 11 receives the output voltage reference value Vref, the inverting input receives the feedback signal Vfb, and the output provides the voltage comparison signal Cmp1. The valley current limiting circuit 12 receives a sampled signal Ics representing the current flowing through the switch circuit 10 and a first current threshold ILim, and compares the sampled signal Ics with the first current threshold ILim to generate a valley current comparison signal OCL. The sampling signal Ics can, for example, represent the current flowing through switch S1, switch S2, or inductor Lo. In one embodiment, the valley current limiting circuit 12 includes a comparator circuit with a non-inverting input, an inverting input, and an output. The non-inverting input receives the sampling signal Ics, the inverting input receives a first current threshold ILim, and the output provides a valley current comparison signal OCL. In one embodiment, when the sampling signal Ics is greater than the first current threshold ILim, the valley current comparison signal OCL goes high. In one embodiment, if the switching converter 100 is unable to directly detect the current of the upper switch S1, the sampling signal Ics, while reflecting the actual decreasing current in the inductor, can only simulate the increasing current in the inductor. In this case, the valley current limiting circuit 12 is used to limit the valley of the inductor current ripple. However, since the sampling signal Ics cannot accurately reflect the increasing current in the inductor, the valley current limiting circuit 12 cannot limit the peak value of the inductor current ripple.

[0022] In one embodiment, the peak current limiting circuit 14 is used to further limit the peak value of the inductor current ripple based on the valley current comparison signal OCL and the switch control signal PWM. For example, the peak current limiting circuit 14 generates an operational signal An1 based on the valley current comparison signal OCL and the switch control signal PWM, and generates a peak current comparison signal OCH by comparing the operational signal An1 with a second current threshold Prog. When the operational signal An1 is greater than the second current threshold Prog, it is considered that the peak value of the inductor current ripple has reached the limit value, and the switch control signal PWM controls the upper switch S1 to turn off. In one embodiment, the peak current limiting circuit 14 integrates the result of the logical operation between the switch control signal PWM and the valley current comparison signal OCL to obtain the operational signal An1. For example, the result of the logical AND operation between the switch control signal PWM and the valley comparison signal can be integrated in the continuous domain or the discrete domain. In one embodiment, the peak current limiting circuit 14 further resets the integration based on the switch control signal PWM and the valley current comparison signal OCL.

[0023] The on-time control circuit 15 receives the switch control signal PWM and generates an on-time control signal COT based on the switch control signal PWM. In one embodiment, the on-time control circuit 15 further generates the on-time control signal COT based on the input voltage Vin, so as to control the on-time of the switch circuit 10 to change with the input voltage Vin. In another embodiment, the on-time control circuit 15 further generates the on-time control signal COT based on the input voltage Vin and the output voltage Vo, so as to control the on-time of the switch circuit 10 to change with the input voltage Vin and the output voltage Vo.

[0024] The switch control circuit 16 generates a switch control signal PWM based on the voltage comparison signal Cmp1, the valley current comparison signal OCL, the peak current comparison signal OCH, and the conduction duration control signal COT. In one embodiment, the switch control circuit 16 controls the turn-on time of the switch circuit 10 based on the voltage comparison signal Cmp1 and the valley current comparison signal OCL, and controls the turn-off time of the switch circuit 10 based on the peak current comparison signal OCH and the conduction duration control signal COT. In one embodiment, when the feedback signal Vfb is less than the output voltage reference value Vref and the sampling signal Ics is less than the first current threshold ILim, the switch control signal PWM controls the switch circuit 10 to turn on, for example, the switch control signal PWM becomes high. In one embodiment, when the conduction duration of the switch circuit 10 (for example, the conduction duration of the upper switch S1) reaches the duration TON preset by the conduction duration control signal COT, or when the effective duration of the operation signal An1 is greater than the second current threshold Prog, the switch control signal PWM controls the switch circuit 10 to turn off.

[0025] Figure 2A This is a schematic diagram of the peak current limiting circuit 14 according to an embodiment of the present invention, integrated in the continuous domain. Figure 2A In the illustrated embodiment, the peak current limiting circuit 14 includes an integration module 141 and a comparison module 142. The integration module 141 receives the switch control signal PWM and the valley current comparison signal OCL, and performs an integration operation on the result of the logical AND operation of the switch control signal PWM and the valley current comparison signal OCL to obtain the operation signal An1. The operation signal An1 can be represented by, for example, the following formula (1):

[0026]

[0027] Where k is a coefficient. Those skilled in the art will understand that, without departing from the essential spirit of this invention, the logical operations of the switch control signal PWM and the valley current comparison signal OCL are not limited to AND operations.

[0028] In one embodiment, the integration module 141 is further reset based on the AND operation of the switch control signal PWM and the valley current comparison signal OCL. For example, the integration module 141 is reset when the result of the AND operation of the switch control signal PWM and the valley current comparison signal OCL is low. The comparison module 142 receives the operation signal An1 and the second current threshold Prog, and obtains the peak current comparison signal OCH by comparing the operation signal An1 and the second current threshold Prog.

[0029] Figure 2B This is a circuit diagram of the peak current limiting circuit 14 according to an embodiment of the present invention, integrated in the continuous domain. Figure 2B In the illustrated embodiment, the integration module 141 includes a current source CS1, a capacitor C1, and a switch S3. Switch S3 is turned on and off under the control of a switch control signal PWM and a valley current comparison signal OCL. The comparison module 142 includes a comparator CMP. The non-inverting input of the comparator CMP receives the voltage VC1 across capacitor C1, the inverting input of the comparator CMP receives a second current threshold Prog, and the output of the comparator CMP generates a peak current comparison signal OCH based on the comparison result of voltage VC1 and the second current threshold Prog.

[0030] In one embodiment, when the logical AND (PWM&OCL) of the switch control signal PWM and the valley current comparison signal OCL is high, switch S3 is turned off, current source CS1 charges capacitor C1, and the voltage VC1 across capacitor C1 increases. Until voltage VC1 increases to the second current threshold Prog, the peak current comparison signal OCH becomes high, and the upper switch S1 is turned off. In another embodiment, when the logical AND (PWM&OCL) of the switch control signal PWM and the valley current comparison signal OCL is low, switch S3 is turned on, and capacitor C1 quickly discharges to 0V.

[0031] Figure 3A This is a schematic diagram of the peak current limiting circuit 14 according to an embodiment of the present invention, integrated in the discrete domain. Figure 3A In the embodiment shown, the integration module 141 is implemented in the discrete domain, and the operation signal An1 can be represented by, for example, the following formula (2):

[0032]

[0033] Figure 3B This is a circuit diagram of the peak current limiting circuit 14 according to an embodiment of the present invention, integrated in the discrete domain. Figure 3B In the illustrated embodiment, the integration module 141 includes an AND gate 31, a multiplication module 32, an adder module 33, and an n-bit D flip-flop 34. The AND gate 31 outputs an AND signal A1 based on the switch control signal PWM and the valley current comparison signal OCL. The multiplication module 32 multiplies the signal A1 with the coefficient k to obtain the product signal M1. The multiplication module 32 can be implemented, for example, using a lookup table or an accumulator. The adder module 33 accumulates the product signal M1 and the operation signal An1 to obtain an n-bit accumulated signal A2. The n-bit accumulated signals A2 are fed into the corresponding D flip-flops 34. The n-bit D flip-flops 34 generate the operation signal An1 based on the n-bit accumulated signals A2. In one embodiment, the operation signal An1 is an n-bit digital signal. In one embodiment, the n-bit D flip-flops 34 are reset based on the AND (PWM & OCL) of the switch control signal PWM and the valley current comparison signal OCL. For example, when the inverted signal of PWM & OCL is high, the n-bit D flip-flops 34 are reset, and the operation signal An1 is reset to zero. The comparison module 142 receives an n-bit computation signal An1 and compares the computation signal An1 with the second current threshold Prog to generate a peak current comparison signal. In one embodiment, the second current threshold Prog is a digital signal.

[0034] Figure 4 This is a circuit diagram of the conduction duration control circuit 15 according to an embodiment of the present invention. Figure 4In the illustrated embodiment, the on-time control circuit 15 receives the input voltage Vin, the output voltage Vo, and the switching control signal PWM, and outputs the on-time control signal COT. Those skilled in the art will understand that the on-time control circuit 15 is not limited to... Figure 4 The specific structure is shown. In, as... Figure 4 In the illustrated embodiment, the conduction duration control circuit 15 includes a current source IS1, a capacitor C2, a switch S4, and a comparator circuit 241. One end of the current source IS1 receives the input voltage Vin, and the other end of the current source IS1 is coupled to one end of the capacitor C2 to output a charging current signal. The other end of the capacitor C2 is coupled to a reference ground. Under the control of the input voltage Vin, the current source IS1 outputs a charging current signal to charge the capacitor C2. In one embodiment, the magnitude of the charging current signal output by the current source IS1 is related to the input voltage Vin, increasing or decreasing as the input voltage Vin increases or decreases. The first end of the switch S4 is coupled to the common terminal of the capacitor C2 and the current source IS1, and the second end of the switch S4 is coupled to the other end of the capacitor C2. The control terminal of the switch S4 receives a switch control signal PWM through a NOT gate N1. In one embodiment, when the switch control signal PWM is valid, for example, high level, switch S4 is off, capacitor C2 is charged through current source IS1, and the voltage across capacitor C2 gradually increases; when the switch control signal PWM is invalid, for example, low level, switch S4 is on, capacitor C2 is discharged through switch S4, and the voltage across capacitor C2 decreases. In one embodiment, the voltage Vs at the common terminal of capacitor C2 and current source IS1 represents the magnitude of the voltage across capacitor C2. The non-inverting input of comparator circuit 241 receives the voltage Vs across capacitor C2, the inverting input of comparator circuit 241 receives the output voltage Vo, and outputs an on-time control signal COT based on the comparison result of the voltage Vs across capacitor C2 and the output voltage Vo.

[0035] Figure 5 This is a schematic diagram of a switch control circuit 16 according to an embodiment of the present invention. Those skilled in the art will understand that the switch control circuit 16 is not limited to... Figure 5 The specific structure is shown. In Figure 5In the illustrated embodiment, the switch control circuit 16 includes logic circuits 161, 162, and 163. Logic circuit 161 receives a voltage comparison signal Cmp1 and a valley current comparison signal OCL, and generates a set signal SET based on Cmp1 and OCL. Logic circuit 162 receives a peak current comparison signal OCH and a conduction duration control signal COT, and generates a reset signal RESET based on OCH and COT. Logic circuit 163 receives the set signal SET and the reset signal RESET, and generates a switch control signal PWM based on SET and RESET. In one embodiment, logic circuit 161 includes a NOT gate N2 and an AND gate AND1. The NOT gate N2 receives the valley circuit comparison signal OCL. AND gate AND1 includes a first input, a second input, and an output. Its first input is coupled to the output of NOT gate N2 to receive the inverted valley comparison signal OCL. Its second input receives a voltage comparison signal Cmp1, and its output provides a set signal SET. In one embodiment, logic circuit 162 includes OR gate OR1. OR gate OR1 includes a first input, a second input, and an output. Its first input receives an on-time control signal COT, its second input receives a peak current comparison signal OCH, and its output provides a reset signal RESET. In one embodiment, logic circuit 163 includes an RS flip-flop, including a set input S, a reset input R, and an output Q. Its set input S receives the set signal SET, its reset input R receives the reset signal RESET, and its output provides a switch control signal PWM.

[0036] Figure 6 The waveform diagram is of a switching converter 100 according to an embodiment of the present invention. Figure 6 The waveform diagram shown below, from top to bottom, displays the sampling signal Ics, the valley current comparison signal OCL, the feedback signal Vfb, the switching control signal PWM, the operation signal An1, and the peak current comparison signal OCH.

[0037] At time t1, the feedback signal Vfb decreases to below the output voltage reference value Vref, and simultaneously the sampling signal Ics is less than the first current threshold ILim. The switching control signal PWM flips from the first state to the second state, for example, from low level to high level, to control the switching circuit 10 to conduct, for example, to control switch S1 to conduct and switch S2 to turn off. At time t2, the sampling signal Ics is greater than the first current threshold ILim, and the valley current comparison signal OCL flips. At this time, the switching control signal PWM is still in the second state, if it remains at a high level, and the operation signal An1 becomes high level. Until time t3, the conduction time of the switching circuit 10 reaches the preset time TON, and the switching control signal PWM flips to the first state, if it becomes low level, to control the switching circuit 10 to turn off, for example, to control switch S1 to turn off and switch S2 to conduct, and the operation signal An1 becomes low level. The duration of the operation signal An1 being high level is less than the second current threshold Prog, the peak current comparison signal OCH remains in its original state without flipping, and the peak current limiting circuit 14 does not limit the inductor current. At time t4, the feedback signal Vfb decreases to below the output voltage reference value Vref, and simultaneously, the sampling signal Ics is less than the first current threshold ILim. The switching control signal PWM flips from the first state to the second state, the switching circuit 10 is turned on, and the next switching cycle begins. At time t5, the sampling signal Ics is greater than the first current threshold ILim, the valley current comparison signal OCL flips, and the operation signal An1 goes high. Until time t6, the operation signal An1 remains high for the duration of the second current threshold Prog, the peak current comparison signal OCH flips (e.g., goes high), the switching control signal PWM goes low, and the switching circuit 10 is turned off.

[0038] Figure 7 This is a flowchart 700 of a control method for a switching converter according to an embodiment of the present invention. The switching converter includes a switching circuit that converts an input voltage into an output voltage under the control of a switching control signal. The control method includes steps S11 to S14.

[0039] In step S11, a voltage comparison signal is generated by comparing the output voltage with the output voltage reference value.

[0040] In step S12, the current flowing through the switching circuit is compared with the first current threshold to generate a valley current comparison signal.

[0041] In step S13, a peak current comparison signal is generated based on the valley current comparison signal, the switch control signal, and the second current threshold.

[0042] In step S14, the turn-on time of the switching circuit is controlled according to the voltage comparison signal and the valley current comparison signal, and the turn-off time of the switching circuit is controlled according to the peak current comparison signal and a turn-on duration control signal.

[0043] In one embodiment, the control method further includes integrating the switch control signal and the valley current comparison signal over a certain period of time to obtain a calculated signal, and comparing the calculated signal with a second current threshold to obtain a peak current comparison signal. In one embodiment, when the calculated signal is greater than the second current threshold, the switch control signal controls the switch circuit to turn off.

[0044] It should be noted that the execution order of the steps in the flowchart above is not limited to... Figure 5 As shown, two consecutive function blocks can be executed simultaneously or in reverse order.

[0045] Although the invention has been described with reference to several exemplary embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Since the invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A controller for a switching converter, the switching converter including a switching circuit, the switching circuit being turned on and off under the control of a switching control signal, and converting an input voltage into an output voltage, the controller comprising: The comparator circuit compares the feedback signal representing the output voltage with the output voltage reference value to generate a voltage comparison signal. The valley current limiting circuit compares a sampled signal representing the current flowing through the switching circuit with a first current threshold to generate a valley current comparison signal. The peak current limiting circuit integrates the switch control signal and the valley current comparison signal over a certain period of time to obtain a calculation signal, and generates a peak current comparison signal by comparing the calculation signal with a second current threshold. The conduction duration control circuit generates a conduction duration control signal based on the switch control signal; as well as The switching control circuit generates a switching control signal based on a voltage comparison signal, a valley current comparison signal, a peak current comparison signal, and a conduction duration control signal, in order to control the switching circuit to turn on and off.

2. The controller of claim 1, wherein the peak current limiting circuit further comprises: The integration module receives the switch control signal and the valley current comparison signal, and integrates the logical operation results of the switch control signal and the valley current comparison signal to obtain the operation signal; as well as The comparison module receives the calculation signal and the second current threshold, and obtains the peak current comparison signal by comparing the calculation signal and the second current threshold.

3. The controller of claim 2, wherein the integration module comprises: The switch is configured to be turned on and off under the control of a switch control signal and a valley current comparison signal; A capacitor, the voltage across its terminals represents the operational signal; The current source is configured to charge the capacitor when the switch is off and to discharge the capacitor when the switch is on.

4. The controller of claim 1, wherein the peak current limiting circuit further comprises: A logic circuit receives a switch control signal and a valley current comparison signal, and the logic circuit generates an operation signal based on the switch control signal and the valley current comparison signal. as well as The timing circuit receives an arithmetic signal and a second current threshold. Under the control of the arithmetic signal, the timing circuit starts timing. When the timing duration reaches the second current threshold, the peak current comparison signal changes from a first state to a second state.

5. The controller as claimed in claim 1, wherein the switch control circuit controls the turn-on time of the switch circuit according to the voltage comparison signal and the valley current comparison signal, and controls the turn-off time of the switch circuit according to the peak current comparison signal and the turn-on duration control signal.

6. The controller of claim 5, wherein when the output voltage is less than the output voltage reference value and the current flowing through the switching circuit is less than the first current threshold, the switch control signal controls the switching circuit to turn on.

7. The controller as described in claim 5, wherein the peak current limiting circuit integrates the switch control signal and the valley current comparison signal over a certain period of time to obtain an integral value, and when the integral value is greater than the second current threshold, the switch control signal controls the switch circuit to turn off.

8. A switching converter, comprising a controller as claimed in any one of claims 1 to 7.

9. A control method for a switching converter, the switching converter including a switching circuit, the switching circuit converting an input voltage into an output voltage under the control of a switching control signal, the control method comprising: A voltage comparison signal is generated by comparing the output voltage with the output voltage reference value; The current flowing through the switching circuit is compared with a first current threshold to generate a valley current comparison signal; The switching control signal and the valley current comparison signal are integrated over a certain period of time to obtain the calculation signal, and the peak current comparison signal is generated by comparing the calculation signal with the second current threshold. The switching circuit is controlled to turn on based on a voltage comparison signal and a valley current comparison signal, and to turn off based on a peak current comparison signal and a turn-on duration control signal.

10. The control method as described in claim 9, further comprising: When the calculated signal is greater than the second current threshold, the switch control signal controls the switch circuit to turn off.

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