Storage control chip, LED module and storage control method

Abstract

The present invention relates to a storage control chip, device and method for an LED module, wherein the chip comprises a first enhanced driving module and a level conversion module. The first enhanced driving module is used to execute a first processing process; the first processing process comprises an enhancement of driving capability; the first enhanced driving module comprises a first multiplexing terminal group, which is used to transmit a second part refresh signal or a second part read / write signal; the refresh signal is used to control the screen refresh of the module; the read / write signal is used to control the read / write of a non-volatile memory storing parameter information of the module; the level conversion module is used to execute a second processing process; the second processing process comprises a step-down conversion; the present invention realizes a substantial reduction in the cost of the entire chip.

Description

Technical Field

[0001] The invention relates to LED module control technology, and in particular to a storage control chip, an LED module and a storage control method. Background Art

[0002] The LED display screen is composed of a controller and a module. The controller includes a receiving card. Different modules have different control parameters, such as screen parameters and correction coefficients, and may also include other control parameters. Screen parameters are parameters such as the number of pixels, line scans, and driver chip type of the module. The correction coefficient refers to the chromaticity and brightness correction coefficient of each pixel of the module, which is used to make the chromaticity and brightness of all pixels consistent. In actual production, the controller and the module are produced by different manufacturers, and it is not known which controller the module will be used with when the module is produced. If the control parameters are saved on the controller, after installing the module and the controller, the installer must configure the control parameters that match the module on the receiving card. If the module is damaged and replaced, the control parameters of each module are different, so it is necessary to reconfigure the control parameters for the new module. If the control parameters are saved on the module and the manufacturer configures the control parameters when the module is produced, when it is used, the receiving card reads the control parameters from the module when it is turned on, and there is no need to configure the parameters. If the module needs to be replaced, there is no need to configure the parameters.

[0003] There are existing technologies for storing control parameters in modules, but the cost is relatively high. This is because if the control parameter data needs to be stored in the module, a storage medium needs to be added, and an additional circuit is needed to solve the voltage mismatch between the storage medium and the module, as well as the module cascade problem, which increases the cost of the module.

[0004] Figure 1 The figure is a structural diagram of a solution in the prior art. Figure 1 Shows part of the structure used to read and write control parameters in SPI Flash. Figure 1As shown, SPI Flash is added to the module as a storage medium to save control parameters such as screen parameters and correction coefficients. In order for SPI Flash to work properly, it is also necessary to add resistors, LDO (low dropout regulator) chips and driver enhancement chips. The controller and the module are connected by cables, and the cables are relatively long, so a driver enhancement chip is needed to enhance the signal. After adding SPI Flash, an additional driver enhancement chip is needed to transmit the read and write signals of the controller to SPI Flash. The signal level output by the driver enhancement chip is 5V, and the signal received by SPI Flash is 3.3V, so a resistor needs to be connected in series at the connection between the driver enhancement chip and the SPI Flash pin to reduce the signal level voltage. The module itself uses 5V voltage as the working power supply, while SPIFlash uses 3.3V voltage as the working power supply, so it is necessary to add an LDO chip to convert the 5V voltage into 3.3V output as a power supply to the SPI Flash. The addition of the above circuit structure makes the cost of using SPI Flash as a storage medium higher. Moreover, Figure 1 In the solution, different signals from the controller need to be used to control each module separately. There is no way to connect multiple modules in series and control them with the same control signal, which means that the module cascade function cannot be realized.

[0005] Figure 2 This is a structural diagram of another solution in the prior art. Figure 1 Shows part of the structure used to read and write control parameters in SPI Flash. Figure 2 In the module, after adding SPI Flash as storage medium, a driver enhancement chip, LDO chip and microcontroller are also added. The controller exchanges data with the microcontroller through the driver enhancement chip. The microcontroller is used to read and write SPI Flash and provide control signals for SPI Flash. Microcontrollers of different modules can be used to transmit data to support module cascading. The LDO chip provides power for SPI Flash. Figure 2 In the scheme shown, since a single chip microcomputer is used, it necessarily includes a complex digital circuit structure and is very costly. Summary of the invention

[0006] In view of the deficiencies of the prior art, the present invention discloses a storage control chip, an LED module and a storage control method to solve the problems of complex module circuit structure and high cost in the prior art.

[0007] The technical solution adopted by the present invention is as follows:

[0008] A storage control chip includes a first enhanced driving module and a level conversion module;

[0009] The first enhanced driving module is used to perform a first processing process; the first processing process includes enhancing the driving capability; the first enhanced driving module includes: a first data end group, used to transmit a first part of the refresh signal; a second data end group, used to transmit a first part of the read-write signal; a first multiplexed end group, used to transmit the second part of the refresh signal or the second part of the read-write signal; the refresh signal is used to control the screen refresh of the module; the read-write signal is used to control the reading and writing of the non-volatile memory storing the parameter information of the module; a third data end group, a fourth data end group and a second multiplexed end group, respectively, for correspondingly transmitting the signals transmitted by the first data end group, the second data end group and the first multiplexed end group and processed by the first processing process;

[0010] The level conversion module is used to perform a second processing process; the second processing process includes a step-down conversion; the level conversion module includes: a fifth data end group, connected to the second multiplexing end group and the fourth data end group; a sixth data end group, used to transmit the signal transmitted by the fifth data end group and processed by the second processing process.

[0011] A further technical solution is that it also includes a second enhanced driving module; the second enhanced driving module is used to execute a third processing process; the third processing process includes enhancing and / or generating a chip select signal.

[0012] Its further technical solution is that it also includes an LDO module; the LDO module is used to perform a fourth processing process on the working power signal; the fourth processing process includes a step-down conversion; the signal output by the LDO module provides working power for the non-volatile memory and other internal modules in the storage control chip.

[0013] Its further technical solution is that the storage control chip also includes external pins; the external pins include a first multiplexed pin group, a first transmission pin group, a second transmission pin group, a second multiplexed pin group, a third transmission pin group, a fourth transmission pin group and a fifth transmission pin group; the internal end of the first multiplexed pin group is connected to the first multiplexed end group; the internal end of the first transmission pin group is connected to the first data end group; the internal end of the second transmission pin group is connected to the second data end group; the internal end of the second multiplexed pin group is connected to the second multiplexed end group; the internal end of the third transmission pin group is connected to the third data end group; the internal end of the fourth transmission pin group is connected to the fourth data end group; the internal end of the fifth transmission pin group is connected to the sixth data end group.

[0014] An LED module, characterized in that a control signal is transmitted between a controller and the module; the control signal includes a refresh signal, a read / write signal and a chip select signal; the module includes:

[0015] A storage control chip as described in any one of the above items;

[0016] A driving enhancement chip, used for receiving the third partial refresh signal, executing a fifth processing process, and outputting a signal corresponding to the third partial refresh signal; the fifth processing process includes enhancing driving capability;

[0017] A non-volatile memory, used to store control parameters of the module; the control parameters include screen parameters and correction coefficients;

[0018] The input end of the storage control chip and the input end of the drive enhancement chip are connected to the data transmission end of the controller; the read and write ends of the non-volatile memory are connected to the sixth data end group of the storage control chip; the non-volatile memory also receives the working power signal and chip select signal output by the storage control chip; the third data end group and the second multiplexing end group of the storage control chip, as well as the output end of the drive enhancement chip are all connected to the drive chip of the module.

[0019] A further technical solution is that the module is as described above; there are N modules, and the N modules are cascaded in sequence;

[0020] The third data end group, the fourth data end group and the second multiplexing end group of the nth storage control chip are respectively connected to the first data end group, the second data end group and the first multiplexing end group of the n+1th storage control chip; the first chip selection signal output end of the nth storage control chip is connected to the chip selection signal input end of the n+1th storage control chip; n and N are natural numbers; 1≤n≤N-1; when n=1, the first data end group, the second data end group and the first multiplexing end group of the nth storage control chip are connected to the data transmission end of the controller, and the chip selection signal input end of the nth storage control chip is connected to the data transmission end of the controller;

[0021] The third data terminal group and the second multiplexing terminal group of the nth storage control chip are also connected to the driving chip of the nth module; the sixth data terminal group, the power signal output terminal and the second chip selection signal output terminal of the nth storage control chip are connected to the nth non-volatile memory;

[0022] A storage control method for an LED module, including a control method for a storage control chip:

[0023] The first enhanced driving module receives the refresh signal and executes a first processing process; the first processing process includes enhancing the driving capability; the LED display screen receives the refresh signal processed by the first processing process and refreshes the display content;

[0024] Alternatively, the second enhanced driving module receives the chip select signal and performs a third processing process; the third processing process includes enhancing and / or generating the chip select signal; thereafter, the first enhanced driving module transmits the read / write signal and performs the first processing process; the level conversion module transmits the read / write signal processed by the first processing process and performs a second processing process, the second processing process includes a step-down conversion; the non-volatile memory transmits the read / write signal processed by the second processing process to perform parameter reading and writing;

[0025] The second part of the refresh signal and the second part of the read-write signal are both input through the first multiplexing terminal group; the non-volatile memory determines whether to start the working state according to the chip selection signal.

[0026] A further technical solution is that the LDO module receives a working power supply signal and executes a fourth processing process; the fourth processing process includes a step-down conversion; the signal output by the LDO module provides working power for the non-volatile memory and other internal modules in the storage control chip.

[0027] A further technical solution is to further include a storage control method for the N modules:

[0028] The nth storage control chip outputs the refresh signal processed by the first processing process to the driving chip of the nth module to control the screen refresh of the nth module. At the same time, the nth storage control chip outputs the refresh signal processed by the first processing process to the n+1th storage control chip; n and N are natural numbers; 1≤n≤N-1;

[0029] Alternatively, the nth storage control chip receives a chip select signal and transmits the chip select signal to the nth non-volatile memory, and the nth level conversion module transmits the read / write signal processed by the first processing process and the second processing process in sequence to the nth non-volatile memory, and performs parameter reading and writing on the nth non-volatile memory; at the same time, the nth level conversion module transmits the chip select signal to the n+1th storage control chip, and transmits the read / write signal processed by the first processing process to the n+1th storage control chip;

[0030] The n+1th storage control chip controls the screen refresh of the n+1th module or reads and writes parameters to the n+1th non-volatile memory.

[0031] A further technical solution is that the chip selection signal is a level sequence; the level sequence includes N unit signals, each of which is a first level signal or a second level signal different from the first level signal;

[0032] The nth storage control chip receives m unit signals, forwards the first m-1 unit signals of the level sequence to the n+1th storage control chip, and latches the last unit signal; wherein n+m-1=N;

[0033] When the received unit signal is a first level signal, the non-volatile memory is selected and starts to execute the second processing process; when the received unit signal is a second level signal, the non-volatile memory is not selected and does not work.

[0034] The beneficial effects of the present invention are as follows:

[0035] (1) The present invention uses the simplest control logic. Complex control logic will inevitably lead to an increase in digital electronics costs. The present invention combines the simplest digital logic in the level conversion module to run the second processing process (step-down conversion) on the read and write signals. At the same time, the working power supply is also stepped down through the integrated LDO module. At the same time, the present invention also prefers the simplest control method for the cascading of modules, and controls the read and write status of each level of non-volatile memory through the transmission of level signals. The present invention reduces the logic control cost of the circuit to a minimum from multiple aspects through a simple logic control process.

[0036] (2) Compared with the prior art, the present invention does not increase the number of chips. Compared with some prior art, the present invention even reduces the number of chips while achieving the same function. In the prior art, in order to achieve the control of the module signal, at least two driver enhancement chips are required to enhance the module refresh signal. If it is necessary to further read and write the non-volatile memory, it is necessary to add at least one additional driver enhancement chip (20 pins) for enhancing the read and write signals and a storage control chip (12 pins) for converting the signal into a voltage suitable for the non-volatile memory operating voltage on the basis of the two driver enhancement chips. The storage control chip and the corresponding control method proposed by the present invention are based on the prior art, integrating the enhanced driving module and the level conversion module, combining the multiplexing of the pins, and realizing the functions of enhancing the read-write signal and stepping down the read-write signal at the same time, without affecting the enhancement of the refresh signal of the original module. Furthermore, by processing the chip select signal, the cascading of the module is supported, which is equivalent to replacing a driving enhancement chip (20 pins) in the prior art with a storage control chip (24 pins), and only increasing the cost of the level conversion module and the pins by a few cents. Generally speaking, the increase in the number of chips means a substantial increase in cost, which is particularly reflected in the packaging cost of the chip. Based on this, the present invention has obvious advantages over the prior art.

[0037] (3) The present invention also proposes a solution for multiplexing pins, multiplexing the input pins of a part of the module's refresh signal and a part of the read / write signal of the non-volatile memory, and multiplexing the corresponding output pins. The packaging cost of the chip mainly depends on the number of pins. Multiplexing pins can reduce the number of pins, thereby further reducing the cost of the chip.

[0038] The above three features of the present invention do not exist independently, but have the benefit of mutual cooperation. Together, they can realize a significant reduction in the cost of the entire chip, and can fully realize the refresh function of the LED module and the read and write function of the non-volatile memory, and support the cascading of modules. If any of the above features cannot be realized, that is, only one or two of the features are available, the cost will increase significantly. In this field, the annual sales volume of LED modules is more than 100 million pieces, so even if the cost is reduced by a few cents or a few dimes, it will have a huge scale effect and objectively achieve a significant technical effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 The figure is a structural diagram of a solution in the prior art.

[0040] Figure 2 This is a structural diagram of another solution in the prior art.

[0041] Figure 3 It is an overall schematic diagram of the structure of the technical solution of the present invention.

[0042] Figure 4 A schematic diagram of an embodiment of the internal module structure of a storage control chip.

[0043] Figure 5 The diagram is a schematic diagram of an embodiment of the structure of the external pins of a storage control chip.

[0044] Figure 6 A schematic diagram of an embodiment of the structure of a module.

[0045] Figure 7 A schematic diagram of an embodiment of a module cascade structure.

[0046] Figure 8 Schematic diagram of signal transmission between the controller and the module.

[0047] Fig. 9 Schematic diagram of signal transmission between the storage control chip and the non-volatile memory. DETAILED DESCRIPTION

[0048] The specific implementation of the present invention will be described below in conjunction with the accompanying drawings.

[0049] Figure 3It is a schematic diagram of the overall structure of the technical solution of the present invention. Figure 3 As shown, the present invention discloses a storage control chip for reading and writing a non-volatile memory (for example, SPI Flash), and the non-volatile memory stores the control parameters of the LED module. The present invention realizes the driving enhancement function and voltage reduction function of the read and write signals by integrating the enhanced driving module and the level conversion module, and combines the multiplexing of the pins and the simplest logic control method, without affecting the original screen refresh function of the LED module, and further supports module cascading through the transmission of the chip select signal. The present invention reduces the implementation cost of the entire technology to a minimum through the synergistic effect of the above multiple means, and has superior technical effects compared to the prior art.

[0050] Example 1.

[0051] Embodiment 1 discloses a storage control chip for an LED module, which is used to receive a control signal from a controller, refresh an LED screen, and read and write a non-volatile memory. Figure 4 FIG. 1 is a schematic diagram of an embodiment of the internal module structure of a storage control chip. Figure 4 As shown, including:

[0052] The first enhanced driving module 1 is used to perform a first processing process. The first processing process includes enhancing the driving capability of the input signal. The first enhanced driving module includes:

[0053] The first data terminal group 101 is used to transmit a first partial refresh signal.

[0054] The second data terminal group 102 is used to transmit the first part of the read / write signal.

[0055] The first multiplexing terminal group 103 is used to transmit the second part of the refresh signal or the second part of the read / write signal. The refresh signal is used to control the screen refresh of the module. The read / write signal is used to read and write the non-volatile memory storing the parameter information of the module. The parameter information of the module can be screen parameters and correction coefficients, etc.

[0056] The third data end group 104, the fourth data end group 105 and the second multiplexing end group 106 are respectively used to transmit the signals transmitted by the first data end group 101, the second data end group 102 and the first multiplexing end group 103 and processed by the first processing process.

[0057] The level conversion module 2 is used to perform the second processing process. The second processing process includes step-down conversion. The level conversion module 2 includes: a fifth data terminal group 201, connected to the second multiplexing terminal group 106 and the fourth data terminal group 105. A sixth data terminal group 202 is used to transmit the signal transmitted by the fifth data terminal group 201 and processed by the second processing process.

[0058] The second driving enhancement module 3 is used to perform a third processing process. The third processing process includes enhancing and / or generating a chip select signal. The second driving enhancement module 3 includes a chip select signal input terminal 301 for receiving a chip select signal, and also includes a first chip select signal output terminal 302 and a second chip select signal 303. The first chip select signal output terminal 302 outputs an enhanced signal, and the signal output by the second chip select signal output terminal 303 is generated by the second driving enhancement module and can be used to select a non-volatile memory.

[0059] The LDO module 4 is used to perform the fourth processing process. The fourth processing process includes step-down conversion of the working power supply signal. The power supply signal input terminal 401 of the LDO module inputs a 5V voltage signal, and the multiple power supply signal output terminals 402 output 3.3V voltage signals. On the one hand, the storage control chip is output to provide a working power supply signal for the non-volatile memory, so that there is no need to add an additional power supply processing chip for the work of the non-volatile memory in the module. On the other hand, it also provides working power for other internal modules of the storage control chip.

[0060] Furthermore, the storage control chip also includes external pins. Figure 5 The diagram is a schematic diagram of an embodiment of the structure of the external pins of a storage control chip. Figure 4 and Figure 5 The relationship is, Figure 4 for Figure 5 The internal functional modules, Figure 5 The figure shows the package pins outside the chip. The signal transmission end of the functional module is connected to the internal end of the corresponding pin inside the chip, and the external end of the pin is used to connect to the circuit structure outside the chip. Figure 5 As shown, the external pins include a first multiplexing pin group 501 , a first transmission pin group 502 , a second transmission pin group 503 , a second multiplexing pin group 504 , a third transmission pin group 505 , a fourth transmission pin group 506 and a fifth transmission pin group 507 .

[0061] Combination Figure 4 , Figure 5 , the internal end of the first multiplex pin group 501 is connected to the first multiplex end group 103. The internal end of the first transmission pin group 502 is connected to the first data end group 101. The internal end of the second transmission pin group 503 is connected to the second data end group 102. The external end of the first multiplex pin group 501, the external end of the first transmission pin group 502 and the external end of the second transmission pin group 503 are used to connect to the controller, or in the case of cascading, are also used to connect to the storage control chip of the previous level.

[0062] The internal end of the second multiplex pin group 504 is connected to the second multiplex terminal group 106. The internal end of the third transmission pin group 505 is connected to the third data terminal group 104. The internal end of the fourth transmission pin group 506 is connected to the fourth data terminal group 105. The internal end of the fifth transmission pin group 507 is connected to the sixth data terminal group 202. The external end of the second multiplex pin group 504 and the external end of the third transmission pin group 505 are used to connect the driver chip of the module, and the external end of the fifth transmission pin group 507 is used to connect the non-volatile memory. Or in the case of cascading, the external end of the second multiplex pin group 504, the external end of the third transmission pin group 505 and the external end of the fourth transmission pin group 506 are simultaneously used to connect the storage control chip of the next level.

[0063] The external pins also include a chip select signal input pin 508, a first chip select signal output pin 509, and a second chip select signal output pin 510. The chip select signal input pin 508 is connected to the controller or the upper level storage control chip to receive the chip select signal. The first chip select signal output pin 509 is connected to the next level storage control chip in the case of cascading. The second chip select signal output pin 510 is connected to the non-volatile memory.

[0064] The external pins also include a power signal output pin 511, which outputs a 3.3V voltage to provide working power for the non-volatile memory.

[0065] Embodiment 1 discloses a storage control chip for an LED module, which is suitable for screen refresh control of the LED module and data reading and writing of a non-volatile memory. The storage control chip integrates an enhanced driving module and a level conversion module, and uses one chip to simultaneously realize the process of processing a part of the module's refresh signal and processing the non-volatile memory read and write signal, thereby saving the number of chips and saving costs without affecting the function. The level conversion module directly outputs a data transmission signal that is suitable for the non-volatile memory to work in terms of voltage, without adding a step-down chip to the module. The working power supply signal is also stepped down through the LDO module, so there is no need to connect a resistor in series in the module circuit to obtain a working power supply signal suitable for the non-volatile memory. The storage control chip also further saves the chip packaging cost by reusing external pins.

[0066] In addition, since the first enhanced driving module can enhance the read and write signals of the non-volatile memory while enhancing the module refresh signal, and combined with the transmission of the chip select signal by the second enhanced driving module, the storage control chip also supports the module cascade working state. Without adding additional chips, it can be ensured that the signal has sufficient driving capability in the cascade state, ensuring that each level of module and each level of non-volatile memory can work normally. The storage control chip transmits the chip select signal through the second enhanced driving module to support the cascade working state.

[0067] The enhanced driving module of Example 1 can select a module with similar functions to the chip model 74HC245, which has a signal enhancement function but does not include the chip packaging structure. Those skilled in the art will know that the enhanced driving module can also use circuits of other structures as long as the signal enhancement function can be achieved and there are a sufficient number of input terminals and output terminals.

[0068] Example 2.

[0069] Embodiment 2 discloses a storage control chip for an LED module. Compared with Embodiment 1, Embodiment 2 is one of the specific solutions for the refresh signal and read / write signal processed in Embodiment 1. The refresh signals processed by the storage control chip in Embodiment 2 are the row signal and latch signal of the module. The read / write signal is a signal for reading and writing parameters stored in the SPI Flash. Based on Embodiment 1, those skilled in the art can also process the read / write signal and other types of LED module refresh signals simultaneously through the storage control chip according to actual needs.

[0070] like Figure 4 , Figure 5 As shown, embodiment 2 includes:

[0071] The first enhanced driving module 1 is used to perform a first processing process. The first processing process includes enhancing the driving capability of the input signal. The first enhanced driving module 1 includes:

[0072] The first data terminal group 101 is used to input the first partial refresh signal LED3 A, LED4 A, LED5 A, LED6 A. The first partial refresh signal includes a part of the LED row signal and the latch signal, which are processed by the first processing process to obtain the row signal with enhanced driving and the latch signal LED3 B, LED4 B, LED5 B, LED6 B, respectively, and are output by the third data terminal group 104.

[0073] The second data terminal group 102 is used to transmit a first part of the read / write signal. The first part of the read / write signal is a master input slave output signal MISO A. After a first processing process, the corresponding signal MISO B is obtained and transmitted by the fourth data terminal group 105 .

[0074] The first multiplexing terminal group 103 is used to input the second part of the refresh signal or the second part of the read / write signal. The second part of the refresh signal includes another part of the LED row signal LED1 A, LED2 A, which respectively correspond to the row signals LED1 B, LED2 B with enhanced driving after the first processing process, and are output by the second multiplexing terminal group 106. The second part of the read / write signal is the Flash clock signal CLK A and the master output slave input signal MOSI A, which respectively correspond to the signals CLK B and MOSI B after the first processing process, and are output by the second multiplexing terminal group 106.

[0075] The refresh signal composed of the first refresh signal and the second refresh signal is used to control the LED row signal and the latch signal. The read and write signal is used to read and write the content stored in the SPI Flash. The SPI Flash can store the screen parameters and correction coefficients of the module.

[0076] The level conversion module 2 is used to perform the second processing process, and the second processing process includes step-down conversion. The level conversion module 2 includes a fifth data terminal group 201, which is connected to the second multiplexing terminal group 106 and the fourth data terminal group 105, receives signals CLKB, MOSI B and MISO B, and obtains signals Flash CLK, Flash MOSI and Flash MISO respectively after the second processing process, which are transmitted by the sixth data terminal group 202.

[0077] The second enhanced driving module 3 is used to perform the third processing process. The third processing process includes enhancing and / or generating a chip select signal. The second enhanced driving module enhances the chip select signal SEL A and outputs a signal SEL B, which is used to be transmitted to the next level storage control chip in the case of cascading, and generates a signal FLASH CS in the second enhanced driving module for selecting a non-volatile memory.

[0078] The LDO module 4 is used to perform a fourth processing process on the working power signal; the fourth processing process includes a step-down conversion; a 5V voltage signal is input to the power signal input end of the LDO module 4, and a 3.3V voltage is output to the power signal output end of the LDO module 4, providing working power for the non-volatile memory and simultaneously providing working power for other modules in the storage control chip.

[0079] The method of connecting the inner end and the outer end of the pin structure of the second embodiment is the same as that of the first embodiment.

[0080] On the basis of the technical effects that can be achieved in Example 1, Example 2 shows an implementation scheme for processing specific signals. In this scheme, the enhanced driving module and the level conversion module are integrated into a storage control chip, and the number of external pins of the storage control chip is reduced to a minimum through pin multiplexing, and the row signal latch signal and the SPI Flash reading and writing functions of the control module can be realized. It can be understood by those skilled in the art that other refresh parameters of the module and the SPI Flash read and write signals can also be integrated as needed and processed by the storage control chip.

[0081] For most LED modules, there are 14 signals that need to be enhanced: five row signals ABCDE, latch signal, enable (or grayscale clock) signal, data clock signal and two groups of RGB signals. There are also LED modules with different numbers of RGB signals, for example, there may be four groups of RGB signals or only one group of RGB signals. There are also LED modules with different numbers of row signals, for example, there may be only three row signals ABC. Some LED modules also have special signals added, for example: adding serial port signals to communicate with the MCU on the module. However, as long as it is a color LED module, it needs to refresh more than eight signals, and using only one driver enhancement chip cannot enhance all signals at the same time.

[0082] In a specific implementation, the signals to be processed can be allocated as needed, a part of the refresh signal is enhanced by the driver enhancement chip, and another part of the refresh signal is enhanced by the storage control chip, and at the same time, the storage control chip can also process the read and write signals of the SPI Flash, and control the operation of the non-volatile memory through the chip selection signal.

[0083] Example 3.

[0084] Embodiment 3 discloses an LED module, wherein control signals are transmitted between a controller and the module, and the control signals include a refresh signal, a read / write signal, and a chip select signal. Figure 6 FIG. 1 is a schematic diagram of an embodiment of the structure of a module. Figure 6 As shown, the module includes:

[0085] The structure and function of the storage control chip refer to Example 1 or Example 2.

[0086] The driver enhancement chip is used to receive the third partial refresh signal, execute the fifth processing process, and output a signal corresponding to the third partial refresh signal. The fifth processing process includes enhancing the driving capability. The driver enhancement chip can be a chip of model 74HC245.

[0087] The third part of the refresh signal and the first part of the refresh signal and the second part of the refresh signal processed by the storage control chip together constitute the entire screen refresh signal of an LED module, which is input to the driver chip of the module. The specific signal type in each part of the refresh signal can be allocated according to actual conditions and actual needs. If corresponding to Example 2, when the storage control chip is used to process the five row signals ABCDE and latch signals of the LED, the third part of the refresh signal may include the RGB signal, enable (or grayscale clock) signal and / or data clock signal of the module.

[0088] The non-volatile memory, specifically SPI Flash, is used to store the control parameters of the module, including screen parameters and correction coefficients.

[0089] The external ends of the first multiplexed pin group 501 of the storage control chip, the external ends of the first transmission pin group 502 and the second transmission pin group 503 are all connected to the data transmission end of the controller.

[0090] The external end of the second multiplexed pin group 504 of the storage control chip, the external end of the third transmission pin group 505, and the output pin of the driving enhancement chip are connected to the driving chip of the module.

[0091] The external end of the fifth transmission pin group 507 of the storage control chip is connected to the non-volatile memory. The non-volatile memory and the storage control chip are connected via a standard SPI interface, and the signal voltage is 3.3V.

[0092] The external end of the chip select signal input pin 508 of the storage control chip is connected to the controller to receive the chip select signal of the controller; the external end of the second chip select signal output pin 510 is connected to the non-volatile memory to transmit the chip select signal to the non-volatile memory to determine the working state of the non-volatile memory.

[0093] The external end of the power signal output pin 511 of the storage control chip is connected to the non-volatile memory to provide a 3.3V operating voltage for the non-volatile memory.

[0094] The module in Example 3 includes two chips, in which the driver enhancement chip is used to realize the processing of refresh signals of a part of the modules. The storage control chip can realize the processing of refresh signals of another part of the modules and the enhancement and voltage reduction processing of the read and write signals of the non-volatile memory by integrating the first enhancement drive module and the level conversion module, and combining the multiplexing of the external pins. The two processes in the storage control chip do not interfere with each other. The signal involved in the enhancement processing of the signal is a 5V voltage signal, and the voltage reduction processing of the signal is to convert the 5V signal into a 3.3V voltage signal. The storage control chip also includes an LDO module, which outputs a 3.3V working power supply signal and provides it to the non-volatile memory. And the storage control chip transmits the chip select signal to the non-volatile memory through the second enhancement drive module to determine the working state of the non-volatile memory.

[0095] Therefore, there is no need to add an additional LDO chip, a single-chip microcomputer, or a series resistor in the module. Moreover, since the storage control chip can also reuse the output pins, combined with the chip select signal, it provides the conditions for the cascading of the module. The number of chips required in the module in Example 3 is the same as that in the prior art, or even less than that in some prior arts, but more and more complete functions are realized.

[0096] Example 4.

[0097] Embodiment 4 discloses a structure of cascading multiple LED modules. The structure and function of each module in Embodiment 4 refer to Embodiment 3, and the structure and function of the storage control chip refer to Embodiment 1 or Embodiment 2. Figure 7 FIG. 1 is a schematic diagram of an embodiment of a module cascade structure. Figure 7 As shown, in Example 4, n and N are natural numbers; 1≤n≤N-1;

[0098] There are N modules, which are cascaded in sequence; each module has several LED driver chips.

[0099] The third data terminal group 104, the fourth data terminal group 105 and the second multiplexing terminal group 106 of the nth storage control chip are respectively connected to the first data terminal group 101, the second data terminal group 102 and the first multiplexing terminal group 103 of the n+1th storage control chip through external pins. When n=1, the first data terminal group 101, the second data terminal group 102 and the first multiplexing terminal group 103 of the nth storage control chip are connected to the output end of the controller.

[0100] The first chip selection signal output terminal 509 of the nth storage control chip is connected to the chip selection signal input terminal 508 of the n+1th storage control chip. When n=1, the chip selection signal input terminal 508 of the nth storage control chip is connected to the data transmission terminal of the controller.

[0101] The third data terminal group 104 and the second multiplexing terminal group 106 of the nth storage control chip are also connected to the driving chip of the nth module. The sixth data terminal group 202 of the nth storage control chip is connected to the nth non-volatile memory. The second chip selection signal output terminal 510 of the nth storage control chip is connected to the nth non-volatile memory to transmit the chip selection signal. The power signal output terminal 511 of the nth storage control chip is connected to the nth non-volatile memory to provide a 3.3V working voltage for the non-volatile memory.

[0102] Each level of module in Example 4 performs a step of enhancing the input signal, which can ensure that the signal received by each level of storage control chip has sufficient driving capability and can normally control each level of module and each level of non-volatile memory.

[0103] Example 5

[0104] Embodiment 5 discloses a control method for a module, wherein the structure and function of the module refer to Embodiment 3, and the structure and function of the storage control chip refer to Embodiment 1 and Embodiment 2.

[0105] In the control method of the module, the control method of the storage control chip includes:

[0106] The first enhanced driving module receives the refresh signal and executes the first processing process. The first processing process includes the enhancement of the driving capability. The module receives the refresh signal processed by the first processing process and performs the screen refresh of the module.

[0107] Alternatively, the second enhanced driving module receives the chip select signal and executes a third processing process; the third processing process includes enhancing and / or generating the chip select signal; thereafter, the first enhanced driving module transmits the read / write signal and executes the first processing process; the level conversion module transmits the read / write signal processed by the first processing process and executes the second processing process, and the second processing process includes a step-down conversion; the non-volatile memory transmits the read / write signal processed by the second processing process to perform parameter reading and writing. Figure 8 Schematic diagram of signal transmission between the controller and the module. Figure 8 The transmission of communication signals between the controller and the module is shown. The chip select signal SEL is used to select the module. The controller sends the clock signal through the CLK signal, sends instructions and data through the MOSI signal, and receives instructions or data through the MISO signal. The non-volatile memory receives the chip select signal processed by the third processing process to determine the working state, and receives the read and write signal processed by the second processing process to read and write parameters. Fig. 9 This is a schematic diagram of signal transmission between the storage control chip and the non-volatile memory. Fig. 9In fact, SEL, MOSI, MISO and CLK are the communication data between the controller and SPI Flash. The storage control chip performs enhancement and voltage reduction processes on them.

[0108] Among them, the second part refresh signal and the second part read-write signal are both input through the first multiplexing terminal group 103, and the second part refresh signal and the second part read-write signal processed by the first processing process are both output through the second multiplexing terminal group 106, which can control the screen refresh of the module and also control the reading and writing of the non-volatile memory.

[0109] In the process of controlling the module, although the read / write signal and the refresh signal exist at the same time, the read / write of the non-volatile memory and the screen refresh of the LED module will not occur at the same time. If the chip select signal sent by the controller does not select any non-volatile memory, the Flash CS chip select signal output by the second drive enhancement module of all modules is in an invalid state (for example, it can be a high level). At this time, the read / write signal of the non-volatile memory has no effect on the non-volatile memory. At this time, the storage control chip enhances the driving capability of the first part of the refresh signal and the second part of the refresh signal, and outputs them to control the refresh of the LED module.

[0110] If the chip select signal sent by the controller selects one of the non-volatile memories, the Flash CS chip select signal output by the second driver enhancement module of the corresponding module is in a valid state (for example, it can be a low level), and the non-volatile memory is read and written at this time. During this process, the enable signal (or grayscale clock signal) in the screen refresh signal can be turned off to control the LED module not to refresh the screen. At this time, the LED screen does not display any content, and only the non-volatile memory is read and written.

[0111] During the reading and writing process of the non-volatile memory, the level conversion module performs the second processing process, changes the voltage of the read and write signals, and does not involve complex logic control. Therefore, the cost of the level conversion module is very low, so the cost of the entire storage control chip is also reduced to a minimum in this regard.

[0112] Example 6.

[0113] Embodiment 6 discloses a control method for modules in a cascade state. Based on the control method of embodiment 5, embodiment 6 includes N modules and N modules. n and N are natural numbers; 1≤n≤N-1.

[0114] The nth storage control chip outputs the refresh signal processed by the first processing process to the driving chip of the nth module to control the screen refresh of the nth module. At the same time, the nth storage control chip outputs the refresh signal processed by the first processing process to the n+1th storage control chip. The n+1th storage control chip controls the driving chip of the n+1th module.

[0115] Alternatively, the nth storage control chip outputs a chip select signal to the nth non-volatile memory, and the nth level conversion module outputs a read / write signal processed by the first processing process and the second processing process in sequence to the nth non-volatile memory to control the reading and writing of the nth non-volatile memory, and at the same time, the nth level conversion module outputs a read / write signal processed by the first processing process to the n+1th storage control chip, and the nth storage control chip outputs a chip select signal to the n+1th storage control chip. The n+1th storage control chip controls the n+1th non-volatile memory.

[0116] Embodiment 6 provides a control method for module cascading. No new chip is added for module cascading, and no more expensive MCU is needed in the module to realize the cascading function.

[0117] Example 7.

[0118] Embodiment 7 is based on Embodiment 6 and proposes a preferred control method for the communication between the controller and each level of modules in the cascade state, thereby further reducing the logic control cost on the basis of reducing the structural cost.

[0119] In Embodiment 7, the read and write signals for the non-volatile memory include a chip select signal. The chip select signal is a level sequence. For a system including N modules and N modules, the level sequence includes N unit signals, and the unit signal is a first level signal or a second level signal. The first level signal and the second level signal are different from each other, and the first level signal and the second level signal are high level signals, low level signals and / or a combination of high level signals and low level signals with different durations.

[0120] After receiving m unit signals, the nth storage control chip forwards the first m-1 unit signals of the level sequence to the n+1th storage control chip, and latches the last unit signal. Where n+m-1=N. m is a natural number, and 1≤m≤N.

[0121] When the latched unit signal is a first level signal, the corresponding non-volatile memory is selected. When the latched unit signal is a second level signal, the corresponding non-volatile memory is not selected and does not work.

[0122] For example, a combination of a 750ns high level signal and a 250ns low level signal can be set as a first level signal, represented by 1, a combination of a 250ns high level signal and a 750ns low level signal can be set as a second level signal, represented by 0, and a long low level is idle. The system includes 4 modules. The level sequence is a signal of 4 units 0010.

[0123] The first storage control chip receives the four unit signals 0010, forwards the first three unit signals 001 to the second storage control chip, and latches the last unit signal 0.

[0124] The second storage control chip receives three unit signals 001, forwards the first two unit signals 00 to the third storage control chip, and latches the last unit signal 1.

[0125] The third storage control chip receives two unit signals 00, forwards the first unit signal 0 to the fourth storage control chip, and latches the last unit signal 0.

[0126] The fourth storage control chip receives 1 unit signal 0 and latches it.

[0127] The non-volatile memory corresponding to the second storage control chip is selected through the above level sequence.

[0128] Embodiment 7 provides a control method that can select the working state of each level of non-volatile memory in a cascade state, and its control method is very simple and can be implemented with only a small amount of logic circuits, without increasing the complexity of the module circuit, further reducing the circuit cost.

[0129] The above description is an explanation of the present invention, not a limitation of the present invention. The scope of the present invention is defined in the claims. The present invention may be modified in any form without violating the basic structure of the present invention.

Claims

1. A storage control chip, characterized in that: It includes a first enhanced driving module and a level conversion module; The first enhanced driving module (1) is used to execute a first processing process; The first processing includes enhancing the driving capability; The first enhanced driving module (1) comprises: a first data end group (101) for transmitting a first part of a refresh signal; a second data end group (102) for transmitting a first part of a read / write signal; a first multiplexing end group (103) for transmitting a second part of the refresh signal or a second part of the read / write signal; the refresh signal is used to control the screen refresh of the module; the read / write signal is used to control the reading and writing of a non-volatile memory storing parameter information of the module; a third data end group (104), a fourth data end group (105) and a second multiplexing end group (106) for correspondingly transmitting the signals transmitted by the first data end group (101), the second data end group (102) and the first multiplexing end group (103) and processed by the first processing process; The level conversion module (2) is used to perform a second processing process; the second processing process includes a step-down conversion; the level conversion module (2) includes: a fifth data terminal group (201) connected to the second multiplexing terminal group (106) and the fourth data terminal group (105); and a sixth data terminal group (202) used to transmit the signal transmitted by the fifth data terminal group (201) and processed by the second processing process.

2. The storage control chip according to claim 1, characterized in that: It also comprises a second enhanced driving module (3); the second enhanced driving module (3) is used to execute a third processing process; the third processing process comprises enhancing and / or generating a chip selection signal.

3. The storage control chip according to claim 1, characterized in that: It also includes an LDO module (4); the LDO module (4) is used to perform a fourth processing process on the working power supply signal; the fourth processing process includes a step-down conversion; the signal output by the LDO module (4) provides working power for the non-volatile memory and other internal modules in the storage control chip.

4. The storage control chip according to claim 3, characterized in that: The storage control chip further comprises external pins; the external pins comprise a first multiplexing pin group (501), a first transmission pin group (502), a second transmission pin group (503), a second multiplexing pin group (504), a third transmission pin group (505), a fourth transmission pin group (506) and a fifth transmission pin group (507); the internal end of the first multiplexing pin group (501) is connected to the first multiplexing end group (103); the internal end of the first transmission pin group (502) is connected to the first data end group (101); the internal end of the second transmission pin group (503) is connected to the second data end group (102); the internal end of the second multiplexing pin group (504) is connected to the second multiplexing end group (106); the internal end of the third transmission pin group (505) is connected to the third data end group (104); the internal end of the fourth transmission pin group (506) is connected to the fourth data end group (105); and the internal end of the fifth transmission pin group (507) is connected to the sixth data end group (202).

5. An LED module, characterized in that: The control signal is transmitted between the controller and the module; the control signal includes a refresh signal, a read / write signal and a chip select signal; the module includes: A storage control chip as claimed in any one of claims 1 to 4; A driving enhancement chip, used for receiving the third partial refresh signal, executing a fifth processing process, and outputting a signal corresponding to the third partial refresh signal; the fifth processing process includes enhancing the driving capability; A non-volatile memory, used to store control parameters of the module; the control parameters include screen parameters and correction coefficients; The input end of the storage control chip and the input end of the drive enhancement chip are connected to the data transmission end of the controller; the read / write end of the non-volatile memory is connected to the sixth data end group (202) of the storage control chip; the non-volatile memory also receives the working power supply signal and the chip selection signal output by the storage control chip; the third data end group (104) and the second multiplexing end group (106) of the storage control chip, and the output end of the drive enhancement chip are all connected to the drive chip of the module.

6. The LED module according to claim 5, characterized in that: The module as claimed in claim 5; there are N modules, and the N modules are cascaded in sequence; The third data end group (104), the fourth data end group (105) and the second multiplexing end group (106) of the nth storage control chip are respectively connected to the first data end group (101), the second data end group (102) and the first multiplexing end group (103) of the n+1th storage control chip; the first chip selection signal output end (302) of the nth storage control chip is connected to the chip selection signal input end (301) of the n+1th storage control chip; n and N are natural numbers; 1≤n≤N-1; when n=1, the first data end group (101), the second data end group (102) and the first multiplexing end group (103) of the nth storage control chip are connected to the data transmission end of the controller, and the chip selection signal input end (301) of the nth storage control chip is connected to the data transmission end of the controller; The third data terminal group (104) and the second multiplexing terminal group (106) of the nth storage control chip are also connected to the driving chip of the nth module; the sixth data terminal group (202), the power signal output terminal (402) and the second chip selection signal output terminal (303) of the nth storage control chip are connected to the nth non-volatile memory.

7. A storage control method for an LED module, characterized in that: Including the control method of storage control chip: The first enhanced driving module receives the refresh signal and performs a first processing process; the first processing process includes enhancing the driving capability; The LED display screen receives the refresh signal processed by the first processing process and refreshes the display content; Alternatively, the second enhanced driving module receives the chip select signal and performs a third processing process; the third processing process includes enhancing and / or generating the chip select signal; thereafter, the first enhanced driving module transmits the read / write signal and performs the first processing process; The level conversion module transmits the read / write signal processed by the first processing process and performs a second processing process, wherein the second processing process includes a step-down conversion; The non-volatile memory transmits the read / write signal processed by the second processing process to perform parameter reading and writing; The second part of the refresh signal and the second part of the read / write signal are both input through the first multiplexing terminal group (103); the non-volatile memory determines whether to start the working state according to the chip selection signal.

8. The storage control method for LED module according to claim 7, characterized in that: include: The LDO module (4) receives a working power supply signal and performs a fourth processing process; the fourth processing process includes a step-down conversion; the signal output by the LDO module (4) provides working power supply for the non-volatile memory and other internal modules in the storage control chip.

9. The storage control method for LED module according to claim 7, characterized in that: It also includes a storage control method for N modules: The nth storage control chip outputs the refresh signal processed by the first processing process to the driving chip of the nth module to control the screen refresh of the nth module. At the same time, the nth storage control chip outputs the refresh signal processed by the first processing process to the n+1th storage control chip; n and N are natural numbers; 1≤n≤N-1; Alternatively, the nth storage control chip receives a chip select signal and transmits the chip select signal to the nth non-volatile memory, and the nth level conversion module transmits the read / write signal processed by the first processing process and the second processing process in sequence to the nth non-volatile memory, and performs parameter reading and writing on the nth non-volatile memory; at the same time, the nth level conversion module transmits the chip select signal to the n+1th storage control chip, and transmits the read / write signal processed by the first processing process to the n+1th storage control chip; The n+1th storage control chip controls the screen refresh of the n+1th module or reads and writes parameters to the n+1th non-volatile memory.

10. The storage control method for LED module according to claim 9, characterized in that: The chip selection signal is a level sequence; the level sequence includes N unit signals, each of which is a first level signal or a second level signal different from the first level signal; The nth storage control chip receives m unit signals, forwards the first m-1 unit signals of the level sequence to the n+1th storage control chip, and latches the last unit signal; wherein n+m-1=N; When the received unit signal is a first level signal, the non-volatile memory is selected and starts to execute the second processing process; when the received unit signal is a second level signal, the non-volatile memory is not selected and does not work.

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