Semiconductor device for selectively performing isolation function and layout alternative method thereof

Abstract

A semiconductor device includes: a first active region and a second active region extending in a first direction, wherein the first active region and the second active region are arranged in a substrate; a first gate electrode extending in a second direction perpendicular to the first direction, wherein the first gate electrode extends continuously on the first active region and the second active region; a second gate electrode extending in the second direction on the first active region; a third gate electrode extending in the second direction on the first active region and the second active region; a first contact arranged on the first active region at a first side of the first gate electrode; a second contact arranged on the first active region at a second side of the second gate electrode; a third contact arranged on the first gate electrode; a fourth contact arranged on the second gate electrode; a first wire connected to the first gate electrode via the third contact; and a second wire overlapping with a portion of the first contact, a portion of the second contact, and a portion of the fourth contact, wherein a first voltage is provided to the second wire, wherein at least a portion of the second wire extends in the first direction, and at least a portion of the second wire intersects with the second gate electrode in a plan view.

Description

[0001] This case is a divisional application of the invention patent application with the application date of January 25, 2017, application number 201710061158.3, and invention name "Semiconductor device for selectively performing isolation function and layout alternative method thereof".

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 288,750, filed in the U.S. Patent and Trademark Office on January 29, 2016, and Korean Patent Application No. 10-2016-0058860, filed in the Korean Intellectual Property Office on May 13, 2016, the disclosures of which are incorporated herein by reference in their entirety. Background Art 1. Technical Field

[0005] Apparatuses consistent with exemplary embodiments relate to a semiconductor device, and more particularly, to a layout of a semiconductor device that selectively operates as an isolation circuit or a driving circuit.

[0006] 2. Related technical description

[0007] The size of semiconductor devices is gradually reduced as semiconductor devices are highly integrated and their storage capacity increases. Accordingly, the resolution of semiconductor manufacturing processes is increasing. However, the increased resolution of semiconductor manufacturing processes causes the distance between gate electrodes of semiconductor devices to decrease. In this case, unexpected short circuits or product defects also increase. For this reason, electrical insulation problems also begin to emerge.

[0008] Typically, an insulating film produced by a separate process such as a shallow trench isolation (STI) process can be used for semiconductor device insulation. Alternatively, a method of increasing the distance between gate electrodes or inserting a dummy gate can be used for semiconductor device insulation. However, because the chip size of the semiconductor device increases and additional / extra processes are performed, the efficiency of this method is very low. Summary of the invention

[0009] According to an exemplary embodiment, a system on chip includes: a first semiconductor device, the first semiconductor device includes a first transistor and a second transistor, the first transistor and the second transistor include a first gate electrode and a second gate electrode respectively, the first semiconductor device is arranged on an active region, the active region is arranged on a substrate, the active region extends in a first direction, and the first gate electrode and the second gate electrode extend in a second direction different from the first direction and are arranged along the first direction. The system on chip further includes a second semiconductor device, the second semiconductor device includes a third transistor and a fourth transistor, the third transistor and the fourth transistor include a third gate electrode and a fourth gate electrode respectively, the second semiconductor device is arranged on the active region, and the third gate electrode and the fourth gate electrode extend in the second direction and are arranged along the first direction. The second transistor is configured to be turned off in response to turning on the first transistor, the third transistor, and the fourth transistor, so as to electrically insulate the first transistor from a device adjacent to the first transistor.

[0010] According to an exemplary embodiment, a semiconductor device includes: an active region arranged on a substrate and extending in a first direction; and a first transistor, the first transistor including a first gate electrode and a first source and drain region arranged on the active region, the first source and drain region being arranged at opposite sides of the first gate electrode. The semiconductor device further includes a second transistor, the second transistor including a second gate electrode and a second source and drain region arranged on the active region, the second source and drain region being arranged at opposite sides of the second gate electrode; and a third transistor, the third transistor including a third gate electrode and a third source and drain region arranged on the active region, the third source and drain region being arranged at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode and the third gate electrode extending in a second direction different from the first direction and arranged along the first direction. The second transistor is configured to be turned on and off based on an operation mode of the semiconductor device.

[0011] According to an exemplary embodiment, a semiconductor device includes a first active region and a second active region, the first active region and the second active region extending in a first direction and arranged on a substrate along a second direction different from the first direction; and a first transistor, the first transistor including a first gate electrode and a first source and drain region, the first gate electrode being arranged on the first active region and the second active region and extending in the second direction, and the first source and drain region being arranged on the first active region and arranged at opposite sides of the first gate electrode. The semiconductor device further includes a second transistor, the second transistor including a second gate electrode and a second source and drain region, the second gate electrode being arranged on the first active region and extending in the second direction, and the second source and drain region being arranged on the first active region and arranged at opposite sides of the second gate electrode; and a third transistor, the third transistor including the first gate electrode and a third source and drain region, the third source and drain region being arranged on the second active region and arranged at opposite sides of the first gate electrode. The semiconductor device further includes a fourth transistor, the fourth transistor including a third gate electrode and a fourth source and drain region, the third gate electrode being arranged on the second active region and extending in the second direction, and the fourth source and drain region being arranged on the second active region and at an opposite side of the third gate electrode. A source or drain region shared by the first transistor and the second transistor among the first source and drain region and the second source and drain region is connected to a source or drain region shared by the third transistor and the fourth transistor among the third source and drain region and the fourth source and drain region, and the second transistor and the fourth transistor are configured to be turned on and off.

[0012] According to an exemplary embodiment, a semiconductor device includes a first active region and a second active region, the first active region and the second active region extending in a first direction and arranged on a substrate along a second direction different from the first direction; and a first transistor, the first transistor including a first gate electrode and a first source and drain region, the first gate electrode being arranged on the first active region and the second active region and extending in the second direction, and the first source and drain region being arranged on the first active region and arranged at opposite sides of the first gate electrode. The semiconductor device further includes a second transistor, the second transistor including a second gate electrode and a second source and drain region, the second gate electrode being arranged on the first active region and the second active region and extending in the second direction, and the second source and drain region being arranged on the first active region and arranged at opposite sides of the second gate electrode; and a third transistor, the third transistor including the first gate electrode and a third source and drain region, the third source and drain region being arranged on the second active region and arranged at opposite sides of the first gate electrode. The semiconductor device further includes a fourth transistor, the fourth transistor including the second gate electrode and a fourth source and drain region, the fourth source and drain region being arranged on the second active region and at an opposite side of the second gate electrode. A source or drain region shared by the first transistor and the second transistor among the first source and drain region and the second source and drain region is connected to a source or drain region shared by the third transistor and the fourth transistor among the third source and drain region and the fourth source and drain region.

[0013] According to an exemplary embodiment, a semiconductor device includes: a first active region and a second active region, which extend in a first direction, and the first active region and the second active region are arranged in a substrate; a first gate electrode, which extends in a second direction perpendicular to the first direction, wherein the first gate electrode extends continuously on the first active region and the second active region; a second gate electrode, which extends in the second direction on the first active region; a third gate electrode, which extends in the second direction on the first active region and the second active region; a first contact, which is arranged on the first active region at a first side of the first gate electrode; a second contact, which is arranged on the first active region at a second side of the second gate electrode; a third contact, which is arranged on the first gate electrode; a fourth contact, which is arranged on the second gate electrode; a first wire, which is connected to the first gate electrode via the third contact; and a second wire, which overlaps with a portion of the first contact, a portion of the second contact, and a portion of the fourth contact, wherein a first voltage is provided to the second wire, wherein at least a portion of the second wire extends in the first direction, and at least a portion of the second wire intersects with the second gate electrode in a plan view.

[0014] According to an exemplary embodiment, a semiconductor device includes: a first active region and a second active region, which extend along a first direction, and the first active region and the second active region are arranged in a substrate; a first gate electrode, which extends along a second direction perpendicular to the first direction, wherein the first gate electrode extends continuously on the first active region and the second active region; a second gate electrode, which extends along the second direction on the first active region; a third gate electrode, which extends along the second direction on the first active region and the second active region; a fourth gate electrode, which extends along the second direction on the second active region, wherein the second gate electrode and the fourth gate electrode are on a common range line; a first source / drain contact, which is arranged on the first active region at a first side of the first gate electrode; a second source / drain contact, which is arranged on the first active region at a second side of the second gate electrode; a third source / drain contact, which is arranged on the second active region at a first side of the first gate electrode; a fourth source / drain contact, which is arranged on the second active region at a first side of the third gate electrode; a first gate contact, which is arranged on a first gate electrode; a second gate contact disposed on the second gate electrode; a third gate contact disposed on the fourth gate electrode; a first wire connected to the first gate electrode via the first gate contact; a second wire overlapping a portion of the first source / drain contact, a portion of the second source / drain contact, and a portion of the second gate contact; and a third wire overlapping a portion of the third source / drain contact, a portion of the fourth source / drain contact, and a portion of the third gate contact, wherein a first voltage is supplied to the second wire, wherein a second voltage is supplied to the third wire, wherein at least a portion of the third wire extends in a first direction, and at least a portion of the third wire intersects with the fourth gate electrode in a plan view, and wherein the first active region and the second active region extend continuously, so that at least a portion of the first gate electrode, at least a portion of the second gate electrode, and at least a portion of the third gate electrode overlap with the first active region in a plan view, and at least a portion of the first gate electrode, at least a portion of the third gate electrode, and at least a portion of the fourth gate electrode overlap with the second active region in a plan view.

[0015] According to an exemplary embodiment, a semiconductor device includes: a first active region and a second active region, which extend along a first direction, and the first active region and the second active region are arranged in a substrate; a first gate electrode, which extends along a second direction perpendicular to the first direction, wherein the first gate electrode extends continuously on the first active region and the second active region; a second gate electrode, which extends along the second direction on the first active region; a third gate electrode, which extends continuously on the first active region and the second active region along the second direction; a fourth gate electrode, which extends along the second direction on the second active region, wherein the second gate electrode and the fourth gate electrode are on a common range line; a wire, which extends along the first direction and is configured to provide a power supply voltage; and a gate contact, which is arranged on the second gate electrode, wherein the second gate electrode extends through the wire, wherein a portion of the gate contact is arranged at an intersection of the second gate electrode and the wire, and wherein a gap extending along the second direction exists between the second gate electrode and the fourth gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a plan view showing a layout of a semiconductor device according to an exemplary embodiment.

[0017] Figure 2 is a circuit diagram of a semiconductor device in a first operation mode according to an exemplary embodiment.

[0018] Figure 3 is a circuit diagram of a semiconductor device in a second operation mode according to an exemplary embodiment.

[0019] Figure 4 is a block diagram illustrating a system on chip (SOC) according to an exemplary embodiment.

[0020] Figure 5 It is shown Figure 4 A block diagram of one of the first and second static random access memories (SRAMs) shown in FIG.

[0021] Figure 6 It is shown in Figure 4 FIG. 4 is a view of the waveforms of the signals during the read operation of the first SRAM shown in FIG.

[0022] Figure 7 It is shown in Figure 4 FIG. 4 is a view of the waveforms of the signals during the read operation of the first SRAM shown in FIG.

[0023] Figure 8 yes Figure 5 Detailed circuit diagram of the delay chain circuit.

[0024] Fig. 9 It is shown Figure 8 A plan view of a portion of the layout of the delay chain circuit shown in FIG.

[0025] Fig.10 yes Figure 5 Detailed circuit diagram of the delay chain circuit.

[0026] Fig.11 It is shown Fig.10 A plan view of a portion of the layout of the delay chain circuit shown in FIG.

[0027] Fig.12 yes Figure 5 Detailed circuit diagram of the delay chain circuit.

[0028] Fig.13 yes Fig.12 0048 is a circuit diagram of a delay chain circuit in a first operating mode as shown in .

[0029] Fig.14 yes Fig.12 0048 is a circuit diagram of a delay chain circuit in a second operating mode as shown in .

[0030] Fig.15 It is shown Fig.12 A plan view of a portion of the layout of the delay chain circuit shown in FIG.

[0031] Fig.16 yes Figure 5 Detailed circuit diagram of the input / output circuit shown in .

[0032] Fig.17 It is shown Fig.16 A plan view of a portion of the layout of the driving circuit shown in FIG.

[0033] Fig.18 yes Figure 5 Detailed circuit diagram of the input / output circuit shown in .

[0034] Fig.19 It is shown Fig.18 A plan view of a portion of the layout of the driving circuit shown in FIG.

[0035] Fig. 20 yes Figure 5 Detailed circuit diagram of the input / output circuit.

[0036] Fig.21 It is shown Fig. 20 A plan view of a portion of the layout of the driving circuit shown in FIG. DETAILED DESCRIPTION

[0037] Figure 1is a plan view showing a layout of a semiconductor device according to an exemplary embodiment. Figure 2 is a circuit diagram of a semiconductor device in a first operation mode according to an exemplary embodiment. Figure 3 is a circuit diagram of a semiconductor device in a second operation mode according to an exemplary embodiment.

[0038] Reference Figure 1 , an active region AR may be formed on the substrate Sub. The active region AR may include source and drain regions and a channel region constituting a transistor. For example, the substrate Sub may be a silicon substrate, a germanium substrate, or a silicon on insulator (SOI) substrate.

[0039] The first to third transistors TR1 to TR3 may be formed on the active region AR. For example, the active region AR may be formed to extend in the first direction D1. For example, each of the first to third transistors TR1 to TR3 may be a PMOS or NMOS field effect transistor (FET). Figure 1 In the drawings, for convenience of description, it is assumed that the active region AR is an NMOS region, and each of the first to third transistors TR1 to TR3 is an NMOS FET.

[0040] The first to third transistors TR1 to TR3 may include corresponding gate electrodes G1 to G3 formed to extend in the second direction D2, and each of the first to third transistors TR1 to TR3 may include source and drain regions formed on the active region AR and arranged at opposite sides of each of the gate electrodes, and a channel region. Figure 1 As shown in FIG. 1 , the first to third transistors TR1 to TR3 may be connected in series with each other. That is, the first and second transistors TR1 and TR2 may share a source or drain region, and the second and third transistors TR2 and TR3 may share a source or drain region.

[0041] The first input voltage IN1 may be provided to the first gate electrode G1. The first input voltage IN1 or the ground voltage VSS may be selectively provided to the second gate electrode G2. For example, the first input voltage IN1 or the ground voltage VSS may be provided through the first wire M1. SS In addition, the second input voltage IN2 may be applied to the third gate electrode G3. For example, the first and second input voltages IN1 and IN2 may be voltages for turning on each of the first and third transistors TR1 and TR3. For example, the ground voltage V SS It may be a voltage that is insufficient to turn on the second transistor TR2. Although the explanation is made using the ground voltage V SS , but can use a voltage other than ground V SSA voltage other than that is not sufficient to turn on the second transistor TR2.

[0042] As in Figure 1 and Figure 2 As shown in FIG. 1 , a ground voltage V may be applied to the source or drain region of the first transistor TR1. SS , and a ground voltage V may be applied to the source or drain region shared by the second and third transistors TR2 and TR3 SS To apply the ground voltage V SS , the second conductor M2 can be arranged as Figure 1 However, for providing the ground voltage V SS The wires may not be limited thereto.

[0043] An output OUT1 from a source or drain region shared by the first and second transistors TR1 and TR2 may be output through a third conductive line M3. In addition, an output OUT2 from another source or drain region of the third transistor TR3 may be output through a fourth conductive line M4.

[0044] Since the second transistor TR2 is selectively turned on or off according to the voltage (or signal) input to the second gate electrode G2, the function of the second transistor TR2 may be changed. For example, by applying the ground voltage V SS When the second transistor TR2 is turned off, the second transistor TR2 can act as an isolator in which the first and third transistors TR1 and TR3 are electrically insulated from each other. Conversely, when the second transistor TR2 is turned on by applying the first input voltage IN1 to the second gate electrode G2, the second transistor TR2 can act as a driver for improving the driving force of the semiconductor device.

[0045] For example, Figure 2 and Figure 3 The multiplexer MUX shown in FIG. 1 can be selectively used to work as either an insulator or a driver. Figure 1 and Figure 2 During the first operation mode, the multiplexer MUX can select the ground voltage V SS As a voltage applied to the second gate electrode G2. Therefore, since the second transistor TR2 is turned off, the second transistor TR2 can act as an isolator for electrically insulating the first and second transistors TR1 and TR2 from each other. For example, the multiplexer MUX can be controlled by a separate control signal.

[0046] In addition, refer to Figure 1 and Figure 3During the second operation mode, the multiplexer MUX may select the first input voltage IN1 (eg, the power supply voltage) as the voltage applied to the second gate electrode G2. Therefore, the second transistor TR2 is turned on, and thus the second transistor TR2 may act as a driver for improving the driving force of the semiconductor device. Figure 1 , Figure 2 and Figure 3 In the exemplary embodiment of the present invention, the first operation mode and the second operation mode are selectively executed by the multiplexer MUX. However, according to the exemplary embodiment, in the semiconductor device, a circuit for executing the first operation mode and a circuit for executing the second operation mode may be implemented at the same time. Figure 4 And describe this.

[0047] Figure 4 is a block diagram illustrating a system on chip (SOC) according to an exemplary embodiment. Figure 4 , the SOC 100 may include a first static random access memory (SRAM) 110 and a second SRAM 120 .

[0048] The first SRAM 110 and the second SRAM 120 may perform substantially the same functions as each other. However, the size of the first SRAM 110 is larger than that of the second SRAM 120. In more detail, the number of bit lines connected to the sense amplifier circuit of the first SRAM 110 is larger than the number of bit lines connected to the sense amplifier circuit of the second SRAM 120.

[0049] For example, as described above, the first SRAM 110 may include a reference Figure 1 and Figure 2 The semiconductor device that performs a function (eg, an insulating layer function) in the first operation mode described above. In contrast, the second SRAM 120 may include a semiconductor device that performs a function (eg, an insulating layer function) in the first operation mode described above. Figure 1 and Figure 3 A semiconductor device that performs a function (eg, a driver function) in the second operation mode is described.

[0050] As such, although the first SRAM 110 performs the same function as the second SRAM 120 , the first and second SRAMs 110 and 120 may perform different operation modes based on their sizes and uses, respectively, thereby improving the insulation function and driving force of the SRAMs.

[0051] Figure 5 It is shown Figure 4 1 is a block diagram of one of the first SRAM 110 and the second SRAM 120 shown in FIG. Figure 5, the SRAM 200 may include an SRAM cell array 210 , a sense amplifier circuit 220 , an address (ADDR) decoder 230 , a control logic 240 , and an input / output (I / O) circuit 250 .

[0052] The SRAM cell array 210 may include SRAM cells connected to a plurality of bit lines BL and a plurality of word lines WL. Each SRAM cell in the SRAM cell may be accessed through the word line and the bit line. Each SRAM cell in the SRAM cell may be connected to the bit line pair BL and / BL based on the word line voltage. Each SRAM cell in the SRAM cell may include a latch circuit and a pass transistor that receives the word line voltage as a gate voltage. During the sensing operation, the voltage of the bit line pair BL and / BL precharged according to the data stored in the latch circuit may change. Data may be sensed by sensing the changing voltage.

[0053] The sense amplifier circuit 220 may include a plurality of sense amplifiers (S / A) 221 to 22n. The bit line pair BL and / BL may be connected to each of the sense amplifiers. During a sensing operation, each of the sense amplifiers may sense data by sensing voltage fluctuations of the bit line pair BL and / BL.

[0054] The address decoder 230 may decode an address ADDR received from an external device to select any one of a plurality of bit lines WL or any combination thereof.

[0055] The control logic 240 may control the overall operation of the SRAM 200. For example, the control logic 240 may send the sense amplifier enable signal SAE received from the input / output circuit 250 to the sense amplifier circuit 220. For example, the control logic 240 may include a delay chain circuit 242 that delays the sense amplifier enable signal IN_SAE received from the input / output circuit 250 to output a delayed sense amplifier enable signal OUT_SAE.

[0056] The input / output circuit 250 may exchange input / output (I / O) data (e.g., write data or read data) with an external device (e.g., a controller). The input / output circuit 250 may send an address received from an external device to the address decoder 230. The input / output circuit 250 may send a sense amplifier enable signal SAE received from an external device to the control logic 240.

[0057] Reference Figure 5During a read operation of the SRAM 200, the word line WL of the SRAM cell array 210 may be activated by the address decoder 230, and one of the bit line pairs BL and / BL may be discharged based on the data stored in the SRAM cell. Thereafter, when the sense amplifier circuit 220 is activated by the sense amplifier enable signal SAE, the voltage difference between the bit line pair BL and / BL may be amplified by the sense amplifier circuit 220. That is, there is a sufficient interval between the time point when the word line WL of the SRAM cell array 210 is activated and the time point when the sense amplifier circuit 220 is activated by the sense amplifier enable signal SAE. Hereinafter, this interval may be referred to as a "WL to SAE interval".

[0058] Figure 6 It is shown in Figure 4 FIG. 1 is a view of waveforms of signals during a read operation of the first SRAM 110 shown in FIG. Figure 7 It is shown in Figure 4 FIG. 1 is a diagram showing waveforms of signals during a read operation of the second SRAM 120. Figure 6 and Figure 7 , the discharge of the bit line BL starts at the time point t1 when the activation of the word line WL starts. In addition, the sense amplifier enable signal SAE is activated at the time point when the activation of the word line WL ends. That is, the sense amplifier enable signal SAE is activated at the time point t2 when the bit line BL is fully discharged.

[0059] Will refer to Figure 4 , Figure 5 and Figure 6 The read operation of the first SRAM 110 is described. In the first SRAM 110 having a relatively large size, the WL to SAE interval t1 to t3 may be relatively long. In more detail, the WL to SAE interval may become longer as the number of SRAM cells connected to the bit line pair BL and / BL (the bit line pair is connected to each of the sense amplifiers S / A of the sense amplifier circuit 220) increases. The reason is that a relatively long time is used to discharge the SRAM cell during the read operation of the SRAM 200. In order to perform this function, the delay chain circuit 242 is used to increase the delay amount of the sense amplifier enable signal SAE.

[0060] Will refer to Figure 4 , Figure 5 and Figure 7The read operation to the second SRAM 120 is described. In the second SRAM 120 having a relatively small size, the WL to SAE interval t1 to t3 may be relatively short. In more detail, the WL to SAE interval may become shorter as the number of SRAM cells connected to the bit line pair BL and / BL (the bit line pair is connected to each of the sense amplifiers S / A of the sense amplifier circuit 220) decreases. The reason is that a relatively short time is used to discharge the SRAM cell during the read operation to the SRAM 200. In order to perform this function, the delay chain circuit 242 is used to reduce the delay amount of the sense amplifier enable signal SAE.

[0061] As described above, the WL to SAE interval may vary depending on the configuration of the SRAM (eg, the number of SRAM cells connected to the bit line). Figures 1 to 3 The semiconductor device described can be used to implement the delay chain circuit 242 that adjusts the WL to SAE interval in consideration of the configuration of the SRAM. Figures 8 to 15 And describe this in more detail.

[0062] Figure 8 yes Figure 5 Detailed circuit diagram of the delay chain circuit 242. For example, in Figure 8 The delay chain circuit 300 shown in FIG. Figure 4 1. In order to help understand, reference will be made to the first SRAM 110 having a relatively large size. Figure 5 , Figure 6 and Figure 8 Rather, exemplary embodiments are described.

[0063] The delay chain circuit 300 may include a delay chain block 310 and an isolation circuit 320. The delay chain block 310 may include a plurality of inverters 311 to 314 connected in series with each other. In an exemplary embodiment, the delay chain block 310 includes four inverters. However, the exemplary embodiment may not be limited thereto. The isolation circuit 320 may include a plurality of isolators 321 to 324. Likewise, in an exemplary embodiment, the isolation circuit 320 includes four isolators. However, the exemplary embodiment may not be limited thereto.

[0064] The delay chain block 310 may receive an input signal for outputting a delayed input signal. For example, the delay chain block 310 may receive a sense amplifier enable signal IN_SAE from the input / output circuit 250 to output a delayed sense amplifier enable signal OUT_SAE. For example, the sense amplifier enable signal IN_SAE may be delayed by t2-t1 by the delay chain block 310. For example, each of the inverters constituting the delay chain block 310 may be implemented using a PMOS transistor and an NMOS transistor. However, the configuration of the delay chain block 310 may not be limited thereto.

[0065] Each of the isolators constituting the isolation circuit 320 may be implemented using a PMOS transistor and an NMOS transistor. For example, the isolators may be connected to inverters, respectively. For example, the output terminal of the first isolator 321 may be connected to the output terminal of the first inverter 311. The output terminal of the second isolator 322 may be connected to the output terminal of the second inverter 312. The output terminals of the third and fourth isolators 323 and 324 may also be connected, respectively, in a manner similar to the output terminals of the first and second isolators.

[0066] A power supply voltage V may be applied to one end of each of the PMOS transistors constituting the isolation circuit 320. DD , and a ground voltage V may be applied to one end of each of the NMOS transistors constituting the isolation circuit 320 SS In addition, a power supply voltage V may be applied to the gate terminal of each of the PMOS transistors constituting the isolation circuit 320. DD , and a ground voltage V may be applied to the gate terminal of each of the NMOS transistors constituting the isolation circuit 320 SS Therefore, the PMOS and NMOS transistors constituting the isolation circuit 320 may be disconnected, and thus the isolation circuit 320 may electrically insulate the delay chain block 310 from other circuits adjacent to the delay chain block 310 .

[0067] Fig. 9 It is shown Figure 8 FIG. 1 is a plan view of a portion of the layout of the delay chain circuit 300 shown in FIG. 1 . In an exemplary embodiment, Fig. 9 Schematic diagram of the layout of the first inverter 311 and the first isolator 321 of the delay chain circuit 300 is shown in FIG.

[0068] To help understand, refer to Figure 8 and Fig. 9, a first active region AR1 and a second active region AR2 may be formed on the substrate. For example, the first active region AR1 and the second active region AR2 may extend in a first direction D1 and may be arranged along a second direction D2 perpendicular to the first direction D1. Each of the first and second active regions AR1 and AR2 may include a source and drain region and a channel region for forming a corresponding transistor. For example, the substrate Sub may be a silicon substrate, a germanium substrate, or a silicon on insulator (SOI) substrate.

[0069] The first and second transistors TR1 and TR2 may be formed on the first active region AR1. For example, each of the first and second transistors TR1 and TR2 may be a PMOS FET.

[0070] The first and second transistors TR1 and TR2 may include corresponding gate electrodes G1 and G2 formed to extend in the second direction D2, and each of the first and second transistors TR1 and TR2 may include source and drain regions formed on the first active region AR1 and arranged at opposite sides of each of the gate electrodes G1 and G2, and a channel region. Fig. 9 As shown in FIG. 1 , the first and second transistors TR1 and TR2 may be connected in series with each other. That is, the first and second transistors TR1 and TR2 may share a source or drain region.

[0071] The third and fourth transistors TR3 and TR4 may be formed on the second active region AR2. For example, each of the third and fourth transistors TR3 and TR4 may be an NMOS FET.

[0072] The third and fourth transistors TR3 and TR4 may include corresponding gate electrodes G1 and G3 formed to extend in the second direction D2, and each of the third and fourth transistors TR3 and TR4 may include source and drain regions formed on the second active region AR2 and arranged at opposite sides of each of the gate electrodes G1 and G3, and a channel region. That is, the second and fourth transistors TR2 and TR4 may not share a gate electrode (e.g., the second gate electrode G2). As in Fig. 9 As shown in FIG. 1 , the third to fourth transistors TR3 to TR4 may be connected in series with each other. That is, the third and fourth transistors TR3 and TR4 may share a source or drain region.

[0073] A sense amplifier enable signal IN_SAE may be applied to the first gate electrode G1. A power supply voltage V may be applied to the second gate electrode G2. DD In addition, a ground voltage V may be applied to the third gate electrode G3. SSFor example, the sense amplifier enable signal IN_SAE may be applied to the first gate electrode G1 through the first wire M1. For example, the power supply voltage V may be applied to the second gate electrode G2 through the second wire M2. DD For example, a ground voltage V may be applied to the third gate electrode G3 through the third wire M3. SS For example, the ground voltage V SS It may be a voltage that is insufficient to turn on the third transistor TR3. However, a voltage other than the ground voltage V SS A voltage other than that is not sufficient to turn on the third transistor TR3.

[0074] A power supply voltage V may be applied to the source or drain region of the first transistor TR1. DD , and a power supply voltage V may be applied to the source or drain region of the second transistor TR2 DD A ground voltage V may be applied to the source or drain region of the third transistor TR3. SS , and a ground voltage V may be applied to the source or drain region of the fourth transistor TR4 SS .

[0075] For example, a power supply voltage V may be applied to the first and second transistors TR1 and TR2 through the second conductive line M2. DD For example, the ground voltage V may be applied to the third and fourth transistors TR3 and TR4 through the third conductive line M3. SS However, for applying the power supply voltage V DD and ground voltage V SS The configuration is not limited to this.

[0076] The output signal OUT_SAE from the source or drain region shared by the first and second transistors TR1 and TR2 may be output through the fourth wire M4. The output signal OUT_SAE from the source or drain region shared by the third and fourth transistors TR3 and TR4 may be output through the fourth wire M4. However, in an exemplary embodiment, the first isolator 321 including the second and fourth transistors TR2 and TR4 may be maintained in a disconnected state. Accordingly, the signal output through the fourth wire M4 may be a signal output from the first inverter 311 including the first and third transistors TR1 and TR3.

[0077] According to reference Fig. 9 With the described layout and bias conditions, the first isolator 321 including the second and fourth transistors TR2 and TR4 can electrically insulate the first inverter 311 from another device. For example, the first isolator 321 can electrically insulate the first inverter 311 from the transistor including the fourth gate electrode G4.

[0078] By properly placing Fig. 9 The layout shown in FIG. 3 can implement the delay chain circuit 300 as follows: Figure 8 Because the outputs of the first inverter 311 and the first isolator 321 are used as the inputs of the second inverter 312, suitable wires for this configuration may be used, and a detailed description thereof will not be repeated here.

[0079] By using Fig. 9 The delay chain circuit 300 implemented by the layout shown in FIG. 1 does not need to place separate devices for electrical isolation and does not need to increase the distance between gate electrodes. By using the layout placement and adjusting the bias conditions, an isolation device can be implemented, thereby improving area efficiency and isolation performance.

[0080] Fig.10 yes Figure 5 Detailed circuit diagram of the delay chain circuit 242. For example, in Fig.10 The delay chain circuit 400 shown in FIG. 4 may be Figure 4 The second SRAM 120 shown in FIG. 1 has a relatively small size. To help understand, reference will be made to Figure 5 , Figure 7 and Fig.10 to describe exemplary embodiments.

[0081] The delay chain circuit 400 may include a delay chain block 410 and a driving circuit 420. The delay chain block 410 may include a plurality of inverters 411 to 414 connected in series with each other. In an exemplary embodiment, the delay chain block 410 includes four inverters. However, the exemplary embodiment is not limited thereto. The driving circuit 420 may include a plurality of drivers 421 to 424. Likewise, in an exemplary embodiment, the driving circuit 420 includes four drivers. However, the exemplary embodiment is not limited thereto.

[0082] The delay chain block 410 may receive an input signal for outputting a delayed input signal. For example, the delay chain block 410 may receive the sense amplifier enable signal IN_SAE so as to output the delayed sense amplifier enable signal OUT_SAE. For example, the sense amplifier enable signal IN_SAE may be delayed by (t2-t1) through the delay chain block 410. However, the delay time of the delay chain block 410 may be shorter than the delay time of the delay chain block 310 (refer to Figure 8 ). For example, each of the inverters constituting the delay chain block 410 may be implemented using a PMOS transistor and an NMOS transistor.

[0083] Each of the drivers constituting the driver circuit 420 can be implemented using PMOS transistors and NMOS transistors. For example, the drivers can be connected to the inverters in parallel, respectively. For example, the input and output terminals of the first driver 421 can be connected to the input and output terminals of the first inverter 411, respectively. The input and output terminals of the second to fourth drivers 422 to 424 can also be connected in a manner similar to those of the first driver 411.

[0084] A power supply voltage V may be applied to the input terminal of the inverter constituting the drive circuit 420. DD Therefore, the driving circuit 420 can improve the driving capability of the delay chain block 410. That is, the delay time of the delay chain block 410 can become relatively shorter.

[0085] Fig.11 It is shown Fig.10 FIG. 4 is a plan view of a portion of the layout of the delay chain circuit 400 shown in FIG. 4. In an exemplary embodiment, Fig.11 4 shows the layout of the first inverter 411 and the first isolator 421 of the delay chain circuit 400.

[0086] To help understand, refer to Fig.10 and Fig.11 , first and second active regions AR1 and AR2 may be formed on a substrate. Each of the first and second active regions AR1 and AR2 may include source and drain regions and a channel region for forming a transistor. For example, the substrate Sub may be a silicon substrate, a germanium substrate, or a silicon on insulator (SOI) substrate.

[0087] The first and second transistors TR1 and TR2 may be formed on the first active region AR1. For example, each of the first and second transistors TR1 and TR2 may be a PMOS FET.

[0088] The first and second transistors TR1 and TR2 may include corresponding gate electrodes G1 and G2 formed to extend in the second direction D2, and each of the first and second transistors TR1 and TR2 may include source and drain regions formed on the first active region AR1 and arranged at opposite sides of each of the gate electrodes G1 and G2, and a channel region. Fig.11 As shown in FIG. 1 , the first and second transistors TR1 and TR2 may be connected in series with each other. That is, the first and second transistors TR1 and TR2 may share a source or drain region.

[0089] The third and fourth transistors TR3 and TR4 may be formed on the second active region AR2. For example, each of the third and fourth transistors TR3 and TR4 may be an NMOS FET.

[0090] The third and fourth transistors TR3 and TR4 may include corresponding gate electrodes G1 and G2 formed to extend in the second direction D2, and each of the third and fourth transistors TR3 and TR4 may include source and drain regions formed on the second active region AR2 and arranged at opposite sides of each of the gate electrodes G1 and G2, and a channel region. Fig.11 As shown in FIG. 1 , the third and fourth transistors TR3 to TR4 may be connected in series with each other. That is, the third transistor TR3 may share a gate electrode G1 with the first transistor TR1, and the fourth transistor TR4 may share a gate electrode G2 with the second transistor TR2. In addition, the third and fourth transistors TR3 and TR4 may share a source or drain region.

[0091] The sense amplifier enable signal IN_SAE may be applied to the first and second gate electrodes G1 and G2. For example, the sense amplifier enable signal IN_SAE may be applied to the first and second gate electrodes G1 and G2 through the first conductive line M1.

[0092] A power supply voltage V may be applied to the source or drain region of the first transistor TR1. DD , and a power supply voltage V may be applied to the source or drain region of the second transistor TR2 DD A ground voltage V may be applied to the source or drain region of the third transistor TR3. SS , and a ground voltage V may be applied to the source or drain region of the fourth transistor TR4 SS .

[0093] For example, a power supply voltage V may be applied to the first and second transistors TR1 and TR2 through the second conductive line M2. DD For example, the ground voltage V may be applied to the third and fourth transistors TR3 and TR4 through the third conductive line M3. SS However, for applying the power supply voltage V DD and ground voltage V SS The configuration is not limited to this.

[0094] An output signal OUT_SAE from a source or drain region shared by the first and second transistors TR1 and TR2 may be output through a fourth conductive line M4. An output signal OUT_SAE from a source or drain region shared by the third and fourth transistors TR3 and TR4 may be output through a fourth conductive line M4.

[0095] According to reference Fig.11 The layout and bias conditions described above, including the first driver 421 of the second and fourth transistors TR2 and TR4 can improve the driving capability of the first inverter 411. That is, the delay time of the delay chain block 410 can be shorter than the delay time of the delay chain block 310 (refer to Figure 8 ).

[0096] By properly placing Fig.11 The layout shown in FIG. 4 can implement the delay chain circuit 400 as follows Fig.10 Since the outputs of the first inverter 411 and the first driver 421 are used as the inputs of the second inverter 412, suitable wires for this configuration can be used. Therefore, a detailed description thereof will not be repeated here.

[0097] As mentioned above, from Fig. 9 and Fig.11 It is understood that the semiconductor devices performing different functions described above have similar layouts. That is, Fig. 9 The isolation circuit 320 can electrically isolate the delay chain block 310 from another device, and Fig.11 The driving circuit 420 can reduce the delay time (ie, WL to SAE interval) of the delay chain block 410. The second and fourth transistors TR2 and TR4 can be determined according to the bias conditions and whether they share a gate electrode. Fig. 9 The isolator 320 with Fig.11 The difference between the driving circuit 420.

[0098] According to reference Figures 8 to 11 The exemplary embodiment described, the devices that differently affect the delay chain blocks 310 and 410 can be implemented by using substantially the same layout but only differently adjusting the bias conditions. Therefore, devices that improve area efficiency, isolation performance, or driving capability can be selectively used according to the configuration of the SRAM.

[0099] Fig.12 yes Figure 5 Detailed circuit diagram of the delay chain circuit 242. For example, in Fig.12 The delay chain circuit 500 shown in FIG. 5 may be Figure 4 To help understand, reference will be made to the first and second SRAMs 110 and 120 shown in FIG. Figure 5 , Figure 6 , Figure 7 and Fig.12 to describe exemplary embodiments.

[0100] The delay chain circuit 500 may include a delay chain block 510, an auxiliary block 520, and a multiplexing circuit 530. The delay chain block 510 may include a plurality of inverters 511 to 514 connected in series with each other. In an exemplary embodiment, the delay chain block 510 includes four inverters. However, the exemplary embodiment is not limited thereto. The auxiliary block 520 may include first to fourth auxiliary blocks 521 to 524. Likewise, in an exemplary embodiment, the delay chain circuit 500 includes four auxiliary blocks. However, the exemplary embodiment is not limited thereto.

[0101] The delay chain block 510 may receive an input signal for outputting a delayed input signal. For example, the delay chain block 510 may receive a sense amplifier enable signal IN_SAE so as to output a delayed sense amplifier enable signal OUT_SAE. For example, the sense amplifier enable signal IN_SAE may be delayed by (t2-t1) through the delay chain block 510. For example, each of the inverters constituting the delay chain block 510 may be implemented using a PMOS transistor and an NMOS transistor.

[0102] Each of the first to fourth auxiliary blocks 521 to 524 may include a PMOS transistor and an NMOS transistor connected in series to each other. A power supply voltage V may be applied to one end of the PMOS transistor. DD , and a ground voltage V can be applied to one end of the NMOS transistor SS In addition, an output terminal between the PMOS transistor and the NMOS transistor may be connected to an output terminal of the first inverter 511 corresponding thereto.

[0103] The first multiplexer MUX1 may be connected to the gate electrodes of the PMOS transistors constituting the first to fourth auxiliary blocks 521 to 524. In addition, the second multiplexer MUX2 may be connected to the gate electrodes of the NMOS transistors constituting the first to fourth auxiliary blocks 521 to 524. The first multiplexer MUX1 may select the sense amplifier enable signal IN_SAE and the power supply voltage V under the control of an external device. DD In addition, the second multiplexer MUX2 can select the sense amplifier enable signal IN_SAE and the ground voltage V under the control of the external device. SS one.

[0104] Fig.13 yes Fig.12 FIG. 5 is a circuit diagram of a delay chain circuit 500 in a first operation mode. During the first operation mode, the first multiplexer MUX1 can be configured to receive the sense amplifier enable signal IN_SAE and the power supply voltage V based on the control signal CTRL. DD Select the power supply voltage V DDIn addition, during the first operation mode, the second multiplexer MUX2 can be based on the control signal CTRL from the sense amplifier enable signal IN_SAE and the ground voltage V SS Select the ground voltage V SS In this case, the transistors constituting the auxiliary block 520 may be turned off, and thus the auxiliary block 520 may electrically insulate the delay chain block 510 from another device. This electrical insulation function may be similar to that of reference Figure 8 The described, and therefore repeated, description will not be repeated here.

[0105] Fig.14 yes Fig.12 FIG. 5 is a circuit diagram of a delay chain circuit 500 in a second operation mode. During the second operation mode, the first multiplexer MUX1 can be configured to receive the sense amplifier enable signal IN_SAE and the power supply voltage V based on the control signal CTRL. DD In addition, during the second operation mode, the second multiplexer MUX2 can select the sense amplifier enable signal IN_SAE and the ground voltage V based on the control signal CTRL. SS In this case, the transistors constituting the auxiliary block 520 may be turned on, and thus the auxiliary block 520 may act as a driver to improve the driving capability of the delay chain block 510. This driver function may be similar to that of the reference Fig.10 The described, and therefore repeated, description will not be repeated here.

[0106] According to the above, the operation mode can be selected according to the control signal from the external device. For example, in order to maintain the WL to SAE interval of the SRAM longer, the delay chain circuit 500 can enter the first operation mode based on the control signal CTRL. In this case, the auxiliary block 520 can operate as an insulating circuit; the WL to SAE interval of the SRAM may be affected by the delay chain circuit 510. On the contrary, in order to maintain the WL to SAE interval of the SRAM shorter, the delay chain circuit 500 can enter the first operation mode based on the control signal CTRL. In this case, because the auxiliary block 520 operates as an insulating circuit; the WL to SAE interval of the SRAM may be reduced due to the increase of the driving capability through the auxiliary block 520.

[0107] Fig.15 It is shown Fig.12 FIG. 5 is a plan view of a portion of the layout of the delay chain circuit 500 shown in FIG. 5 . In an exemplary embodiment, Fig.15 . , the layout of the first inverter 511 and the first auxiliary block 521 of the delay chain circuit 500 is shown.

[0108] To help understand, refer to Fig.12 and Fig.15 , first and second active regions AR1 and AR2 may be formed on a substrate. Each of the first and second active regions AR1 and AR2 may include source and drain regions and a channel region for forming a transistor. For example, the substrate Sub may be a silicon substrate, a germanium substrate, or a silicon on insulator (SOI) substrate.

[0109] The first and second transistors TR1 and TR2 may be formed on the first active region AR1. For example, each of the first and second transistors TR1 and TR2 may be a PMOS FET.

[0110] The first and second transistors TR1 and TR2 may include corresponding gate electrodes G1 and G2 formed to extend in the second direction D2, and each of the first and second transistors TR1 and TR2 may include source and drain regions formed on the first active region AR1 and arranged at opposite sides of each of the gate electrodes G1 and G2, and a channel region. Fig.15 As shown in FIG. 1 , the first to second transistors TR1 to TR2 may be connected in series with each other. That is, the first and second transistors TR1 and TR2 may share a source or drain region.

[0111] The third and fourth transistors TR3 and TR4 may be formed on the second active region AR2. For example, each of the third and fourth transistors TR3 and TR4 may be an NMOS FET.

[0112] The third and fourth transistors TR3 and TR4 may include corresponding gate electrodes G1 and G3 formed to extend in the second direction D2, and each of the third and fourth transistors TR3 and TR4 may include source and drain regions formed on the second active region AR2 and arranged at opposite sides of each of the gate electrodes G1 and G3, and a channel region. Fig.15 As shown in FIG. 1 , the third to fourth transistors TR3 to TR4 may be connected in series with each other. That is, the fourth transistor TR4 may not share a gate electrode with the second transistor TR2. In addition, the third and fourth transistors TR3 and TR4 may share a source or drain region.

[0113] The sense amplifier enable signal IN_SAE may be applied to the first gate electrode G1. For example, the sense amplifier enable signal IN_SAE may be applied to the first gate electrode G1 through the first conductive line M1.

[0114] The sense amplifier enable signal IN_SAE or the power supply voltage V may be selectively applied to the second gate electrode G2. DDFor example, the first multiplexer MUX1 may selectively apply the power supply voltage V to the second gate electrode G2 based on a control signal from an external device. DD For example, the sense amplifier enable signal IN_SAE or the power supply voltage V may be applied to the second gate electrode G2 through the second conductive line M2. DD .

[0115] A power supply voltage V may be applied to the source or drain region of the first transistor TR1. DD , and a power supply voltage V may be applied to the source or drain region of the second transistor TR2 DD A ground voltage V may be applied to the source or drain region of the third transistor TR3. SS , and a ground voltage V may be applied to the source or drain region of the fourth transistor TR4 SS .

[0116] For example, the power supply voltage V may be applied to the first and second transistors TR1 and TR2 through the third conductive line M3. DD For example, the ground voltage V may be applied to the third and fourth transistors TR3 and TR4 through the fourth conductive line M4. SS However, for applying the power supply voltage V DD and ground voltage V SS The configuration is not limited to this.

[0117] The output signal OUT_SAE from the source or drain region shared by the first and second transistors TR1 and TR2 may be output through the fifth wire M5. In addition, the output signal OUT_SAE from the source or drain region shared by the third and fourth transistors TR3 and TR4 may be output through the fifth wire M5. However, when the delay chain circuit 500 operates in the first operation mode, the auxiliary block 520 may operate as an isolation circuit. Therefore, the outputs from the second and fourth transistors TR2 and TR4 may be missing.

[0118] According to the reference Fig.13 The described layout and bias conditions select the function of the auxiliary block 520. For example, when the delay chain circuit 500 operates in the first operation mode, the power supply voltage V DD , and a ground voltage V may be applied to the sixth wire M6 SS Therefore, the auxiliary block 521 including the second transistor TR2 and the fourth transistor TR4 may electrically insulate the first inverter 311 including the first transistor TR1 and the third transistor TR3 from another device.

[0119] In contrast, when the delay chain circuit 500 operates in the second operation mode, the sense amplifier enable signal IN_SAE may be applied to the second conductive line M2, and the sense amplifier enable signal IN_SAE may be applied to the sixth conductive line M6. Therefore, the auxiliary block 521 including the second and fourth transistors TR2 and TR4 may electrically operate as a driver that improves the driving capability of the first inverter 511 including the first and third transistors TR1 and TR3.

[0120] The operation mode of the delay chain circuit 500 can be selected according to the configuration of the SRAM (eg, the number of SRAMs connected to the bit line pairs BL and / BL), thereby improving the area efficiency, insulation performance, or driving capability of the SRAM. In addition, the reliability of the SRAM can be enhanced.

[0121] As described above, the layout of a semiconductor device that adjusts the WL to SAE interval of an SRAM based on an operation mode is described. However, a semiconductor device that performs different functions based on an operation mode can also be used as a driver circuit for driving a load. For example, Figure 5 The input / output circuit 250 shown in FIG. 1 may be a driving circuit, and will be referred to as Figures 16 to 21 Describe it in more detail.

[0122] Fig.16 It is a display Figure 5 . For example, in Fig.16 The input / output circuit 600 shown in FIG. Figure 4 That is, when the number of loads is relatively small (i.e., when the size of the SRAM is relatively small), it can be used. Fig.16 The input / output circuit 600 shown in FIG.

[0123] The input / output circuit 600 may include a driver circuit 610 and a load circuit 620. The driver circuit 610 may include an inverter 611 and an isolator 613. The load circuit 620 may include a plurality of loads 621 to 62n. For example, the driver circuit 610 receiving the input signal IN may output an output signal OUT. In addition, each of the loads connected to the load circuit 620 may be driven by the output signal OUT to output data.

[0124] The isolator 613 may include a PMOS transistor and an NMOS transistor. A power supply voltage V may be applied to one end of the PMOS transistor. DD , and a ground voltage V can be applied to one end of the NMOS transistor SS A power supply voltage V can be applied to the gate terminal of the PMOS transistor. DD, and a ground voltage V may be applied to the gate terminal of the NMOS transistor SS Therefore, the transistor constituting the isolation circuit 613 may be turned off, and thus the isolation circuit 613 may electrically insulate the inverter 611 from other circuits adjacent to the inverter 611 .

[0125] Fig.17 It is shown Fig.16 FIG. 6 is a plan view of a portion of the layout of the delay chain circuit 610 shown in FIG. Fig.16 and Fig.17 , first and second active regions AR1 and AR2 may be formed on a substrate. Each of the first and second active regions AR1 and AR2 may include source and drain regions and a channel region for forming a transistor. For example, the substrate Sub may be a silicon substrate, a germanium substrate, or a silicon on insulator (SOI) substrate.

[0126] The first and second transistors TR1 and TR2 may be formed on the first active region AR1. For example, each of the first and second transistors TR1 and TR2 may be a PMOS FET.

[0127] The first and second transistors TR1 and TR2 may include corresponding gate electrodes G1 and G2 formed to extend in the second direction D2, and each of the first and second transistors TR1 and TR2 may include source and drain regions formed on the first active region AR1 and arranged at opposite sides of each of the gate electrodes, and a channel region. Fig.17 As shown in FIG. 1 , the first to second transistors TR1 to TR2 may be connected in series with each other. That is, the first and second transistors TR1 and TR2 may share a source or drain region.

[0128] The third and fourth transistors TR3 and TR4 may be formed on the second active region AR2. For example, each of the third and fourth transistors TR3 and TR4 may be an NMOS FET.

[0129] The third and fourth transistors TR3 and TR4 may include corresponding gate electrodes G1 and G3 formed to extend in the second direction D2, and each of the third and fourth transistors TR3 and TR4 may include source and drain regions formed on the second active region AR2 and arranged at opposite sides of each of the gate electrodes G1 and G3, and a channel region. That is, the second and fourth transistors TR2 and TR4 may not share a gate electrode. As in Fig.17As shown in FIG. 1 , the third to fourth transistors TR3 to TR4 may be connected in series with each other. That is, the third and fourth transistors TR3 and TR4 may share a source or drain region.

[0130] An input voltage IN may be provided to the first gate electrode G1. A power supply voltage V may be applied to the second gate electrode G2. DD In addition, a ground voltage V may be applied to the third gate electrode G3. SS For example, an input signal IN may be applied to the first gate electrode G1 through the first wire M1. For example, a power supply voltage VDD may be applied to the second gate electrode G2 through the second wire M2. For example, a ground voltage V may be applied to the third gate electrode G3 through the third wire M3. SS .

[0131] A power supply voltage V may be applied to the source or drain region of the first transistor TR1. DD , and a power supply voltage V may be applied to the source or drain region of the second transistor TR2 DD A ground voltage V may be applied to the source or drain region of the third transistor TR3. SS , and a ground voltage V may be applied to the source or drain region of the fourth transistor TR4 SS .

[0132] For example, a power supply voltage V may be applied to the first and second transistors TR1 and TR2 through the second conductive line M2. DD For example, the ground voltage V may be applied to the third and fourth transistors TR3 and TR4 through the third conductive line M3. SS However, for applying the power supply voltage V DD and ground voltage V SS The configuration is not limited to this.

[0133] The output signal OUT from the source or drain region shared by the first and second transistors TR1 and TR2 may be output through the fourth wire M4. In addition, the output signal OUT_SAE from the source or drain region shared by the third and fourth transistors TR3 and TR4 may be output through the fourth wire M4. However, in an exemplary embodiment, the isolator 613 including the second transistor TR2 and the fourth transistor TR4 may be maintained in a disconnected state. Accordingly, the signal output through the fourth wire M4 may be a signal output from the inverter 611 including the first transistor TR1 and the third transistor TR3.

[0134] According to reference Fig.17According to the described layout and bias conditions, the isolator 613 including the second transistor TR2 and the fourth transistor TR4 can electrically insulate the inverter 611 from another device. For example, the isolator 613 can electrically insulate the inverter 611 from the transistor including the fourth gate electrode G4.

[0135] Fig.18 It is a display Figure 5 . For example, in Fig.18 The input / output circuit 700 shown in FIG. Figure 4 That is, when the number of loads is relatively large (ie, when the size of the SRAM is relatively large), the input / output circuit of the first SRAM 110 shown in FIG. Fig.18 The input / output circuit 700 shown in FIG.

[0136] The input / output circuit 700 may include a drive circuit 710 and a load circuit 720. The drive circuit 710 may include an inverter 711 and a driver 713. The load circuit 720 may include a plurality of loads 721 to 72n. For example, Fig.18 The number of loads 721 to 72n shown in FIG. 7 may be greater than Fig.16 The number of loads 621 to 62n shown in .

[0137] The driver 713 may include a PMOS transistor and an NMOS transistor. A power supply voltage V may be applied to one end of the PMOS transistor. DD , and a ground voltage V can be applied to one end of the NMOS transistor SS The input signal IN may be applied to the gate terminal of the PMOS transistor and the gate terminal of the NMOS transistor. Therefore, the driver 713 may improve the driving capability of the driving circuit 710. On the other hand, even if the number of the loads 721 to 72n is relatively large, it is still possible to secure the driving capability sufficient to drive the loads 721 to 72n.

[0138] Fig.19 It is shown Fig.18 FIG. 7 is a plan view of a portion of the layout of the delay chain circuit 710 shown in FIG. Fig.18 and Fig.19 , first and second active regions AR1 and AR2 may be formed on a substrate. Each of the first and second active regions AR1 and AR2 may include source and drain regions and a channel region for forming a transistor. For example, the substrate Sub may be a silicon substrate, a germanium substrate, or a silicon on insulator (SOI) substrate.

[0139] The first and second transistors TR1 and TR2 may be formed on the first active region AR1. For example, each of the first and second transistors TR1 and TR2 may be a PMOS FET.

[0140] The first and second transistors TR1 and TR2 may include corresponding gate electrodes G1 and G2 formed to extend in the second direction D2, and each of the first and second transistors TR1 and TR2 may include source and drain regions formed on the first active region AR1 and arranged at opposite sides of each of the gate electrodes G1 and G2, and a channel region. Fig.17 As shown in FIG. 1 , the first to second transistors TR1 to TR2 may be connected in series with each other. That is, the first and second transistors TR1 and TR2 may share a source or drain region.

[0141] The third and fourth transistors TR3 and TR4 may be formed on the second active region AR2. For example, each of the third and fourth transistors TR3 and TR4 may be an NMOS FET.

[0142] The third and fourth transistors TR3 and TR4 may include corresponding gate electrodes G1 and G2 formed to extend in the second direction D2, and each of the third and fourth transistors TR3 and TR4 may include source and drain regions formed on the second active region AR2 and arranged at opposite sides of each of the gate electrodes G1 and G2, and a channel region. Fig.19 As shown in FIG. 1 , the third to fourth transistors TR3 to TR4 may be connected in series with each other. That is, the third and fourth transistors TR3 and TR4 may share a source or drain region.

[0143] An input signal IN may be applied to the first and second gate electrodes G1 and G2. A power supply voltage V may be applied to the second gate electrode G2. DD For example, an input signal IN may be applied to the first and second gate electrodes G1 and G2 through the first conductive line M1.

[0144] A power supply voltage V may be applied to the source or drain region of the first transistor TR1. DD , and a power supply voltage V may be applied to the source or drain region of the second transistor TR2 DD A ground voltage V may be applied to the source or drain region of the third transistor TR3. SS , and a ground voltage V may be applied to the source or drain region of the fourth transistor TR4 SS .

[0145] For example, a power supply voltage V may be applied to the first and second transistors TR1 and TR2 through the second conductive line M2.DD For example, the ground voltage V may be applied to the third and fourth transistors TR3 and TR4 through the third conductive line M3. SS However, for applying the power supply voltage V DD and ground voltage V SS The configuration is not limited to this.

[0146] An output signal OUT from a source or drain region shared by the first and second transistors TR1 and TR2 may be output through a fourth conductive line M4. Also, an output signal OUT_SAE from a source or drain region shared by the third and fourth transistors TR3 and TR4 may be output through a fourth conductive line M4.

[0147] According to reference Fig.19 The described layout and bias conditions of the driver 713 including the second and fourth transistors TR2 and TR4 can improve the driving capability of the driving circuit 710.

[0148] As mentioned above, refer to Fig.17 and Fig.19 Semiconductor devices that perform different functions are described, but it should be understood that their layouts are similar to each other. That is, Fig.17 The isolator 613 can electrically isolate the inverter 711 from another device, and Fig.19 The driver 713 can improve the driving capability of the driving circuit 710. Fig.17 The isolator 613 and Fig.19 The difference between the drivers 713 may be different from each other in bias conditions and whether the second and fourth transistors TR2 and TR4 share a gate electrode.

[0149] According to reference Figures 16 to 19 In the exemplary embodiment shown, devices having different effects on the driver circuit 710 can be realized by using substantially the same layout but adjusting only the bias conditions differently. Therefore, devices having improved area efficiency, insulation performance, or driving capability can be selectively used according to the configuration of the SRAM.

[0150] Fig. 20 yes Figure 5 Detailed circuit diagram of the input / output circuit 250. For example, in Fig. 20 The input / output circuit 800 shown in FIG. Figure 4 The input / output circuit 800 may include a driving circuit 810 , a load circuit 820 , and a multiplexing circuit 830 .

[0151] The driving circuit 810 may include an inverter 811 and an auxiliary circuit 813. The load circuit 820 may include a plurality of loads 821 to 82n. The driving circuit 810 may receive an input signal IN to output an output signal OUT. The inverter 811 and the auxiliary circuit 813 of the driving circuit 810 may have their output terminals connected to each other.

[0152] A power supply voltage V can be applied to one end of the PMOS transistor DD , and a ground voltage V can be applied to one end of the NMOS transistor SS The gate terminal of the PMOS transistor of the auxiliary circuit 813 may be connected to the output terminal of the first multiplexer MUX1, and the gate terminal of the NMOS transistor of the auxiliary circuit 813 may be connected to the output terminal of the second multiplexer MUX2.

[0153] The first multiplexer MUX1 can select the input signal IN and the power supply voltage V based on the control signal CTRL from the external device. DD In addition, the second multiplexer MUX2 can select the input signal IN and the ground voltage V based on the control signal CTRL from the external device. SS one.

[0154] For example, during the first operation mode, the first multiplexer MUX1 can select the power supply voltage V under the control of the control signal CTRL. DD , and the second multiplexer MUX2 can select the ground voltage V under the control of the control signal CTRL SS Therefore, the auxiliary circuit 813 can operate as an isolator that electrically isolates the inverter 811 from another device. Because the auxiliary circuit 813 operates as an isolator, the driving capability originally possessed by the driving circuit 810 can be maintained as it should be. Accordingly, the operation of the input / output circuit 800 in the first operating mode can be relatively suitable for the second SRAM 120 (refer to Figure 4 ).

[0155] In contrast, during the second operation mode, the first and second multiplexers MUX1 and MUX2 can select the input signal IN under the control signal CTRL. Therefore, the auxiliary circuit 813 can operate as a driver that improves the driving capability of the driving circuit 810. Because the auxiliary circuit 813 operates as a driver, the driving capability that the driving circuit 810 originally has can be improved. Accordingly, the operation of the input / output circuit 800 in the second operation mode can be relatively suitable for the first SRAM 110 (refer to Figure 4 ).

[0156] Fig.21 It is shown Fig. 20FIG. 8 is a plan view of a portion of the layout of the input / output circuit 800 shown in FIG. 8. In an exemplary embodiment, Fig.21 8 shows the layout of the inverter 811 and the auxiliary circuit 813 of the input / output circuit 800.

[0157] To help understand, refer to Fig. 20 and Fig.21 , first and second active regions AR1 and AR2 may be formed on a substrate. Each of the first and second active regions AR1 and AR2 may include source and drain regions and a channel region for forming a transistor. For example, the substrate Sub may be a silicon substrate, a germanium substrate, or a silicon on insulator (SOI) substrate.

[0158] The first and second transistors TR1 and TR2 may be formed on the first active region AR1. For example, each of the first and second transistors TR1 and TR2 may be a PMOS FET.

[0159] The first and second transistors TR1 and TR2 may include corresponding gate electrodes G1 and G2 formed to extend in the second direction D2, and each of the first and second transistors TR1 and TR2 may include source and drain regions formed on the first active region AR1 and arranged at opposite sides of each of the gate electrodes, and a channel region. Fig.21 As shown in FIG. 1 , the first to second transistors TR1 to TR2 may be connected in series with each other. That is, the first and second transistors TR1 and TR2 may share a source or drain region.

[0160] The third and fourth transistors TR3 and TR4 may be formed on the second active region AR2. For example, each of the third and fourth transistors TR3 and TR4 may be an NMOS FET.

[0161] The third and fourth transistors TR3 and TR4 may include corresponding gate electrodes G1 and G3 formed to extend in the second direction D2, and each of the third and fourth transistors TR3 and TR4 may include source and drain regions formed on the second active region AR2 and arranged at opposite sides of each of the gate electrodes, and a channel region. Fig.21 As shown in FIG. 1 , the third to fourth transistors TR3 to TR4 may be connected in series with each other. That is, the fourth transistor TR4 may not share a gate electrode with the second transistor TR2. In addition, the third and fourth transistors TR3 and TR4 may share a source or drain region.

[0162] The first gate electrode G1 may be provided with an input voltage IN. For example, the input signal IN may be applied to the first gate electrode G1 through the first conductive line M1.

[0163] The input signal IN or the power supply voltage V may be selectively applied to the second gate electrode G2. DD For example, the first multiplexer MUX1 may selectively apply the power supply voltage V to the second gate electrode G2 based on a control signal CTRL from an external device. DD For example, an input signal IN or a power supply voltage V may be applied to the second gate electrode G2 through the second wire M2. DD .

[0164] A power supply voltage V may be applied to the source or drain region of the first transistor TR1. DD , and a power supply voltage V may be applied to the source or drain region of the second transistor TR2 DD A ground voltage V may be applied to the source or drain region of the third transistor TR3. SS , and a ground voltage V may be applied to the source or drain region of the fourth transistor TR4 SS .

[0165] For example, the power supply voltage V may be applied to the first and second transistors TR1 and TR2 through the third conductive line M3. DD For example, the ground voltage V may be applied to the third and fourth transistors TR3 and TR4 through the fourth conductive line M4. SS However, for applying the power supply voltage V DD and ground voltage V SS The configuration is not limited to this.

[0166] The output signal OUT from the source or drain region shared by the first and second transistors TR1 and TR2 can be output through the fifth conductor M5. In addition, the output signal OUT from the source or drain region shared by the third and fourth transistors TR3 and TR4 can be output through the fifth conductor M5. However, when the input / output circuit 800 operates in the first operating mode, the auxiliary circuit 813 can operate as an isolator. Therefore, the output from the second and fourth transistors TR2 and TR4 may be missing.

[0167] Can be based on reference Fig.21 The described layout and bias conditions select the function of the auxiliary circuit 813. For example, when the input / output circuit 800 operates in the first operation mode, the power supply voltage V DD , and a ground voltage V may be applied to the sixth wire M6 SSTherefore, the auxiliary circuit 813 including the second and fourth transistors TR2 and TR4 may electrically insulate the inverter 811 including the first and third transistors TR1 and TR3 from another device.

[0168] In contrast, when the input / output circuit 800 operates in the second operation mode, the input signal IN may be applied to the second wire M2, and the input signal IN may be applied to the sixth wire M6. Therefore, the auxiliary circuit 813 including the second and fourth transistors TR2 and TR4 may electrically operate as a driver that improves the driving capability of the inverter 811 including the first and third transistors TR1 and TR3.

[0169] As mentioned above, in reference Figures 17 to 21 In the exemplary embodiments described, the configuration and operation of the input / output circuit of the SRAM may be described. Figures 17 to 21 The described exemplary embodiments are not limited thereto and may be used as a driving circuit configured to drive a plurality of loads. For example, the described exemplary embodiments may also be used as an input / output circuit of a flash memory device, an input / output circuit of a display panel, and the like.

[0170] The operation mode of the input / output circuit 800 can be selected according to the configuration of the SRAM (eg, the number of loads), thereby improving the area efficiency, insulation performance, or driving capability of the SRAM. In addition, the reliability of the SRAM can be enhanced.

[0171] Example embodiments provide a layout of a semiconductor device that selectively operates as an isolation circuit or a driving circuit.

[0172] According to example embodiments, area efficiency, insulation performance, or driving capability of a semiconductor device may be improved.

[0173] As is customary in the field of inventive conception, exemplary embodiments are described and shown in the accompanying drawings in the form of functional blocks, units and / or modules. Those skilled in the art will recognize that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (e.g., logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc.), which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where a block, unit and / or module is implemented by a microprocessor or the like, software (e.g., microcode) can be used to program it to perform the various functions discussed herein and can be optionally driven by firmware and / or software. Alternatively, each block, unit and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware for performing certain functions and a processor (e.g., one or more programmed microprocessors and associated circuits) for performing other functions. Moreover, without departing from the scope of the inventive conception, each block, unit and / or module of the exemplary embodiment can be physically separated into two or more interacting and discrete blocks, units and / or modules. Furthermore, without departing from the scope of the inventive concept, the blocks, units and / or modules of the exemplary embodiments may be physically combined into more complex blocks, units and / or modules.

[0174] Those skilled in the art will recognize that various changes and modifications may be made to the exemplary embodiments described herein without departing from the scope and spirit of the inventive concept. If modifications of the exemplary embodiments are included within the scope of the following claims and equivalents, the inventive concept is deemed to include these modifications and changes of the exemplary embodiments.

Claims

1. A semiconductor device, include: A first active region and a second active region extending along a first direction and arranged along a second direction perpendicular to the first direction, the first active region and the second active region being disposed in a substrate; A first gate electrode extending in a second direction perpendicular to the first direction, wherein the first gate electrode extends over the first active region and the second active region; a second gate electrode extending along a second direction on the first active region; a third gate electrode extending along a second direction on the first active region and the second active region; a fourth gate electrode extending along the second direction on the second active region, wherein the second gate electrode and the fourth gate electrode are on a common line; a first contact disposed on the first active region at a first side of the first gate electrode; a second contact disposed on the first active region at the first side of the second gate electrode; a third contact disposed on the second active region at the first side of the first gate electrode; a fourth contact disposed on the second active region at the first side of the fourth gate electrode; a first gate contact disposed on the first gate electrode; a second gate contact disposed on the second gate electrode; a third gate contact disposed on the fourth gate electrode; a first conductive line connected to the first gate electrode via a first gate contact; a second conductive line that overlaps at least a portion of the first contact, at least a portion of the second contact, and at least a portion of the second gate contact in a plan view, a third conductive line that overlaps at least a portion of the third contact, at least a portion of the fourth contact, and at least a portion of the third gate contact in a plan view; and a fourth conductive line disposed on the first active region and the second active region between the second side of the first gate electrode and the second sides of the second gate electrode and the fourth gate electrode, wherein the power supply voltage is supplied to the second conductor, Wherein, the ground voltage is provided to the third conductor, Wherein, at least a portion of the third conductive line extends along the first direction, At least a portion of the third conductive line intersects the fourth gate electrode in plan view, and wherein the first active region and the second active region extend so that at least a portion of the first gate electrode, at least a portion of the second gate electrode, and at least a portion of the third gate electrode overlap with the first active region in a plan view, and at least a portion of the first gate electrode, at least a portion of the third gate electrode, and at least a portion of the fourth gate electrode overlap with the second active region in a plan view.

2. The semiconductor device according to claim 1, in, At least a portion of the third conductive line extends along a first direction, and At least a portion of the third conductive line intersects the fourth gate electrode in a plan view.

3. The semiconductor device according to claim 1, in, The first conductive line does not overlap the first active region in a plan view.

4. The semiconductor device according to claim 1, in, The first conductive line extends along a first direction, wherein at least a portion of the second conductive line extends along a first direction, and Wherein, at least a portion of the third conductive line extends along the first direction.

5. The semiconductor device according to claim 2, in, The third conductive line extends along the second direction.

6. The semiconductor device according to claim 5, in, A first signal is input to the first conductive line, wherein a second signal is output from the fourth conductive line.

7. The semiconductor device according to claim 1, in, The fourth contact is disposed on the second gate electrode so as not to overlap with the first active region.

8. The semiconductor device according to claim 1, in, The third gate contact is disposed on the fourth gate electrode so as not to overlap with the second active region.

9. The semiconductor device according to claim 1, in, The first active region is a PMOS region, and the second active region is an NMOS region.

10. The semiconductor device according to claim 1, in, The first gate electrode, the first active region at the first side of the first gate electrode, and the first active region at the second side of the first gate electrode comprise a first transistor, wherein the second gate electrode, the first active region at the first side of the second gate electrode, and the first active region at the second side of the second gate electrode comprise a second transistor, wherein the first gate electrode, the second active region at the first side of the first gate electrode, and the second active region at the second side of the first gate electrode comprise a third transistor, The fourth gate electrode, the second active region at the first side of the fourth gate electrode, and the second active region at the second side of the fourth gate electrode comprise a fourth transistor.

11. The semiconductor device according to claim 10, in, The second transistor and the fourth transistor are turn-off transistors.

12. A semiconductor device, include: A first active region and a second active region extending along a first direction and arranged along a second direction perpendicular to the first direction, the first active region and the second active region being disposed in a substrate; a first gate electrode extending in a second direction perpendicular to the first direction, wherein the first gate electrode extends over the first active region and the second active region; a second gate electrode extending along a second direction on the first active region; a third gate electrode extending along a second direction on the first active region and the second active region; a fourth gate electrode extending along a second direction on the second active region, wherein the second gate electrode and the fourth gate electrode are on a common line; a first contact disposed on the first active region at a first side of the first gate electrode; a second contact disposed on the first active region at a second side of the second gate electrode; a third contact disposed on the second active region at the first side of the first gate electrode; a fourth contact disposed on the second active region at the first side of the third gate electrode; a first gate contact disposed on the first gate electrode; a second gate contact disposed on the second gate electrode; a third gate contact disposed on the fourth gate electrode; a first conductive line connected to the first gate electrode via a first gate contact; a second conductive line that overlaps a portion of the first source contact, a portion of the second contact, and a portion of the second gate contact; and a third conductive line that overlaps a portion of the third contact, a portion of the fourth contact, and a portion of the third gate contact, wherein a power supply voltage is provided to the second conductor, wherein a ground voltage is provided to the third conductor, wherein at least a portion of the third conductive line extends along the first direction, and at least a portion of the third conductive line intersects with the fourth gate electrode in a plan view, and wherein the first active region and the second active region extend so that at least a portion of the first gate electrode, at least a portion of the second gate electrode, and at least a portion of the third gate electrode overlap with the first active region in a plan view, and at least a portion of the first gate electrode, at least a portion of the third gate electrode, and at least a portion of the fourth gate electrode overlap with the second active region in a plan view.

13. The semiconductor device according to claim 12, in, The first conductive line extends along a first direction, wherein at least a portion of the second conductive line extends along the first direction, and At least a portion of the third conductive line extends along the first direction.

14. The semiconductor device according to claim 12, in, The second gate contact is disposed on the second gate electrode so as not to overlap with the first active region, and The third gate contact is disposed on the fourth gate electrode so as not to overlap with the second active region.

15. The semiconductor device according to claim 12, in, The second gate contact completely overlaps the second conductive line in a plan view, and The third gate contact completely overlaps with the third conductive line in a plan view.

16. A semiconductor device, include: A first active region and a second active region extending along a first direction and arranged along a second direction perpendicular to the first direction, the first active region and the second active region being disposed in a substrate; a first gate electrode extending in a second direction perpendicular to the first direction, wherein the first gate electrode extends over the first active region and the second active region; a second gate electrode extending along a second direction on the first active region; a third gate electrode extending along a second direction on the first active region and the second active region; a fourth gate electrode extending along a second direction on the second active region, wherein the second gate electrode and the fourth gate electrode are on a common line; a conductive line extending in a first direction and configured to provide a power supply voltage; and a gate contact disposed on the second gate electrode, wherein the second gate electrode extends through the conductive line, wherein a portion of the gate contact is disposed at an intersection of the second gate electrode and the conductive line, and There is a gap between the second gate electrode and the fourth gate electrode extending along the second direction.

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