Multilayer ceramic capacitor with ultra-wideband performance

Abstract

The present invention relates to a multilayer ceramic capacitor having ultra-wideband performance. A plurality of active electrodes can be disposed within a monolithic body of the capacitor and parallel to a longitudinal direction. A first shield electrode can be disposed within the monolithic body and parallel to the longitudinal direction. The first shield electrode can be connected with a first external terminal. The first shield electrode can have a first longitudinal edge and a second longitudinal edge, both aligned with a lateral direction and facing away from the first external terminal. A second shield electrode can be offset from the first longitudinal edge in the longitudinal direction by a shield electrode offset distance. The second shield electrode can be connected with a second external terminal. The second shield electrode can be substantially aligned with the first shield electrode in a Z direction.

Description

[0001] This application is a divisional application of Chinese Invention Patent Application No. 202080010344.4, filed on January 24, 2020, entitled “Multilayer Ceramic Capacitor with Ultra-wideband Performance”.

[0002] Cross Reference to Related Applications

[0003] This application claims priority to U.S. Provisional Application Serial No. 62 / 811,111, filed February 27, 2019, and U.S. Provisional Application Serial No. 62 / 797,523, filed January 28, 2019, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0004] The present invention relates to a multilayer ceramic capacitor with ultra-wideband performance. BACKGROUND

[0005] The diversity of modern technological applications has created a demand for efficient electronic components and integrated circuits for use therein. Capacitors are fundamental components used for filtering, coupling, bypassing, and other aspects of such modern applications, which can include wireless communications, alarm systems, radar systems, circuit switching, matching networks, and many others. The dramatic increase in integrated circuit speed and packaging density has particularly required advances in coupling capacitor technology. As high-capacitance coupling capacitors are subjected to high frequencies of many current applications, performance characteristics become increasingly important. Since capacitors are critical to such a wide range of applications, the precision and efficiency of capacitors are of utmost importance. Accordingly, many specific aspects of capacitor design have become a focus for improving their performance characteristics. SUMMARY

[0006] According to an embodiment of the invention, a wideband multilayer ceramic capacitor can have a first end and a second end spaced apart from the first end in a longitudinal direction perpendicular to a lateral direction. Both the lateral direction and the longitudinal direction can be perpendicular to a Z direction. The wideband multilayer ceramic capacitor can include a monolithic body including a plurality of dielectric layers, a first external terminal disposed along the first end, and a second external terminal disposed along the second end. The wideband multilayer ceramic capacitor can include a plurality of active electrodes arranged within the monolithic body and parallel to the longitudinal direction. The wideband multilayer ceramic capacitor can include a first shield electrode arranged within the monolithic body and parallel to the longitudinal direction. The first shield electrode can be connected with the first external terminal. The first shield electrode can have a first longitudinal edge aligned with the lateral direction and facing away from the first external terminal. The first shield electrode can have a second longitudinal edge aligned with the lateral direction and facing away from the first external terminal. The second longitudinal edge can be offset from the first longitudinal edge in the longitudinal direction by a shield electrode offset distance. A second shield electrode can be connected with the second external terminal and substantially aligned with the first shield electrode in the Z direction.

[0007] According to another embodiment of the invention, a wideband multilayer ceramic capacitor can have a first end and a second end spaced apart from the first end in a longitudinal direction perpendicular to a lateral direction. Both the lateral direction and the longitudinal direction can be perpendicular to a Z direction. The wideband multilayer ceramic capacitor can include a monolithic body including a plurality of dielectric layers, a first external terminal disposed along the first end, and a second external terminal disposed along the second end. The wideband multilayer ceramic capacitor can include a plurality of active electrodes arranged within the monolithic body and parallel to the longitudinal direction. The wideband multilayer ceramic capacitor can include a first shield electrode arranged within the monolithic body and parallel to the longitudinal direction. The first shield electrode can be connected with the first external terminal. A second shield electrode can be arranged within the monolithic body and parallel to the longitudinal direction. The second shield electrode can be connected with the second external terminal. The second shield electrode can be substantially aligned with the first shield electrode in the Z direction. A shield gap distance can be formed between the first shield electrode and the second shield electrode in the longitudinal direction. The capacitor can have a capacitor length between the first end and the second end of the capacitor in the longitudinal direction. A ratio of the capacitor length to the shield gap distance can be greater than about 2.

[0008] According to another embodiment of the present invention, a method for forming a broadband multilayer ceramic capacitor is disclosed. The method may include forming a plurality of active electrodes on a plurality of active electrode layers. The method may include forming a first shielding electrode on a shielding electrode layer. The first shielding electrode may extend to a first end of a monolithic body of the capacitor. The first shielding electrode may have a first longitudinal edge aligned with a lateral direction and facing away from a first external terminal. The first shielding electrode may have a second longitudinal edge aligned with a lateral direction and facing away from the first external terminal. A second shielding electrode may be offset longitudinally from the first longitudinal edge by a shielding electrode offset distance. The method may include forming a second shielding electrode on the shielding electrode layer, the second shielding electrode extending to a second end of the monolithic body and substantially aligned with the first shielding electrode in the Z direction. The method may include stacking a plurality of active electrode layers and a shielding electrode layer to form a monolithic body such that the plurality of active electrode layers and the plurality of shielding electrodes are parallel to the longitudinal direction of the capacitor. Attached Figure Description

[0009] The full and feasible disclosure of the invention (including its best mode to those skilled in the art) is set forth in more detail in the remainder of the specification (including with reference to the accompanying drawings), in which:

[0010] FIG. 1A A top view of one embodiment of the active electrode layer according to aspects of this disclosure is shown;

[0011] FIG. 1B Aspects according to this disclosure are shown as follows FIG. 1A A three-dimensional view of the alternating electrode layers shown.

[0012] FIG. 1C This illustrates a plurality of capacitor regions formed therein, according to aspects of this disclosure. FIG. 1A A top-down view of an implementation scheme for an active electrode layer;

[0013] FIG. 1D A top-down view is shown of an embodiment of a shielding electrode in which multiple capacitor regions are formed according to aspects of this disclosure;

[0014] FIG. 1E A side cross-sectional view of one embodiment of a capacitor comprising multiple regions according to aspects of this disclosure is shown, wherein the active electrode layer is as follows: FIGS. 1A-1C The configuration shown and the shielding electrode layer are as follows FIG. 1C The configuration shown;

[0015] FIG. 2A A top view of another embodiment of the active electrode layer according to aspects of this disclosure is shown;

[0016] FIG. 2Ba cross-sectional view of another embodiment of a capacitor including a plurality of capacitive regions according to aspects of the present disclosure, wherein the active electrode layer is configured as shown in FIG. 2A a top-down view of an embodiment of an active electrode layer;

[0017] FIG. 2C a perspective view of alternating electrode layers configured as shown in FIG. 2A

[0018] FIG. 3A a cross-sectional view of another embodiment of a capacitor including a plurality of capacitive regions according to aspects of the present disclosure, wherein the active electrode layer is configured as shown in FIGS. 2A-2C and the shield electrode layer is configured as shown in FIG. 1D

[0019] FIG. 3B another embodiment of a capacitor according to aspects of the present disclosure;

[0020] FIG. 4 depicts a circuit schematic diagram of an embodiment of a capacitor having a plurality of capacitive regions as shown in FIGS. 1A-1E

[0021] FIG. 5 depicts a circuit schematic diagram of an embodiment of a capacitor having a plurality of capacitive regions as shown in FIGS. 2A-2C

[0022] FIG. 6 shows simulated insertion loss data for a capacitor of FIG. 1E in a first orientation as shown in FIGS. 1A-1E and a second orientation;

[0023] FIGS. 7A-7D shows a top view of an anchor electrode, a shield electrode, and an active electrode of a capacitor according to an embodiment of the present disclosure; FIG. 6

[0024] FIGS. 8A-8D shows a top view of an additional embodiment of an active electrode layer according to certain embodiments of the present disclosure;

[0025] FIG. 9 shows a capacitor of FIG. 1E in a second orientation; and

[0026] FIG. 10 depicts a representative insertion loss response curve measured for one of eight multilayer ceramic capacitors manufactured. DETAILED DESCRIPTION

[0027] It will be understood by one having ordinary skill in the art that the discussion herein is a description of exemplary implementations only and is not intended to limit the broader aspects of the disclosure.​​​​​

[0028] Generally, the present invention relates to a multilayer ceramic capacitor. In particular, the present invention relates to a multilayer ceramic capacitor that includes alternating dielectric and electrode layers within a single monolithic body.

[0029] A plurality of active electrodes, a first shield electrode, and a second shield electrode can be arranged within the monolithic body. The shield electrodes can be configured to improve the response characteristics (e.g., insertion loss, return loss, etc.) of the capacitor. The shield electrodes can have offset longitudinal edges that define one or more steps, such as described below with reference to FIG. 1D For example, the first shield electrode can be connected with a first external terminal. The first shield electrode can have a first longitudinal edge that is aligned with the lateral direction and faces away from the first external terminal. The first shield electrode can have a second longitudinal edge that is aligned with the lateral direction and faces away from the first external terminal. The second shield electrode can be offset from the first longitudinal edge in the longitudinal direction by a shield electrode offset distance. The second shield electrode can be connected with a second external terminal and generally aligned with the first shield electrode in the Z-direction. The wideband multilayer ceramic capacitor can be configured for mounting to a mounting surface such that the first and second shield electrodes are positioned between the plurality of active electrode layers and the mounting surface.

[0030] The active electrode region can include active electrodes that are configured to exhibit a plurality of capacitive elements within a single set of stacked electrodes. For example, primary capacitive elements can be effective at relatively low frequencies, while secondary capacitive elements can be effective at relatively mid and / or high frequencies. For example, the primary capacitance can be within 1 and 500 nF, such as within approximately 10 and 100 nF, while the secondary capacitance can be within 1 and 500 pF, such as within 10 and 100 pF.

[0031] The inventors have discovered that such a configuration can provide a multilayer ceramic capacitor with low insertion loss across a wide frequency range. Generally, insertion loss is the power loss through a capacitor and can be measured using any method known in the art.

[0032] The shield electrodes can be arranged within the monolithic body in various configurations that can exhibit different insertion loss characteristics. For example, in one embodiment, a shield electrode can be positioned between the active electrode region and a bottom surface of the capacitor. A dielectric region without a shield electrode can be positioned between the active electrode region and a top surface of the capacitor, such as described below with reference to FIG. 1EIn such embodiments, the capacitor can exhibit an insertion loss of greater than about -0.5 dB from about 1 GHz to about 40 GHz, in some embodiments greater than about -0.4 dB, in some embodiments greater than about -0.35 dB, and in some embodiments greater than about -0.3 dB. In such embodiments, the capacitor can exhibit an insertion loss of greater than about -0.4 dB at about 10 GHz, in some embodiments greater than about -0.35 dB at about 10 GHz, in some embodiments greater than about -0.3 dB, and in some embodiments greater than about -0.25 dB at about 10 GHz. The capacitor can exhibit an insertion loss of greater than about -0.4 dB at about 20 GHz, in some embodiments greater than about -0.35 dB at about 20 GHz, and in some embodiments greater than about -0.3 dB at about 20 GHz. The capacitor can exhibit an insertion loss of greater than about -0.4 dB at about 30 GHz, in some embodiments greater than about -0.35 dB at about 30 GHz, in some embodiments greater than about -0.3 dB at about 30 GHz, and in some embodiments greater than about -0.25 dB at about 30 GHz. The capacitor can exhibit an insertion loss of greater than about -0.4 dB at about 40 GHz, in some embodiments greater than about -0.35 dB at about 40 GHz, in some embodiments greater than about -0.3 dB at about 40 GHz, and in some embodiments greater than about -0.25 dB at about 40 GHz.

[0033] In some embodiments, the wideband multilayer ceramic capacitor can exhibit an insertion loss of from about -0.05 dB to about -0.4 dB from about 5 GHz to about 20 GHz, in some embodiments from about -0.05 dB to about -0.3 dB from about 10 GHz to about 20 GHz, in some embodiments from about -0.05 dB to about -0.3 dB from about 20 GHz to about 30 GHz, and in some embodiments from about -0.05 dB to about -0.3 dB from about 30 GHz to about 40 GHz.

[0034] In another embodiment, one or more bottom shield electrodes can be disposed between the active electrode region and a bottom surface of the capacitor. One or more top shield electrodes can be disposed between the active electrode region and a top surface of the capacitor, for example as described below with reference to FIG. 3. FIG. 3BThe insertion loss can be about -0.3 dB or more, for example about -0.28 dB or more, for example about -0.25 dB or more, for example about -0.23 dB or more, when measured across a frequency range spanning 4 GHz to 10 GHz. In such embodiments, the insertion loss can be about -0.3 dB or more, for example about -0.28 dB or more, for example about -0.25 dB or more, for example about -0.23 dB or more, when measured across a frequency range spanning 4 GHz to 10 GHz.

[0035] The insertion loss can be about -0.4 dB or more, for example about -0.38 dB or more, for example about -0.35 dB or more, for example about -0.34 dB or more, when measured across a frequency range spanning 13 GHz to 20 GHz. In such embodiments, the insertion loss can be about -0.4 dB or more, for example about -0.38 dB or more, for example about -0.35 dB or more, for example about -0.34 dB or more, when measured across a frequency range spanning 13 GHz to 20 GHz.

[0036] The insertion loss can be about -0.45 dB or more, for example about -0.4 dB or more, for example about -0.38 dB or more, for example about -0.35 dB or more, for example about -0.32 dB or more, when measured across a frequency range spanning 23 GHz to 30 GHz. In such embodiments, the insertion loss can be about -0.45 dB or more, for example about -0.4 dB or more, for example about -0.38 dB or more, for example about -0.35 dB or more, for example about -0.32 dB or more, when measured across a frequency range spanning 23 GHz to 30 GHz.

[0037] The insertion loss can be about -0.55 dB or more, for example about -0.5 dB or more, for example about -0.48 dB or more, for example about -0.45 dB or more, for example about -0.43 dB or more, when measured across a frequency range spanning 33 GHz to 40 GHz. In such embodiments, the insertion loss can be about -0.55 dB or more, for example about -0.5 dB or more, for example about -0.48 dB or more, for example about -0.45 dB or more, for example about -0.43 dB or more, when measured across a frequency range spanning 33 GHz to 40 GHz.

[0038] The ratio of the capacitor length to the shield electrode offset distance can be greater than about 2, in some embodiments greater than about 5, in some embodiments greater than about 10, in some embodiments greater than about 15, in some embodiments greater than about 20, and in some embodiments greater than about 40.

[0039] The first shield gap distance and / or the second shield gap distance can be in a range of about 10 microns to about 200 microns, in some embodiments in a range of about 20 microns to about 150 microns, and in some embodiments in a range of about 30 microns to about 80 microns.

[0040] The shield electrode offset distance can be in a range of about 75 microns to about 300 microns, in some embodiments in a range of about 100 microns to about 250 microns, and in some embodiments in a range of about 125 microns to about 175 microns.

[0041] In some embodiments, the second shield electrode can have a first longitudinal edge aligned with the lateral direction and facing away from the second external terminal. The second shield electrode can have a second longitudinal edge aligned with the lateral direction and facing away from the second external terminal. The second longitudinal edge can be offset from the first longitudinal edge in the longitudinal direction by substantially the shield electrode offset distance.

[0042] A first shield gap distance can be formed in the longitudinal direction between the first longitudinal edge of the first shield electrode and the first longitudinal edge of the second shield electrode. The capacitor can have a capacitor length in the longitudinal direction between the first end and the second end of the capacitor. A ratio of the capacitor length to the first shield gap distance can be greater than about 2, in some embodiments greater than about 5, in some embodiments greater than about 10, in some embodiments greater than about 15, in some embodiments greater than about 20, and in some embodiments greater than about 40. For example, the first shield gap distance can be in a range from about 25 microns to about 400 microns, in some embodiments in a range from about 40 microns to about 300 microns, in some embodiments in a range from about 50 microns to about 200 microns, and in some embodiments in a range from about 75 microns to about 150 microns.

[0043] In some embodiments, a second shield gap distance can be formed in the longitudinal direction between the second longitudinal edge of the first shield electrode and the second longitudinal edge of the second shield electrode. A ratio of the second shield gap distance to the first shield gap distance can be in a range from about 0.5 to about 40, in some embodiments in a range from about 0.7 to about 20, in some embodiments in a range from about 1.1 to about 10, in some embodiments in a range from about 1.5 to about 8, and in some embodiments in a range from about 2 to about 6. A ratio of the second shield gap distance to the capacitor length can be in a range from about 1.1 to about 40, in some embodiments in a range from about 1.2 to about 20, in some embodiments in a range from about 1.3 to about 10, in some embodiments in a range from about 1.5 to about 5, and in some embodiments in a range from about 2 to about 4. For example, the second shield gap distance can be in a range from about 25 microns to about 1200 microns, in some embodiments in a range from about 50 microns to about 1000 microns, in some embodiments in a range from about 100 microns to about 800 microns, and in some embodiments in a range from about 200 microns to about 600 microns.

[0044] However, it should be appreciated that in some embodiments, the second shield gap distance can be substantially equal to the first shield gap distance. In other words, the shield electrodes can be free of stepped portions such that the shield gap distance between the shield electrodes can be substantially uniform across the width of the shield electrodes.

[0045] The first shield electrode can have a third longitudinal edge aligned with the lateral direction and facing away from the first external terminal. The second shield electrode can have a third longitudinal edge aligned with the lateral direction and facing away from the second external terminal. A third shield gap distance can be formed in the longitudinal direction between the third longitudinal edge of the first shield electrode and the third longitudinal edge of the second shield electrode. The first shield electrode can be symmetric about a longitudinal centerline extending in the longitudinal direction in the lateral direction.

[0046] In some embodiments, a shield-to-bottom-surface distance can be defined as a distance between a shield electrode and a bottom surface of the capacitor. If multiple shield electrode layers are included, the shield-to-bottom-surface distance can be defined as a distance between a lowest layer of the shield electrode layers and the bottom surface. A ratio of the capacitor thickness to the shield-to-bottom-surface distance can be greater than about 2, in some embodiments greater than about 5, in some embodiments greater than about 10, in some embodiments greater than about 15, in some embodiments greater than about 20, and in some embodiments greater than about 40.

[0047] At least one of the active electrode layers can include a first electrode including a base portion electrically connected with the first external terminal. A first electrode arm can extend from the base portion in the longitudinal direction. A center portion of the first electrode can extend from the base portion in the longitudinal direction. The center portion of the first electrode can have a first width at a first location and a second width greater than the first width at a second location. The second location can be offset from the first location in the longitudinal direction.

[0048] At least one of the active electrode layers can include a second electrode including a base portion electrically connected with the second external terminal. A center end gap distance can be formed in the longitudinal direction between the center portion of the first electrode and the base portion of the second electrode.

[0049] In some embodiments, at least one of the active electrode layers can include a second electrode including a base portion electrically connected with the second external terminal, and wherein a center edge gap distance is formed in the lateral direction between the center portion of the first electrode and the second electrode arm.

[0050] I. Example Embodiments

[0051] Turning to FIGS. 1A-1E One embodiment of a multilayer ceramic capacitor 100 is disclosed. FIG. 1Eis a simplified side view of a multilayer capacitor 100 mounted to a mounting surface 101, such as a printed circuit board or substrate. The multilayer capacitor 100 can include a plurality of electrode regions 10 stacked in a Z-direction 136. The plurality of electrode regions 10 can include a dielectric region 12, an active electrode region 14, and a shield electrode region 16. The active electrode region 14 can be positioned between the dielectric region 12 and the shield electrode region 16 in the Z-direction 136. The dielectric region 12 can extend from the active electrode region 14 to a top surface 18 of the wideband multilayer ceramic capacitor 100. The capacitor 100 can include a bottom surface 20 opposite the top surface 18 in the Z-direction 136.

[0052] The electrode regions 10 can include a plurality of dielectric layers. Some of the dielectric layers can include electrode layers formed thereon. Generally, the thickness of the dielectric layers and electrode layers are not limited and can be any thickness as desired based on the performance characteristics of the capacitor. For example, the thickness of the electrode layers can be, but are not limited to, about 500 nm or greater, such as about 1 μιη or greater, such as about 2 μιη or greater, such as about 3 μιη or greater, such as about 4 μιη or greater to about 10 μιη or less, such as about 5 μιη or less, such as about 4 μιη or less, such as about 3 μιη or less, such as about 2 μιη or less. For example, the electrode layers can have a thickness of about 1 μιη to about 2 μιη. Further, in an embodiment, the thickness of the dielectric layers can be defined based on the thickness of the electrode layers described above. Further, it should be appreciated that such thicknesses of the dielectric layers, when present and as defined herein, can also apply to the layers between any active electrode layers and / or shield electrode layers, as applicable.

[0053] Generally, the present disclosure provides multilayer capacitors having unique electrode arrangements and configurations that provide various benefits and advantages. In this regard, it should be appreciated that the materials employed to construct the capacitors can be unlimited and can be any materials commonly employed in the art and can be formed using any methods commonly employed in the art.

[0054] Generally, the dielectric layers are generally formed from a material having a relatively high dielectric constant (K), such as about 10 to about 40,000, in some embodiments about 50 to about 30,000, and in some embodiments about 100 to about 20,000.

[0055] In this regard, the dielectric material can be ceramic. The ceramic can be provided in a variety of forms, such as a wafer (e.g., pre-fired) or co-fired within the device itself.

[0056] Particular embodiments of high dielectric material types include, for example, NPO (COG) (up to about 100), X7R (about 3,000 to about 7,000), X7S, Z5U, and / or Y5V materials. It should be appreciated that the above materials are described by their industry-recognized definitions, and that some of these materials are standard classifications established by the Electronic Industries Alliance (EIA), and as such should be recognized by one of ordinary skill in the art. For example, such materials can include ceramics. Such materials can include perovskites, such as barium titanate and related solid solutions (e.g., barium strontium titanate, barium calcium titanate, barium zirconium titanate, barium strontium zirconium titanate, barium calcium zirconium titanate, etc.), lead titanate and related solid solutions (e.g., lead zirconium titanate, lead lanthanum titanate), bismuth sodium titanate, etc. In one particular embodiment, for example, barium strontium titanate of the formula Ba X Sr 1-x TiO3, where x is from 0 to 1, in some embodiments from about 0.15 to about 0.65, and in some embodiments from about 0.25 to about 0.6. Other suitable perovskites can include, for example, Ba X Ca 1-x TiO3, where x is from about 0.2 to about 0.8, and in some embodiments from about 0.4 to about 0.6; Pb X Zr 1-x TiO3 ("PZT"), where x ranges from about 0.05 to about 0.4; lead lanthanum zirconate titanate ("PLZT"), lead titanate (PbTiO3), barium calcium zirconium titanate (BaCaZrTiO3), sodium nitrate (NaN03), KNbO3, LiNbO3, LiTaO3, PbNb2O6, PbTa2O6, KSr(NbO3), and NaBa2(NbO3)5KHb2PO4. Additional complex perovskites can include A[B1 1 / 3 B2 2 / 3 ]O3 materials, where A is Ba X Sr 1-x (x can be a value from 0 to 1); B1 is Mg y Zn 1-y (y can be a value from 0 to 1); B2 is Ta z Nb 1-z (z can be a value from 0 to 1). In one particular embodiment, the dielectric layer can include a titanate.

[0057] The electrode layers can be formed of any of a variety of different metals known in the art. The electrode layers can be made of a metal, such as a conductive metal. The material can include a noble metal (e.g., silver, gold, palladium, platinum, etc.), a base metal (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and the like, as well as various combinations thereof. Sputtered titanium / tungsten (Ti / W) alloys, as well as individual sputtered layers of chromium, nickel, and gold can also be suitable. The electrodes can also be made of a low resistance material, such as silver, copper, gold, aluminum, palladium, and the like. In one particular embodiment, the electrode layers can comprise nickel or an alloy thereof.

[0058] Referring again to FIG. 1E In some embodiments, the dielectric region 12 can not have an electrode layer extending from the first end 119 or the second end 120 of the capacitor 100 greater than about 25% of the length 21 of the capacitor 100, in some embodiments greater than about 20% of the length of the capacitor, in some embodiments greater than about 15% of the length of the capacitor, in some embodiments greater than about 10% of the length of the capacitor, in some embodiments greater than about 5% of the length of the capacitor, and in some embodiments greater than about 2% of the length of the capacitor (schematically illustrated by block 21). For example, in such embodiments, the dielectric region 12 can include one or more floating electrodes and / or dummy electrode tabs. However, in other embodiments, the dielectric region 12 can be free of all electrode layers. In some embodiments, the wideband multilayer ceramic capacitor 100 can be free of a shield electrode 22, 24 above the plurality of active electrode layers 102, 104 in the Z-direction 136. In some embodiments, the wideband multilayer ceramic capacitor 100 can be free of a shield electrode 22, 24 above the lowest electrode layer 19 of the plurality of active electrode layers 102, 104 in the Z-direction 136.

[0059] The plurality of active electrode layers 102, 104 can be disposed within an active electrode region 14. Each active electrode layer 102, 104 can include one or more active electrodes, such as described below with reference to FIGS. 1A-1C For example, in some embodiments, each active electrode layer 102, 104 can include a first electrode 106 and a second electrode 108.

[0060] The multilayer capacitor 100 can include a first external terminal 118 connected to the first electrode 106 of the first electrode layer 102 and the second (opposite) electrode 108 of the second electrode layer 104. The multilayer capacitor 100 can include a second external terminal 120 connected to the first electrode 106 of the second electrode layer 104 and the second (opposite) electrode 108 of the first electrode layer 102.

[0061] The shield electrode region 16 can include one or more shield electrodes, such as described below with reference to FIG. 2, for example. For example, the shield electrode region 16 can include a first shield electrode 22 disposed in a monolithic body of the capacitor 100. The first shield electrode 22 can be parallel to the longitudinal direction 132. The first shield electrode 22 can be connected with the first external terminal 118. The shield electrode region 16 can include a second shield electrode 24 that can be connected with the second external terminal 120. The second shield electrode 24 can be approximately aligned with the first shield electrode 22 in the Z direction 136. FIG. 1D

[0062] Generally, for the embodiments discussed herein, the external terminals can be formed of any of a variety of different metals known in the art. The external terminals can be made of a metal, such as a conductive metal. The material can include a noble metal (e.g., silver, gold, palladium, platinum, etc.), a base metal (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), or the like, and various combinations thereof. In one particular embodiment, the external terminals can include copper or an alloy thereof.

[0063] The external terminals can be formed using any method known in the art. The external terminals can be formed using techniques such as sputtering, painting, printing, electroless plating or fine copper termination (FCT), electroplating, plasma deposition, propellant spray / air brushing, or the like.

[0064] In one embodiment, the external terminals can be formed such that the external terminals are relatively thick. For example, such terminals can be formed by applying a thick film strip of metal to the exposed portions of the electrode layers (e.g., by dipping the capacitor into a liquid external terminal material). Such metal can be in a glass matrix and can include silver or copper. As an example, such a strip can be printed and fired onto the capacitor. Thereafter, an additional metal (e.g., nickel, tin, solder, etc.) plating can be formed over the terminal strip such that the capacitor is solderable to a substrate. Such application of the thick film strip can be performed using any method known in the art (e.g., by a termination machine and printing wheel for transferring a load metal paste over the exposed electrode layers).

[0065] The thick plated external terminals can have an average thickness of about 150 pm or less, such as about 125 pm or less, such as about 100 pm or less, such as about 80 pm or less. The thick plated external terminals can have an average thickness of about 25 pm or more, such as about 35 pm or more, such as about 50 pm or more, such as about 75 pm or more. For example, the thick plated external terminals can have an average thickness of about 25 pm to about 150 pm, such as about 35 pm to about 125 pm, such as about 50 pm to about 100 pm. ​

[0066] In another embodiment, the external terminal can be formed such that the external terminal is a thin film plating of metal. Such a thin film plating can be formed by depositing a conductive material, such as a conductive metal, on the exposed portions of the electrode layer. For example, the front edge of the electrode layer can be exposed such that the front edge can allow for the formation of a plated termination.

[0067] The thin plated external terminal can have an average thickness of about 50 μιη or less, such as about 40 μιη or less, such as about 30 μιη or less, such as about 25 μιη or less. The thin plated external terminal can have an average thickness of about 5 μιη or more, such as about 10 μιη or more, such as about 15 μιη or more. For example, the external terminal can have an average thickness of about 5 μιη to about 50 μιη, such as about 10 μιη to about 40 μιη, such as about 15 μιη to about 30 μιη, such as about 15 μιη to about 25 μιη.

[0068] Generally, the external terminal can include a plated termination. For example, the external terminal can include an electroplated terminal, an electroless plated terminal, or a combination thereof. For example, the electroplated terminal can be formed by electroplating. The electroless plated terminal can be formed by electroless plating.

[0069] When the external terminal is formed of multiple layers, the external terminal can include an electroplated terminal and an electroless plated terminal. For example, the initial layer of material can be deposited first using electroless plating. The plating technique can then be switched to an electrochemical plating system, which can allow for faster build-up of material.

[0070] When forming the plated termination using either plating method, the front edge of the lead tab of the electrode layer exposed from the capacitor body is subjected to the plating solution. In one embodiment, by subjected, the capacitor can be immersed in the plating solution.

[0071] A plating solution including a conductive material, such as a conductive metal, is used to form the plated termination. Such a conductive material can be any of the above-described materials or any material known in the art. For example, the plating solution can be a nickel sulfamate bath or other nickel solution such that the plating layer and the external terminal include nickel. Alternatively, the plating solution can be a copper acid bath or other suitable copper solution such that the plating layer and the external terminal include copper.

[0072] Further, it should be appreciated that the plating solution can include other additives known in the art. For example, the additives can include other organic additives and media that can aid in the plating process. Further, additives can be used to employ the plating solution at a desired pH. In one embodiment, a resistance reducing additive can be used in the solution to aid in full plating coverage as well as to bind the plated material to the exposed leading edges of the capacitor and lead tab.

[0073] The capacitor can be exposed, submerged, or immersed in the plating solution for a predetermined amount of time. Such exposure time is not necessarily limited, but can be a sufficient amount of time to allow for sufficient deposition of plated material to form a plated terminal. In this regard, the time should be sufficient to allow for a continuous connection to be formed between the desired exposed adjacent leading edges of the lead tab of a given polarity of the individual electrode layers within the set of alternating dielectric and electrode layers.

[0074] Generally, the distinction between electroplating and electroless plating is that electroplating employs an electrical bias, such as by using an external power source. Electrolytic plating solutions can generally be subjected to a high current density range, such as ten to fifteen amp / ft 2 A connection can be made by a negative connection to the capacitor that needs to form a plated terminal and a positive connection to a solid material in the same plating solution, such as copper in a copper plating solution. That is, the capacitor is biased to the opposite polarity of the plating solution. Using this method, the conductive material of the plating solution is attracted to the metal of the exposed leading edges of the lead tab of the electrode layer.

[0075] Various pre-treatment steps can be employed prior to immersing or subjecting the capacitor to the plating solution. Such steps can be performed for a variety of purposes, including catalyzing, accelerating, and / or improving adhesion of the plated material to the leading edges of the lead tab.

[0076] Further, an initial cleaning step can be employed prior to plating or any other pre-treatment step. Such a step can be employed to remove any oxide buildup that forms on the exposed lead tab of the electrode layer. This cleaning step can be particularly helpful in assisting in removing any buildup of nickel oxide when the internal electrode or other conductive element is formed of nickel. The part cleaning can be achieved by fully immersing in a pre-cleaning bath, such as a bath including an acidic cleaner. In one embodiment, the exposure can be for a predetermined time, such as on the order of about 10 minutes. Cleaning can alternatively be achieved by a chemical polishing or harperizing step.

[0077] Further, a step of activating the exposed metal front edge of the lead tab of the electrode layer can be performed to facilitate deposition of the conductive material. Activation can be achieved by immersion in a palladium salt, photo patterning of a palladium organometallic precursor (through a mask or laser), screen printing or ink jet deposition of a palladium compound, or electrophoretic palladium deposition. It should be appreciated that the palladium based activation is presently disclosed only as an example of an activation solution that generally works well with activation of exposed tab portions formed from nickel or alloys thereof. However, it should be appreciated that other activation solutions can also be used.

[0078] Further, as an alternative to or in addition to the above activation step, an activation dopant can be introduced into the conductive material when forming the electrode layer of the capacitor. For example, when the electrode layer comprises nickel and the activation dopant comprises palladium, the palladium dopant can be introduced into the nickel ink or composition that forms the electrode layer. Doing so can eliminate the palladium activation step. It should further be appreciated that some of the above activation methods (such as organometallic precursors) also facilitate co-deposition of the glass former by itself to increase adhesion to the general ceramic body of the capacitor. When an activation step is used as described above, trace amounts of the activation agent material can generally remain at the exposed conductive portions before and after termination plating.

[0079] Further, post-plating treatment steps can also be employed. Such steps can be performed for a variety of purposes, including enhancing and / or improving adhesion of the material. For example, a heating (or annealing) step can be employed after performing the plating step. Such heating can be performed by baking, subjecting to a laser, ultraviolet (UV) exposure, microwave exposure, electric arc welding, etc.

[0080] As described herein, the external terminal can include at least one plated layer. In one embodiment, the external terminal can include only one plated layer. However, it should be appreciated that the external terminal can include multiple plated layers. For example, the external terminal can include a first plated layer and a second plated layer. Further, the external terminal can also include a third plated layer. The material of these plated layers can be any of the above described and well known in the art.

[0081] For example, one plated layer (e.g., the first plated layer) can include copper or an alloy thereof. Another plated layer (e.g., the second plated layer) can include nickel or an alloy thereof. Another plated layer (e.g., the third plated layer) can include tin, lead, gold, or a combination such as an alloy. Alternatively, an initial plated layer can include nickel, followed by a tin or gold plated layer. In another embodiment, an initial plated layer of copper can be formed, followed by a nickel layer.

[0082] In one embodiment, the initial or first plating layer can be a conductive metal (e.g., copper). This area can then be covered with a second layer comprising a resistive polymeric material for sealing. This area can then be polished to selectively remove the resistive polymeric material, and then plated again with a third layer comprising a conductive metal material (e.g., copper).

[0083] The above-described second layer over the initial plating layer can correspond to a solder barrier layer, such as a nickel solder barrier layer. In some embodiments, the above-described layer can be formed by electroplating an additional metal (e.g., nickel) layer on top of an initial chemical or electrolytic plating layer (e.g., copper plating). Other exemplary materials for the layer of the above-described solder barrier layer include nickel-phosphorus, gold, and silver. In some embodiments, the third layer over the above-described solder barrier layer can correspond to a conductive layer, such as a plated Ni, Ni / Cr, Ag, Pd, Sn, Pb / Sn, or other suitable plated solder.

[0084] Further, a layer of metal plating can be formed, and then an electroplating step can be performed to provide a resistive alloy or higher resistance metal alloy coating over such metal plating, such as a chemical Ni-P alloy plating. However, it should be understood that any metal coating can be included, as would be understood by one of ordinary skill in the art from the complete disclosure herein.

[0085] It should be understood that any of the above-described steps can occur as a bulk process, such as a barrel plating, fluidized bed plating, and / or flow-through plating termination process, all of which are well known in the art. Such bulk processes enable simultaneous processing of multiple components, thereby providing an efficient and fast termination process. This is a particular advantage over traditional termination methods, such as printing of thick film terminations that require individual component processing.

[0086] As described herein, the formation of the external termination is generally guided by the location of the exposed leading edge of the lead tab of the electrode layer. This phenomenon can be referred to as “self-determining” in that the formation of the external plated termination is determined by the configuration of the exposed conductive metal of the electrode layer at the selected peripheral location on the capacitor. In some embodiments, the capacitor can include a “virtual tab” to provide exposed conductive metal along a portion of the monolithic body of the capacitor that does not include other electrodes (e.g., active electrodes or shield electrodes).

[0087] It should be understood that additional techniques for forming the capacitor termination can also be within the scope of the present technology. Exemplary alternatives include, but are not limited to, forming the termination by plating, magnetism, masking, electrophoresis / electrostatic, sputtering, vacuum deposition, printing, or other techniques for forming a thick film or thin film conductive layer.

[0088] FIG. 1A FIG. 1 illustrates a top view of one embodiment of an active electrode configuration for one or more electrodes in an active electrode zone 14, in accordance with aspects of the present disclosure. More specifically, the active electrode zone 14 can include first electrode layers 102 and second electrode layers 104 arranged in an alternating mirror configuration, for example, as described below with reference to FIGS. 2-4. FIG. 1B Referring to FIG. 2, each active electrode layer 102, 104 can include a first electrode 106 and a second electrode 108. The first electrode 106 can have a base portion 114 extending in a lateral direction 134 along a longitudinal edge of the first electrode 106. The first electrode 106 can have a pair of electrode arms 110 extending in a longitudinal direction 132 from the base portion 114. The second electrode 108 can have a base portion 114 extending in the lateral direction 134 along a longitudinal edge of the second electrode layer 108. The second electrode 108 can have a pair of electrode arms 110 extending in the longitudinal direction 132 from the base portion 114. FIG. 1A

[0089] The first electrode arm 110 of the first electrode 106 can be generally longitudinally aligned with the corresponding electrode arm 110 of the second electrode 108. An arm gap 226 can be defined between the aligned electrode arms 110 of the first electrode 106 and the second electrode 108 in the longitudinal direction 132.

[0090] A center edge gap distance 23 can be defined in the lateral direction 134 between the center portion 122 of the first electrode and the second electrode arm 110. A center end gap distance 24 can be defined in the longitudinal direction 132 between the center portion 122 of the first electrode 106 and the base portion 114 of the second electrode 108. In some embodiments, the center edge gap distance 23 can be generally equal to the center end gap distance 24.

[0091] The center portion 112 of the first electrode 106 can have a first width 27 at a first location and a second width 29 greater than the first width 27 at a second location. The first location of the first width 27 can be offset from the second location of the second width in the longitudinal direction 132. This configuration can allow for adjusting the overlap area between the center portions 112 of adjacent electrodes in the Z-direction 136 without changing the center edge gap distance 23.

[0092] Referring to FIG. 4, the plurality of first electrode layers 102 and the plurality of second electrode layers 104 can be arranged in an alternating mirror configuration. As shown, the center portions 112 of the respective electrode layers at least partially overlap. FIG. 1B FIG. 1B A total of four electrode layers are illustrated; however, it should be understood that any number of electrode layers can be employed to achieve a desired capacitance for a desired application.​​

[0093] Referring to FIG. 1C A number of capacitive regions can be formed between the first electrode 106 and the second electrode 108. For example, in some embodiments, a center capacitive region 122 can be formed between the center portion 112 of the first electrode 106 and the base portion 114 and / or the arms 128 of the second electrode 108. In some embodiments, an arm gap capacitive region 124 can be formed within the arm gap 240 between the electrode arms 110 of the first electrode 106 and the electrode arms 110 of the second electrode 108.

[0094] FIG. 1D A shield electrode layer 26 is illustrated that can be included within a shield electrode region 16 (shown in FIG. 1E As described above, the first shield electrode 22 can be parallel to the longitudinal direction 132 (e.g., parallel to the top surface 18 and the bottom surface 20 shown). The first shield electrode 22 can have a first longitudinal edge 28 that is aligned with the lateral direction 134 and facing away from the first external terminal 118 (shown in FIG. 1E ) and the first end 119. The first shield electrode 22 can have a second longitudinal edge 30 that is aligned with the lateral direction 134 and facing away from the first external terminal 118 (shown in FIG. 1E ) and the first end 119. The second longitudinal edge 30 can be offset from the first longitudinal edge 28 in the longitudinal direction 132 by a shield electrode offset distance 32. FIG. 1E

[0095] The second shield electrode 24 can be connected with the second external terminal 120 (as shown in FIG. 1E ) and the second end 121. The second shield electrode 24 can be generally aligned with the first shield electrode 22 in the Z direction 136 (as shown in FIG. 1E ) and the second end 121. The second shield electrode 24 can have a first longitudinal edge 28 that is aligned with the lateral direction 134 and facing away from the second external terminal 120 (shown in FIG. 1E ) and the second end 121. The second shield electrode 24 can have a second longitudinal edge 30 that is aligned with the lateral direction 134 and facing away from the second external terminal 120 (shown in FIG. 1E ) and the second end 121. The second longitudinal edge 30 of the second shield electrode 24 can be offset from the first longitudinal edge 28 of the second shield electrode 24 in the longitudinal direction 132 by the shield electrode offset distance 32.

[0096] ​The first shielding capacitor region 34 may be formed between the first longitudinal edge 28 of the first shielding electrode 119 and the first longitudinal edge 28 of the second shielding electrode 121. The second shielding capacitor region 36 may be formed between the first longitudinal edge 28 of the first shielding electrode 119 and the second longitudinal edge 30 of the second shielding electrode 121. In some embodiments, the width 38 of the first longitudinal edge 28 in the lateral direction 134 may be smaller than the width 40 of the first shielding electrode 22 in the lateral direction 134.

[0097] The first shielding gap distance 42 can be formed in the longitudinal direction 132, between the first longitudinal edge 28 of the first shielding electrode 22 and the first longitudinal edge 28 of the second shielding electrode 24. The second shielding gap distance 44 can be formed in the longitudinal direction 132, between the second transverse edge 30 of the first shielding electrode 22 and the second transverse edge 30 of the second shielding electrode 24.

[0098] In some embodiments, a third shielding gap distance 46 may be formed between the third longitudinal edge 48 of the first shielding electrode 22 and the third longitudinal edge 48 of the second shielding electrode 24. A third shielding capacitor region 51 may be formed between the third longitudinal edge 48 of the first shielding electrode 119 and the third longitudinal edge 48 of the second shielding electrode 121. In some embodiments, the third shielding gap distance 46 may be approximately equal to the second shielding gap distance 44, such that the third shielding capacitor region 51 may be substantially similar in size and shape to the second shielding capacitor region 36. For example, in some embodiments, the first shielding electrode 22 and / or the second shielding electrode 24 may be symmetrical in the lateral direction 134 about a longitudinal centerline 50 extending in the longitudinal direction 132.

[0099] However, in other embodiments, the third shielding gap distance 46 may be greater than or less than the second shielding gap distance 44, such that the size and / or shape of the third capacitor region 51 is set to be different from that of the second capacitor region 36 and produces a different capacitance than that of the second capacitor region.

[0100] It should be understood that in some embodiments, one or more of the shielding electrodes 22, 24 may be rectangular. In other words, the shielding electrode offset distance 32 may be zero or approximately zero, such that the first longitudinal edge 28 and the second longitudinal edge 30 are aligned or approximately aligned.

[0101] FIG. 2A and FIG. 2BAnother embodiment of the first electrode layer 102 and the second electrode layer 104 is illustrated. More specifically, each electrode layer 102, 104 can include a first electrode 106 and a second electrode 108. The first electrode 106 can have a base portion 114. A pair of electrode arms 110 and at least one center portion 112 can extend from the base portion 114. The second electrode 108 can have a base portion 114 extending along a longitudinal edge of the second electrode layer 108. The second electrode 106 can have a pair of electrode arms 110 extending from the base portion 114. The electrode regions 12, 14, 16 can generally be non-overlapping.

[0102] Referring to FIG. 1E In some embodiments, the wideband multilayer ceramic capacitor 100 can have a capacitor thickness 56 in the Z-direction 136 between the top surface 18 and the bottom surface 20.

[0103] The dielectric region 12 can have a dielectric region thickness 58 in the Z-direction 136. In some embodiments, the ratio of the capacitor thickness 56 to the dielectric region thickness 58 can be in a range from about 1.1 to about 20, in some embodiments in a range from about 1.5 to about 10, in some embodiments in a range from about 1.7 to about 5.

[0104] The active electrode region 14 can have an active electrode region thickness 59 in the Z-direction 136. The active electrode region 14 can be free of the shield electrodes 22, 24, and / or can include only overlapping electrodes. The active electrode region thickness 59 can be defined between the lowest active electrode layer 19 and the highest electrode layer 65. The ratio of the capacitor thickness 56 to the active electrode region thickness 59 can range from about 1.1 to about 20.

[0105] The shield electrode region 16 can have a shield electrode region thickness 61 in the Z-direction 136. The shield electrode region thickness 61 can be defined between the bottom surface 20 of the capacitor 100 and the lowest electrode layer 19 of the plurality of active electrodes. The ratio of the capacitor thickness 56 to the shield electrode region thickness 61 can be in a range from about 1.1 to about 20, in some embodiments in a range from about 1.5 to about 10, in some embodiments in a range from about 1.7 to about 5.

[0106] In some embodiments, the shield-to-bottom surface distance 63 can be defined as the distance between the shield electrodes 22, 24 and the bottom surface 20 of the capacitor 100. If multiple shield electrode layers are included, the shield-to-bottom surface distance 63 can be defined as the distance between the lowest layer of the shield electrode layers and the bottom surface 20. The ratio of the capacitor thickness 56 to the shield-to-bottom surface distance 63 can be in a range from about 1.1 to about 20, in some embodiments in a range from about 1.5 to about 10, in some embodiments in a range from about 1.7 to about 5.

[0107] In some embodiments, shielding electrodes 22, 24 may be spaced apart from active electrodes 106, 108 by a first shield-to-active distance 67. The ratio of the first shield-to-active distance 67 to the distance 63 from the shield to the bottom surface may be in the range of about 1 to about 20, in some embodiments in the range of about 2 to about 10, and in some embodiments in the range of about 3 to about 5.

[0108] also, FIG. 2A The diagram illustrates an electrode arm 110 including a main portion 128 and a stepped portion 130. More specifically, the electrode arm 110 of the first electrode 106 may include a first longitudinal edge 60 extending in the lateral direction 134 and may define the edge of the stepped portion 130. A second longitudinal edge 62 may extend in the lateral direction 134 and may define the edge of the main portion 128 of the arm 110. The first longitudinal edge 60 may be offset from the second longitudinal edge 62 in the longitudinal direction 132 by an arm offset distance 64. One or both electrode arms 110 of the first electrode 106 and / or the second electrode 108 may include their respective main portions 128 and stepped portions 130. For example, the two arms 110 of the two electrodes 106, 108 may include their respective main portions 128 and stepped portions 130, such as... FIG. 2A The diagram shows that a main arm gap 240 can be formed between the stepped portions 130 of the aligned arms 110. A stepped arm gap 242 can be formed between the main portions 128 of the aligned arms 110.

[0109] refer to FIG. 2B , can FIG. 2A A plurality of capacitance regions are formed between the first electrode 106 and the second electrode 108 in the electrode configuration. For example, in some embodiments, a central capacitance region 122 may be formed between the central portion 112 of the first electrode 106 and the base portion 114 and / or arm 110 of the second electrode 108. In some embodiments, a main arm gap capacitance region 125 may be formed within the main arm gap 240, and a step gap capacitance region 126 may be formed within the step arm gap 242.

[0110] refer to FIG. 3A In some embodiments, dielectric region 12 may include a first virtual terminal electrode 52 connected to the first terminal 118 and / or a second virtual terminal electrode 54 connected to the second terminal 120. In some embodiments, shielding electrode region 16 may include a first virtual terminal electrode 55 connected to the first terminal 118 and / or a second virtual terminal electrode 54 connected to the second terminal 120.

[0111] More specifically, the dummy tab electrodes 52, 54, 55, 57 can be used to form (e.g., deposit) the terminals 118, 120, for example, using a pure copper termination process. The dummy tab electrodes 52, 54, 55, 57 can extend less than 25% of the length 21 of the capacitor from the first end 119 or the second end 121.

[0112] Further, in some embodiments, the shield electrode region 16 can include multiple shield electrode layers. For example, a first shield electrode 22 and a second shield electrode 24 can be disposed within a monolithic body of the capacitor 100 and connected with a first external terminal 118 and a second external terminal 120, respectively, for example, as described above with reference to the accompanying drawings. The second shield electrode 24 can be generally aligned with the first shield electrode 22 in the Z-direction 136. An additional shield electrode pair 150 can be located within a shield electrode layer 166 between the first shield electrode 22 and the second shield electrode 24, which can be defined as the lowest shield electrode. In such embodiments, the first shield-to-active distance 67 can be defined between the lowest active electrode 19 and the shield electrode(s) closest to the lowest active electrode 19 in the Z-direction 136. In this example, the first shield-to-active distance 67 is defined between the lowest active electrode 19 and the additional shield electrode pair 150.

[0113] The electrode configurations described herein can allow for a primary capacitive element between the center portions 112 of adjacent electrode layers 102, 104 (i.e., parallel plate capacitance), as well as additional secondary capacitive elements, for example, as described above with reference to FIG. 1C , FIG. 1D and FIG. 2B . These configurations are schematically depicted in FIG. 4 .

[0114] In some embodiments, the capacitor 100 can include one or more floating electrodes 111. The floating electrodes 111 can be located in the dielectric region 12. However, in other embodiments, the floating electrodes 111 can be located in the active electrode region 14 and / or the shield electrode region 16. Generally, such floating electrodes 111 are not directly connected to the external terminals 118, 120.

[0115] However, in some embodiments, the floating electrodes can be part of a floating electrode layer that includes at least one electrode that is electrically connected to an external terminal; however, such a floating electrode layer includes at least one floating electrode that does not directly contact that electrode or the external terminal.

[0116] The floating electrodes can be positioned and configured according to any method known in the art. For example, the floating electrodes can be disposed such that the floating electrodes overlap at least a portion (e.g., a central portion) of the first active electrodes and / or the second active electrodes of the active electrode layer. In this regard, the floating electrode layer can be alternately layered and disposed with the first electrode layer and the second internal electrode layer. In this regard, the layers can be separated by a dielectric layer.

[0117] Further, such floating electrodes can have any shape as is generally known in the art. For example, in an embodiment, the floating electrode layer can include at least one floating electrode having a dagger-like configuration. For example, such a configuration can be similar to the configuration and shape of the first electrodes described herein. However, it should be appreciated that such first electrodes can or can not include electrode arms having stepped portions.

[0118] Further, in an embodiment, the floating electrode layer can include at least one floating electrode, wherein an end of the floating electrode is adjacent to but does not contact at least one external terminal. In this regard, such a gap can be referred to as a floating electrode gap in the longitudinal direction. The length of such a floating electrode gap in the longitudinal direction can be greater than 0% of the capacitor, such as about 3% or more, such as about 5% or more to about 50% or less, such as about 40% or less, such as about 30% or less, such as about 20% or less, such as about 10% or less.

[0119] FIG. 3B Another embodiment of a capacitor 160 is illustrated in accordance with aspects of the present disclosure. The capacitor 160 can include a plurality of electrode regions 162. The plurality of electrode regions 162 can include an active electrode region 14, a first shield electrode region 164, and a second shield electrode region 166. The active electrode region 14 can be located between the first shield electrode region 164 and the second shield electrode region 166.

[0120] In some embodiments, the capacitor 160 or a portion thereof can be symmetrical about a longitudinal centerline 167 extending in the longitudinal direction. For example, the shield electrodes 22, 24 of the bottom shield electrode region 164 can be symmetrical about the longitudinal centerline 167 relative to the shield electrodes 22, 24 of the top electrode region 166. In other words, the shield-to-bottom surface distance 63 can be substantially equal to a shield-to-top surface distance 168, which can be defined between the shield electrodes 22, 24 of the top shield electrode region 166 and the top surface 18 of the capacitor 160. For example, in some embodiments, the ratio of the shield-to-bottom surface distance 63 to the shield-to-top surface distance 168 can be in a range from about 0.8 to about 1.2, in some embodiments in a range from about 0.9 to about 1.1, in some embodiments in a range from about 0.95 to about 1.05, and in some embodiments in a range from about 0.98 to about 1.02.

[0121] The shield electrodes 22, 24 of the top shield electrode region 166 can be spaced apart from the active electrodes 106, 108 by a second shield-to-active distance 169. The ratio of the second shield-to-active distance 169 to the shield-to-top surface distance 168 can be in a range from about 1 to about 20, in some embodiments in a range from about 2 to about 10, and in some embodiments in a range from about 3 to about 5. Further, the ratio of the first shield-to-active distance 67 to the second shield-to-active distance 169 can be in a range from about 0.8 to about 1.2, in some embodiments in a range from about 0.9 to about 1.1, in some embodiments in a range from about 0.95 to about 1.05, and in some embodiments in a range from about 0.98 to about 1.02.

[0122] The capacitor 160 can exhibit comparable insertion loss characteristics in a first orientation (as shown) to a third orientation in which the capacitor 160 is rotated 180 degrees about the longitudinal direction 132 (appears substantially similar as shown in the illustration). However, a second orientation of the capacitor 160 can be defined relative to the first orientation by a rotation of 90 degrees about the longitudinal direction 132, such that the shield electrodes 22, 24 are perpendicular to the mounting surface 101.

[0123] In the first orientation, the capacitor 160 can exhibit a first insertion loss value at a test frequency greater than about 2 GHz. The capacitor 160 can exhibit a second insertion loss value in the second orientation relative to the mounting surface at the test frequency that differs from the first insertion loss value by at least about 0.3 dB.

[0124] FIG. 4 is schematically illustrated FIG. 1Cthree capacitive elements of the electrode configuration: a primary capacitive element 112', a center capacitive element 122', and an arm gap capacitive element 124'. The capacitive elements 112', 122', and 124' correspond to FIG. 1C the center region 112, the center capacitive region 122, and the arm gap capacitive region 124, respectively. Further, the outer terminals are described in FIG. 4 with 118 and 128.

[0125] FIG. 5 schematically illustrates FIG. 2B four capacitive elements of the electrode configuration, where the capacitive elements 112', 122', and 125' and 126' correspond to FIG. 2B the center region 112, the capacitive region 122, the primary arm gap capacitive region 125, and the stepped gap capacitive region 126, respectively. It should be appreciated that the dimensions of the various gaps can be selectively designed to achieve the respective capacitance values desired for the capacitive elements illustrated in FIG. 4 and FIG. 5 More specifically, the configuration of the capacitor and various parameters, such as the number of electrode layers, the surface area of the electrode pairs overlapping the center portion, the distance separating the electrodes, the dielectric constant of the dielectric material, etc., can be selected to achieve the desired capacitance values. However, as disclosed herein, the capacitor can include an array of combined series and parallel capacitors to provide effective broadband performance.

[0126] In one exemplary ultra-wideband capacitor implementation, the primary capacitor 112' generally corresponds to a relatively large capacitance suitable for operation in a generally lower frequency range (e.g., approximately between about a few kilohertz (kHz) to about 200 megahertz (MHz)), while the secondary capacitors 122', 124', 125', and / or 126' can generally correspond to a relatively smaller value capacitor configured for operation in a relatively higher frequency range (e.g., approximately between about 200 megahertz (MHz) to several gigahertz (GHz)).

[0127] Accordingly, the active electrodes can be configured to exhibit multiple capacitive elements within a single set of stacked electrodes. For example, the primary capacitive element can be effective at relatively low frequencies, while the secondary capacitive elements (e.g., the center capacitive region 122 and / or the arm gap capacitive region 124) can be effective at relatively mid and / or high frequencies. For example, the primary capacitance can be within 1 and 500 nF, such as approximately within 10 and 100 nF, while the secondary capacitance can be within 1 and 500 pF, such as within 10 and 100 pF.

[0128] Referring to FIG. 6In some embodiments, the multilayer capacitor 300 can include a first external terminal 118 disposed along a first end 119 and a second external terminal 120 disposed along a second end 121 opposite the first end 119 in the longitudinal direction 132. The multilayer capacitor 300 can include a plurality of dielectric layers and a plurality of electrode layers, with the electrode layers interleaved in opposing and spaced apart relation with a dielectric layer between each adjacent electrode layer.

[0129] Further, as noted above, the multilayer capacitor can include shield electrodes. For example, as FIG. 6 illustrated, the multilayer capacitor 300 can include a first shield region 210 and a second shield region 212, and each of the shield regions 210, 212 can include one or more shield electrode layers 214. The shield regions 210, 212 can be spaced apart from an active electrode region 216 by a dielectric region (e.g., a region that does not contain any electrode layers).

[0130] The shield electrode layers 214 can have a first shield electrode configuration, with each shield electrode 220 generally rectangular. In other embodiments, the shield electrode layers 214 can have a second shield electrode configuration, with the shield electrodes 222 including steps 224, for example, as explained above with reference to the electrodes of FIG. 2B. FIG. 1D

[0131] In some embodiments, an active electrode 218 region can be disposed between the first shield region 210 and the second shield region 212. The active electrode region 216 can include a plurality of alternating active electrode layers 218, for example, as explained above with reference to FIG. 2B. Additionally, a pair of ceramic covers 227 can be disposed along a top surface and / or a bottom surface of the capacitor 300. The ceramic covers 227 can include a dielectric material that is the same as or similar to the dielectric material of the plurality of dielectric layers. FIGS. 2A-2C

[0132] With reference to FIG. 6 ​​In some embodiments, the multilayer capacitor 300 can also include anchor electrode regions 302, 304, 316, and / or 318. For example, the multilayer capacitor 300 can include a first anchor electrode region 304 on top of the active electrode region 216. In addition, the shield electrode region 210, which includes the shield electrode layer 214, can be located above the first anchor electrode region 304, such as on top of the first anchor electrode region. Furthermore, a second anchor electrode region 302 can be located above, such as on top of, the shield electrode region 210. Similarly, the multilayer capacitor 300 can include a third anchor electrode region 316 below, such as directly below, the active electrode region 216. In addition, the shield electrode region 210, which includes the shield electrode layer 214, can be located below, such as directly below, the third anchor electrode region 316. Furthermore, a fourth anchor electrode region 318 can be located below, such as directly below, the shield electrode region 210. In this regard, the active electrode region 216 can be disposed, for example, between the first anchor electrode region 304 and the third anchor electrode region 316. The active electrode region 216 can be configured as described above with reference to FIGS. 1A-1C 、 FIGS. 2A-2C or as described below with reference to FIGS. 8A-8D .

[0133] Referring to FIG. 7A , the anchor electrode regions 302, 304, 316, and / or 318 can include a plurality of anchor electrode layers 310, each having a pair of anchor electrodes 312. The anchor electrodes 312 can include a pair of electrode arms 314. The electrode arms 314 of the anchor electrodes 312 can include a main portion 328 and a step portion 330, for example, in a similar manner as described above with reference to the electrodes of FIG. 1A and FIGS. 2A-2C .

[0134] Referring to FIGS. 7B-7D , the anchor electrodes 312 can have various configurations. For example, referring to FIG. 7B , in some embodiments, the electrode arms 314 of the anchor electrodes 312 can not include a step. For example, such electrodes can exhibit a C-shaped configuration without a step. Referring to FIG. 7C , in some embodiments, the electrode arms 314 of the anchor electrodes 312 can include a step portion 320 that is offset inward from the outer lateral edge 322 of the anchor electrode 312. Referring to FIG. 7D , in other embodiments, the step portion 320 can be offset from the inner lateral edge 324 of the arm 314 of the anchor electrode 312. Other configurations are also possible. For example, in some embodiments, the step portion 320 can be offset from both the outer lateral edge 322 and the inner lateral edge 324.

[0135] Referring to FIGS. 8A-8CIn some embodiments, the active electrodes 106, 108 can have various other configurations. For example, with reference to FIG. 6, the active electrodes 106, 108 can each include a single arm 110, rather than a pair of arms 110, 202 as described above with respect to FIGS. 1-5. In this regard, such an electrode can include an electrode that includes a central portion extending from a base portion and one electrode arm also extending from the base portion; while a counter electrode can include a base portion and only one electrode arm extending from the base portion of the second electrode. FIG. 8A In some embodiments, each of the first electrode 106 and the second electrode 108 can include a single arm 110, rather than a pair of arms 110, 202 as described above with respect to FIGS. 1-5. In this regard, such an electrode can include an electrode that includes a central portion extending from a base portion and one electrode arm also extending from the base portion; while a counter electrode can include a base portion and only one electrode arm extending from the base portion of the second electrode. FIG. 1A

[0136] With reference to FIG. 7, the active electrodes 106, 108 can each include a central portion 112. For example, each electrode 106, 108 can include a central portion 112 extending from a respective base portion, as well as at least one electrode arm 110, 202 (e.g., two electrode arms 110, 202) extending from the respective base portion. FIG. 8B

[0137] With reference to FIG. 8, the active electrodes 106, 108 can each include a central portion 112. For example, each electrode 106, 108 can include a central portion 112 extending from a respective base portion, as well as a pair of electrode arms 110, 202 extending from the respective base portion. FIG. 8C In some embodiments, the electrode arms 110, 202 of the electrodes 106, 108 can have a step portion 130 that is offset outwardly from a lateral centerline 236 of at least one of the electrodes 106, 108 of the electrode layer from an inner lateral edge 324 of a main portion of the electrode arm. Finally, with reference to FIG. 10, in some embodiments, the electrode arms 110 of the electrodes 106, 108 can have a step portion 130 that is offset from both an outer lateral edge 322 and an inner lateral edge 324 of the electrode arms 110, 202. FIG. 8D In some embodiments, the electrode arms 110 of the electrodes 106, 108 can have a step portion 130 that is offset outwardly from a lateral centerline 236 of at least one of the electrodes 106, 108 of the electrode layer from an inner lateral edge 324 of a main portion of the electrode arm. Finally, with reference to FIG. 10, in some embodiments, the electrode arms 110 of the electrodes 106, 108 can have a step portion 130 that is offset from both an outer lateral edge 322 and an inner lateral edge 324 of the electrode arms 110, 202.

[0138] II. Insertion Loss

[0139] Aspects of the present disclosure relate to a wideband multilayer capacitor exhibiting orientation sensitive insertion loss characteristics. The wideband multilayer capacitor can exhibit an insertion loss at a test frequency in a first orientation that varies more than about 0.3 dB from an insertion loss at the test frequency in a second orientation. In the first orientation, a longitudinal direction 132 of the multilayer ceramic capacitor 100 can be parallel to a mounting surface 101 (e.g., as shown in FIG. 1). In the first orientation, the electrodes (e.g., active electrodes 106, 108 and shield electrodes 22, 24) can be generally parallel to the mounting surface 101. Additionally, the shield electrode region 1 (including shield electrodes 22, 24) can be positioned between the active electrode region 14 (including the plurality of active electrodes 106, 108) and the mounting surface 101 in the first orientation, e.g., as shown in FIG. 1. FIG. 1E Aspects of the present disclosure relate to a wideband multilayer capacitor exhibiting orientation sensitive insertion loss characteristics. The wideband multilayer capacitor can exhibit an insertion loss at a test frequency in a first orientation that varies more than about 0.3 dB from an insertion loss at the test frequency in a second orientation. In the first orientation, a longitudinal direction 132 of the multilayer ceramic capacitor 100 can be parallel to a mounting surface 101 (e.g., as shown in FIG. 1). In the first orientation, the electrodes (e.g., active electrodes 106, 108 and shield electrodes 22, 24) can be generally parallel to the mounting surface 101. Additionally, the shield electrode region 1 (including shield electrodes 22, 24) can be positioned between the active electrode region 14 (including the plurality of active electrodes 106, 108) and the mounting surface 101 in the first orientation, e.g., as shown in FIG. 1. FIG. 1E Aspects of the present disclosure relate to a wideband multilayer capacitor exhibiting orientation sensitive insertion loss characteristics. The wideband multilayer capacitor can exhibit an insertion loss at a test frequency in a first orientation that varies more than about 0.3 dB from an insertion loss at the test frequency in a second orientation. In the first orientation, a longitudinal direction 132 of the multilayer ceramic capacitor 100 can be parallel to a mounting surface 101 (e.g., as shown in FIG. 1). In the first orientation, the electrodes (e.g., active electrodes 106, 108 and shield electrodes 22, 24) can be generally parallel to the mounting surface 101. Additionally, the shield electrode region 1 (including shield electrodes 22, 24) can be positioned between the active electrode region 14 (including the plurality of active electrodes 106, 108) and the mounting surface 101 in the first orientation, e.g., as shown in FIG. 1.

[0140] ​​Reference FIG. 9 In the second orientation, the multilayer ceramic capacitor 100 can be rotated 180 degrees about the longitudinal direction 136 relative to the first orientation (shown in FIG. 1). Thus, in the second orientation, the dielectric region 16 can be positioned between the active electrode region 14 and the mounting surface 101 relative to the Z direction 136. FIG. 1E

[0141] The capacitor can exhibit a first insertion loss value in the first orientation at a test frequency (greater than about 2 GHz) and a second insertion loss value in the second orientation at the test frequency. In some embodiments, the test frequency can be in a range from about 10 GHz to about 30 GHz, or higher. The second insertion loss value can differ from the first insertion loss value by at least about 0.3 dB.

[0142] III. Test Method

[0143] According to aspects of the disclosure, a test assembly can be used to test performance characteristics of a capacitor, such as insertion loss and return loss. For example, the capacitor can be mounted to a test board. An input line and an output line can both be connected with the test board. The test board can include microstrip lines or test traces that electrically connect the input line and the output line with respective external terminals of the capacitor. The test traces can be spaced apart by about 0.432 mm (0.017 inches) or about 0.610 mm (0.024 inches).

[0144] An input signal can be applied to the input line using a source signal generator (e.g., a 1806 Keithley 2400 Series source-measure unit (SMU), such as a Keithley 2410-C SMU), and a resulting output signal of the capacitor can be measured at the output line (e.g., using the source signal generator). This test method can be repeated for a plurality of capacitors having the same design and nominal dimensions. Insertion loss results can be measured in the first orientation and the second orientation. Differences between these insertion loss results can be calculated and averaged to determine a nominal insertion loss sensitivity value for the group of capacitors.

[0145] This process can be repeated for various configurations of capacitors described herein.

[0146] EMBODIMENT

[0147] Eight multilayer ceramic capacitors having the above-described FIGS. 1A-1E The eight multilayer ceramic capacitors of the described configuration were manufactured and tested for insertion loss response characteristics in the first orientation and the second orientation. The multilayer ceramic capacitors had the following dimensions, corresponding to​FIGS. 1A-1E the labeled dimensions.

[0148]

[0149] Thus, the ratio of the length of the capacitor 21 to the shield electrode offset distance 32 is about 6.7. The ratio of the second shield gap distance to the first shield gap distance is about 6.9. The ratio of the capacitor thickness to the shield-to-bottom surface distance is about 40.2.

[0150] The insertion loss response characteristics were measured for eight multilayer ceramic capacitors having the same design and nominal dimensions (within manufacturing tolerances). For each of the eight multilayer ceramic capacitors in the first orientation and the second orientation, the insertion loss values were sampled at 30 GHz and 40 GHz. For each capacitor, the difference between the insertion loss values for the first orientation and the second orientation was calculated at 30 GHz and 40 GHz. The resulting insertion loss delta values at 30 GHz and 40 GHz were averaged to determine the average insertion loss delta values between the first orientation and the second orientation at 30 GHz and 40 GHz, respectively, as follows:

[0151] Test Frequency (GHz) Average Insertion Loss Δ (dB) Standard Deviation of Insertion Loss 30 0.332 0.041 40 0.324 0.051

[0152] As shown in the above table, the average insertion loss of the manufactured multilayer ceramic capacitors was greater than 0.3 dB at 30 GHz and 40 GHz, with a standard deviation of 0.041 and 0.05 at 30 GHz and 40 GHz, respectively. As shown in the above table, the standard deviation of the average insertion loss delta values for the group of eight multilayer ceramic capacitors was also calculated at 30 GHz and 40 GHz.

[0153] FIG. 10 An insertion loss response curve for one of the plurality of ceramic capacitors is depicted, which exhibits an insertion loss very close to the average values described above. According to FIG. 10 the insertion loss response curve, the difference between the insertion loss for the first orientation and the insertion loss for the second orientation is as follows:

[0154] Test Frequency (GHz) Insertion Loss (dB) 30 0.330 40 0.325

[0155] In addition, the capacitor can exhibit superior insertion loss characteristics in the first orientation. Referring to FIG. 10 , the insertion loss 302 for the first orientation is greater than about -0.8 dB at about 10 GHz, about 20 GHz, about 30 GHz, about 40 GHz, about 50 GHz, and about 60 GHz. The insertion loss 302 for the first orientation is greater than about -0.5 dB at about 10 GHz, about 20 GHz, about 30 GHz, about 40 GHz, about 50 GHz, and about 60 GHz.

[0156] These and other modifications and variations to the illustrative embodiments can be practiced by those of ordinary skill in the art, without departing from the spirit and scope of the present application. In addition, it should be understood that aspects of the various embodiments can be interchanged both in whole and in part. In addition, those of ordinary skill in the art will appreciate that the foregoing description is by way of example only, and is not intended to limit the application further described in the appended claims.

Claims

1. A wideband multilayer ceramic capacitor having a first end and a second end spaced apart from the first end in a longitudinal direction perpendicular to a lateral direction, the lateral direction and the longitudinal direction both being perpendicular to a Z-direction, the wideband multilayer ceramic capacitor comprising: a monolithic body including a plurality of dielectric layers; a first external terminal disposed along the first end; a second external terminal disposed along the second end; a plurality of active electrode layers arranged within the monolithic body and parallel to the longitudinal direction, wherein at least one of the plurality of active electrode layers includes a first electrode having a base portion and an electrode arm extending from the base portion, the electrode arm having a main portion and a stepped portion, a first longitudinal edge of the stepped portion being offset from a second longitudinal edge of the main portion by an arm offset distance; a first shield electrode arranged within the monolithic body and parallel to the longitudinal direction, the first shield electrode connected with the first external terminal, the first shield electrode having a first longitudinal edge aligned with the lateral direction and facing away from the first external terminal, wherein the first shield electrode has a second longitudinal edge aligned with the lateral direction and facing away from the first external terminal, and wherein the second longitudinal edge of the first shield electrode is offset from the first longitudinal edge of the first shield electrode in the longitudinal direction by a shield electrode offset distance.

2. The wideband multilayer ceramic capacitor of claim 1, wherein, the wideband multilayer ceramic capacitor configured for mounting to a mounting surface such that the first shield electrode is positioned between the plurality of active electrode layers and the mounting surface.

3. The wideband multilayer ceramic capacitor of claim 1, wherein, the wideband multilayer ceramic capacitor is free of shield electrodes over the plurality of active electrode layers in the Z-direction.

4. The wideband multilayer ceramic capacitor of claim 1, wherein, the wideband multilayer ceramic capacitor is free of shield electrodes over a lowest electrode layer of the plurality of active electrode layers in the Z-direction.

5. The wideband multilayer ceramic capacitor of claim 1, wherein, the first shield electrode is symmetric about a longitudinal centerline extending in the longitudinal direction in the lateral direction.

6. The wideband multilayer ceramic capacitor of claim 1, wherein, the base portion is electrically connected with the first external terminal, and wherein the first electrode further includes a center portion extending from the base portion in the longitudinal direction.

7. The wideband multilayer ceramic capacitor of claim 6, wherein, the center portion has a first width at a first location and a second width greater than the first width at a second location, and wherein the second location is offset from the first location in the longitudinal direction.

8. The wideband multilayer ceramic capacitor of claim 6, wherein, the at least one of the plurality of active electrode layers includes a second electrode including a base portion electrically connected with the second external terminal, and wherein a center end gap distance is formed between the center portion of the first electrode and the base portion of the second electrode in the longitudinal direction.

9. The wideband multilayer ceramic capacitor of claim 6, wherein, The at least one of the plurality of active electrode layers includes a second electrode including a base portion electrically connected with the second external terminal and a second electrode arm extending from the base portion of the second electrode, and wherein a center edge gap distance is formed in the lateral direction between the center portion of the first electrode and the second electrode arm of the second electrode.

10. The wideband multilayer ceramic capacitor of claim 1, wherein, The wideband multilayer ceramic capacitor exhibits an insertion loss greater than -0.4 dB at 10 GHz.

11. The wide-band multilayer ceramic capacitor of claim 1, wherein, The wideband multilayer ceramic capacitor exhibits an insertion loss greater than -0.4 dB at 20 GHz.

12. The wideband multilayer ceramic capacitor of claim 1, wherein, The wideband multilayer ceramic capacitor exhibits an insertion loss greater than -0.4 dB at 30 GHz.

13. The wide-band multilayer ceramic capacitor of claim 1, wherein, The wideband multilayer ceramic capacitor exhibits an insertion loss in a range of -0.05 dB to -0.4 dB from 5 GHz to 20 GHz.

14. The wide-band multilayer ceramic capacitor of claim 1, wherein, The wideband multilayer ceramic capacitor exhibits an insertion loss in a range of -0.05 dB to -0.5 dB from 20 GHz to 40 GHz.

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